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scons,python: Fix `--without-python` flag
[gem5.git] / src / arch / arm / isa.cc
1 /*
2 * Copyright (c) 2010-2020 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 #include "arch/arm/isa.hh"
39
40 #include "arch/arm/faults.hh"
41 #include "arch/arm/htm.hh"
42 #include "arch/arm/interrupts.hh"
43 #include "arch/arm/mmu.hh"
44 #include "arch/arm/pmu.hh"
45 #include "arch/arm/self_debug.hh"
46 #include "arch/arm/system.hh"
47 #include "arch/arm/tlbi_op.hh"
48 #include "cpu/base.hh"
49 #include "cpu/checker/cpu.hh"
50 #include "debug/Arm.hh"
51 #include "debug/MiscRegs.hh"
52 #include "dev/arm/generic_timer.hh"
53 #include "dev/arm/gic_v3.hh"
54 #include "dev/arm/gic_v3_cpu_interface.hh"
55 #include "params/ArmISA.hh"
56 #include "sim/faults.hh"
57 #include "sim/stat_control.hh"
58 #include "sim/system.hh"
59
60 namespace ArmISA
61 {
62
63 ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
64 _decoderFlavor(p.decoderFlavor), _vecRegRenameMode(Enums::Full),
65 pmu(p.pmu), impdefAsNop(p.impdef_nop),
66 afterStartup(false)
67 {
68 miscRegs[MISCREG_SCTLR_RST] = 0;
69
70 // Hook up a dummy device if we haven't been configured with a
71 // real PMU. By using a dummy device, we don't need to check that
72 // the PMU exist every time we try to access a PMU register.
73 if (!pmu)
74 pmu = &dummyDevice;
75
76 // Give all ISA devices a pointer to this ISA
77 pmu->setISA(this);
78
79 system = dynamic_cast<ArmSystem *>(p.system);
80
81 // Cache system-level properties
82 if (FullSystem && system) {
83 highestELIs64 = system->highestELIs64();
84 haveSecurity = system->haveSecurity();
85 haveLPAE = system->haveLPAE();
86 haveCrypto = system->haveCrypto();
87 haveVirtualization = system->haveVirtualization();
88 haveLargeAsid64 = system->haveLargeAsid64();
89 physAddrRange = system->physAddrRange();
90 haveSVE = system->haveSVE();
91 havePAN = system->havePAN();
92 haveSecEL2 = system->haveSecEL2();
93 sveVL = system->sveVL();
94 haveLSE = system->haveLSE();
95 haveTME = system->haveTME();
96 } else {
97 highestELIs64 = true; // ArmSystem::highestELIs64 does the same
98 haveSecurity = haveLPAE = haveVirtualization = false;
99 haveCrypto = true;
100 haveLargeAsid64 = false;
101 physAddrRange = 32; // dummy value
102 haveSVE = true;
103 havePAN = false;
104 haveSecEL2 = true;
105 sveVL = p.sve_vl_se;
106 haveLSE = true;
107 haveTME = true;
108 }
109
110 // Initial rename mode depends on highestEL
111 const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) =
112 highestELIs64 ? Enums::Full : Enums::Elem;
113
114 selfDebug = new SelfDebug();
115 initializeMiscRegMetadata();
116 preUnflattenMiscReg();
117
118 clear();
119 }
120
121 std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS);
122
123 const ArmISAParams &
124 ISA::params() const
125 {
126 return dynamic_cast<const Params &>(_params);
127 }
128
129 void
130 ISA::clear()
131 {
132 const Params &p(params());
133
134 // Invalidate cached copies of miscregs in the TLBs
135 if (tc) {
136 getMMUPtr(tc)->invalidateMiscReg();
137 }
138
139 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
140 memset(miscRegs, 0, sizeof(miscRegs));
141
142 initID32(p);
143
144 // We always initialize AArch64 ID registers even
145 // if we are in AArch32. This is done since if we
146 // are in SE mode we don't know if our ArmProcess is
147 // AArch32 or AArch64
148 initID64(p);
149
150 // Start with an event in the mailbox
151 miscRegs[MISCREG_SEV_MAILBOX] = 1;
152
153 // Separate Instruction and Data TLBs
154 miscRegs[MISCREG_TLBTR] = 1;
155
156 MVFR0 mvfr0 = 0;
157 mvfr0.advSimdRegisters = 2;
158 mvfr0.singlePrecision = 2;
159 mvfr0.doublePrecision = 2;
160 mvfr0.vfpExceptionTrapping = 0;
161 mvfr0.divide = 1;
162 mvfr0.squareRoot = 1;
163 mvfr0.shortVectors = 1;
164 mvfr0.roundingModes = 1;
165 miscRegs[MISCREG_MVFR0] = mvfr0;
166
167 MVFR1 mvfr1 = 0;
168 mvfr1.flushToZero = 1;
169 mvfr1.defaultNaN = 1;
170 mvfr1.advSimdLoadStore = 1;
171 mvfr1.advSimdInteger = 1;
172 mvfr1.advSimdSinglePrecision = 1;
173 mvfr1.advSimdHalfPrecision = 1;
174 mvfr1.vfpHalfPrecision = 1;
175 miscRegs[MISCREG_MVFR1] = mvfr1;
176
177 // Reset values of PRRR and NMRR are implementation dependent
178
179 // @todo: PRRR and NMRR in secure state?
180 miscRegs[MISCREG_PRRR_NS] =
181 (1 << 19) | // 19
182 (0 << 18) | // 18
183 (0 << 17) | // 17
184 (1 << 16) | // 16
185 (2 << 14) | // 15:14
186 (0 << 12) | // 13:12
187 (2 << 10) | // 11:10
188 (2 << 8) | // 9:8
189 (2 << 6) | // 7:6
190 (2 << 4) | // 5:4
191 (1 << 2) | // 3:2
192 0; // 1:0
193
194 miscRegs[MISCREG_NMRR_NS] =
195 (1 << 30) | // 31:30
196 (0 << 26) | // 27:26
197 (0 << 24) | // 25:24
198 (3 << 22) | // 23:22
199 (2 << 20) | // 21:20
200 (0 << 18) | // 19:18
201 (0 << 16) | // 17:16
202 (1 << 14) | // 15:14
203 (0 << 12) | // 13:12
204 (2 << 10) | // 11:10
205 (0 << 8) | // 9:8
206 (3 << 6) | // 7:6
207 (2 << 4) | // 5:4
208 (0 << 2) | // 3:2
209 0; // 1:0
210
211 if (FullSystem && system->highestELIs64()) {
212 // Initialize AArch64 state
213 clear64(p);
214 return;
215 }
216
217 // Initialize AArch32 state...
218 clear32(p, sctlr_rst);
219 }
220
221 void
222 ISA::clear32(const ArmISAParams &p, const SCTLR &sctlr_rst)
223 {
224 CPSR cpsr = 0;
225 cpsr.mode = MODE_USER;
226
227 if (FullSystem) {
228 miscRegs[MISCREG_MVBAR] = system->resetAddr();
229 }
230
231 miscRegs[MISCREG_CPSR] = cpsr;
232 updateRegMap(cpsr);
233
234 SCTLR sctlr = 0;
235 sctlr.te = (bool) sctlr_rst.te;
236 sctlr.nmfi = (bool) sctlr_rst.nmfi;
237 sctlr.v = (bool) sctlr_rst.v;
238 sctlr.u = 1;
239 sctlr.xp = 1;
240 sctlr.rao2 = 1;
241 sctlr.rao3 = 1;
242 sctlr.rao4 = 0xf; // SCTLR[6:3]
243 sctlr.uci = 1;
244 sctlr.dze = 1;
245 miscRegs[MISCREG_SCTLR_NS] = sctlr;
246 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
247 miscRegs[MISCREG_HCPTR] = 0;
248
249 miscRegs[MISCREG_CPACR] = 0;
250
251 miscRegs[MISCREG_FPSID] = p.fpsid;
252
253 if (haveLPAE) {
254 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
255 ttbcr.eae = 0;
256 miscRegs[MISCREG_TTBCR_NS] = ttbcr;
257 // Enforce consistency with system-level settings
258 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
259 }
260
261 if (haveSecurity) {
262 miscRegs[MISCREG_SCTLR_S] = sctlr;
263 miscRegs[MISCREG_SCR] = 0;
264 miscRegs[MISCREG_VBAR_S] = 0;
265 } else {
266 // we're always non-secure
267 miscRegs[MISCREG_SCR] = 1;
268 }
269
270 //XXX We need to initialize the rest of the state.
271 }
272
273 void
274 ISA::clear64(const ArmISAParams &p)
275 {
276 CPSR cpsr = 0;
277 Addr rvbar = system->resetAddr();
278 switch (system->highestEL()) {
279 // Set initial EL to highest implemented EL using associated stack
280 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
281 // value
282 case EL3:
283 cpsr.mode = MODE_EL3H;
284 miscRegs[MISCREG_RVBAR_EL3] = rvbar;
285 break;
286 case EL2:
287 cpsr.mode = MODE_EL2H;
288 miscRegs[MISCREG_RVBAR_EL2] = rvbar;
289 break;
290 case EL1:
291 cpsr.mode = MODE_EL1H;
292 miscRegs[MISCREG_RVBAR_EL1] = rvbar;
293 break;
294 default:
295 panic("Invalid highest implemented exception level");
296 break;
297 }
298
299 // Initialize rest of CPSR
300 cpsr.daif = 0xf; // Mask all interrupts
301 cpsr.ss = 0;
302 cpsr.il = 0;
303 miscRegs[MISCREG_CPSR] = cpsr;
304 updateRegMap(cpsr);
305
306 // Initialize other control registers
307 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
308 if (haveSecurity) {
309 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
310 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
311 } else if (haveVirtualization) {
312 // also MISCREG_SCTLR_EL2 (by mapping)
313 miscRegs[MISCREG_HSCTLR] = 0x30c50830;
314 } else {
315 // also MISCREG_SCTLR_EL1 (by mapping)
316 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
317 // Always non-secure
318 miscRegs[MISCREG_SCR_EL3] = 1;
319 }
320 }
321
322 void
323 ISA::initID32(const ArmISAParams &p)
324 {
325 // Initialize configurable default values
326
327 uint32_t midr;
328 if (p.midr != 0x0)
329 midr = p.midr;
330 else if (highestELIs64)
331 // Cortex-A57 TRM r0p0 MIDR
332 midr = 0x410fd070;
333 else
334 // Cortex-A15 TRM r0p0 MIDR
335 midr = 0x410fc0f0;
336
337 miscRegs[MISCREG_MIDR] = midr;
338 miscRegs[MISCREG_MIDR_EL1] = midr;
339 miscRegs[MISCREG_VPIDR] = midr;
340
341 miscRegs[MISCREG_ID_ISAR0] = p.id_isar0;
342 miscRegs[MISCREG_ID_ISAR1] = p.id_isar1;
343 miscRegs[MISCREG_ID_ISAR2] = p.id_isar2;
344 miscRegs[MISCREG_ID_ISAR3] = p.id_isar3;
345 miscRegs[MISCREG_ID_ISAR4] = p.id_isar4;
346 miscRegs[MISCREG_ID_ISAR5] = p.id_isar5;
347 miscRegs[MISCREG_ID_ISAR6] = p.id_isar6;
348
349 miscRegs[MISCREG_ID_MMFR0] = p.id_mmfr0;
350 miscRegs[MISCREG_ID_MMFR1] = p.id_mmfr1;
351 miscRegs[MISCREG_ID_MMFR2] = p.id_mmfr2;
352 miscRegs[MISCREG_ID_MMFR3] = p.id_mmfr3;
353 miscRegs[MISCREG_ID_MMFR4] = p.id_mmfr4;
354
355 miscRegs[MISCREG_ID_ISAR5] = insertBits(
356 miscRegs[MISCREG_ID_ISAR5], 19, 4,
357 haveCrypto ? 0x1112 : 0x0);
358 }
359
360 void
361 ISA::initID64(const ArmISAParams &p)
362 {
363 // Initialize configurable id registers
364 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p.id_aa64afr0_el1;
365 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p.id_aa64afr1_el1;
366 miscRegs[MISCREG_ID_AA64DFR0_EL1] =
367 (p.id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
368 (p.pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3
369
370 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p.id_aa64dfr1_el1;
371 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p.id_aa64isar0_el1;
372 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p.id_aa64isar1_el1;
373 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p.id_aa64mmfr0_el1;
374 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p.id_aa64mmfr1_el1;
375 miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p.id_aa64mmfr2_el1;
376
377 miscRegs[MISCREG_ID_DFR0_EL1] =
378 (p.pmu ? 0x03000000ULL : 0); // Enable PMUv3
379
380 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
381
382 // SVE
383 miscRegs[MISCREG_ID_AA64ZFR0_EL1] = 0; // SVEver 0
384 if (haveSecurity) {
385 miscRegs[MISCREG_ZCR_EL3] = sveVL - 1;
386 } else if (haveVirtualization) {
387 miscRegs[MISCREG_ZCR_EL2] = sveVL - 1;
388 } else {
389 miscRegs[MISCREG_ZCR_EL1] = sveVL - 1;
390 }
391
392 // Enforce consistency with system-level settings...
393
394 // EL3
395 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
396 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
397 haveSecurity ? 0x2 : 0x0);
398 // EL2
399 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
400 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
401 haveVirtualization ? 0x2 : 0x0);
402 // SVE
403 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
404 miscRegs[MISCREG_ID_AA64PFR0_EL1], 35, 32,
405 haveSVE ? 0x1 : 0x0);
406 // SecEL2
407 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
408 miscRegs[MISCREG_ID_AA64PFR0_EL1], 39, 36,
409 haveSecEL2 ? 0x1 : 0x0);
410 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
411 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 39, 36,
412 haveSecEL2 ? 0x1 : 0x0);
413 // Large ASID support
414 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
415 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
416 haveLargeAsid64 ? 0x2 : 0x0);
417 // Physical address size
418 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
419 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
420 encodePhysAddrRange64(physAddrRange));
421 // Crypto
422 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
423 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4,
424 haveCrypto ? 0x1112 : 0x0);
425 // LSE
426 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
427 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20,
428 haveLSE ? 0x2 : 0x0);
429 // PAN
430 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
431 miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,
432 havePAN ? 0x1 : 0x0);
433 // TME
434 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
435 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 27, 24,
436 haveTME ? 0x1 : 0x0);
437 }
438
439 void
440 ISA::startup()
441 {
442 BaseISA::startup();
443
444 if (tc) {
445 setupThreadContext();
446
447 if (haveTME) {
448 std::unique_ptr<BaseHTMCheckpoint> cpt(new HTMCheckpoint());
449 tc->setHtmCheckpointPtr(std::move(cpt));
450 }
451 }
452
453 afterStartup = true;
454 }
455
456 void
457 ISA::setupThreadContext()
458 {
459 pmu->setThreadContext(tc);
460
461 if (!system)
462 return;
463
464 selfDebug->init(tc);
465
466 Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
467 if (!gicv3)
468 return;
469
470 if (!gicv3CpuInterface)
471 gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
472
473 gicv3CpuInterface->setISA(this);
474 gicv3CpuInterface->setThreadContext(tc);
475 }
476
477 void
478 ISA::takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
479 {
480 tc = new_tc;
481 setupThreadContext();
482 }
483
484 RegVal
485 ISA::readMiscRegNoEffect(int misc_reg) const
486 {
487 assert(misc_reg < NumMiscRegs);
488
489 const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
490 const auto &map = getMiscIndices(misc_reg);
491 int lower = map.first, upper = map.second;
492 // NB!: apply architectural masks according to desired register,
493 // despite possibly getting value from different (mapped) register.
494 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
495 |(miscRegs[upper] << 32));
496 if (val & reg.res0()) {
497 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n",
498 miscRegName[misc_reg], val & reg.res0());
499 }
500 if ((val & reg.res1()) != reg.res1()) {
501 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n",
502 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1());
503 }
504 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao
505 }
506
507
508 RegVal
509 ISA::readMiscReg(int misc_reg)
510 {
511 CPSR cpsr = 0;
512 PCState pc = 0;
513 SCR scr = 0;
514
515 if (misc_reg == MISCREG_CPSR) {
516 cpsr = miscRegs[misc_reg];
517 pc = tc->pcState();
518 cpsr.j = pc.jazelle() ? 1 : 0;
519 cpsr.t = pc.thumb() ? 1 : 0;
520 return cpsr;
521 }
522
523 #ifndef NDEBUG
524 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
525 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
526 warn("Unimplemented system register %s read.\n",
527 miscRegName[misc_reg]);
528 else
529 panic("Unimplemented system register %s read.\n",
530 miscRegName[misc_reg]);
531 }
532 #endif
533 misc_reg = redirectRegVHE(tc, misc_reg);
534
535 switch (unflattenMiscReg(misc_reg)) {
536 case MISCREG_HCR:
537 case MISCREG_HCR2:
538 if (!haveVirtualization)
539 return 0;
540 break;
541 case MISCREG_CPACR:
542 {
543 const uint32_t ones = (uint32_t)(-1);
544 CPACR cpacrMask = 0;
545 // Only cp10, cp11, and ase are implemented, nothing else should
546 // be readable? (straight copy from the write code)
547 cpacrMask.cp10 = ones;
548 cpacrMask.cp11 = ones;
549 cpacrMask.asedis = ones;
550
551 // Security Extensions may limit the readability of CPACR
552 if (haveSecurity) {
553 scr = readMiscRegNoEffect(MISCREG_SCR);
554 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
555 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
556 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
557 // NB: Skipping the full loop, here
558 if (!nsacr.cp10) cpacrMask.cp10 = 0;
559 if (!nsacr.cp11) cpacrMask.cp11 = 0;
560 }
561 }
562 RegVal val = readMiscRegNoEffect(MISCREG_CPACR);
563 val &= cpacrMask;
564 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
565 miscRegName[misc_reg], val);
566 return val;
567 }
568 case MISCREG_MPIDR:
569 case MISCREG_MPIDR_EL1:
570 return readMPIDR(system, tc);
571 case MISCREG_VMPIDR:
572 case MISCREG_VMPIDR_EL2:
573 // top bit defined as RES1
574 return readMiscRegNoEffect(misc_reg) | 0x80000000;
575 case MISCREG_ID_AFR0: // not implemented, so alias MIDR
576 case MISCREG_REVIDR: // not implemented, so alias MIDR
577 case MISCREG_MIDR:
578 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
579 scr = readMiscRegNoEffect(MISCREG_SCR);
580 if ((cpsr.mode == MODE_HYP) || isSecure(tc)) {
581 return readMiscRegNoEffect(misc_reg);
582 } else {
583 return readMiscRegNoEffect(MISCREG_VPIDR);
584 }
585 break;
586 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
587 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI
588 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI
589 case MISCREG_AIDR: // AUX ID set to 0
590 case MISCREG_TCMTR: // No TCM's
591 return 0;
592
593 case MISCREG_CLIDR:
594 warn_once("The clidr register always reports 0 caches.\n");
595 warn_once("clidr LoUIS field of 0b001 to match current "
596 "ARM implementations.\n");
597 return 0x00200000;
598 case MISCREG_CCSIDR:
599 warn_once("The ccsidr register isn't implemented and "
600 "always reads as 0.\n");
601 break;
602 case MISCREG_CTR: // AArch32, ARMv7, top bit set
603 case MISCREG_CTR_EL0: // AArch64
604 {
605 //all caches have the same line size in gem5
606 //4 byte words in ARM
607 unsigned lineSizeWords =
608 tc->getSystemPtr()->cacheLineSize() / 4;
609 unsigned log2LineSizeWords = 0;
610
611 while (lineSizeWords >>= 1) {
612 ++log2LineSizeWords;
613 }
614
615 CTR ctr = 0;
616 //log2 of minimun i-cache line size (words)
617 ctr.iCacheLineSize = log2LineSizeWords;
618 //b11 - gem5 uses pipt
619 ctr.l1IndexPolicy = 0x3;
620 //log2 of minimum d-cache line size (words)
621 ctr.dCacheLineSize = log2LineSizeWords;
622 //log2 of max reservation size (words)
623 ctr.erg = log2LineSizeWords;
624 //log2 of max writeback size (words)
625 ctr.cwg = log2LineSizeWords;
626 //b100 - gem5 format is ARMv7
627 ctr.format = 0x4;
628
629 return ctr;
630 }
631 case MISCREG_ACTLR:
632 warn("Not doing anything for miscreg ACTLR\n");
633 break;
634
635 case MISCREG_PMXEVTYPER_PMCCFILTR:
636 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
637 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
638 case MISCREG_PMCR ... MISCREG_PMOVSSET:
639 return pmu->readMiscReg(misc_reg);
640
641 case MISCREG_CPSR_Q:
642 panic("shouldn't be reading this register seperately\n");
643 case MISCREG_FPSCR_QC:
644 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
645 case MISCREG_FPSCR_EXC:
646 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
647 case MISCREG_FPSR:
648 {
649 const uint32_t ones = (uint32_t)(-1);
650 FPSCR fpscrMask = 0;
651 fpscrMask.ioc = ones;
652 fpscrMask.dzc = ones;
653 fpscrMask.ofc = ones;
654 fpscrMask.ufc = ones;
655 fpscrMask.ixc = ones;
656 fpscrMask.idc = ones;
657 fpscrMask.qc = ones;
658 fpscrMask.v = ones;
659 fpscrMask.c = ones;
660 fpscrMask.z = ones;
661 fpscrMask.n = ones;
662 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
663 }
664 case MISCREG_FPCR:
665 {
666 const uint32_t ones = (uint32_t)(-1);
667 FPSCR fpscrMask = 0;
668 fpscrMask.len = ones;
669 fpscrMask.fz16 = ones;
670 fpscrMask.stride = ones;
671 fpscrMask.rMode = ones;
672 fpscrMask.fz = ones;
673 fpscrMask.dn = ones;
674 fpscrMask.ahp = ones;
675 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
676 }
677 case MISCREG_NZCV:
678 {
679 CPSR cpsr = 0;
680 cpsr.nz = tc->readCCReg(CCREG_NZ);
681 cpsr.c = tc->readCCReg(CCREG_C);
682 cpsr.v = tc->readCCReg(CCREG_V);
683 return cpsr;
684 }
685 case MISCREG_DAIF:
686 {
687 CPSR cpsr = 0;
688 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
689 return cpsr;
690 }
691 case MISCREG_SP_EL0:
692 {
693 return tc->readIntReg(INTREG_SP0);
694 }
695 case MISCREG_SP_EL1:
696 {
697 return tc->readIntReg(INTREG_SP1);
698 }
699 case MISCREG_SP_EL2:
700 {
701 return tc->readIntReg(INTREG_SP2);
702 }
703 case MISCREG_SPSEL:
704 {
705 return miscRegs[MISCREG_CPSR] & 0x1;
706 }
707 case MISCREG_CURRENTEL:
708 {
709 return miscRegs[MISCREG_CPSR] & 0xc;
710 }
711 case MISCREG_PAN:
712 {
713 return miscRegs[MISCREG_CPSR] & 0x400000;
714 }
715 case MISCREG_L2CTLR:
716 {
717 // mostly unimplemented, just set NumCPUs field from sim and return
718 L2CTLR l2ctlr = 0;
719 // b00:1CPU to b11:4CPUs
720 l2ctlr.numCPUs = tc->getSystemPtr()->threads.size() - 1;
721 return l2ctlr;
722 }
723 case MISCREG_DBGDIDR:
724 /* For now just implement the version number.
725 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
726 */
727 return 0x5 << 16;
728 case MISCREG_DBGDSCRint:
729 return readMiscRegNoEffect(MISCREG_DBGDSCRint);
730 case MISCREG_ISR:
731 {
732 auto ic = dynamic_cast<ArmISA::Interrupts *>(
733 tc->getCpuPtr()->getInterruptController(tc->threadId()));
734 return ic->getISR(
735 readMiscRegNoEffect(MISCREG_HCR),
736 readMiscRegNoEffect(MISCREG_CPSR),
737 readMiscRegNoEffect(MISCREG_SCR));
738 }
739 case MISCREG_ISR_EL1:
740 {
741 auto ic = dynamic_cast<ArmISA::Interrupts *>(
742 tc->getCpuPtr()->getInterruptController(tc->threadId()));
743 return ic->getISR(
744 readMiscRegNoEffect(MISCREG_HCR_EL2),
745 readMiscRegNoEffect(MISCREG_CPSR),
746 readMiscRegNoEffect(MISCREG_SCR_EL3));
747 }
748 case MISCREG_DCZID_EL0:
749 return 0x04; // DC ZVA clear 64-byte chunks
750 case MISCREG_HCPTR:
751 {
752 RegVal val = readMiscRegNoEffect(misc_reg);
753 // The trap bit associated with CP14 is defined as RAZ
754 val &= ~(1 << 14);
755 // If a CP bit in NSACR is 0 then the corresponding bit in
756 // HCPTR is RAO/WI
757 bool secure_lookup = haveSecurity && isSecure(tc);
758 if (!secure_lookup) {
759 RegVal mask = readMiscRegNoEffect(MISCREG_NSACR);
760 val |= (mask ^ 0x7FFF) & 0xBFFF;
761 }
762 // Set the bits for unimplemented coprocessors to RAO/WI
763 val |= 0x33FF;
764 return (val);
765 }
766 case MISCREG_HDFAR: // alias for secure DFAR
767 return readMiscRegNoEffect(MISCREG_DFAR_S);
768 case MISCREG_HIFAR: // alias for secure IFAR
769 return readMiscRegNoEffect(MISCREG_IFAR_S);
770
771 case MISCREG_ID_PFR0:
772 // !ThumbEE | !Jazelle | Thumb | ARM
773 return 0x00000031;
774 case MISCREG_ID_PFR1:
775 { // Timer | Virti | !M Profile | TrustZone | ARMv4
776 bool haveTimer = (system->getGenericTimer() != NULL);
777 return 0x00000001
778 | (haveSecurity ? 0x00000010 : 0x0)
779 | (haveVirtualization ? 0x00001000 : 0x0)
780 | (haveTimer ? 0x00010000 : 0x0);
781 }
782 case MISCREG_ID_AA64PFR0_EL1:
783 return 0x0000000000000002 | // AArch{64,32} supported at EL0
784 0x0000000000000020 | // EL1
785 (haveVirtualization ? 0x0000000000000200 : 0) | // EL2
786 (haveSecurity ? 0x0000000000002000 : 0) | // EL3
787 (haveSVE ? 0x0000000100000000 : 0) | // SVE
788 (haveSecEL2 ? 0x0000001000000000 : 0) | // SecEL2
789 (gicv3CpuInterface ? 0x0000000001000000 : 0);
790 case MISCREG_ID_AA64PFR1_EL1:
791 return 0; // bits [63:0] RES0 (reserved for future use)
792
793 // Generic Timer registers
794 case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
795 case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
796 return getGenericTimer().readMiscReg(misc_reg);
797
798 case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15:
799 case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
800 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
801 return getGICv3CPUInterface().readMiscReg(misc_reg);
802
803 default:
804 break;
805
806 }
807 return readMiscRegNoEffect(misc_reg);
808 }
809
810 void
811 ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
812 {
813 assert(misc_reg < NumMiscRegs);
814
815 const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
816 const auto &map = getMiscIndices(misc_reg);
817 int lower = map.first, upper = map.second;
818
819 auto v = (val & ~reg.wi()) | reg.rao();
820 if (upper > 0) {
821 miscRegs[lower] = bits(v, 31, 0);
822 miscRegs[upper] = bits(v, 63, 32);
823 DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d:%d) : %#x\n",
824 miscRegName[misc_reg], misc_reg, lower, upper, v);
825 } else {
826 miscRegs[lower] = v;
827 DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d) : %#x\n",
828 miscRegName[misc_reg], misc_reg, lower, v);
829 }
830 }
831
832 void
833 ISA::setMiscReg(int misc_reg, RegVal val)
834 {
835
836 RegVal newVal = val;
837 bool secure_lookup;
838 SCR scr;
839
840 if (misc_reg == MISCREG_CPSR) {
841 updateRegMap(val);
842
843
844 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
845 int old_mode = old_cpsr.mode;
846 CPSR cpsr = val;
847 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) {
848 getMMUPtr(tc)->invalidateMiscReg();
849 }
850
851 if (cpsr.pan != old_cpsr.pan) {
852 getMMUPtr(tc)->invalidateMiscReg(MMU::D_TLBS);
853 }
854
855 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
856 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
857 PCState pc = tc->pcState();
858 pc.nextThumb(cpsr.t);
859 pc.nextJazelle(cpsr.j);
860 pc.illegalExec(cpsr.il == 1);
861 selfDebug->setDebugMask(cpsr.d == 1);
862
863 tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits() >> 7) - 1);
864
865 // Follow slightly different semantics if a CheckerCPU object
866 // is connected
867 CheckerCPU *checker = tc->getCheckerCpuPtr();
868 if (checker) {
869 tc->pcStateNoRecord(pc);
870 } else {
871 tc->pcState(pc);
872 }
873 } else {
874 #ifndef NDEBUG
875 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
876 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
877 warn("Unimplemented system register %s write with %#x.\n",
878 miscRegName[misc_reg], val);
879 else
880 panic("Unimplemented system register %s write with %#x.\n",
881 miscRegName[misc_reg], val);
882 }
883 #endif
884 misc_reg = redirectRegVHE(tc, misc_reg);
885
886 switch (unflattenMiscReg(misc_reg)) {
887 case MISCREG_CPACR:
888 {
889
890 const uint32_t ones = (uint32_t)(-1);
891 CPACR cpacrMask = 0;
892 // Only cp10, cp11, and ase are implemented, nothing else should
893 // be writable
894 cpacrMask.cp10 = ones;
895 cpacrMask.cp11 = ones;
896 cpacrMask.asedis = ones;
897
898 // Security Extensions may limit the writability of CPACR
899 if (haveSecurity) {
900 scr = readMiscRegNoEffect(MISCREG_SCR);
901 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
902 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
903 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
904 // NB: Skipping the full loop, here
905 if (!nsacr.cp10) cpacrMask.cp10 = 0;
906 if (!nsacr.cp11) cpacrMask.cp11 = 0;
907 }
908 }
909
910 RegVal old_val = readMiscRegNoEffect(MISCREG_CPACR);
911 newVal &= cpacrMask;
912 newVal |= old_val & ~cpacrMask;
913 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
914 miscRegName[misc_reg], newVal);
915 }
916 break;
917 case MISCREG_CPACR_EL1:
918 {
919 const uint32_t ones = (uint32_t)(-1);
920 CPACR cpacrMask = 0;
921 cpacrMask.tta = ones;
922 cpacrMask.fpen = ones;
923 if (haveSVE) {
924 cpacrMask.zen = ones;
925 }
926 newVal &= cpacrMask;
927 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
928 miscRegName[misc_reg], newVal);
929 }
930 break;
931 case MISCREG_CPTR_EL2:
932 {
933 const uint32_t ones = (uint32_t)(-1);
934 CPTR cptrMask = 0;
935 cptrMask.tcpac = ones;
936 cptrMask.tta = ones;
937 cptrMask.tfp = ones;
938 if (haveSVE) {
939 cptrMask.tz = ones;
940 }
941 newVal &= cptrMask;
942 cptrMask = 0;
943 cptrMask.res1_13_12_el2 = ones;
944 cptrMask.res1_7_0_el2 = ones;
945 if (!haveSVE) {
946 cptrMask.res1_8_el2 = ones;
947 }
948 cptrMask.res1_9_el2 = ones;
949 newVal |= cptrMask;
950 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
951 miscRegName[misc_reg], newVal);
952 }
953 break;
954 case MISCREG_CPTR_EL3:
955 {
956 const uint32_t ones = (uint32_t)(-1);
957 CPTR cptrMask = 0;
958 cptrMask.tcpac = ones;
959 cptrMask.tta = ones;
960 cptrMask.tfp = ones;
961 if (haveSVE) {
962 cptrMask.ez = ones;
963 }
964 newVal &= cptrMask;
965 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
966 miscRegName[misc_reg], newVal);
967 }
968 break;
969 case MISCREG_CSSELR:
970 warn_once("The csselr register isn't implemented.\n");
971 return;
972
973 case MISCREG_DC_ZVA_Xt:
974 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
975 return;
976
977 case MISCREG_FPSCR:
978 {
979 const uint32_t ones = (uint32_t)(-1);
980 FPSCR fpscrMask = 0;
981 fpscrMask.ioc = ones;
982 fpscrMask.dzc = ones;
983 fpscrMask.ofc = ones;
984 fpscrMask.ufc = ones;
985 fpscrMask.ixc = ones;
986 fpscrMask.idc = ones;
987 fpscrMask.ioe = ones;
988 fpscrMask.dze = ones;
989 fpscrMask.ofe = ones;
990 fpscrMask.ufe = ones;
991 fpscrMask.ixe = ones;
992 fpscrMask.ide = ones;
993 fpscrMask.len = ones;
994 fpscrMask.fz16 = ones;
995 fpscrMask.stride = ones;
996 fpscrMask.rMode = ones;
997 fpscrMask.fz = ones;
998 fpscrMask.dn = ones;
999 fpscrMask.ahp = ones;
1000 fpscrMask.qc = ones;
1001 fpscrMask.v = ones;
1002 fpscrMask.c = ones;
1003 fpscrMask.z = ones;
1004 fpscrMask.n = ones;
1005 newVal = (newVal & (uint32_t)fpscrMask) |
1006 (readMiscRegNoEffect(MISCREG_FPSCR) &
1007 ~(uint32_t)fpscrMask);
1008 tc->getDecoderPtr()->setContext(newVal);
1009 }
1010 break;
1011 case MISCREG_FPSR:
1012 {
1013 const uint32_t ones = (uint32_t)(-1);
1014 FPSCR fpscrMask = 0;
1015 fpscrMask.ioc = ones;
1016 fpscrMask.dzc = ones;
1017 fpscrMask.ofc = ones;
1018 fpscrMask.ufc = ones;
1019 fpscrMask.ixc = ones;
1020 fpscrMask.idc = ones;
1021 fpscrMask.qc = ones;
1022 fpscrMask.v = ones;
1023 fpscrMask.c = ones;
1024 fpscrMask.z = ones;
1025 fpscrMask.n = ones;
1026 newVal = (newVal & (uint32_t)fpscrMask) |
1027 (readMiscRegNoEffect(MISCREG_FPSCR) &
1028 ~(uint32_t)fpscrMask);
1029 misc_reg = MISCREG_FPSCR;
1030 }
1031 break;
1032 case MISCREG_FPCR:
1033 {
1034 const uint32_t ones = (uint32_t)(-1);
1035 FPSCR fpscrMask = 0;
1036 fpscrMask.len = ones;
1037 fpscrMask.fz16 = ones;
1038 fpscrMask.stride = ones;
1039 fpscrMask.rMode = ones;
1040 fpscrMask.fz = ones;
1041 fpscrMask.dn = ones;
1042 fpscrMask.ahp = ones;
1043 newVal = (newVal & (uint32_t)fpscrMask) |
1044 (readMiscRegNoEffect(MISCREG_FPSCR) &
1045 ~(uint32_t)fpscrMask);
1046 misc_reg = MISCREG_FPSCR;
1047 }
1048 break;
1049 case MISCREG_CPSR_Q:
1050 {
1051 assert(!(newVal & ~CpsrMaskQ));
1052 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
1053 misc_reg = MISCREG_CPSR;
1054 }
1055 break;
1056 case MISCREG_FPSCR_QC:
1057 {
1058 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1059 (newVal & FpscrQcMask);
1060 misc_reg = MISCREG_FPSCR;
1061 }
1062 break;
1063 case MISCREG_FPSCR_EXC:
1064 {
1065 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1066 (newVal & FpscrExcMask);
1067 misc_reg = MISCREG_FPSCR;
1068 }
1069 break;
1070 case MISCREG_FPEXC:
1071 {
1072 // vfpv3 architecture, section B.6.1 of DDI04068
1073 // bit 29 - valid only if fpexc[31] is 0
1074 const uint32_t fpexcMask = 0x60000000;
1075 newVal = (newVal & fpexcMask) |
1076 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
1077 }
1078 break;
1079 case MISCREG_HCR2:
1080 if (!haveVirtualization)
1081 return;
1082 break;
1083 case MISCREG_HCR:
1084 {
1085 const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1086 selfDebug->setenableTDETGE((HCR)val, mdcr);
1087 if (!haveVirtualization)
1088 return;
1089 }
1090 break;
1091
1092 case MISCREG_HDCR:
1093 {
1094 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1095 selfDebug->setenableTDETGE(hcr, (HDCR)val);
1096 }
1097 break;
1098 case MISCREG_DBGOSLAR:
1099 {
1100 OSL r = tc->readMiscReg(MISCREG_DBGOSLSR);
1101 const uint32_t temp = (val == 0xC5ACCE55)? 0x1 : 0x0;
1102 selfDebug->updateOSLock((RegVal) temp);
1103 r.oslk = bits(temp,0);
1104 tc->setMiscReg(MISCREG_DBGOSLSR, r);
1105 }
1106 break;
1107 case MISCREG_DBGBCR0:
1108 selfDebug->updateDBGBCR(0, val);
1109 break;
1110 case MISCREG_DBGBCR1:
1111 selfDebug->updateDBGBCR(1, val);
1112 break;
1113 case MISCREG_DBGBCR2:
1114 selfDebug->updateDBGBCR(2, val);
1115 break;
1116 case MISCREG_DBGBCR3:
1117 selfDebug->updateDBGBCR(3, val);
1118 break;
1119 case MISCREG_DBGBCR4:
1120 selfDebug->updateDBGBCR(4, val);
1121 break;
1122 case MISCREG_DBGBCR5:
1123 selfDebug->updateDBGBCR(5, val);
1124 break;
1125 case MISCREG_DBGBCR6:
1126 selfDebug->updateDBGBCR(6, val);
1127 break;
1128 case MISCREG_DBGBCR7:
1129 selfDebug->updateDBGBCR(7, val);
1130 break;
1131 case MISCREG_DBGBCR8:
1132 selfDebug->updateDBGBCR(8, val);
1133 break;
1134 case MISCREG_DBGBCR9:
1135 selfDebug->updateDBGBCR(9, val);
1136 break;
1137 case MISCREG_DBGBCR10:
1138 selfDebug->updateDBGBCR(10, val);
1139 break;
1140 case MISCREG_DBGBCR11:
1141 selfDebug->updateDBGBCR(11, val);
1142 break;
1143 case MISCREG_DBGBCR12:
1144 selfDebug->updateDBGBCR(12, val);
1145 break;
1146 case MISCREG_DBGBCR13:
1147 selfDebug->updateDBGBCR(13, val);
1148 break;
1149 case MISCREG_DBGBCR14:
1150 selfDebug->updateDBGBCR(14, val);
1151 break;
1152 case MISCREG_DBGBCR15:
1153 selfDebug->updateDBGBCR(15, val);
1154 break;
1155 case MISCREG_DBGWCR0:
1156 selfDebug->updateDBGWCR(0, val);
1157 break;
1158 case MISCREG_DBGWCR1:
1159 selfDebug->updateDBGWCR(1, val);
1160 break;
1161 case MISCREG_DBGWCR2:
1162 selfDebug->updateDBGWCR(2, val);
1163 break;
1164 case MISCREG_DBGWCR3:
1165 selfDebug->updateDBGWCR(3, val);
1166 break;
1167 case MISCREG_DBGWCR4:
1168 selfDebug->updateDBGWCR(4, val);
1169 break;
1170 case MISCREG_DBGWCR5:
1171 selfDebug->updateDBGWCR(5, val);
1172 break;
1173 case MISCREG_DBGWCR6:
1174 selfDebug->updateDBGWCR(6, val);
1175 break;
1176 case MISCREG_DBGWCR7:
1177 selfDebug->updateDBGWCR(7, val);
1178 break;
1179 case MISCREG_DBGWCR8:
1180 selfDebug->updateDBGWCR(8, val);
1181 break;
1182 case MISCREG_DBGWCR9:
1183 selfDebug->updateDBGWCR(9, val);
1184 break;
1185 case MISCREG_DBGWCR10:
1186 selfDebug->updateDBGWCR(10, val);
1187 break;
1188 case MISCREG_DBGWCR11:
1189 selfDebug->updateDBGWCR(11, val);
1190 break;
1191 case MISCREG_DBGWCR12:
1192 selfDebug->updateDBGWCR(12, val);
1193 break;
1194 case MISCREG_DBGWCR13:
1195 selfDebug->updateDBGWCR(13, val);
1196 break;
1197 case MISCREG_DBGWCR14:
1198 selfDebug->updateDBGWCR(14, val);
1199 break;
1200 case MISCREG_DBGWCR15:
1201 selfDebug->updateDBGWCR(15, val);
1202 break;
1203
1204 case MISCREG_MDCR_EL2:
1205 {
1206 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1207 selfDebug->setenableTDETGE(hcr, (HDCR)val);
1208 }
1209 break;
1210 case MISCREG_SDCR:
1211 case MISCREG_MDCR_EL3:
1212 {
1213 selfDebug->setbSDD(val);
1214 }
1215 break;
1216 case MISCREG_DBGDSCRext:
1217 {
1218 selfDebug->setMDBGen(val);
1219 DBGDS32 r = tc->readMiscReg(MISCREG_DBGDSCRint);
1220 DBGDS32 v = val;
1221 r.moe = v.moe;
1222 r.udccdis = v.udccdis;
1223 r.mdbgen = v.mdbgen;
1224 tc->setMiscReg(MISCREG_DBGDSCRint, r);
1225 r = tc->readMiscReg(MISCREG_DBGDSCRint);
1226 }
1227
1228 break;
1229 case MISCREG_MDSCR_EL1:
1230 {
1231 selfDebug->setMDSCRvals(val);
1232 }
1233 break;
1234
1235 case MISCREG_OSLAR_EL1:
1236 {
1237 selfDebug->updateOSLock(val);
1238 OSL r = tc->readMiscReg(MISCREG_OSLSR_EL1);
1239 r.oslk = bits(val, 0);
1240 r.oslm_3 = 1;
1241 tc->setMiscReg(MISCREG_OSLSR_EL1, r);
1242 }
1243 break;
1244
1245 case MISCREG_DBGBCR0_EL1:
1246 selfDebug->updateDBGBCR(0, val);
1247 break;
1248 case MISCREG_DBGBCR1_EL1:
1249 selfDebug->updateDBGBCR(1, val);
1250 break;
1251 case MISCREG_DBGBCR2_EL1:
1252 selfDebug->updateDBGBCR(2, val);
1253 break;
1254 case MISCREG_DBGBCR3_EL1:
1255 selfDebug->updateDBGBCR(3, val);
1256 break;
1257 case MISCREG_DBGBCR4_EL1:
1258 selfDebug->updateDBGBCR(4, val);
1259 break;
1260 case MISCREG_DBGBCR5_EL1:
1261 selfDebug->updateDBGBCR(5, val);
1262 break;
1263 case MISCREG_DBGBCR6_EL1:
1264 selfDebug->updateDBGBCR(6, val);
1265 break;
1266 case MISCREG_DBGBCR7_EL1:
1267 selfDebug->updateDBGBCR(7, val);
1268 break;
1269 case MISCREG_DBGBCR8_EL1:
1270 selfDebug->updateDBGBCR(8, val);
1271 break;
1272 case MISCREG_DBGBCR9_EL1:
1273 selfDebug->updateDBGBCR(9, val);
1274 break;
1275 case MISCREG_DBGBCR10_EL1:
1276 selfDebug->updateDBGBCR(10, val);
1277 break;
1278 case MISCREG_DBGBCR11_EL1:
1279 selfDebug->updateDBGBCR(11, val);
1280 break;
1281 case MISCREG_DBGBCR12_EL1:
1282 selfDebug->updateDBGBCR(12, val);
1283 break;
1284 case MISCREG_DBGBCR13_EL1:
1285 selfDebug->updateDBGBCR(13, val);
1286 break;
1287 case MISCREG_DBGBCR14_EL1:
1288 selfDebug->updateDBGBCR(14, val);
1289 break;
1290 case MISCREG_DBGBCR15_EL1:
1291 selfDebug->updateDBGBCR(15, val);
1292 break;
1293 case MISCREG_DBGWCR0_EL1:
1294 selfDebug->updateDBGWCR(0, val);
1295 break;
1296 case MISCREG_DBGWCR1_EL1:
1297 selfDebug->updateDBGWCR(1, val);
1298 break;
1299 case MISCREG_DBGWCR2_EL1:
1300 selfDebug->updateDBGWCR(2, val);
1301 break;
1302 case MISCREG_DBGWCR3_EL1:
1303 selfDebug->updateDBGWCR(3, val);
1304 break;
1305 case MISCREG_DBGWCR4_EL1:
1306 selfDebug->updateDBGWCR(4, val);
1307 break;
1308 case MISCREG_DBGWCR5_EL1:
1309 selfDebug->updateDBGWCR(5, val);
1310 break;
1311 case MISCREG_DBGWCR6_EL1:
1312 selfDebug->updateDBGWCR(6, val);
1313 break;
1314 case MISCREG_DBGWCR7_EL1:
1315 selfDebug->updateDBGWCR(7, val);
1316 break;
1317 case MISCREG_DBGWCR8_EL1:
1318 selfDebug->updateDBGWCR(8, val);
1319 break;
1320 case MISCREG_DBGWCR9_EL1:
1321 selfDebug->updateDBGWCR(9, val);
1322 break;
1323 case MISCREG_DBGWCR10_EL1:
1324 selfDebug->updateDBGWCR(10, val);
1325 break;
1326 case MISCREG_DBGWCR11_EL1:
1327 selfDebug->updateDBGWCR(11, val);
1328 break;
1329 case MISCREG_DBGWCR12_EL1:
1330 selfDebug->updateDBGWCR(12, val);
1331 break;
1332 case MISCREG_DBGWCR13_EL1:
1333 selfDebug->updateDBGWCR(13, val);
1334 break;
1335 case MISCREG_DBGWCR14_EL1:
1336 selfDebug->updateDBGWCR(14, val);
1337 break;
1338 case MISCREG_DBGWCR15_EL1:
1339 selfDebug->updateDBGWCR(15, val);
1340 break;
1341 case MISCREG_IFSR:
1342 {
1343 // ARM ARM (ARM DDI 0406C.b) B4.1.96
1344 const uint32_t ifsrMask =
1345 mask(31, 13) | mask(11, 11) | mask(8, 6);
1346 newVal = newVal & ~ifsrMask;
1347 }
1348 break;
1349 case MISCREG_DFSR:
1350 {
1351 // ARM ARM (ARM DDI 0406C.b) B4.1.52
1352 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
1353 newVal = newVal & ~dfsrMask;
1354 }
1355 break;
1356 case MISCREG_AMAIR0:
1357 case MISCREG_AMAIR1:
1358 {
1359 // ARM ARM (ARM DDI 0406C.b) B4.1.5
1360 // Valid only with LPAE
1361 if (!haveLPAE)
1362 return;
1363 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
1364 }
1365 break;
1366 case MISCREG_SCR:
1367 getMMUPtr(tc)->invalidateMiscReg();
1368 break;
1369 case MISCREG_SCTLR:
1370 {
1371 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
1372 scr = readMiscRegNoEffect(MISCREG_SCR);
1373
1374 MiscRegIndex sctlr_idx;
1375 if (haveSecurity && !highestELIs64 && !scr.ns) {
1376 sctlr_idx = MISCREG_SCTLR_S;
1377 } else {
1378 sctlr_idx = MISCREG_SCTLR_NS;
1379 }
1380
1381 SCTLR sctlr = miscRegs[sctlr_idx];
1382 SCTLR new_sctlr = newVal;
1383 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;
1384 miscRegs[sctlr_idx] = (RegVal)new_sctlr;
1385 getMMUPtr(tc)->invalidateMiscReg();
1386 }
1387 case MISCREG_MIDR:
1388 case MISCREG_ID_PFR0:
1389 case MISCREG_ID_PFR1:
1390 case MISCREG_ID_DFR0:
1391 case MISCREG_ID_MMFR0:
1392 case MISCREG_ID_MMFR1:
1393 case MISCREG_ID_MMFR2:
1394 case MISCREG_ID_MMFR3:
1395 case MISCREG_ID_MMFR4:
1396 case MISCREG_ID_ISAR0:
1397 case MISCREG_ID_ISAR1:
1398 case MISCREG_ID_ISAR2:
1399 case MISCREG_ID_ISAR3:
1400 case MISCREG_ID_ISAR4:
1401 case MISCREG_ID_ISAR5:
1402
1403 case MISCREG_MPIDR:
1404 case MISCREG_FPSID:
1405 case MISCREG_TLBTR:
1406 case MISCREG_MVFR0:
1407 case MISCREG_MVFR1:
1408
1409 case MISCREG_ID_AA64AFR0_EL1:
1410 case MISCREG_ID_AA64AFR1_EL1:
1411 case MISCREG_ID_AA64DFR0_EL1:
1412 case MISCREG_ID_AA64DFR1_EL1:
1413 case MISCREG_ID_AA64ISAR0_EL1:
1414 case MISCREG_ID_AA64ISAR1_EL1:
1415 case MISCREG_ID_AA64MMFR0_EL1:
1416 case MISCREG_ID_AA64MMFR1_EL1:
1417 case MISCREG_ID_AA64MMFR2_EL1:
1418 case MISCREG_ID_AA64PFR0_EL1:
1419 case MISCREG_ID_AA64PFR1_EL1:
1420 // ID registers are constants.
1421 return;
1422
1423 // TLB Invalidate All
1424 case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
1425 {
1426 assert32();
1427 scr = readMiscReg(MISCREG_SCR);
1428
1429 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1430 tlbiOp(tc);
1431 return;
1432 }
1433 // TLB Invalidate All, Inner Shareable
1434 case MISCREG_TLBIALLIS:
1435 {
1436 assert32();
1437 scr = readMiscReg(MISCREG_SCR);
1438
1439 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1440 tlbiOp.broadcast(tc);
1441 return;
1442 }
1443 // Instruction TLB Invalidate All
1444 case MISCREG_ITLBIALL:
1445 {
1446 assert32();
1447 scr = readMiscReg(MISCREG_SCR);
1448
1449 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1450 tlbiOp(tc);
1451 return;
1452 }
1453 // Data TLB Invalidate All
1454 case MISCREG_DTLBIALL:
1455 {
1456 assert32();
1457 scr = readMiscReg(MISCREG_SCR);
1458
1459 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1460 tlbiOp(tc);
1461 return;
1462 }
1463 // TLB Invalidate by VA
1464 // mcr tlbimval(is) is invalidating all matching entries
1465 // regardless of the level of lookup, since in gem5 we cache
1466 // in the tlb the last level of lookup only.
1467 case MISCREG_TLBIMVA:
1468 case MISCREG_TLBIMVAL:
1469 {
1470 assert32();
1471 scr = readMiscReg(MISCREG_SCR);
1472
1473 TLBIMVA tlbiOp(EL1,
1474 haveSecurity && !scr.ns,
1475 mbits(newVal, 31, 12),
1476 bits(newVal, 7,0));
1477
1478 tlbiOp(tc);
1479 return;
1480 }
1481 // TLB Invalidate by VA, Inner Shareable
1482 case MISCREG_TLBIMVAIS:
1483 case MISCREG_TLBIMVALIS:
1484 {
1485 assert32();
1486 scr = readMiscReg(MISCREG_SCR);
1487
1488 TLBIMVA tlbiOp(EL1,
1489 haveSecurity && !scr.ns,
1490 mbits(newVal, 31, 12),
1491 bits(newVal, 7,0));
1492
1493 tlbiOp.broadcast(tc);
1494 return;
1495 }
1496 // TLB Invalidate by ASID match
1497 case MISCREG_TLBIASID:
1498 {
1499 assert32();
1500 scr = readMiscReg(MISCREG_SCR);
1501
1502 TLBIASID tlbiOp(EL1,
1503 haveSecurity && !scr.ns,
1504 bits(newVal, 7,0));
1505
1506 tlbiOp(tc);
1507 return;
1508 }
1509 // TLB Invalidate by ASID match, Inner Shareable
1510 case MISCREG_TLBIASIDIS:
1511 {
1512 assert32();
1513 scr = readMiscReg(MISCREG_SCR);
1514
1515 TLBIASID tlbiOp(EL1,
1516 haveSecurity && !scr.ns,
1517 bits(newVal, 7,0));
1518
1519 tlbiOp.broadcast(tc);
1520 return;
1521 }
1522 // mcr tlbimvaal(is) is invalidating all matching entries
1523 // regardless of the level of lookup, since in gem5 we cache
1524 // in the tlb the last level of lookup only.
1525 // TLB Invalidate by VA, All ASID
1526 case MISCREG_TLBIMVAA:
1527 case MISCREG_TLBIMVAAL:
1528 {
1529 assert32();
1530 scr = readMiscReg(MISCREG_SCR);
1531
1532 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1533 mbits(newVal, 31,12));
1534
1535 tlbiOp(tc);
1536 return;
1537 }
1538 // TLB Invalidate by VA, All ASID, Inner Shareable
1539 case MISCREG_TLBIMVAAIS:
1540 case MISCREG_TLBIMVAALIS:
1541 {
1542 assert32();
1543 scr = readMiscReg(MISCREG_SCR);
1544
1545 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1546 mbits(newVal, 31,12));
1547
1548 tlbiOp.broadcast(tc);
1549 return;
1550 }
1551 // mcr tlbimvalh(is) is invalidating all matching entries
1552 // regardless of the level of lookup, since in gem5 we cache
1553 // in the tlb the last level of lookup only.
1554 // TLB Invalidate by VA, Hyp mode
1555 case MISCREG_TLBIMVAH:
1556 case MISCREG_TLBIMVALH:
1557 {
1558 assert32();
1559 scr = readMiscReg(MISCREG_SCR);
1560
1561 TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
1562 mbits(newVal, 31,12));
1563
1564 tlbiOp(tc);
1565 return;
1566 }
1567 // TLB Invalidate by VA, Hyp mode, Inner Shareable
1568 case MISCREG_TLBIMVAHIS:
1569 case MISCREG_TLBIMVALHIS:
1570 {
1571 assert32();
1572 scr = readMiscReg(MISCREG_SCR);
1573
1574 TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
1575 mbits(newVal, 31,12));
1576
1577 tlbiOp.broadcast(tc);
1578 return;
1579 }
1580 // mcr tlbiipas2l(is) is invalidating all matching entries
1581 // regardless of the level of lookup, since in gem5 we cache
1582 // in the tlb the last level of lookup only.
1583 // TLB Invalidate by Intermediate Physical Address, Stage 2
1584 case MISCREG_TLBIIPAS2:
1585 case MISCREG_TLBIIPAS2L:
1586 {
1587 assert32();
1588 scr = readMiscReg(MISCREG_SCR);
1589
1590 TLBIIPA tlbiOp(EL1,
1591 haveSecurity && !scr.ns,
1592 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1593
1594 tlbiOp(tc);
1595 return;
1596 }
1597 // TLB Invalidate by Intermediate Physical Address, Stage 2,
1598 // Inner Shareable
1599 case MISCREG_TLBIIPAS2IS:
1600 case MISCREG_TLBIIPAS2LIS:
1601 {
1602 assert32();
1603 scr = readMiscReg(MISCREG_SCR);
1604
1605 TLBIIPA tlbiOp(EL1,
1606 haveSecurity && !scr.ns,
1607 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1608
1609 tlbiOp.broadcast(tc);
1610 return;
1611 }
1612 // Instruction TLB Invalidate by VA
1613 case MISCREG_ITLBIMVA:
1614 {
1615 assert32();
1616 scr = readMiscReg(MISCREG_SCR);
1617
1618 ITLBIMVA tlbiOp(EL1,
1619 haveSecurity && !scr.ns,
1620 mbits(newVal, 31, 12),
1621 bits(newVal, 7,0));
1622
1623 tlbiOp(tc);
1624 return;
1625 }
1626 // Data TLB Invalidate by VA
1627 case MISCREG_DTLBIMVA:
1628 {
1629 assert32();
1630 scr = readMiscReg(MISCREG_SCR);
1631
1632 DTLBIMVA tlbiOp(EL1,
1633 haveSecurity && !scr.ns,
1634 mbits(newVal, 31, 12),
1635 bits(newVal, 7,0));
1636
1637 tlbiOp(tc);
1638 return;
1639 }
1640 // Instruction TLB Invalidate by ASID match
1641 case MISCREG_ITLBIASID:
1642 {
1643 assert32();
1644 scr = readMiscReg(MISCREG_SCR);
1645
1646 ITLBIASID tlbiOp(EL1,
1647 haveSecurity && !scr.ns,
1648 bits(newVal, 7,0));
1649
1650 tlbiOp(tc);
1651 return;
1652 }
1653 // Data TLB Invalidate by ASID match
1654 case MISCREG_DTLBIASID:
1655 {
1656 assert32();
1657 scr = readMiscReg(MISCREG_SCR);
1658
1659 DTLBIASID tlbiOp(EL1,
1660 haveSecurity && !scr.ns,
1661 bits(newVal, 7,0));
1662
1663 tlbiOp(tc);
1664 return;
1665 }
1666 // TLB Invalidate All, Non-Secure Non-Hyp
1667 case MISCREG_TLBIALLNSNH:
1668 {
1669 assert32();
1670
1671 TLBIALLN tlbiOp(EL1);
1672 tlbiOp(tc);
1673 return;
1674 }
1675 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
1676 case MISCREG_TLBIALLNSNHIS:
1677 {
1678 assert32();
1679
1680 TLBIALLN tlbiOp(EL1);
1681 tlbiOp.broadcast(tc);
1682 return;
1683 }
1684 // TLB Invalidate All, Hyp mode
1685 case MISCREG_TLBIALLH:
1686 {
1687 assert32();
1688
1689 TLBIALLN tlbiOp(EL2);
1690 tlbiOp(tc);
1691 return;
1692 }
1693 // TLB Invalidate All, Hyp mode, Inner Shareable
1694 case MISCREG_TLBIALLHIS:
1695 {
1696 assert32();
1697
1698 TLBIALLN tlbiOp(EL2);
1699 tlbiOp.broadcast(tc);
1700 return;
1701 }
1702 // AArch64 TLB Invalidate All, EL3
1703 case MISCREG_TLBI_ALLE3:
1704 {
1705 assert64();
1706
1707 TLBIALLEL tlbiOp(EL3, true);
1708 tlbiOp(tc);
1709 return;
1710 }
1711 // AArch64 TLB Invalidate All, EL3, Inner Shareable
1712 case MISCREG_TLBI_ALLE3IS:
1713 {
1714 assert64();
1715
1716 TLBIALLEL tlbiOp(EL3, true);
1717 tlbiOp.broadcast(tc);
1718 return;
1719 }
1720 // AArch64 TLB Invalidate All, EL2
1721 case MISCREG_TLBI_ALLE2:
1722 {
1723 assert64();
1724 scr = readMiscReg(MISCREG_SCR);
1725
1726 TLBIALLEL tlbiOp(EL2, haveSecurity && !scr.ns);
1727 tlbiOp(tc);
1728 return;
1729 }
1730 // AArch64 TLB Invalidate All, EL2, Inner Shareable
1731 case MISCREG_TLBI_ALLE2IS:
1732 {
1733 assert64();
1734 scr = readMiscReg(MISCREG_SCR);
1735
1736 TLBIALLEL tlbiOp(EL2, haveSecurity && !scr.ns);
1737 tlbiOp.broadcast(tc);
1738 return;
1739 }
1740 // AArch64 TLB Invalidate All, EL1
1741 case MISCREG_TLBI_ALLE1:
1742 {
1743 assert64();
1744 scr = readMiscReg(MISCREG_SCR);
1745
1746 TLBIALLEL tlbiOp(EL1, haveSecurity && !scr.ns);
1747 tlbiOp(tc);
1748 return;
1749 }
1750 // AArch64 TLB Invalidate All, EL1, Inner Shareable
1751 case MISCREG_TLBI_ALLE1IS:
1752 {
1753 assert64();
1754 scr = readMiscReg(MISCREG_SCR);
1755
1756 TLBIALLEL tlbiOp(EL1, haveSecurity && !scr.ns);
1757 tlbiOp.broadcast(tc);
1758 return;
1759 }
1760 case MISCREG_TLBI_VMALLS12E1:
1761 {
1762 assert64();
1763 scr = readMiscReg(MISCREG_SCR);
1764
1765 TLBIVMALL tlbiOp(EL1, haveSecurity && !scr.ns, true);
1766 tlbiOp(tc);
1767 return;
1768 }
1769 case MISCREG_TLBI_VMALLE1:
1770 {
1771 assert64();
1772 scr = readMiscReg(MISCREG_SCR);
1773
1774 HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1775 bool is_host = (hcr.tge && hcr.e2h);
1776 ExceptionLevel target_el = is_host ? EL2 : EL1;
1777 TLBIVMALL tlbiOp(target_el, haveSecurity && !scr.ns, false);
1778 tlbiOp(tc);
1779 return;
1780 }
1781 case MISCREG_TLBI_VMALLS12E1IS:
1782 {
1783 assert64();
1784 scr = readMiscReg(MISCREG_SCR);
1785
1786 TLBIVMALL tlbiOp(EL1, haveSecurity && !scr.ns, true);
1787 tlbiOp.broadcast(tc);
1788 return;
1789 }
1790 case MISCREG_TLBI_VMALLE1IS:
1791 {
1792 assert64();
1793 scr = readMiscReg(MISCREG_SCR);
1794
1795 HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1796 bool is_host = (hcr.tge && hcr.e2h);
1797 ExceptionLevel target_el = is_host ? EL2 : EL1;
1798 TLBIVMALL tlbiOp(target_el, haveSecurity && !scr.ns, false);
1799 tlbiOp.broadcast(tc);
1800 return;
1801 }
1802 // VAEx(IS) and VALEx(IS) are the same because TLBs
1803 // only store entries
1804 // from the last level of translation table walks
1805 // AArch64 TLB Invalidate by VA, EL3
1806 case MISCREG_TLBI_VAE3_Xt:
1807 case MISCREG_TLBI_VALE3_Xt:
1808 {
1809 assert64();
1810
1811 TLBIMVA tlbiOp(EL3, true,
1812 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1813 0xbeef);
1814 tlbiOp(tc);
1815 return;
1816 }
1817 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable
1818 case MISCREG_TLBI_VAE3IS_Xt:
1819 case MISCREG_TLBI_VALE3IS_Xt:
1820 {
1821 assert64();
1822
1823 TLBIMVA tlbiOp(EL3, true,
1824 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1825 0xbeef);
1826
1827 tlbiOp.broadcast(tc);
1828 return;
1829 }
1830 // AArch64 TLB Invalidate by VA, EL2
1831 case MISCREG_TLBI_VAE2_Xt:
1832 case MISCREG_TLBI_VALE2_Xt:
1833 {
1834 assert64();
1835 scr = readMiscReg(MISCREG_SCR);
1836
1837 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1838 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1839 0xbeef);
1840 tlbiOp(tc);
1841 return;
1842 }
1843 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable
1844 case MISCREG_TLBI_VAE2IS_Xt:
1845 case MISCREG_TLBI_VALE2IS_Xt:
1846 {
1847 assert64();
1848 scr = readMiscReg(MISCREG_SCR);
1849
1850 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1851 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1852 0xbeef);
1853
1854 tlbiOp.broadcast(tc);
1855 return;
1856 }
1857 // AArch64 TLB Invalidate by VA, EL1
1858 case MISCREG_TLBI_VAE1_Xt:
1859 case MISCREG_TLBI_VALE1_Xt:
1860 {
1861 assert64();
1862 scr = readMiscReg(MISCREG_SCR);
1863 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1864 bits(newVal, 55, 48);
1865
1866 HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1867 bool is_host = (hcr.tge && hcr.e2h);
1868 ExceptionLevel target_el = is_host ? EL2 : EL1;
1869 TLBIMVA tlbiOp(target_el, haveSecurity && !scr.ns,
1870 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1871 asid);
1872
1873 tlbiOp(tc);
1874 return;
1875 }
1876 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable
1877 case MISCREG_TLBI_VAE1IS_Xt:
1878 case MISCREG_TLBI_VALE1IS_Xt:
1879 {
1880 assert64();
1881 scr = readMiscReg(MISCREG_SCR);
1882 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1883 bits(newVal, 55, 48);
1884
1885 HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1886 bool is_host = (hcr.tge && hcr.e2h);
1887 ExceptionLevel target_el = is_host ? EL2 : EL1;
1888 TLBIMVA tlbiOp(target_el, haveSecurity && !scr.ns,
1889 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1890 asid);
1891
1892 tlbiOp.broadcast(tc);
1893 return;
1894 }
1895 // AArch64 TLB Invalidate by ASID, EL1
1896 case MISCREG_TLBI_ASIDE1_Xt:
1897 {
1898 assert64();
1899 scr = readMiscReg(MISCREG_SCR);
1900 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1901 bits(newVal, 55, 48);
1902
1903 HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1904 bool is_host = (hcr.tge && hcr.e2h);
1905 ExceptionLevel target_el = is_host ? EL2 : EL1;
1906 TLBIASID tlbiOp(target_el, haveSecurity && !scr.ns, asid);
1907 tlbiOp(tc);
1908 return;
1909 }
1910 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable
1911 case MISCREG_TLBI_ASIDE1IS_Xt:
1912 {
1913 assert64();
1914 scr = readMiscReg(MISCREG_SCR);
1915 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1916 bits(newVal, 55, 48);
1917
1918 HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1919 bool is_host = (hcr.tge && hcr.e2h);
1920 ExceptionLevel target_el = is_host ? EL2 : EL1;
1921 TLBIASID tlbiOp(target_el, haveSecurity && !scr.ns, asid);
1922 tlbiOp.broadcast(tc);
1923 return;
1924 }
1925 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1926 // entries from the last level of translation table walks
1927 // AArch64 TLB Invalidate by VA, All ASID, EL1
1928 case MISCREG_TLBI_VAAE1_Xt:
1929 case MISCREG_TLBI_VAALE1_Xt:
1930 {
1931 assert64();
1932 scr = readMiscReg(MISCREG_SCR);
1933
1934 HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1935 bool is_host = (hcr.tge && hcr.e2h);
1936 ExceptionLevel target_el = is_host ? EL2 : EL1;
1937 TLBIMVAA tlbiOp(target_el, haveSecurity && !scr.ns,
1938 static_cast<Addr>(bits(newVal, 43, 0)) << 12);
1939
1940 tlbiOp(tc);
1941 return;
1942 }
1943 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable
1944 case MISCREG_TLBI_VAAE1IS_Xt:
1945 case MISCREG_TLBI_VAALE1IS_Xt:
1946 {
1947 assert64();
1948 scr = readMiscReg(MISCREG_SCR);
1949
1950 HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1951 bool is_host = (hcr.tge && hcr.e2h);
1952 ExceptionLevel target_el = is_host ? EL2 : EL1;
1953 TLBIMVAA tlbiOp(target_el, haveSecurity && !scr.ns,
1954 static_cast<Addr>(bits(newVal, 43, 0)) << 12);
1955
1956 tlbiOp.broadcast(tc);
1957 return;
1958 }
1959 // AArch64 TLB Invalidate by Intermediate Physical Address,
1960 // Stage 2, EL1
1961 case MISCREG_TLBI_IPAS2E1_Xt:
1962 case MISCREG_TLBI_IPAS2LE1_Xt:
1963 {
1964 assert64();
1965 scr = readMiscReg(MISCREG_SCR);
1966
1967 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
1968 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1969
1970 tlbiOp(tc);
1971 return;
1972 }
1973 // AArch64 TLB Invalidate by Intermediate Physical Address,
1974 // Stage 2, EL1, Inner Shareable
1975 case MISCREG_TLBI_IPAS2E1IS_Xt:
1976 case MISCREG_TLBI_IPAS2LE1IS_Xt:
1977 {
1978 assert64();
1979 scr = readMiscReg(MISCREG_SCR);
1980
1981 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
1982 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1983
1984 tlbiOp.broadcast(tc);
1985 return;
1986 }
1987 case MISCREG_ACTLR:
1988 warn("Not doing anything for write of miscreg ACTLR\n");
1989 break;
1990
1991 case MISCREG_PMXEVTYPER_PMCCFILTR:
1992 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
1993 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
1994 case MISCREG_PMCR ... MISCREG_PMOVSSET:
1995 pmu->setMiscReg(misc_reg, newVal);
1996 break;
1997
1998
1999 case MISCREG_HSTR: // TJDBX, now redifined to be RES0
2000 {
2001 HSTR hstrMask = 0;
2002 hstrMask.tjdbx = 1;
2003 newVal &= ~((uint32_t) hstrMask);
2004 break;
2005 }
2006 case MISCREG_HCPTR:
2007 {
2008 // If a CP bit in NSACR is 0 then the corresponding bit in
2009 // HCPTR is RAO/WI. Same applies to NSASEDIS
2010 secure_lookup = haveSecurity && isSecure(tc);
2011 if (!secure_lookup) {
2012 RegVal oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
2013 RegVal mask =
2014 (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
2015 newVal = (newVal & ~mask) | (oldValue & mask);
2016 }
2017 break;
2018 }
2019 case MISCREG_HDFAR: // alias for secure DFAR
2020 misc_reg = MISCREG_DFAR_S;
2021 break;
2022 case MISCREG_HIFAR: // alias for secure IFAR
2023 misc_reg = MISCREG_IFAR_S;
2024 break;
2025 case MISCREG_ATS1CPR:
2026 addressTranslation(TLB::S1CTran, BaseTLB::Read, 0, val);
2027 return;
2028 case MISCREG_ATS1CPW:
2029 addressTranslation(TLB::S1CTran, BaseTLB::Write, 0, val);
2030 return;
2031 case MISCREG_ATS1CUR:
2032 addressTranslation(TLB::S1CTran, BaseTLB::Read,
2033 TLB::UserMode, val);
2034 return;
2035 case MISCREG_ATS1CUW:
2036 addressTranslation(TLB::S1CTran, BaseTLB::Write,
2037 TLB::UserMode, val);
2038 return;
2039 case MISCREG_ATS12NSOPR:
2040 if (!haveSecurity)
2041 panic("Security Extensions required for ATS12NSOPR");
2042 addressTranslation(TLB::S1S2NsTran, BaseTLB::Read, 0, val);
2043 return;
2044 case MISCREG_ATS12NSOPW:
2045 if (!haveSecurity)
2046 panic("Security Extensions required for ATS12NSOPW");
2047 addressTranslation(TLB::S1S2NsTran, BaseTLB::Write, 0, val);
2048 return;
2049 case MISCREG_ATS12NSOUR:
2050 if (!haveSecurity)
2051 panic("Security Extensions required for ATS12NSOUR");
2052 addressTranslation(TLB::S1S2NsTran, BaseTLB::Read,
2053 TLB::UserMode, val);
2054 return;
2055 case MISCREG_ATS12NSOUW:
2056 if (!haveSecurity)
2057 panic("Security Extensions required for ATS12NSOUW");
2058 addressTranslation(TLB::S1S2NsTran, BaseTLB::Write,
2059 TLB::UserMode, val);
2060 return;
2061 case MISCREG_ATS1HR:
2062 addressTranslation(TLB::HypMode, BaseTLB::Read, 0, val);
2063 return;
2064 case MISCREG_ATS1HW:
2065 addressTranslation(TLB::HypMode, BaseTLB::Write, 0, val);
2066 return;
2067 case MISCREG_TTBCR:
2068 {
2069 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
2070 const uint32_t ones = (uint32_t)(-1);
2071 TTBCR ttbcrMask = 0;
2072 TTBCR ttbcrNew = newVal;
2073
2074 // ARM DDI 0406C.b, ARMv7-32
2075 ttbcrMask.n = ones; // T0SZ
2076 if (haveSecurity) {
2077 ttbcrMask.pd0 = ones;
2078 ttbcrMask.pd1 = ones;
2079 }
2080 ttbcrMask.epd0 = ones;
2081 ttbcrMask.irgn0 = ones;
2082 ttbcrMask.orgn0 = ones;
2083 ttbcrMask.sh0 = ones;
2084 ttbcrMask.ps = ones; // T1SZ
2085 ttbcrMask.a1 = ones;
2086 ttbcrMask.epd1 = ones;
2087 ttbcrMask.irgn1 = ones;
2088 ttbcrMask.orgn1 = ones;
2089 ttbcrMask.sh1 = ones;
2090 if (haveLPAE)
2091 ttbcrMask.eae = ones;
2092
2093 if (haveLPAE && ttbcrNew.eae) {
2094 newVal = newVal & ttbcrMask;
2095 } else {
2096 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
2097 }
2098 // Invalidate TLB MiscReg
2099 getMMUPtr(tc)->invalidateMiscReg();
2100 break;
2101 }
2102 case MISCREG_TTBR0:
2103 case MISCREG_TTBR1:
2104 {
2105 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
2106 if (haveLPAE) {
2107 if (ttbcr.eae) {
2108 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
2109 // ARMv8 AArch32 bit 63-56 only
2110 uint64_t ttbrMask = mask(63,56) | mask(47,40);
2111 newVal = (newVal & (~ttbrMask));
2112 }
2113 }
2114 // Invalidate TLB MiscReg
2115 getMMUPtr(tc)->invalidateMiscReg();
2116 break;
2117 }
2118 case MISCREG_SCTLR_EL1:
2119 case MISCREG_CONTEXTIDR:
2120 case MISCREG_PRRR:
2121 case MISCREG_NMRR:
2122 case MISCREG_MAIR0:
2123 case MISCREG_MAIR1:
2124 case MISCREG_DACR:
2125 case MISCREG_VTTBR:
2126 case MISCREG_SCR_EL3:
2127 case MISCREG_TCR_EL1:
2128 case MISCREG_TCR_EL2:
2129 case MISCREG_TCR_EL3:
2130 case MISCREG_SCTLR_EL2:
2131 case MISCREG_SCTLR_EL3:
2132 case MISCREG_HSCTLR:
2133 case MISCREG_TTBR0_EL1:
2134 case MISCREG_TTBR1_EL1:
2135 case MISCREG_TTBR0_EL2:
2136 case MISCREG_TTBR1_EL2:
2137 case MISCREG_TTBR0_EL3:
2138 getMMUPtr(tc)->invalidateMiscReg();
2139 break;
2140 case MISCREG_HCR_EL2:
2141 {
2142 const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
2143 selfDebug->setenableTDETGE((HCR)val, mdcr);
2144 getMMUPtr(tc)->invalidateMiscReg();
2145 }
2146 break;
2147 case MISCREG_NZCV:
2148 {
2149 CPSR cpsr = val;
2150
2151 tc->setCCReg(CCREG_NZ, cpsr.nz);
2152 tc->setCCReg(CCREG_C, cpsr.c);
2153 tc->setCCReg(CCREG_V, cpsr.v);
2154 }
2155 break;
2156 case MISCREG_DAIF:
2157 {
2158 CPSR cpsr = miscRegs[MISCREG_CPSR];
2159 cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
2160 newVal = cpsr;
2161 misc_reg = MISCREG_CPSR;
2162 }
2163 break;
2164 case MISCREG_SP_EL0:
2165 tc->setIntReg(INTREG_SP0, newVal);
2166 break;
2167 case MISCREG_SP_EL1:
2168 tc->setIntReg(INTREG_SP1, newVal);
2169 break;
2170 case MISCREG_SP_EL2:
2171 tc->setIntReg(INTREG_SP2, newVal);
2172 break;
2173 case MISCREG_SPSEL:
2174 {
2175 CPSR cpsr = miscRegs[MISCREG_CPSR];
2176 cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
2177 newVal = cpsr;
2178 misc_reg = MISCREG_CPSR;
2179 }
2180 break;
2181 case MISCREG_CURRENTEL:
2182 {
2183 CPSR cpsr = miscRegs[MISCREG_CPSR];
2184 cpsr.el = (uint8_t) ((CPSR) newVal).el;
2185 newVal = cpsr;
2186 misc_reg = MISCREG_CPSR;
2187 }
2188 break;
2189 case MISCREG_PAN:
2190 {
2191 // PAN is affecting data accesses
2192 getMMUPtr(tc)->invalidateMiscReg(MMU::D_TLBS);
2193
2194 CPSR cpsr = miscRegs[MISCREG_CPSR];
2195 cpsr.pan = (uint8_t) ((CPSR) newVal).pan;
2196 newVal = cpsr;
2197 misc_reg = MISCREG_CPSR;
2198 }
2199 break;
2200 case MISCREG_AT_S1E1R_Xt:
2201 addressTranslation64(TLB::S1E1Tran, BaseTLB::Read, 0, val);
2202 return;
2203 case MISCREG_AT_S1E1W_Xt:
2204 addressTranslation64(TLB::S1E1Tran, BaseTLB::Write, 0, val);
2205 return;
2206 case MISCREG_AT_S1E0R_Xt:
2207 addressTranslation64(TLB::S1E0Tran, BaseTLB::Read,
2208 TLB::UserMode, val);
2209 return;
2210 case MISCREG_AT_S1E0W_Xt:
2211 addressTranslation64(TLB::S1E0Tran, BaseTLB::Write,
2212 TLB::UserMode, val);
2213 return;
2214 case MISCREG_AT_S1E2R_Xt:
2215 addressTranslation64(TLB::S1E2Tran, BaseTLB::Read, 0, val);
2216 return;
2217 case MISCREG_AT_S1E2W_Xt:
2218 addressTranslation64(TLB::S1E2Tran, BaseTLB::Write, 0, val);
2219 return;
2220 case MISCREG_AT_S12E1R_Xt:
2221 addressTranslation64(TLB::S12E1Tran, BaseTLB::Read, 0, val);
2222 return;
2223 case MISCREG_AT_S12E1W_Xt:
2224 addressTranslation64(TLB::S12E1Tran, BaseTLB::Write, 0, val);
2225 return;
2226 case MISCREG_AT_S12E0R_Xt:
2227 addressTranslation64(TLB::S12E0Tran, BaseTLB::Read,
2228 TLB::UserMode, val);
2229 return;
2230 case MISCREG_AT_S12E0W_Xt:
2231 addressTranslation64(TLB::S12E0Tran, BaseTLB::Write,
2232 TLB::UserMode, val);
2233 return;
2234 case MISCREG_AT_S1E3R_Xt:
2235 addressTranslation64(TLB::S1E3Tran, BaseTLB::Read, 0, val);
2236 return;
2237 case MISCREG_AT_S1E3W_Xt:
2238 addressTranslation64(TLB::S1E3Tran, BaseTLB::Write, 0, val);
2239 return;
2240 case MISCREG_SPSR_EL3:
2241 case MISCREG_SPSR_EL2:
2242 case MISCREG_SPSR_EL1:
2243 {
2244 RegVal spsr_mask = havePAN ?
2245 ~(0x2 << 22) : ~(0x3 << 22);
2246
2247 newVal = val & spsr_mask;
2248 break;
2249 }
2250 case MISCREG_L2CTLR:
2251 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
2252 miscRegName[misc_reg], uint32_t(val));
2253 break;
2254
2255 // Generic Timer registers
2256 case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
2257 case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
2258 getGenericTimer().setMiscReg(misc_reg, newVal);
2259 break;
2260 case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15:
2261 case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
2262 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
2263 getGICv3CPUInterface().setMiscReg(misc_reg, newVal);
2264 return;
2265 case MISCREG_ZCR_EL3:
2266 case MISCREG_ZCR_EL2:
2267 case MISCREG_ZCR_EL1:
2268 tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits() >> 7) - 1);
2269 break;
2270 }
2271 }
2272 setMiscRegNoEffect(misc_reg, newVal);
2273 }
2274
2275 BaseISADevice &
2276 ISA::getGenericTimer()
2277 {
2278 // We only need to create an ISA interface the first time we try
2279 // to access the timer.
2280 if (timer)
2281 return *timer.get();
2282
2283 assert(system);
2284 GenericTimer *generic_timer(system->getGenericTimer());
2285 if (!generic_timer) {
2286 panic("Trying to get a generic timer from a system that hasn't "
2287 "been configured to use a generic timer.\n");
2288 }
2289
2290 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
2291 timer->setThreadContext(tc);
2292
2293 return *timer.get();
2294 }
2295
2296 BaseISADevice &
2297 ISA::getGICv3CPUInterface()
2298 {
2299 panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!");
2300 return *gicv3CpuInterface.get();
2301 }
2302
2303 unsigned
2304 ISA::getCurSveVecLenInBits() const
2305 {
2306 if (!FullSystem) {
2307 return sveVL * 128;
2308 }
2309
2310 panic_if(!tc,
2311 "A ThreadContext is needed to determine the SVE vector length "
2312 "in full-system mode");
2313
2314 CPSR cpsr = miscRegs[MISCREG_CPSR];
2315 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
2316
2317 unsigned len = 0;
2318
2319 if (el == EL1 || (el == EL0 && !ELIsInHost(tc, el))) {
2320 len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL1]).len;
2321 }
2322
2323 if (el == EL2 || (el == EL0 && ELIsInHost(tc, el))) {
2324 len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len;
2325 } else if (haveVirtualization && !isSecure(tc) &&
2326 (el == EL0 || el == EL1)) {
2327 len = std::min(
2328 len,
2329 static_cast<unsigned>(
2330 static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len));
2331 }
2332
2333 if (el == EL3) {
2334 len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len;
2335 } else if (haveSecurity) {
2336 len = std::min(
2337 len,
2338 static_cast<unsigned>(
2339 static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len));
2340 }
2341
2342 len = std::min(len, sveVL - 1);
2343
2344 return (len + 1) * 128;
2345 }
2346
2347 void
2348 ISA::zeroSveVecRegUpperPart(VecRegContainer &vc, unsigned eCount)
2349 {
2350 auto vv = vc.as<uint64_t>();
2351 for (int i = 2; i < eCount; ++i) {
2352 vv[i] = 0;
2353 }
2354 }
2355
2356 void
2357 ISA::serialize(CheckpointOut &cp) const
2358 {
2359 DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
2360 SERIALIZE_MAPPING(miscRegs, miscRegName, NUM_PHYS_MISCREGS);
2361 }
2362
2363 void
2364 ISA::unserialize(CheckpointIn &cp)
2365 {
2366 DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
2367 UNSERIALIZE_MAPPING(miscRegs, miscRegName, NUM_PHYS_MISCREGS);
2368 CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
2369 updateRegMap(tmp_cpsr);
2370 }
2371
2372 void
2373 ISA::addressTranslation64(TLB::ArmTranslationType tran_type,
2374 BaseTLB::Mode mode, Request::Flags flags, RegVal val)
2375 {
2376 // If we're in timing mode then doing the translation in
2377 // functional mode then we're slightly distorting performance
2378 // results obtained from simulations. The translation should be
2379 // done in the same mode the core is running in. NOTE: This
2380 // can't be an atomic translation because that causes problems
2381 // with unexpected atomic snoop requests.
2382 warn_once("Doing AT (address translation) in functional mode! Fix Me!\n");
2383
2384 auto req = std::make_shared<Request>(
2385 val, 0, flags, Request::funcRequestorId,
2386 tc->pcState().pc(), tc->contextId());
2387
2388 Fault fault = getMMUPtr(tc)->translateFunctional(
2389 req, tc, mode, tran_type);
2390
2391 PAR par = 0;
2392 if (fault == NoFault) {
2393 Addr paddr = req->getPaddr();
2394 uint64_t attr = getMMUPtr(tc)->getAttr();
2395 uint64_t attr1 = attr >> 56;
2396 if (!attr1 || attr1 ==0x44) {
2397 attr |= 0x100;
2398 attr &= ~ uint64_t(0x80);
2399 }
2400 par = (paddr & mask(47, 12)) | attr;
2401 DPRINTF(MiscRegs,
2402 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
2403 val, par);
2404 } else {
2405 ArmFault *arm_fault = static_cast<ArmFault *>(fault.get());
2406 arm_fault->update(tc);
2407 // Set fault bit and FSR
2408 FSR fsr = arm_fault->getFsr(tc);
2409
2410 par.f = 1; // F bit
2411 par.fst = fsr.status; // FST
2412 par.ptw = (arm_fault->iss() >> 7) & 0x1; // S1PTW
2413 par.s = arm_fault->isStage2() ? 1 : 0; // S
2414
2415 DPRINTF(MiscRegs,
2416 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
2417 val, fsr, par);
2418 }
2419 setMiscRegNoEffect(MISCREG_PAR_EL1, par);
2420 return;
2421 }
2422
2423 void
2424 ISA::addressTranslation(TLB::ArmTranslationType tran_type,
2425 BaseTLB::Mode mode, Request::Flags flags, RegVal val)
2426 {
2427 // If we're in timing mode then doing the translation in
2428 // functional mode then we're slightly distorting performance
2429 // results obtained from simulations. The translation should be
2430 // done in the same mode the core is running in. NOTE: This
2431 // can't be an atomic translation because that causes problems
2432 // with unexpected atomic snoop requests.
2433 warn_once("Doing AT (address translation) in functional mode! Fix Me!\n");
2434
2435 auto req = std::make_shared<Request>(
2436 val, 0, flags, Request::funcRequestorId,
2437 tc->pcState().pc(), tc->contextId());
2438
2439 Fault fault = getMMUPtr(tc)->translateFunctional(
2440 req, tc, mode, tran_type);
2441
2442 PAR par = 0;
2443 if (fault == NoFault) {
2444 Addr paddr = req->getPaddr();
2445 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
2446 HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
2447
2448 uint8_t max_paddr_bit = 0;
2449 if (haveLPAE && (ttbcr.eae || tran_type & TLB::HypMode ||
2450 ((tran_type & TLB::S1S2NsTran) && hcr.vm) )) {
2451
2452 max_paddr_bit = 39;
2453 } else {
2454 max_paddr_bit = 31;
2455 }
2456
2457 par = (paddr & mask(max_paddr_bit, 12)) |
2458 (getMMUPtr(tc)->getAttr());
2459
2460 DPRINTF(MiscRegs,
2461 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
2462 val, par);
2463 } else {
2464 ArmFault *arm_fault = static_cast<ArmFault *>(fault.get());
2465 arm_fault->update(tc);
2466 // Set fault bit and FSR
2467 FSR fsr = arm_fault->getFsr(tc);
2468
2469 par.f = 0x1; // F bit
2470 par.lpae = fsr.lpae;
2471 par.ptw = (arm_fault->iss() >> 7) & 0x1;
2472 par.s = arm_fault->isStage2() ? 1 : 0;
2473
2474 if (par.lpae) {
2475 // LPAE - rearange fault status
2476 par.fst = fsr.status;
2477 } else {
2478 // VMSA - rearange fault status
2479 par.fs4_0 = fsr.fsLow | (fsr.fsHigh << 5);
2480 par.fs5 = fsr.ext;
2481 }
2482 DPRINTF(MiscRegs,
2483 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
2484 val, fsr, par);
2485 }
2486 setMiscRegNoEffect(MISCREG_PAR, par);
2487 return;
2488 }
2489
2490 ISA::MiscRegLUTEntryInitializer::chain
2491 ISA::MiscRegLUTEntryInitializer::highest(ArmSystem *const sys) const
2492 {
2493 switch (FullSystem ? sys->highestEL() : EL1) {
2494 case EL0:
2495 case EL1: priv(); break;
2496 case EL2: hyp(); break;
2497 case EL3: mon(); break;
2498 }
2499 return *this;
2500 }
2501
2502 } // namespace ArmISA