2 * Copyright (c) 2010-2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
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23 * this software without specific prior written permission.
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 #include "arch/arm/isa.hh"
42 #include "cpu/checker/cpu.hh"
43 #include "debug/Arm.hh"
44 #include "debug/MiscRegs.hh"
45 #include "sim/faults.hh"
46 #include "sim/stat_control.hh"
47 #include "sim/system.hh"
55 SCTLR sctlr_rst
= miscRegs
[MISCREG_SCTLR_RST
];
56 uint32_t midr
= miscRegs
[MISCREG_MIDR
];
57 memset(miscRegs
, 0, sizeof(miscRegs
));
59 cpsr
.mode
= MODE_USER
;
60 miscRegs
[MISCREG_CPSR
] = cpsr
;
64 sctlr
.te
= (bool)sctlr_rst
.te
;
65 sctlr
.nmfi
= (bool)sctlr_rst
.nmfi
;
66 sctlr
.v
= (bool)sctlr_rst
.v
;
72 miscRegs
[MISCREG_SCTLR
] = sctlr
;
73 miscRegs
[MISCREG_SCTLR_RST
] = sctlr_rst
;
75 // Preserve MIDR accross reset
76 miscRegs
[MISCREG_MIDR
] = midr
;
78 /* Start with an event in the mailbox */
79 miscRegs
[MISCREG_SEV_MAILBOX
] = 1;
81 // Separate Instruction and Data TLBs.
82 miscRegs
[MISCREG_TLBTR
] = 1;
85 mvfr0
.advSimdRegisters
= 2;
86 mvfr0
.singlePrecision
= 2;
87 mvfr0
.doublePrecision
= 2;
88 mvfr0
.vfpExceptionTrapping
= 0;
91 mvfr0
.shortVectors
= 1;
92 mvfr0
.roundingModes
= 1;
93 miscRegs
[MISCREG_MVFR0
] = mvfr0
;
96 mvfr1
.flushToZero
= 1;
98 mvfr1
.advSimdLoadStore
= 1;
99 mvfr1
.advSimdInteger
= 1;
100 mvfr1
.advSimdSinglePrecision
= 1;
101 mvfr1
.advSimdHalfPrecision
= 1;
102 mvfr1
.vfpHalfPrecision
= 1;
103 miscRegs
[MISCREG_MVFR1
] = mvfr1
;
105 miscRegs
[MISCREG_MPIDR
] = 0;
107 // Reset values of PRRR and NMRR are implementation dependent
109 miscRegs
[MISCREG_PRRR
] =
122 miscRegs
[MISCREG_NMRR
] =
139 miscRegs
[MISCREG_CPACR
] = 0;
140 miscRegs
[MISCREG_FPSID
] = 0x410430A0;
142 // See section B4.1.84 of ARM ARM
143 // All values are latest for ARMv7-A profile
144 miscRegs
[MISCREG_ID_ISAR0
] = 0x02101111;
145 miscRegs
[MISCREG_ID_ISAR1
] = 0x02112111;
146 miscRegs
[MISCREG_ID_ISAR2
] = 0x21232141;
147 miscRegs
[MISCREG_ID_ISAR3
] = 0x01112131;
148 miscRegs
[MISCREG_ID_ISAR4
] = 0x10010142;
149 miscRegs
[MISCREG_ID_ISAR5
] = 0x00000000;
151 //XXX We need to initialize the rest of the state.
155 ISA::readMiscRegNoEffect(int misc_reg
)
157 assert(misc_reg
< NumMiscRegs
);
160 if (misc_reg
== MISCREG_SPSR
)
161 flat_idx
= flattenMiscIndex(misc_reg
);
164 MiscReg val
= miscRegs
[flat_idx
];
166 DPRINTF(MiscRegs
, "Reading From misc reg %d (%d) : %#x\n",
167 misc_reg
, flat_idx
, val
);
173 ISA::readMiscReg(int misc_reg
, ThreadContext
*tc
)
175 if (misc_reg
== MISCREG_CPSR
) {
176 CPSR cpsr
= miscRegs
[misc_reg
];
177 PCState pc
= tc
->pcState();
178 cpsr
.j
= pc
.jazelle() ? 1 : 0;
179 cpsr
.t
= pc
.thumb() ? 1 : 0;
182 if (misc_reg
>= MISCREG_CP15_UNIMP_START
)
183 panic("Unimplemented CP15 register %s read.\n",
184 miscRegName
[misc_reg
]);
189 return 0x80000000 | // multiprocessor extensions available
192 case MISCREG_ID_MMFR0
:
193 return 0x03; // VMSAv7 support
194 case MISCREG_ID_MMFR2
:
195 return 0x01230000; // no HW access | WFI stalling | ISB and DSB
196 // | all TLB maintenance | no Harvard
197 case MISCREG_ID_MMFR3
:
198 return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint |
199 // BP Maint | Cache Maint Set/way | Cache Maint MVA
201 warn_once("The clidr register always reports 0 caches.\n");
202 warn_once("clidr LoUIS field of 0b001 to match current "
203 "ARM implementations.\n");
206 warn_once("The ccsidr register isn't implemented and "
207 "always reads as 0.\n");
209 case MISCREG_ID_PFR0
:
210 warn("Returning thumbEE disabled for now since we don't support CP14"
211 "config registers and jumping to ThumbEE vectors\n");
212 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
213 case MISCREG_ID_PFR1
:
214 return 0x00001; // !Timer | !Virti | !M Profile | !TrustZone | ARMv4
216 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
218 warn("Not doing anything for miscreg ACTLR\n");
221 case MISCREG_PMCCNTR
:
223 warn("Not doing anything for read to miscreg %s\n",
224 miscRegName
[misc_reg
]);
227 panic("shouldn't be reading this register seperately\n");
228 case MISCREG_FPSCR_QC
:
229 return readMiscRegNoEffect(MISCREG_FPSCR
) & ~FpscrQcMask
;
230 case MISCREG_FPSCR_EXC
:
231 return readMiscRegNoEffect(MISCREG_FPSCR
) & ~FpscrExcMask
;
234 // mostly unimplemented, just set NumCPUs field from sim and return
236 // b00:1CPU to b11:4CPUs
237 l2ctlr
.numCPUs
= tc
->getSystemPtr()->numContexts() - 1;
240 case MISCREG_DBGDIDR
:
241 /* For now just implement the version number.
242 * Return 0 as we don't support debug architecture yet.
245 case MISCREG_DBGDSCR_INT
:
248 return readMiscRegNoEffect(misc_reg
);
252 ISA::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
)
254 assert(misc_reg
< NumMiscRegs
);
257 if (misc_reg
== MISCREG_SPSR
)
258 flat_idx
= flattenMiscIndex(misc_reg
);
261 miscRegs
[flat_idx
] = val
;
263 DPRINTF(MiscRegs
, "Writing to misc reg %d (%d) : %#x\n", misc_reg
,
268 ISA::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadContext
*tc
)
271 MiscReg newVal
= val
;
276 if (misc_reg
== MISCREG_CPSR
) {
280 CPSR old_cpsr
= miscRegs
[MISCREG_CPSR
];
281 int old_mode
= old_cpsr
.mode
;
283 if (old_mode
!= cpsr
.mode
) {
284 tc
->getITBPtr()->invalidateMiscReg();
285 tc
->getDTBPtr()->invalidateMiscReg();
288 DPRINTF(Arm
, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
289 miscRegs
[misc_reg
], cpsr
, cpsr
.f
, cpsr
.i
, cpsr
.a
, cpsr
.mode
);
290 PCState pc
= tc
->pcState();
291 pc
.nextThumb(cpsr
.t
);
292 pc
.nextJazelle(cpsr
.j
);
294 // Follow slightly different semantics if a CheckerCPU object
296 CheckerCPU
*checker
= tc
->getCheckerCpuPtr();
298 tc
->pcStateNoRecord(pc
);
302 } else if (misc_reg
>= MISCREG_CP15_UNIMP_START
&&
303 misc_reg
< MISCREG_CP15_END
) {
304 panic("Unimplemented CP15 register %s wrote with %#x.\n",
305 miscRegName
[misc_reg
], val
);
311 const uint32_t ones
= (uint32_t)(-1);
313 // Only cp10, cp11, and ase are implemented, nothing else should
315 cpacrMask
.cp10
= ones
;
316 cpacrMask
.cp11
= ones
;
317 cpacrMask
.asedis
= ones
;
319 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
320 miscRegName
[misc_reg
], newVal
);
324 warn_once("The csselr register isn't implemented.\n");
328 const uint32_t ones
= (uint32_t)(-1);
330 fpscrMask
.ioc
= ones
;
331 fpscrMask
.dzc
= ones
;
332 fpscrMask
.ofc
= ones
;
333 fpscrMask
.ufc
= ones
;
334 fpscrMask
.ixc
= ones
;
335 fpscrMask
.idc
= ones
;
336 fpscrMask
.len
= ones
;
337 fpscrMask
.stride
= ones
;
338 fpscrMask
.rMode
= ones
;
341 fpscrMask
.ahp
= ones
;
347 newVal
= (newVal
& (uint32_t)fpscrMask
) |
348 (miscRegs
[MISCREG_FPSCR
] & ~(uint32_t)fpscrMask
);
353 assert(!(newVal
& ~CpsrMaskQ
));
354 newVal
= miscRegs
[MISCREG_CPSR
] | newVal
;
355 misc_reg
= MISCREG_CPSR
;
358 case MISCREG_FPSCR_QC
:
360 newVal
= miscRegs
[MISCREG_FPSCR
] | (newVal
& FpscrQcMask
);
361 misc_reg
= MISCREG_FPSCR
;
364 case MISCREG_FPSCR_EXC
:
366 newVal
= miscRegs
[MISCREG_FPSCR
] | (newVal
& FpscrExcMask
);
367 misc_reg
= MISCREG_FPSCR
;
372 // vfpv3 architecture, section B.6.1 of DDI04068
373 // bit 29 - valid only if fpexc[31] is 0
374 const uint32_t fpexcMask
= 0x60000000;
375 newVal
= (newVal
& fpexcMask
) |
376 (miscRegs
[MISCREG_FPEXC
] & ~fpexcMask
);
381 DPRINTF(MiscRegs
, "Writing SCTLR: %#x\n", newVal
);
382 SCTLR sctlr
= miscRegs
[MISCREG_SCTLR
];
383 SCTLR new_sctlr
= newVal
;
384 new_sctlr
.nmfi
= (bool)sctlr
.nmfi
;
385 miscRegs
[MISCREG_SCTLR
] = (MiscReg
)new_sctlr
;
386 tc
->getITBPtr()->invalidateMiscReg();
387 tc
->getDTBPtr()->invalidateMiscReg();
389 // Check if all CPUs are booted with caches enabled
390 // so we can stop enforcing coherency of some kernel
391 // structures manually.
392 sys
= tc
->getSystemPtr();
393 for (x
= 0; x
< sys
->numContexts(); x
++) {
394 oc
= sys
->getThreadContext(x
);
395 SCTLR other_sctlr
= oc
->readMiscRegNoEffect(MISCREG_SCTLR
);
396 if (!other_sctlr
.c
&& oc
->status() != ThreadContext::Halted
)
400 for (x
= 0; x
< sys
->numContexts(); x
++) {
401 oc
= sys
->getThreadContext(x
);
402 oc
->getDTBPtr()->allCpusCaching();
403 oc
->getITBPtr()->allCpusCaching();
405 // If CheckerCPU is connected, need to notify it.
406 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
408 checker
->getDTBPtr()->allCpusCaching();
409 checker
->getITBPtr()->allCpusCaching();
420 case MISCREG_TLBIALLIS
:
421 case MISCREG_TLBIALL
:
422 sys
= tc
->getSystemPtr();
423 for (x
= 0; x
< sys
->numContexts(); x
++) {
424 oc
= sys
->getThreadContext(x
);
425 assert(oc
->getITBPtr() && oc
->getDTBPtr());
426 oc
->getITBPtr()->flushAll();
427 oc
->getDTBPtr()->flushAll();
429 // If CheckerCPU is connected, need to notify it of a flush
430 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
432 checker
->getITBPtr()->flushAll();
433 checker
->getDTBPtr()->flushAll();
437 case MISCREG_ITLBIALL
:
438 tc
->getITBPtr()->flushAll();
440 case MISCREG_DTLBIALL
:
441 tc
->getDTBPtr()->flushAll();
443 case MISCREG_TLBIMVAIS
:
444 case MISCREG_TLBIMVA
:
445 sys
= tc
->getSystemPtr();
446 for (x
= 0; x
< sys
->numContexts(); x
++) {
447 oc
= sys
->getThreadContext(x
);
448 assert(oc
->getITBPtr() && oc
->getDTBPtr());
449 oc
->getITBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
451 oc
->getDTBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
454 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
456 checker
->getITBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
458 checker
->getDTBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
463 case MISCREG_TLBIASIDIS
:
464 case MISCREG_TLBIASID
:
465 sys
= tc
->getSystemPtr();
466 for (x
= 0; x
< sys
->numContexts(); x
++) {
467 oc
= sys
->getThreadContext(x
);
468 assert(oc
->getITBPtr() && oc
->getDTBPtr());
469 oc
->getITBPtr()->flushAsid(bits(newVal
, 7,0));
470 oc
->getDTBPtr()->flushAsid(bits(newVal
, 7,0));
471 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
473 checker
->getITBPtr()->flushAsid(bits(newVal
, 7,0));
474 checker
->getDTBPtr()->flushAsid(bits(newVal
, 7,0));
478 case MISCREG_TLBIMVAAIS
:
479 case MISCREG_TLBIMVAA
:
480 sys
= tc
->getSystemPtr();
481 for (x
= 0; x
< sys
->numContexts(); x
++) {
482 oc
= sys
->getThreadContext(x
);
483 assert(oc
->getITBPtr() && oc
->getDTBPtr());
484 oc
->getITBPtr()->flushMva(mbits(newVal
, 31,12));
485 oc
->getDTBPtr()->flushMva(mbits(newVal
, 31,12));
487 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
489 checker
->getITBPtr()->flushMva(mbits(newVal
, 31,12));
490 checker
->getDTBPtr()->flushMva(mbits(newVal
, 31,12));
494 case MISCREG_ITLBIMVA
:
495 tc
->getITBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
498 case MISCREG_DTLBIMVA
:
499 tc
->getDTBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
502 case MISCREG_ITLBIASID
:
503 tc
->getITBPtr()->flushAsid(bits(newVal
, 7,0));
505 case MISCREG_DTLBIASID
:
506 tc
->getDTBPtr()->flushAsid(bits(newVal
, 7,0));
509 warn("Not doing anything for write of miscreg ACTLR\n");
513 // Performance counters not implemented. Instead, interpret
514 // a reset command to this register to reset the simulator
516 // PMCR_E | PMCR_P | PMCR_C
517 const int ResetAndEnableCounters
= 0x7;
518 if (newVal
== ResetAndEnableCounters
) {
519 inform("Resetting all simobject stats\n");
520 Stats::schedStatEvent(false, true);
524 case MISCREG_PMCCNTR
:
526 warn("Not doing anything for write to miscreg %s\n",
527 miscRegName
[misc_reg
]);
529 case MISCREG_V2PCWPR
:
530 case MISCREG_V2PCWPW
:
531 case MISCREG_V2PCWUR
:
532 case MISCREG_V2PCWUW
:
533 case MISCREG_V2POWPR
:
534 case MISCREG_V2POWPW
:
535 case MISCREG_V2POWUR
:
536 case MISCREG_V2POWUW
:
538 RequestPtr req
= new Request
;
543 case MISCREG_V2PCWPR
:
544 flags
= TLB::MustBeOne
;
545 mode
= BaseTLB::Read
;
547 case MISCREG_V2PCWPW
:
548 flags
= TLB::MustBeOne
;
549 mode
= BaseTLB::Write
;
551 case MISCREG_V2PCWUR
:
552 flags
= TLB::MustBeOne
| TLB::UserMode
;
553 mode
= BaseTLB::Read
;
555 case MISCREG_V2PCWUW
:
556 flags
= TLB::MustBeOne
| TLB::UserMode
;
557 mode
= BaseTLB::Write
;
560 panic("Security Extensions not implemented!");
562 warn("Translating via MISCREG in atomic mode! Fix Me!\n");
563 req
->setVirt(0, val
, 1, flags
, tc
->pcState().pc(),
564 Request::funcMasterId
);
565 fault
= tc
->getDTBPtr()->translateAtomic(req
, tc
, mode
);
566 if (fault
== NoFault
) {
567 miscRegs
[MISCREG_PAR
] =
568 (req
->getPaddr() & 0xfffff000) |
569 (tc
->getDTBPtr()->getAttr() );
571 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
572 val
, miscRegs
[MISCREG_PAR
]);
575 // Set fault bit and FSR
576 FSR fsr
= miscRegs
[MISCREG_DFSR
];
577 miscRegs
[MISCREG_PAR
] =
585 case MISCREG_CONTEXTIDR
:
589 tc
->getITBPtr()->invalidateMiscReg();
590 tc
->getDTBPtr()->invalidateMiscReg();
592 case MISCREG_CPSR_MODE
:
593 // This miscreg is used by copy*Regs to set the CPSR mode
594 // without updating other CPSR variables. It's used to
595 // make sure the register map is in such a state that we can
596 // see all of the registers for the copy.
600 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
601 miscRegName
[misc_reg
], uint32_t(val
));
604 setMiscRegNoEffect(misc_reg
, newVal
);