2 * Copyright (c) 2010-2014 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
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8 * to a hardware implementation of the functionality of the software
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41 #include "arch/arm/isa.hh"
42 #include "arch/arm/pmu.hh"
43 #include "arch/arm/system.hh"
44 #include "cpu/checker/cpu.hh"
45 #include "cpu/base.hh"
46 #include "debug/Arm.hh"
47 #include "debug/MiscRegs.hh"
48 #include "params/ArmISA.hh"
49 #include "sim/faults.hh"
50 #include "sim/stat_control.hh"
51 #include "sim/system.hh"
58 * Some registers aliase with others, and therefore need to be translated.
60 * The first value is the misc register that is to be looked up
61 * the second value is the lower part of the translation
62 * the third the upper part
64 const struct ISA::MiscRegInitializerEntry
65 ISA::MiscRegSwitch
[miscRegTranslateMax
] = {
66 {MISCREG_CSSELR_EL1
, {MISCREG_CSSELR
, 0}},
67 {MISCREG_SCTLR_EL1
, {MISCREG_SCTLR
, 0}},
68 {MISCREG_SCTLR_EL2
, {MISCREG_HSCTLR
, 0}},
69 {MISCREG_ACTLR_EL1
, {MISCREG_ACTLR
, 0}},
70 {MISCREG_ACTLR_EL2
, {MISCREG_HACTLR
, 0}},
71 {MISCREG_CPACR_EL1
, {MISCREG_CPACR
, 0}},
72 {MISCREG_CPTR_EL2
, {MISCREG_HCPTR
, 0}},
73 {MISCREG_HCR_EL2
, {MISCREG_HCR
, 0}},
74 {MISCREG_MDCR_EL2
, {MISCREG_HDCR
, 0}},
75 {MISCREG_HSTR_EL2
, {MISCREG_HSTR
, 0}},
76 {MISCREG_HACR_EL2
, {MISCREG_HACR
, 0}},
77 {MISCREG_TTBR0_EL1
, {MISCREG_TTBR0
, 0}},
78 {MISCREG_TTBR1_EL1
, {MISCREG_TTBR1
, 0}},
79 {MISCREG_TTBR0_EL2
, {MISCREG_HTTBR
, 0}},
80 {MISCREG_VTTBR_EL2
, {MISCREG_VTTBR
, 0}},
81 {MISCREG_TCR_EL1
, {MISCREG_TTBCR
, 0}},
82 {MISCREG_TCR_EL2
, {MISCREG_HTCR
, 0}},
83 {MISCREG_VTCR_EL2
, {MISCREG_VTCR
, 0}},
84 {MISCREG_AFSR0_EL1
, {MISCREG_ADFSR
, 0}},
85 {MISCREG_AFSR1_EL1
, {MISCREG_AIFSR
, 0}},
86 {MISCREG_AFSR0_EL2
, {MISCREG_HADFSR
, 0}},
87 {MISCREG_AFSR1_EL2
, {MISCREG_HAIFSR
, 0}},
88 {MISCREG_ESR_EL2
, {MISCREG_HSR
, 0}},
89 {MISCREG_FAR_EL1
, {MISCREG_DFAR
, MISCREG_IFAR
}},
90 {MISCREG_FAR_EL2
, {MISCREG_HDFAR
, MISCREG_HIFAR
}},
91 {MISCREG_HPFAR_EL2
, {MISCREG_HPFAR
, 0}},
92 {MISCREG_PAR_EL1
, {MISCREG_PAR
, 0}},
93 {MISCREG_MAIR_EL1
, {MISCREG_PRRR
, MISCREG_NMRR
}},
94 {MISCREG_MAIR_EL2
, {MISCREG_HMAIR0
, MISCREG_HMAIR1
}},
95 {MISCREG_AMAIR_EL1
, {MISCREG_AMAIR0
, MISCREG_AMAIR1
}},
96 {MISCREG_VBAR_EL1
, {MISCREG_VBAR
, 0}},
97 {MISCREG_VBAR_EL2
, {MISCREG_HVBAR
, 0}},
98 {MISCREG_CONTEXTIDR_EL1
, {MISCREG_CONTEXTIDR
, 0}},
99 {MISCREG_TPIDR_EL0
, {MISCREG_TPIDRURW
, 0}},
100 {MISCREG_TPIDRRO_EL0
, {MISCREG_TPIDRURO
, 0}},
101 {MISCREG_TPIDR_EL1
, {MISCREG_TPIDRPRW
, 0}},
102 {MISCREG_TPIDR_EL2
, {MISCREG_HTPIDR
, 0}},
103 {MISCREG_TEECR32_EL1
, {MISCREG_TEECR
, 0}},
104 {MISCREG_CNTFRQ_EL0
, {MISCREG_CNTFRQ
, 0}},
105 {MISCREG_CNTPCT_EL0
, {MISCREG_CNTPCT
, 0}},
106 {MISCREG_CNTVCT_EL0
, {MISCREG_CNTVCT
, 0}},
107 {MISCREG_CNTVOFF_EL2
, {MISCREG_CNTVOFF
, 0}},
108 {MISCREG_CNTKCTL_EL1
, {MISCREG_CNTKCTL
, 0}},
109 {MISCREG_CNTHCTL_EL2
, {MISCREG_CNTHCTL
, 0}},
110 {MISCREG_CNTP_TVAL_EL0
, {MISCREG_CNTP_TVAL
, 0}},
111 {MISCREG_CNTP_CTL_EL0
, {MISCREG_CNTP_CTL
, 0}},
112 {MISCREG_CNTP_CVAL_EL0
, {MISCREG_CNTP_CVAL
, 0}},
113 {MISCREG_CNTV_TVAL_EL0
, {MISCREG_CNTV_TVAL
, 0}},
114 {MISCREG_CNTV_CTL_EL0
, {MISCREG_CNTV_CTL
, 0}},
115 {MISCREG_CNTV_CVAL_EL0
, {MISCREG_CNTV_CVAL
, 0}},
116 {MISCREG_CNTHP_TVAL_EL2
, {MISCREG_CNTHP_TVAL
, 0}},
117 {MISCREG_CNTHP_CTL_EL2
, {MISCREG_CNTHP_CTL
, 0}},
118 {MISCREG_CNTHP_CVAL_EL2
, {MISCREG_CNTHP_CVAL
, 0}},
119 {MISCREG_DACR32_EL2
, {MISCREG_DACR
, 0}},
120 {MISCREG_IFSR32_EL2
, {MISCREG_IFSR
, 0}},
121 {MISCREG_TEEHBR32_EL1
, {MISCREG_TEEHBR
, 0}},
122 {MISCREG_SDER32_EL3
, {MISCREG_SDER
, 0}}
130 lookUpMiscReg(NUM_MISCREGS
, {0,0})
134 miscRegs
[MISCREG_SCTLR_RST
] = sctlr
;
136 // Hook up a dummy device if we haven't been configured with a
137 // real PMU. By using a dummy device, we don't need to check that
138 // the PMU exist every time we try to access a PMU register.
142 // Give all ISA devices a pointer to this ISA
145 system
= dynamic_cast<ArmSystem
*>(p
->system
);
146 DPRINTFN("ISA system set to: %p %p\n", system
, p
->system
);
148 // Cache system-level properties
149 if (FullSystem
&& system
) {
150 haveSecurity
= system
->haveSecurity();
151 haveLPAE
= system
->haveLPAE();
152 haveVirtualization
= system
->haveVirtualization();
153 haveLargeAsid64
= system
->haveLargeAsid64();
154 physAddrRange64
= system
->physAddrRange64();
156 haveSecurity
= haveLPAE
= haveVirtualization
= false;
157 haveLargeAsid64
= false;
158 physAddrRange64
= 32; // dummy value
161 /** Fill in the miscReg translation table */
162 for (uint32_t i
= 0; i
< miscRegTranslateMax
; i
++) {
163 struct MiscRegLUTEntry new_entry
;
165 uint32_t select
= MiscRegSwitch
[i
].index
;
166 new_entry
= MiscRegSwitch
[i
].entry
;
168 lookUpMiscReg
[select
] = new_entry
;
171 preUnflattenMiscReg();
179 return dynamic_cast<const Params
*>(_params
);
185 const Params
*p(params());
187 SCTLR sctlr_rst
= miscRegs
[MISCREG_SCTLR_RST
];
188 memset(miscRegs
, 0, sizeof(miscRegs
));
190 // Initialize configurable default values
191 miscRegs
[MISCREG_MIDR
] = p
->midr
;
192 miscRegs
[MISCREG_MIDR_EL1
] = p
->midr
;
193 miscRegs
[MISCREG_VPIDR
] = p
->midr
;
195 if (FullSystem
&& system
->highestELIs64()) {
196 // Initialize AArch64 state
201 // Initialize AArch32 state...
204 cpsr
.mode
= MODE_USER
;
205 miscRegs
[MISCREG_CPSR
] = cpsr
;
209 sctlr
.te
= (bool) sctlr_rst
.te
;
210 sctlr
.nmfi
= (bool) sctlr_rst
.nmfi
;
211 sctlr
.v
= (bool) sctlr_rst
.v
;
216 sctlr
.rao4
= 0xf; // SCTLR[6:3]
219 miscRegs
[MISCREG_SCTLR_NS
] = sctlr
;
220 miscRegs
[MISCREG_SCTLR_RST
] = sctlr_rst
;
221 miscRegs
[MISCREG_HCPTR
] = 0;
223 // Start with an event in the mailbox
224 miscRegs
[MISCREG_SEV_MAILBOX
] = 1;
226 // Separate Instruction and Data TLBs
227 miscRegs
[MISCREG_TLBTR
] = 1;
230 mvfr0
.advSimdRegisters
= 2;
231 mvfr0
.singlePrecision
= 2;
232 mvfr0
.doublePrecision
= 2;
233 mvfr0
.vfpExceptionTrapping
= 0;
235 mvfr0
.squareRoot
= 1;
236 mvfr0
.shortVectors
= 1;
237 mvfr0
.roundingModes
= 1;
238 miscRegs
[MISCREG_MVFR0
] = mvfr0
;
241 mvfr1
.flushToZero
= 1;
242 mvfr1
.defaultNaN
= 1;
243 mvfr1
.advSimdLoadStore
= 1;
244 mvfr1
.advSimdInteger
= 1;
245 mvfr1
.advSimdSinglePrecision
= 1;
246 mvfr1
.advSimdHalfPrecision
= 1;
247 mvfr1
.vfpHalfPrecision
= 1;
248 miscRegs
[MISCREG_MVFR1
] = mvfr1
;
250 // Reset values of PRRR and NMRR are implementation dependent
252 // @todo: PRRR and NMRR in secure state?
253 miscRegs
[MISCREG_PRRR_NS
] =
266 miscRegs
[MISCREG_NMRR_NS
] =
283 miscRegs
[MISCREG_CPACR
] = 0;
286 miscRegs
[MISCREG_ID_PFR0
] = p
->id_pfr0
;
287 miscRegs
[MISCREG_ID_PFR1
] = p
->id_pfr1
;
289 miscRegs
[MISCREG_ID_MMFR0
] = p
->id_mmfr0
;
290 miscRegs
[MISCREG_ID_MMFR1
] = p
->id_mmfr1
;
291 miscRegs
[MISCREG_ID_MMFR2
] = p
->id_mmfr2
;
292 miscRegs
[MISCREG_ID_MMFR3
] = p
->id_mmfr3
;
294 miscRegs
[MISCREG_ID_ISAR0
] = p
->id_isar0
;
295 miscRegs
[MISCREG_ID_ISAR1
] = p
->id_isar1
;
296 miscRegs
[MISCREG_ID_ISAR2
] = p
->id_isar2
;
297 miscRegs
[MISCREG_ID_ISAR3
] = p
->id_isar3
;
298 miscRegs
[MISCREG_ID_ISAR4
] = p
->id_isar4
;
299 miscRegs
[MISCREG_ID_ISAR5
] = p
->id_isar5
;
301 miscRegs
[MISCREG_FPSID
] = p
->fpsid
;
304 TTBCR ttbcr
= miscRegs
[MISCREG_TTBCR_NS
];
306 miscRegs
[MISCREG_TTBCR_NS
] = ttbcr
;
307 // Enforce consistency with system-level settings
308 miscRegs
[MISCREG_ID_MMFR0
] = (miscRegs
[MISCREG_ID_MMFR0
] & ~0xf) | 0x5;
312 miscRegs
[MISCREG_SCTLR_S
] = sctlr
;
313 miscRegs
[MISCREG_SCR
] = 0;
314 miscRegs
[MISCREG_VBAR_S
] = 0;
316 // we're always non-secure
317 miscRegs
[MISCREG_SCR
] = 1;
320 //XXX We need to initialize the rest of the state.
324 ISA::clear64(const ArmISAParams
*p
)
327 Addr rvbar
= system
->resetAddr64();
328 switch (system
->highestEL()) {
329 // Set initial EL to highest implemented EL using associated stack
330 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
333 cpsr
.mode
= MODE_EL3H
;
334 miscRegs
[MISCREG_RVBAR_EL3
] = rvbar
;
337 cpsr
.mode
= MODE_EL2H
;
338 miscRegs
[MISCREG_RVBAR_EL2
] = rvbar
;
341 cpsr
.mode
= MODE_EL1H
;
342 miscRegs
[MISCREG_RVBAR_EL1
] = rvbar
;
345 panic("Invalid highest implemented exception level");
349 // Initialize rest of CPSR
350 cpsr
.daif
= 0xf; // Mask all interrupts
353 miscRegs
[MISCREG_CPSR
] = cpsr
;
356 // Initialize other control registers
357 miscRegs
[MISCREG_MPIDR_EL1
] = 0x80000000;
359 miscRegs
[MISCREG_SCTLR_EL3
] = 0x30c50870;
360 miscRegs
[MISCREG_SCR_EL3
] = 0x00000030; // RES1 fields
361 // @todo: uncomment this to enable Virtualization
362 // } else if (haveVirtualization) {
363 // miscRegs[MISCREG_SCTLR_EL2] = 0x30c50870;
365 miscRegs
[MISCREG_SCTLR_EL1
] = 0x30c50870;
367 miscRegs
[MISCREG_SCR_EL3
] = 1;
370 // Initialize configurable id registers
371 miscRegs
[MISCREG_ID_AA64AFR0_EL1
] = p
->id_aa64afr0_el1
;
372 miscRegs
[MISCREG_ID_AA64AFR1_EL1
] = p
->id_aa64afr1_el1
;
373 miscRegs
[MISCREG_ID_AA64DFR0_EL1
] =
374 (p
->id_aa64dfr0_el1
& 0xfffffffffffff0ffULL
) |
375 (p
->pmu
? 0x0000000000000100ULL
: 0); // Enable PMUv3
377 miscRegs
[MISCREG_ID_AA64DFR1_EL1
] = p
->id_aa64dfr1_el1
;
378 miscRegs
[MISCREG_ID_AA64ISAR0_EL1
] = p
->id_aa64isar0_el1
;
379 miscRegs
[MISCREG_ID_AA64ISAR1_EL1
] = p
->id_aa64isar1_el1
;
380 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
] = p
->id_aa64mmfr0_el1
;
381 miscRegs
[MISCREG_ID_AA64MMFR1_EL1
] = p
->id_aa64mmfr1_el1
;
382 miscRegs
[MISCREG_ID_AA64PFR0_EL1
] = p
->id_aa64pfr0_el1
;
383 miscRegs
[MISCREG_ID_AA64PFR1_EL1
] = p
->id_aa64pfr1_el1
;
385 miscRegs
[MISCREG_ID_DFR0_EL1
] =
386 (p
->pmu
? 0x03000000ULL
: 0); // Enable PMUv3
388 miscRegs
[MISCREG_ID_DFR0
] = miscRegs
[MISCREG_ID_DFR0_EL1
];
390 // Enforce consistency with system-level settings...
393 // (no AArch32/64 interprocessing support for now)
394 miscRegs
[MISCREG_ID_AA64PFR0_EL1
] = insertBits(
395 miscRegs
[MISCREG_ID_AA64PFR0_EL1
], 15, 12,
396 haveSecurity
? 0x1 : 0x0);
398 // (no AArch32/64 interprocessing support for now)
399 miscRegs
[MISCREG_ID_AA64PFR0_EL1
] = insertBits(
400 miscRegs
[MISCREG_ID_AA64PFR0_EL1
], 11, 8,
401 haveVirtualization
? 0x1 : 0x0);
402 // Large ASID support
403 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
] = insertBits(
404 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
], 7, 4,
405 haveLargeAsid64
? 0x2 : 0x0);
406 // Physical address size
407 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
] = insertBits(
408 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
], 3, 0,
409 encodePhysAddrRange64(physAddrRange64
));
413 ISA::readMiscRegNoEffect(int misc_reg
) const
415 assert(misc_reg
< NumMiscRegs
);
417 int flat_idx
= flattenMiscIndex(misc_reg
); // Note: indexes of AArch64
418 // registers are left unchanged
421 if (lookUpMiscReg
[flat_idx
].lower
== 0 || flat_idx
== MISCREG_SPSR
422 || flat_idx
== MISCREG_SCTLR_EL1
) {
423 if (flat_idx
== MISCREG_SPSR
)
424 flat_idx
= flattenMiscIndex(MISCREG_SPSR
);
425 if (flat_idx
== MISCREG_SCTLR_EL1
)
426 flat_idx
= flattenMiscIndex(MISCREG_SCTLR
);
427 val
= miscRegs
[flat_idx
];
429 if (lookUpMiscReg
[flat_idx
].upper
> 0)
430 val
= ((miscRegs
[lookUpMiscReg
[flat_idx
].lower
] & mask(32))
431 | (miscRegs
[lookUpMiscReg
[flat_idx
].upper
] << 32));
433 val
= miscRegs
[lookUpMiscReg
[flat_idx
].lower
];
440 ISA::readMiscReg(int misc_reg
, ThreadContext
*tc
)
446 if (misc_reg
== MISCREG_CPSR
) {
447 cpsr
= miscRegs
[misc_reg
];
449 cpsr
.j
= pc
.jazelle() ? 1 : 0;
450 cpsr
.t
= pc
.thumb() ? 1 : 0;
455 if (!miscRegInfo
[misc_reg
][MISCREG_IMPLEMENTED
]) {
456 if (miscRegInfo
[misc_reg
][MISCREG_WARN_NOT_FAIL
])
457 warn("Unimplemented system register %s read.\n",
458 miscRegName
[misc_reg
]);
460 panic("Unimplemented system register %s read.\n",
461 miscRegName
[misc_reg
]);
465 switch (unflattenMiscReg(misc_reg
)) {
468 if (!haveVirtualization
)
471 return readMiscRegNoEffect(MISCREG_HCR
);
475 const uint32_t ones
= (uint32_t)(-1);
477 // Only cp10, cp11, and ase are implemented, nothing else should
478 // be readable? (straight copy from the write code)
479 cpacrMask
.cp10
= ones
;
480 cpacrMask
.cp11
= ones
;
481 cpacrMask
.asedis
= ones
;
483 // Security Extensions may limit the readability of CPACR
485 scr
= readMiscRegNoEffect(MISCREG_SCR
);
486 cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
487 if (scr
.ns
&& (cpsr
.mode
!= MODE_MON
)) {
488 NSACR nsacr
= readMiscRegNoEffect(MISCREG_NSACR
);
489 // NB: Skipping the full loop, here
490 if (!nsacr
.cp10
) cpacrMask
.cp10
= 0;
491 if (!nsacr
.cp11
) cpacrMask
.cp11
= 0;
494 MiscReg val
= readMiscRegNoEffect(MISCREG_CPACR
);
496 DPRINTF(MiscRegs
, "Reading misc reg %s: %#x\n",
497 miscRegName
[misc_reg
], val
);
501 cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
502 scr
= readMiscRegNoEffect(MISCREG_SCR
);
503 if ((cpsr
.mode
== MODE_HYP
) || inSecureState(scr
, cpsr
)) {
504 return getMPIDR(system
, tc
);
506 return readMiscReg(MISCREG_VMPIDR
, tc
);
509 case MISCREG_MPIDR_EL1
:
510 // @todo in the absence of v8 virtualization support just return MPIDR_EL1
511 return getMPIDR(system
, tc
) & 0xffffffff;
513 // top bit defined as RES1
514 return readMiscRegNoEffect(misc_reg
) | 0x80000000;
515 case MISCREG_ID_AFR0
: // not implemented, so alias MIDR
516 case MISCREG_REVIDR
: // not implemented, so alias MIDR
518 cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
519 scr
= readMiscRegNoEffect(MISCREG_SCR
);
520 if ((cpsr
.mode
== MODE_HYP
) || inSecureState(scr
, cpsr
)) {
521 return readMiscRegNoEffect(misc_reg
);
523 return readMiscRegNoEffect(MISCREG_VPIDR
);
526 case MISCREG_JOSCR
: // Jazelle trivial implementation, RAZ/WI
527 case MISCREG_JMCR
: // Jazelle trivial implementation, RAZ/WI
528 case MISCREG_JIDR
: // Jazelle trivial implementation, RAZ/WI
529 case MISCREG_AIDR
: // AUX ID set to 0
530 case MISCREG_TCMTR
: // No TCM's
534 warn_once("The clidr register always reports 0 caches.\n");
535 warn_once("clidr LoUIS field of 0b001 to match current "
536 "ARM implementations.\n");
539 warn_once("The ccsidr register isn't implemented and "
540 "always reads as 0.\n");
544 //all caches have the same line size in gem5
545 //4 byte words in ARM
546 unsigned lineSizeWords
=
547 tc
->getSystemPtr()->cacheLineSize() / 4;
548 unsigned log2LineSizeWords
= 0;
550 while (lineSizeWords
>>= 1) {
555 //log2 of minimun i-cache line size (words)
556 ctr
.iCacheLineSize
= log2LineSizeWords
;
557 //b11 - gem5 uses pipt
558 ctr
.l1IndexPolicy
= 0x3;
559 //log2 of minimum d-cache line size (words)
560 ctr
.dCacheLineSize
= log2LineSizeWords
;
561 //log2 of max reservation size (words)
562 ctr
.erg
= log2LineSizeWords
;
563 //log2 of max writeback size (words)
564 ctr
.cwg
= log2LineSizeWords
;
565 //b100 - gem5 format is ARMv7
571 warn("Not doing anything for miscreg ACTLR\n");
574 case MISCREG_PMXEVTYPER_PMCCFILTR
:
575 case MISCREG_PMINTENSET_EL1
... MISCREG_PMOVSSET_EL0
:
576 case MISCREG_PMEVCNTR0_EL0
... MISCREG_PMEVTYPER5_EL0
:
577 case MISCREG_PMCR
... MISCREG_PMOVSSET
:
578 return pmu
->readMiscReg(misc_reg
);
581 panic("shouldn't be reading this register seperately\n");
582 case MISCREG_FPSCR_QC
:
583 return readMiscRegNoEffect(MISCREG_FPSCR
) & ~FpscrQcMask
;
584 case MISCREG_FPSCR_EXC
:
585 return readMiscRegNoEffect(MISCREG_FPSCR
) & ~FpscrExcMask
;
588 const uint32_t ones
= (uint32_t)(-1);
590 fpscrMask
.ioc
= ones
;
591 fpscrMask
.dzc
= ones
;
592 fpscrMask
.ofc
= ones
;
593 fpscrMask
.ufc
= ones
;
594 fpscrMask
.ixc
= ones
;
595 fpscrMask
.idc
= ones
;
601 return readMiscRegNoEffect(MISCREG_FPSCR
) & (uint32_t)fpscrMask
;
605 const uint32_t ones
= (uint32_t)(-1);
607 fpscrMask
.ioe
= ones
;
608 fpscrMask
.dze
= ones
;
609 fpscrMask
.ofe
= ones
;
610 fpscrMask
.ufe
= ones
;
611 fpscrMask
.ixe
= ones
;
612 fpscrMask
.ide
= ones
;
613 fpscrMask
.len
= ones
;
614 fpscrMask
.stride
= ones
;
615 fpscrMask
.rMode
= ones
;
618 fpscrMask
.ahp
= ones
;
619 return readMiscRegNoEffect(MISCREG_FPSCR
) & (uint32_t)fpscrMask
;
624 cpsr
.nz
= tc
->readCCReg(CCREG_NZ
);
625 cpsr
.c
= tc
->readCCReg(CCREG_C
);
626 cpsr
.v
= tc
->readCCReg(CCREG_V
);
632 cpsr
.daif
= (uint8_t) ((CPSR
) miscRegs
[MISCREG_CPSR
]).daif
;
637 return tc
->readIntReg(INTREG_SP0
);
641 return tc
->readIntReg(INTREG_SP1
);
645 return tc
->readIntReg(INTREG_SP2
);
649 return miscRegs
[MISCREG_CPSR
] & 0x1;
651 case MISCREG_CURRENTEL
:
653 return miscRegs
[MISCREG_CPSR
] & 0xc;
657 // mostly unimplemented, just set NumCPUs field from sim and return
659 // b00:1CPU to b11:4CPUs
660 l2ctlr
.numCPUs
= tc
->getSystemPtr()->numContexts() - 1;
663 case MISCREG_DBGDIDR
:
664 /* For now just implement the version number.
665 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
668 case MISCREG_DBGDSCRint
:
671 return tc
->getCpuPtr()->getInterruptController()->getISR(
672 readMiscRegNoEffect(MISCREG_HCR
),
673 readMiscRegNoEffect(MISCREG_CPSR
),
674 readMiscRegNoEffect(MISCREG_SCR
));
675 case MISCREG_ISR_EL1
:
676 return tc
->getCpuPtr()->getInterruptController()->getISR(
677 readMiscRegNoEffect(MISCREG_HCR_EL2
),
678 readMiscRegNoEffect(MISCREG_CPSR
),
679 readMiscRegNoEffect(MISCREG_SCR_EL3
));
680 case MISCREG_DCZID_EL0
:
681 return 0x04; // DC ZVA clear 64-byte chunks
684 MiscReg val
= readMiscRegNoEffect(misc_reg
);
685 // The trap bit associated with CP14 is defined as RAZ
687 // If a CP bit in NSACR is 0 then the corresponding bit in
689 bool secure_lookup
= haveSecurity
&&
690 inSecureState(readMiscRegNoEffect(MISCREG_SCR
),
691 readMiscRegNoEffect(MISCREG_CPSR
));
692 if (!secure_lookup
) {
693 MiscReg mask
= readMiscRegNoEffect(MISCREG_NSACR
);
694 val
|= (mask
^ 0x7FFF) & 0xBFFF;
696 // Set the bits for unimplemented coprocessors to RAO/WI
700 case MISCREG_HDFAR
: // alias for secure DFAR
701 return readMiscRegNoEffect(MISCREG_DFAR_S
);
702 case MISCREG_HIFAR
: // alias for secure IFAR
703 return readMiscRegNoEffect(MISCREG_IFAR_S
);
704 case MISCREG_HVBAR
: // bottom bits reserved
705 return readMiscRegNoEffect(MISCREG_HVBAR
) & 0xFFFFFFE0;
706 case MISCREG_SCTLR
: // Some bits hardwired
707 // The FI field (bit 21) is common between S/NS versions of the register
708 return (readMiscRegNoEffect(MISCREG_SCTLR_S
) & (1 << 21)) |
709 (readMiscRegNoEffect(misc_reg
) & 0x72DD39FF) | 0x00C00818; // V8 SCTLR
710 case MISCREG_SCTLR_EL1
:
711 // The FI field (bit 21) is common between S/NS versions of the register
712 return (readMiscRegNoEffect(MISCREG_SCTLR_S
) & (1 << 21)) |
713 (readMiscRegNoEffect(misc_reg
) & 0x37DDDBFF) | 0x30D00800; // V8 SCTLR_EL1
714 case MISCREG_SCTLR_EL3
:
715 // The FI field (bit 21) is common between S/NS versions of the register
716 return (readMiscRegNoEffect(MISCREG_SCTLR_S
) & (1 << 21)) |
717 (readMiscRegNoEffect(misc_reg
) & 0x32CD183F) | 0x30C50830; // V8 SCTLR_EL3
718 case MISCREG_HSCTLR
: // FI comes from SCTLR
720 uint32_t mask
= 1 << 27;
721 return (readMiscRegNoEffect(MISCREG_HSCTLR
) & ~mask
) |
722 (readMiscRegNoEffect(MISCREG_SCTLR
) & mask
);
726 CPSR cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
728 return readMiscRegNoEffect(MISCREG_SCR
);
730 return readMiscRegNoEffect(MISCREG_SCR_EL3
);
733 // Generic Timer registers
735 case MISCREG_CNTFRQ_EL0
:
736 inform_once("Read CNTFREQ_EL0 frequency\n");
737 return getSystemCounter(tc
)->freq();
739 case MISCREG_CNTPCT_EL0
:
740 return getSystemCounter(tc
)->value();
742 return getSystemCounter(tc
)->value();
743 case MISCREG_CNTVCT_EL0
:
744 return getSystemCounter(tc
)->value();
745 case MISCREG_CNTP_CVAL
:
746 case MISCREG_CNTP_CVAL_EL0
:
747 return getArchTimer(tc
, tc
->cpuId())->compareValue();
748 case MISCREG_CNTP_TVAL
:
749 case MISCREG_CNTP_TVAL_EL0
:
750 return getArchTimer(tc
, tc
->cpuId())->timerValue();
751 case MISCREG_CNTP_CTL
:
752 case MISCREG_CNTP_CTL_EL0
:
753 return getArchTimer(tc
, tc
->cpuId())->control();
754 // PL1 phys. timer, secure
756 // case MISCREG_CNTPS_CVAL_EL1:
757 // case MISCREG_CNTPS_TVAL_EL1:
758 // case MISCREG_CNTPS_CTL_EL1:
759 // PL2 phys. timer, non-secure
761 // case MISCREG_CNTHCTL:
762 // case MISCREG_CNTHP_CVAL:
763 // case MISCREG_CNTHP_TVAL:
764 // case MISCREG_CNTHP_CTL:
766 // case MISCREG_CNTHCTL_EL2:
767 // case MISCREG_CNTHP_CVAL_EL2:
768 // case MISCREG_CNTHP_TVAL_EL2:
769 // case MISCREG_CNTHP_CTL_EL2:
772 // case MISCREG_CNTV_CVAL:
773 // case MISCREG_CNTV_TVAL:
774 // case MISCREG_CNTV_CTL:
776 // case MISCREG_CNTV_CVAL_EL2:
777 // case MISCREG_CNTV_TVAL_EL2:
778 // case MISCREG_CNTV_CTL_EL2:
783 return readMiscRegNoEffect(misc_reg
);
787 ISA::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
)
789 assert(misc_reg
< NumMiscRegs
);
791 int flat_idx
= flattenMiscIndex(misc_reg
); // Note: indexes of AArch64
792 // registers are left unchanged
794 int flat_idx2
= lookUpMiscReg
[flat_idx
].upper
;
797 miscRegs
[lookUpMiscReg
[flat_idx
].lower
] = bits(val
, 31, 0);
798 miscRegs
[flat_idx2
] = bits(val
, 63, 32);
799 DPRINTF(MiscRegs
, "Writing to misc reg %d (%d:%d) : %#x\n",
800 misc_reg
, flat_idx
, flat_idx2
, val
);
802 if (flat_idx
== MISCREG_SPSR
)
803 flat_idx
= flattenMiscIndex(MISCREG_SPSR
);
804 else if (flat_idx
== MISCREG_SCTLR_EL1
)
805 flat_idx
= flattenMiscIndex(MISCREG_SCTLR
);
807 flat_idx
= (lookUpMiscReg
[flat_idx
].lower
> 0) ?
808 lookUpMiscReg
[flat_idx
].lower
: flat_idx
;
809 miscRegs
[flat_idx
] = val
;
810 DPRINTF(MiscRegs
, "Writing to misc reg %d (%d) : %#x\n",
811 misc_reg
, flat_idx
, val
);
816 ISA::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadContext
*tc
)
819 MiscReg newVal
= val
;
829 if (misc_reg
== MISCREG_CPSR
) {
833 CPSR old_cpsr
= miscRegs
[MISCREG_CPSR
];
834 int old_mode
= old_cpsr
.mode
;
836 if (old_mode
!= cpsr
.mode
) {
837 tc
->getITBPtr()->invalidateMiscReg();
838 tc
->getDTBPtr()->invalidateMiscReg();
841 DPRINTF(Arm
, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
842 miscRegs
[misc_reg
], cpsr
, cpsr
.f
, cpsr
.i
, cpsr
.a
, cpsr
.mode
);
843 PCState pc
= tc
->pcState();
844 pc
.nextThumb(cpsr
.t
);
845 pc
.nextJazelle(cpsr
.j
);
847 // Follow slightly different semantics if a CheckerCPU object
849 CheckerCPU
*checker
= tc
->getCheckerCpuPtr();
851 tc
->pcStateNoRecord(pc
);
857 if (!miscRegInfo
[misc_reg
][MISCREG_IMPLEMENTED
]) {
858 if (miscRegInfo
[misc_reg
][MISCREG_WARN_NOT_FAIL
])
859 warn("Unimplemented system register %s write with %#x.\n",
860 miscRegName
[misc_reg
], val
);
862 panic("Unimplemented system register %s write with %#x.\n",
863 miscRegName
[misc_reg
], val
);
866 switch (unflattenMiscReg(misc_reg
)) {
870 const uint32_t ones
= (uint32_t)(-1);
872 // Only cp10, cp11, and ase are implemented, nothing else should
874 cpacrMask
.cp10
= ones
;
875 cpacrMask
.cp11
= ones
;
876 cpacrMask
.asedis
= ones
;
878 // Security Extensions may limit the writability of CPACR
880 scr
= readMiscRegNoEffect(MISCREG_SCR
);
881 CPSR cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
882 if (scr
.ns
&& (cpsr
.mode
!= MODE_MON
)) {
883 NSACR nsacr
= readMiscRegNoEffect(MISCREG_NSACR
);
884 // NB: Skipping the full loop, here
885 if (!nsacr
.cp10
) cpacrMask
.cp10
= 0;
886 if (!nsacr
.cp11
) cpacrMask
.cp11
= 0;
890 MiscReg old_val
= readMiscRegNoEffect(MISCREG_CPACR
);
892 newVal
|= old_val
& ~cpacrMask
;
893 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
894 miscRegName
[misc_reg
], newVal
);
897 case MISCREG_CPACR_EL1
:
899 const uint32_t ones
= (uint32_t)(-1);
901 cpacrMask
.tta
= ones
;
902 cpacrMask
.fpen
= ones
;
904 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
905 miscRegName
[misc_reg
], newVal
);
908 case MISCREG_CPTR_EL2
:
910 const uint32_t ones
= (uint32_t)(-1);
912 cptrMask
.tcpac
= ones
;
917 cptrMask
.res1_13_12_el2
= ones
;
918 cptrMask
.res1_9_0_el2
= ones
;
920 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
921 miscRegName
[misc_reg
], newVal
);
924 case MISCREG_CPTR_EL3
:
926 const uint32_t ones
= (uint32_t)(-1);
928 cptrMask
.tcpac
= ones
;
932 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
933 miscRegName
[misc_reg
], newVal
);
937 warn_once("The csselr register isn't implemented.\n");
940 case MISCREG_DC_ZVA_Xt
:
941 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
946 const uint32_t ones
= (uint32_t)(-1);
948 fpscrMask
.ioc
= ones
;
949 fpscrMask
.dzc
= ones
;
950 fpscrMask
.ofc
= ones
;
951 fpscrMask
.ufc
= ones
;
952 fpscrMask
.ixc
= ones
;
953 fpscrMask
.idc
= ones
;
954 fpscrMask
.ioe
= ones
;
955 fpscrMask
.dze
= ones
;
956 fpscrMask
.ofe
= ones
;
957 fpscrMask
.ufe
= ones
;
958 fpscrMask
.ixe
= ones
;
959 fpscrMask
.ide
= ones
;
960 fpscrMask
.len
= ones
;
961 fpscrMask
.stride
= ones
;
962 fpscrMask
.rMode
= ones
;
965 fpscrMask
.ahp
= ones
;
971 newVal
= (newVal
& (uint32_t)fpscrMask
) |
972 (readMiscRegNoEffect(MISCREG_FPSCR
) &
973 ~(uint32_t)fpscrMask
);
974 tc
->getDecoderPtr()->setContext(newVal
);
979 const uint32_t ones
= (uint32_t)(-1);
981 fpscrMask
.ioc
= ones
;
982 fpscrMask
.dzc
= ones
;
983 fpscrMask
.ofc
= ones
;
984 fpscrMask
.ufc
= ones
;
985 fpscrMask
.ixc
= ones
;
986 fpscrMask
.idc
= ones
;
992 newVal
= (newVal
& (uint32_t)fpscrMask
) |
993 (readMiscRegNoEffect(MISCREG_FPSCR
) &
994 ~(uint32_t)fpscrMask
);
995 misc_reg
= MISCREG_FPSCR
;
1000 const uint32_t ones
= (uint32_t)(-1);
1001 FPSCR fpscrMask
= 0;
1002 fpscrMask
.ioe
= ones
;
1003 fpscrMask
.dze
= ones
;
1004 fpscrMask
.ofe
= ones
;
1005 fpscrMask
.ufe
= ones
;
1006 fpscrMask
.ixe
= ones
;
1007 fpscrMask
.ide
= ones
;
1008 fpscrMask
.len
= ones
;
1009 fpscrMask
.stride
= ones
;
1010 fpscrMask
.rMode
= ones
;
1011 fpscrMask
.fz
= ones
;
1012 fpscrMask
.dn
= ones
;
1013 fpscrMask
.ahp
= ones
;
1014 newVal
= (newVal
& (uint32_t)fpscrMask
) |
1015 (readMiscRegNoEffect(MISCREG_FPSCR
) &
1016 ~(uint32_t)fpscrMask
);
1017 misc_reg
= MISCREG_FPSCR
;
1020 case MISCREG_CPSR_Q
:
1022 assert(!(newVal
& ~CpsrMaskQ
));
1023 newVal
= readMiscRegNoEffect(MISCREG_CPSR
) | newVal
;
1024 misc_reg
= MISCREG_CPSR
;
1027 case MISCREG_FPSCR_QC
:
1029 newVal
= readMiscRegNoEffect(MISCREG_FPSCR
) |
1030 (newVal
& FpscrQcMask
);
1031 misc_reg
= MISCREG_FPSCR
;
1034 case MISCREG_FPSCR_EXC
:
1036 newVal
= readMiscRegNoEffect(MISCREG_FPSCR
) |
1037 (newVal
& FpscrExcMask
);
1038 misc_reg
= MISCREG_FPSCR
;
1043 // vfpv3 architecture, section B.6.1 of DDI04068
1044 // bit 29 - valid only if fpexc[31] is 0
1045 const uint32_t fpexcMask
= 0x60000000;
1046 newVal
= (newVal
& fpexcMask
) |
1047 (readMiscRegNoEffect(MISCREG_FPEXC
) & ~fpexcMask
);
1052 if (!haveVirtualization
)
1058 // ARM ARM (ARM DDI 0406C.b) B4.1.96
1059 const uint32_t ifsrMask
=
1060 mask(31, 13) | mask(11, 11) | mask(8, 6);
1061 newVal
= newVal
& ~ifsrMask
;
1066 // ARM ARM (ARM DDI 0406C.b) B4.1.52
1067 const uint32_t dfsrMask
= mask(31, 14) | mask(8, 8);
1068 newVal
= newVal
& ~dfsrMask
;
1071 case MISCREG_AMAIR0
:
1072 case MISCREG_AMAIR1
:
1074 // ARM ARM (ARM DDI 0406C.b) B4.1.5
1075 // Valid only with LPAE
1078 DPRINTF(MiscRegs
, "Writing AMAIR: %#x\n", newVal
);
1082 tc
->getITBPtr()->invalidateMiscReg();
1083 tc
->getDTBPtr()->invalidateMiscReg();
1087 DPRINTF(MiscRegs
, "Writing SCTLR: %#x\n", newVal
);
1088 MiscRegIndex sctlr_idx
;
1089 scr
= readMiscRegNoEffect(MISCREG_SCR
);
1090 if (haveSecurity
&& !scr
.ns
) {
1091 sctlr_idx
= MISCREG_SCTLR_S
;
1093 sctlr_idx
= MISCREG_SCTLR_NS
;
1094 // The FI field (bit 21) is common between S/NS versions
1095 // of the register, we store this in the secure copy of
1097 miscRegs
[MISCREG_SCTLR_S
] &= ~(1 << 21);
1098 miscRegs
[MISCREG_SCTLR_S
] |= newVal
& (1 << 21);
1100 SCTLR sctlr
= miscRegs
[sctlr_idx
];
1101 SCTLR new_sctlr
= newVal
;
1102 new_sctlr
.nmfi
= ((bool)sctlr
.nmfi
) && !haveVirtualization
;
1103 miscRegs
[sctlr_idx
] = (MiscReg
)new_sctlr
;
1104 tc
->getITBPtr()->invalidateMiscReg();
1105 tc
->getDTBPtr()->invalidateMiscReg();
1108 case MISCREG_ID_PFR0
:
1109 case MISCREG_ID_PFR1
:
1110 case MISCREG_ID_DFR0
:
1111 case MISCREG_ID_MMFR0
:
1112 case MISCREG_ID_MMFR1
:
1113 case MISCREG_ID_MMFR2
:
1114 case MISCREG_ID_MMFR3
:
1115 case MISCREG_ID_ISAR0
:
1116 case MISCREG_ID_ISAR1
:
1117 case MISCREG_ID_ISAR2
:
1118 case MISCREG_ID_ISAR3
:
1119 case MISCREG_ID_ISAR4
:
1120 case MISCREG_ID_ISAR5
:
1128 case MISCREG_ID_AA64AFR0_EL1
:
1129 case MISCREG_ID_AA64AFR1_EL1
:
1130 case MISCREG_ID_AA64DFR0_EL1
:
1131 case MISCREG_ID_AA64DFR1_EL1
:
1132 case MISCREG_ID_AA64ISAR0_EL1
:
1133 case MISCREG_ID_AA64ISAR1_EL1
:
1134 case MISCREG_ID_AA64MMFR0_EL1
:
1135 case MISCREG_ID_AA64MMFR1_EL1
:
1136 case MISCREG_ID_AA64PFR0_EL1
:
1137 case MISCREG_ID_AA64PFR1_EL1
:
1138 // ID registers are constants.
1141 // TLBI all entries, EL0&1 inner sharable (ignored)
1142 case MISCREG_TLBIALLIS
:
1143 case MISCREG_TLBIALL
: // TLBI all entries, EL0&1,
1145 target_el
= 1; // el 0 and 1 are handled together
1146 scr
= readMiscReg(MISCREG_SCR
, tc
);
1147 secure_lookup
= haveSecurity
&& !scr
.ns
;
1148 sys
= tc
->getSystemPtr();
1149 for (x
= 0; x
< sys
->numContexts(); x
++) {
1150 oc
= sys
->getThreadContext(x
);
1151 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1152 oc
->getITBPtr()->flushAllSecurity(secure_lookup
, target_el
);
1153 oc
->getDTBPtr()->flushAllSecurity(secure_lookup
, target_el
);
1155 // If CheckerCPU is connected, need to notify it of a flush
1156 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1158 checker
->getITBPtr()->flushAllSecurity(secure_lookup
,
1160 checker
->getDTBPtr()->flushAllSecurity(secure_lookup
,
1165 // TLBI all entries, EL0&1, instruction side
1166 case MISCREG_ITLBIALL
:
1168 target_el
= 1; // el 0 and 1 are handled together
1169 scr
= readMiscReg(MISCREG_SCR
, tc
);
1170 secure_lookup
= haveSecurity
&& !scr
.ns
;
1171 tc
->getITBPtr()->flushAllSecurity(secure_lookup
, target_el
);
1173 // TLBI all entries, EL0&1, data side
1174 case MISCREG_DTLBIALL
:
1176 target_el
= 1; // el 0 and 1 are handled together
1177 scr
= readMiscReg(MISCREG_SCR
, tc
);
1178 secure_lookup
= haveSecurity
&& !scr
.ns
;
1179 tc
->getDTBPtr()->flushAllSecurity(secure_lookup
, target_el
);
1181 // TLBI based on VA, EL0&1 inner sharable (ignored)
1182 case MISCREG_TLBIMVAIS
:
1183 case MISCREG_TLBIMVA
:
1185 target_el
= 1; // el 0 and 1 are handled together
1186 scr
= readMiscReg(MISCREG_SCR
, tc
);
1187 secure_lookup
= haveSecurity
&& !scr
.ns
;
1188 sys
= tc
->getSystemPtr();
1189 for (x
= 0; x
< sys
->numContexts(); x
++) {
1190 oc
= sys
->getThreadContext(x
);
1191 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1192 oc
->getITBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
1194 secure_lookup
, target_el
);
1195 oc
->getDTBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
1197 secure_lookup
, target_el
);
1199 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1201 checker
->getITBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
1202 bits(newVal
, 7,0), secure_lookup
, target_el
);
1203 checker
->getDTBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
1204 bits(newVal
, 7,0), secure_lookup
, target_el
);
1208 // TLBI by ASID, EL0&1, inner sharable
1209 case MISCREG_TLBIASIDIS
:
1210 case MISCREG_TLBIASID
:
1212 target_el
= 1; // el 0 and 1 are handled together
1213 scr
= readMiscReg(MISCREG_SCR
, tc
);
1214 secure_lookup
= haveSecurity
&& !scr
.ns
;
1215 sys
= tc
->getSystemPtr();
1216 for (x
= 0; x
< sys
->numContexts(); x
++) {
1217 oc
= sys
->getThreadContext(x
);
1218 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1219 oc
->getITBPtr()->flushAsid(bits(newVal
, 7,0),
1220 secure_lookup
, target_el
);
1221 oc
->getDTBPtr()->flushAsid(bits(newVal
, 7,0),
1222 secure_lookup
, target_el
);
1223 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1225 checker
->getITBPtr()->flushAsid(bits(newVal
, 7,0),
1226 secure_lookup
, target_el
);
1227 checker
->getDTBPtr()->flushAsid(bits(newVal
, 7,0),
1228 secure_lookup
, target_el
);
1232 // TLBI by address, EL0&1, inner sharable (ignored)
1233 case MISCREG_TLBIMVAAIS
:
1234 case MISCREG_TLBIMVAA
:
1236 target_el
= 1; // el 0 and 1 are handled together
1237 scr
= readMiscReg(MISCREG_SCR
, tc
);
1238 secure_lookup
= haveSecurity
&& !scr
.ns
;
1240 tlbiMVA(tc
, newVal
, secure_lookup
, hyp
, target_el
);
1242 // TLBI by address, EL2, hypervisor mode
1243 case MISCREG_TLBIMVAH
:
1244 case MISCREG_TLBIMVAHIS
:
1246 target_el
= 1; // aarch32, use hyp bit
1247 scr
= readMiscReg(MISCREG_SCR
, tc
);
1248 secure_lookup
= haveSecurity
&& !scr
.ns
;
1250 tlbiMVA(tc
, newVal
, secure_lookup
, hyp
, target_el
);
1252 // TLBI by address and asid, EL0&1, instruction side only
1253 case MISCREG_ITLBIMVA
:
1255 target_el
= 1; // el 0 and 1 are handled together
1256 scr
= readMiscReg(MISCREG_SCR
, tc
);
1257 secure_lookup
= haveSecurity
&& !scr
.ns
;
1258 tc
->getITBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
1259 bits(newVal
, 7,0), secure_lookup
, target_el
);
1261 // TLBI by address and asid, EL0&1, data side only
1262 case MISCREG_DTLBIMVA
:
1264 target_el
= 1; // el 0 and 1 are handled together
1265 scr
= readMiscReg(MISCREG_SCR
, tc
);
1266 secure_lookup
= haveSecurity
&& !scr
.ns
;
1267 tc
->getDTBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
1268 bits(newVal
, 7,0), secure_lookup
, target_el
);
1270 // TLBI by ASID, EL0&1, instrution side only
1271 case MISCREG_ITLBIASID
:
1273 target_el
= 1; // el 0 and 1 are handled together
1274 scr
= readMiscReg(MISCREG_SCR
, tc
);
1275 secure_lookup
= haveSecurity
&& !scr
.ns
;
1276 tc
->getITBPtr()->flushAsid(bits(newVal
, 7,0), secure_lookup
,
1279 // TLBI by ASID EL0&1 data size only
1280 case MISCREG_DTLBIASID
:
1282 target_el
= 1; // el 0 and 1 are handled together
1283 scr
= readMiscReg(MISCREG_SCR
, tc
);
1284 secure_lookup
= haveSecurity
&& !scr
.ns
;
1285 tc
->getDTBPtr()->flushAsid(bits(newVal
, 7,0), secure_lookup
,
1288 // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB
1289 case MISCREG_TLBIALLNSNH
:
1290 case MISCREG_TLBIALLNSNHIS
:
1292 target_el
= 1; // el 0 and 1 are handled together
1294 tlbiALLN(tc
, hyp
, target_el
);
1296 // TLBI all entries, EL2, hyp,
1297 case MISCREG_TLBIALLH
:
1298 case MISCREG_TLBIALLHIS
:
1300 target_el
= 1; // aarch32, use hyp bit
1302 tlbiALLN(tc
, hyp
, target_el
);
1304 // AArch64 TLBI: invalidate all entries EL3
1305 case MISCREG_TLBI_ALLE3IS
:
1306 case MISCREG_TLBI_ALLE3
:
1309 secure_lookup
= true;
1310 tlbiALL(tc
, secure_lookup
, target_el
);
1312 // @todo: uncomment this to enable Virtualization
1313 // case MISCREG_TLBI_ALLE2IS:
1314 // case MISCREG_TLBI_ALLE2:
1315 // TLBI all entries, EL0&1
1316 case MISCREG_TLBI_ALLE1IS
:
1317 case MISCREG_TLBI_ALLE1
:
1318 // AArch64 TLBI: invalidate all entries, stage 1, current VMID
1319 case MISCREG_TLBI_VMALLE1IS
:
1320 case MISCREG_TLBI_VMALLE1
:
1321 // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID
1322 case MISCREG_TLBI_VMALLS12E1IS
:
1323 case MISCREG_TLBI_VMALLS12E1
:
1324 // @todo: handle VMID and stage 2 to enable Virtualization
1326 target_el
= 1; // el 0 and 1 are handled together
1327 scr
= readMiscReg(MISCREG_SCR
, tc
);
1328 secure_lookup
= haveSecurity
&& !scr
.ns
;
1329 tlbiALL(tc
, secure_lookup
, target_el
);
1331 // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID
1332 // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries
1333 // from the last level of translation table walks
1334 // @todo: handle VMID to enable Virtualization
1335 // TLBI all entries, EL0&1
1336 case MISCREG_TLBI_VAE3IS_Xt
:
1337 case MISCREG_TLBI_VAE3_Xt
:
1338 // TLBI by VA, EL3 regime stage 1, last level walk
1339 case MISCREG_TLBI_VALE3IS_Xt
:
1340 case MISCREG_TLBI_VALE3_Xt
:
1343 asid
= 0xbeef; // does not matter, tlbi is global
1344 secure_lookup
= true;
1345 tlbiVA(tc
, newVal
, asid
, secure_lookup
, target_el
);
1348 case MISCREG_TLBI_VAE2IS_Xt
:
1349 case MISCREG_TLBI_VAE2_Xt
:
1350 // TLBI by VA, EL2, stage1 last level walk
1351 case MISCREG_TLBI_VALE2IS_Xt
:
1352 case MISCREG_TLBI_VALE2_Xt
:
1355 asid
= 0xbeef; // does not matter, tlbi is global
1356 scr
= readMiscReg(MISCREG_SCR
, tc
);
1357 secure_lookup
= haveSecurity
&& !scr
.ns
;
1358 tlbiVA(tc
, newVal
, asid
, secure_lookup
, target_el
);
1360 // TLBI by VA EL1 & 0, stage1, ASID, current VMID
1361 case MISCREG_TLBI_VAE1IS_Xt
:
1362 case MISCREG_TLBI_VAE1_Xt
:
1363 case MISCREG_TLBI_VALE1IS_Xt
:
1364 case MISCREG_TLBI_VALE1_Xt
:
1366 asid
= bits(newVal
, 63, 48);
1367 target_el
= 1; // el 0 and 1 are handled together
1368 scr
= readMiscReg(MISCREG_SCR
, tc
);
1369 secure_lookup
= haveSecurity
&& !scr
.ns
;
1370 tlbiVA(tc
, newVal
, asid
, secure_lookup
, target_el
);
1372 // AArch64 TLBI: invalidate by ASID, stage 1, current VMID
1373 // @todo: handle VMID to enable Virtualization
1374 case MISCREG_TLBI_ASIDE1IS_Xt
:
1375 case MISCREG_TLBI_ASIDE1_Xt
:
1377 target_el
= 1; // el 0 and 1 are handled together
1378 scr
= readMiscReg(MISCREG_SCR
, tc
);
1379 secure_lookup
= haveSecurity
&& !scr
.ns
;
1380 sys
= tc
->getSystemPtr();
1381 for (x
= 0; x
< sys
->numContexts(); x
++) {
1382 oc
= sys
->getThreadContext(x
);
1383 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1384 asid
= bits(newVal
, 63, 48);
1385 if (!haveLargeAsid64
)
1387 oc
->getITBPtr()->flushAsid(asid
, secure_lookup
, target_el
);
1388 oc
->getDTBPtr()->flushAsid(asid
, secure_lookup
, target_el
);
1389 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1391 checker
->getITBPtr()->flushAsid(asid
,
1392 secure_lookup
, target_el
);
1393 checker
->getDTBPtr()->flushAsid(asid
,
1394 secure_lookup
, target_el
);
1398 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID
1399 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1400 // entries from the last level of translation table walks
1401 // @todo: handle VMID to enable Virtualization
1402 case MISCREG_TLBI_VAAE1IS_Xt
:
1403 case MISCREG_TLBI_VAAE1_Xt
:
1404 case MISCREG_TLBI_VAALE1IS_Xt
:
1405 case MISCREG_TLBI_VAALE1_Xt
:
1407 target_el
= 1; // el 0 and 1 are handled together
1408 scr
= readMiscReg(MISCREG_SCR
, tc
);
1409 secure_lookup
= haveSecurity
&& !scr
.ns
;
1410 sys
= tc
->getSystemPtr();
1411 for (x
= 0; x
< sys
->numContexts(); x
++) {
1412 // @todo: extra controls on TLBI broadcast?
1413 oc
= sys
->getThreadContext(x
);
1414 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1415 Addr va
= ((Addr
) bits(newVal
, 43, 0)) << 12;
1416 oc
->getITBPtr()->flushMva(va
,
1417 secure_lookup
, false, target_el
);
1418 oc
->getDTBPtr()->flushMva(va
,
1419 secure_lookup
, false, target_el
);
1421 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1423 checker
->getITBPtr()->flushMva(va
,
1424 secure_lookup
, false, target_el
);
1425 checker
->getDTBPtr()->flushMva(va
,
1426 secure_lookup
, false, target_el
);
1430 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID
1431 case MISCREG_TLBI_IPAS2LE1IS_Xt
:
1432 case MISCREG_TLBI_IPAS2LE1_Xt
:
1433 case MISCREG_TLBI_IPAS2E1IS_Xt
:
1434 case MISCREG_TLBI_IPAS2E1_Xt
:
1436 // @todo: implement these as part of Virtualization
1437 warn("Not doing anything for write of miscreg ITLB_IPAS2\n");
1440 warn("Not doing anything for write of miscreg ACTLR\n");
1443 case MISCREG_PMXEVTYPER_PMCCFILTR
:
1444 case MISCREG_PMINTENSET_EL1
... MISCREG_PMOVSSET_EL0
:
1445 case MISCREG_PMEVCNTR0_EL0
... MISCREG_PMEVTYPER5_EL0
:
1446 case MISCREG_PMCR
... MISCREG_PMOVSSET
:
1447 pmu
->setMiscReg(misc_reg
, newVal
);
1451 case MISCREG_HSTR
: // TJDBX, now redifined to be RES0
1455 newVal
&= ~((uint32_t) hstrMask
);
1460 // If a CP bit in NSACR is 0 then the corresponding bit in
1461 // HCPTR is RAO/WI. Same applies to NSASEDIS
1462 secure_lookup
= haveSecurity
&&
1463 inSecureState(readMiscRegNoEffect(MISCREG_SCR
),
1464 readMiscRegNoEffect(MISCREG_CPSR
));
1465 if (!secure_lookup
) {
1466 MiscReg oldValue
= readMiscRegNoEffect(MISCREG_HCPTR
);
1467 MiscReg mask
= (readMiscRegNoEffect(MISCREG_NSACR
) ^ 0x7FFF) & 0xBFFF;
1468 newVal
= (newVal
& ~mask
) | (oldValue
& mask
);
1472 case MISCREG_HDFAR
: // alias for secure DFAR
1473 misc_reg
= MISCREG_DFAR_S
;
1475 case MISCREG_HIFAR
: // alias for secure IFAR
1476 misc_reg
= MISCREG_IFAR_S
;
1478 case MISCREG_ATS1CPR
:
1479 case MISCREG_ATS1CPW
:
1480 case MISCREG_ATS1CUR
:
1481 case MISCREG_ATS1CUW
:
1482 case MISCREG_ATS12NSOPR
:
1483 case MISCREG_ATS12NSOPW
:
1484 case MISCREG_ATS12NSOUR
:
1485 case MISCREG_ATS12NSOUW
:
1486 case MISCREG_ATS1HR
:
1487 case MISCREG_ATS1HW
:
1490 BaseTLB::Mode mode
= BaseTLB::Read
;
1491 TLB::ArmTranslationType tranType
= TLB::NormalTran
;
1494 case MISCREG_ATS1CPR
:
1495 flags
= TLB::MustBeOne
;
1496 tranType
= TLB::S1CTran
;
1497 mode
= BaseTLB::Read
;
1499 case MISCREG_ATS1CPW
:
1500 flags
= TLB::MustBeOne
;
1501 tranType
= TLB::S1CTran
;
1502 mode
= BaseTLB::Write
;
1504 case MISCREG_ATS1CUR
:
1505 flags
= TLB::MustBeOne
| TLB::UserMode
;
1506 tranType
= TLB::S1CTran
;
1507 mode
= BaseTLB::Read
;
1509 case MISCREG_ATS1CUW
:
1510 flags
= TLB::MustBeOne
| TLB::UserMode
;
1511 tranType
= TLB::S1CTran
;
1512 mode
= BaseTLB::Write
;
1514 case MISCREG_ATS12NSOPR
:
1516 panic("Security Extensions required for ATS12NSOPR");
1517 flags
= TLB::MustBeOne
;
1518 tranType
= TLB::S1S2NsTran
;
1519 mode
= BaseTLB::Read
;
1521 case MISCREG_ATS12NSOPW
:
1523 panic("Security Extensions required for ATS12NSOPW");
1524 flags
= TLB::MustBeOne
;
1525 tranType
= TLB::S1S2NsTran
;
1526 mode
= BaseTLB::Write
;
1528 case MISCREG_ATS12NSOUR
:
1530 panic("Security Extensions required for ATS12NSOUR");
1531 flags
= TLB::MustBeOne
| TLB::UserMode
;
1532 tranType
= TLB::S1S2NsTran
;
1533 mode
= BaseTLB::Read
;
1535 case MISCREG_ATS12NSOUW
:
1537 panic("Security Extensions required for ATS12NSOUW");
1538 flags
= TLB::MustBeOne
| TLB::UserMode
;
1539 tranType
= TLB::S1S2NsTran
;
1540 mode
= BaseTLB::Write
;
1542 case MISCREG_ATS1HR
: // only really useful from secure mode.
1543 flags
= TLB::MustBeOne
;
1544 tranType
= TLB::HypMode
;
1545 mode
= BaseTLB::Read
;
1547 case MISCREG_ATS1HW
:
1548 flags
= TLB::MustBeOne
;
1549 tranType
= TLB::HypMode
;
1550 mode
= BaseTLB::Write
;
1553 // If we're in timing mode then doing the translation in
1554 // functional mode then we're slightly distorting performance
1555 // results obtained from simulations. The translation should be
1556 // done in the same mode the core is running in. NOTE: This
1557 // can't be an atomic translation because that causes problems
1558 // with unexpected atomic snoop requests.
1559 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg
);
1560 Request
req(0, val
, 1, flags
, Request::funcMasterId
,
1561 tc
->pcState().pc(), tc
->contextId(),
1563 fault
= tc
->getDTBPtr()->translateFunctional(&req
, tc
, mode
, tranType
);
1564 TTBCR ttbcr
= readMiscRegNoEffect(MISCREG_TTBCR
);
1565 HCR hcr
= readMiscRegNoEffect(MISCREG_HCR
);
1568 if (fault
== NoFault
) {
1569 Addr paddr
= req
.getPaddr();
1570 if (haveLPAE
&& (ttbcr
.eae
|| tranType
& TLB::HypMode
||
1571 ((tranType
& TLB::S1S2NsTran
) && hcr
.vm
) )) {
1572 newVal
= (paddr
& mask(39, 12)) |
1573 (tc
->getDTBPtr()->getAttr());
1575 newVal
= (paddr
& 0xfffff000) |
1576 (tc
->getDTBPtr()->getAttr());
1579 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
1582 ArmFault
*armFault
= reinterpret_cast<ArmFault
*>(fault
.get());
1583 // Set fault bit and FSR
1584 FSR fsr
= armFault
->getFsr(tc
);
1586 newVal
= ((fsr
>> 9) & 1) << 11;
1588 // LPAE - rearange fault status
1589 newVal
|= ((fsr
>> 0) & 0x3f) << 1;
1591 // VMSA - rearange fault status
1592 newVal
|= ((fsr
>> 0) & 0xf) << 1;
1593 newVal
|= ((fsr
>> 10) & 0x1) << 5;
1594 newVal
|= ((fsr
>> 12) & 0x1) << 6;
1596 newVal
|= 0x1; // F bit
1597 newVal
|= ((armFault
->iss() >> 7) & 0x1) << 8;
1598 newVal
|= armFault
->isStage2() ? 0x200 : 0;
1600 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
1603 setMiscRegNoEffect(MISCREG_PAR
, newVal
);
1608 TTBCR ttbcr
= readMiscRegNoEffect(MISCREG_TTBCR
);
1609 const uint32_t ones
= (uint32_t)(-1);
1610 TTBCR ttbcrMask
= 0;
1611 TTBCR ttbcrNew
= newVal
;
1613 // ARM DDI 0406C.b, ARMv7-32
1614 ttbcrMask
.n
= ones
; // T0SZ
1616 ttbcrMask
.pd0
= ones
;
1617 ttbcrMask
.pd1
= ones
;
1619 ttbcrMask
.epd0
= ones
;
1620 ttbcrMask
.irgn0
= ones
;
1621 ttbcrMask
.orgn0
= ones
;
1622 ttbcrMask
.sh0
= ones
;
1623 ttbcrMask
.ps
= ones
; // T1SZ
1624 ttbcrMask
.a1
= ones
;
1625 ttbcrMask
.epd1
= ones
;
1626 ttbcrMask
.irgn1
= ones
;
1627 ttbcrMask
.orgn1
= ones
;
1628 ttbcrMask
.sh1
= ones
;
1630 ttbcrMask
.eae
= ones
;
1632 if (haveLPAE
&& ttbcrNew
.eae
) {
1633 newVal
= newVal
& ttbcrMask
;
1635 newVal
= (newVal
& ttbcrMask
) | (ttbcr
& (~ttbcrMask
));
1641 TTBCR ttbcr
= readMiscRegNoEffect(MISCREG_TTBCR
);
1644 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1645 // ARMv8 AArch32 bit 63-56 only
1646 uint64_t ttbrMask
= mask(63,56) | mask(47,40);
1647 newVal
= (newVal
& (~ttbrMask
));
1651 case MISCREG_SCTLR_EL1
:
1653 tc
->getITBPtr()->invalidateMiscReg();
1654 tc
->getDTBPtr()->invalidateMiscReg();
1655 setMiscRegNoEffect(misc_reg
, newVal
);
1657 case MISCREG_CONTEXTIDR
:
1664 case MISCREG_SCR_EL3
:
1665 case MISCREG_TCR_EL1
:
1666 case MISCREG_TCR_EL2
:
1667 case MISCREG_TCR_EL3
:
1668 case MISCREG_SCTLR_EL2
:
1669 case MISCREG_SCTLR_EL3
:
1670 case MISCREG_TTBR0_EL1
:
1671 case MISCREG_TTBR1_EL1
:
1672 case MISCREG_TTBR0_EL2
:
1673 case MISCREG_TTBR0_EL3
:
1674 tc
->getITBPtr()->invalidateMiscReg();
1675 tc
->getDTBPtr()->invalidateMiscReg();
1681 tc
->setCCReg(CCREG_NZ
, cpsr
.nz
);
1682 tc
->setCCReg(CCREG_C
, cpsr
.c
);
1683 tc
->setCCReg(CCREG_V
, cpsr
.v
);
1688 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1689 cpsr
.daif
= (uint8_t) ((CPSR
) newVal
).daif
;
1691 misc_reg
= MISCREG_CPSR
;
1694 case MISCREG_SP_EL0
:
1695 tc
->setIntReg(INTREG_SP0
, newVal
);
1697 case MISCREG_SP_EL1
:
1698 tc
->setIntReg(INTREG_SP1
, newVal
);
1700 case MISCREG_SP_EL2
:
1701 tc
->setIntReg(INTREG_SP2
, newVal
);
1705 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1706 cpsr
.sp
= (uint8_t) ((CPSR
) newVal
).sp
;
1708 misc_reg
= MISCREG_CPSR
;
1711 case MISCREG_CURRENTEL
:
1713 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1714 cpsr
.el
= (uint8_t) ((CPSR
) newVal
).el
;
1716 misc_reg
= MISCREG_CPSR
;
1719 case MISCREG_AT_S1E1R_Xt
:
1720 case MISCREG_AT_S1E1W_Xt
:
1721 case MISCREG_AT_S1E0R_Xt
:
1722 case MISCREG_AT_S1E0W_Xt
:
1723 case MISCREG_AT_S1E2R_Xt
:
1724 case MISCREG_AT_S1E2W_Xt
:
1725 case MISCREG_AT_S12E1R_Xt
:
1726 case MISCREG_AT_S12E1W_Xt
:
1727 case MISCREG_AT_S12E0R_Xt
:
1728 case MISCREG_AT_S12E0W_Xt
:
1729 case MISCREG_AT_S1E3R_Xt
:
1730 case MISCREG_AT_S1E3W_Xt
:
1732 RequestPtr req
= new Request
;
1734 BaseTLB::Mode mode
= BaseTLB::Read
;
1735 TLB::ArmTranslationType tranType
= TLB::NormalTran
;
1738 case MISCREG_AT_S1E1R_Xt
:
1739 flags
= TLB::MustBeOne
;
1740 tranType
= TLB::S1CTran
;
1741 mode
= BaseTLB::Read
;
1743 case MISCREG_AT_S1E1W_Xt
:
1744 flags
= TLB::MustBeOne
;
1745 tranType
= TLB::S1CTran
;
1746 mode
= BaseTLB::Write
;
1748 case MISCREG_AT_S1E0R_Xt
:
1749 flags
= TLB::MustBeOne
| TLB::UserMode
;
1750 tranType
= TLB::S1CTran
;
1751 mode
= BaseTLB::Read
;
1753 case MISCREG_AT_S1E0W_Xt
:
1754 flags
= TLB::MustBeOne
| TLB::UserMode
;
1755 tranType
= TLB::S1CTran
;
1756 mode
= BaseTLB::Write
;
1758 case MISCREG_AT_S1E2R_Xt
:
1759 flags
= TLB::MustBeOne
;
1760 tranType
= TLB::HypMode
;
1761 mode
= BaseTLB::Read
;
1763 case MISCREG_AT_S1E2W_Xt
:
1764 flags
= TLB::MustBeOne
;
1765 tranType
= TLB::HypMode
;
1766 mode
= BaseTLB::Write
;
1768 case MISCREG_AT_S12E0R_Xt
:
1769 flags
= TLB::MustBeOne
| TLB::UserMode
;
1770 tranType
= TLB::S1S2NsTran
;
1771 mode
= BaseTLB::Read
;
1773 case MISCREG_AT_S12E0W_Xt
:
1774 flags
= TLB::MustBeOne
| TLB::UserMode
;
1775 tranType
= TLB::S1S2NsTran
;
1776 mode
= BaseTLB::Write
;
1778 case MISCREG_AT_S12E1R_Xt
:
1779 flags
= TLB::MustBeOne
;
1780 tranType
= TLB::S1S2NsTran
;
1781 mode
= BaseTLB::Read
;
1783 case MISCREG_AT_S12E1W_Xt
:
1784 flags
= TLB::MustBeOne
;
1785 tranType
= TLB::S1S2NsTran
;
1786 mode
= BaseTLB::Write
;
1788 case MISCREG_AT_S1E3R_Xt
:
1789 flags
= TLB::MustBeOne
;
1790 tranType
= TLB::HypMode
; // There is no TZ mode defined.
1791 mode
= BaseTLB::Read
;
1793 case MISCREG_AT_S1E3W_Xt
:
1794 flags
= TLB::MustBeOne
;
1795 tranType
= TLB::HypMode
; // There is no TZ mode defined.
1796 mode
= BaseTLB::Write
;
1799 // If we're in timing mode then doing the translation in
1800 // functional mode then we're slightly distorting performance
1801 // results obtained from simulations. The translation should be
1802 // done in the same mode the core is running in. NOTE: This
1803 // can't be an atomic translation because that causes problems
1804 // with unexpected atomic snoop requests.
1805 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg
);
1806 req
->setVirt(0, val
, 1, flags
, Request::funcMasterId
,
1807 tc
->pcState().pc());
1808 req
->setThreadContext(tc
->contextId(), tc
->threadId());
1809 fault
= tc
->getDTBPtr()->translateFunctional(req
, tc
, mode
,
1813 if (fault
== NoFault
) {
1814 Addr paddr
= req
->getPaddr();
1815 uint64_t attr
= tc
->getDTBPtr()->getAttr();
1816 uint64_t attr1
= attr
>> 56;
1817 if (!attr1
|| attr1
==0x44) {
1819 attr
&= ~ uint64_t(0x80);
1821 newVal
= (paddr
& mask(47, 12)) | attr
;
1823 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
1826 ArmFault
*armFault
= reinterpret_cast<ArmFault
*>(fault
.get());
1827 // Set fault bit and FSR
1828 FSR fsr
= armFault
->getFsr(tc
);
1830 newVal
= ((fsr
>> 9) & 1) << 11;
1831 // rearange fault status
1832 newVal
|= ((fsr
>> 0) & 0x3f) << 1;
1833 newVal
|= 0x1; // F bit
1834 newVal
|= ((armFault
->iss() >> 7) & 0x1) << 8;
1835 newVal
|= armFault
->isStage2() ? 0x200 : 0;
1837 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
1841 setMiscRegNoEffect(MISCREG_PAR_EL1
, newVal
);
1844 case MISCREG_SPSR_EL3
:
1845 case MISCREG_SPSR_EL2
:
1846 case MISCREG_SPSR_EL1
:
1847 // Force bits 23:21 to 0
1848 newVal
= val
& ~(0x7 << 21);
1850 case MISCREG_L2CTLR
:
1851 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
1852 miscRegName
[misc_reg
], uint32_t(val
));
1855 // Generic Timer registers
1856 case MISCREG_CNTFRQ
:
1857 case MISCREG_CNTFRQ_EL0
:
1858 getSystemCounter(tc
)->setFreq(val
);
1860 case MISCREG_CNTP_CVAL
:
1861 case MISCREG_CNTP_CVAL_EL0
:
1862 getArchTimer(tc
, tc
->cpuId())->setCompareValue(val
);
1864 case MISCREG_CNTP_TVAL
:
1865 case MISCREG_CNTP_TVAL_EL0
:
1866 getArchTimer(tc
, tc
->cpuId())->setTimerValue(val
);
1868 case MISCREG_CNTP_CTL
:
1869 case MISCREG_CNTP_CTL_EL0
:
1870 getArchTimer(tc
, tc
->cpuId())->setControl(val
);
1872 // PL1 phys. timer, secure
1874 case MISCREG_CNTPS_CVAL_EL1
:
1875 case MISCREG_CNTPS_TVAL_EL1
:
1876 case MISCREG_CNTPS_CTL_EL1
:
1877 // PL2 phys. timer, non-secure
1879 case MISCREG_CNTHCTL
:
1880 case MISCREG_CNTHP_CVAL
:
1881 case MISCREG_CNTHP_TVAL
:
1882 case MISCREG_CNTHP_CTL
:
1884 case MISCREG_CNTHCTL_EL2
:
1885 case MISCREG_CNTHP_CVAL_EL2
:
1886 case MISCREG_CNTHP_TVAL_EL2
:
1887 case MISCREG_CNTHP_CTL_EL2
:
1890 case MISCREG_CNTV_CVAL
:
1891 case MISCREG_CNTV_TVAL
:
1892 case MISCREG_CNTV_CTL
:
1894 // case MISCREG_CNTV_CVAL_EL2:
1895 // case MISCREG_CNTV_TVAL_EL2:
1896 // case MISCREG_CNTV_CTL_EL2:
1900 setMiscRegNoEffect(misc_reg
, newVal
);
1904 ISA::tlbiVA(ThreadContext
*tc
, MiscReg newVal
, uint16_t asid
,
1905 bool secure_lookup
, uint8_t target_el
)
1907 if (!haveLargeAsid64
)
1909 Addr va
= ((Addr
) bits(newVal
, 43, 0)) << 12;
1910 System
*sys
= tc
->getSystemPtr();
1911 for (int x
= 0; x
< sys
->numContexts(); x
++) {
1912 ThreadContext
*oc
= sys
->getThreadContext(x
);
1913 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1914 oc
->getITBPtr()->flushMvaAsid(va
, asid
,
1915 secure_lookup
, target_el
);
1916 oc
->getDTBPtr()->flushMvaAsid(va
, asid
,
1917 secure_lookup
, target_el
);
1919 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1921 checker
->getITBPtr()->flushMvaAsid(
1922 va
, asid
, secure_lookup
, target_el
);
1923 checker
->getDTBPtr()->flushMvaAsid(
1924 va
, asid
, secure_lookup
, target_el
);
1930 ISA::tlbiALL(ThreadContext
*tc
, bool secure_lookup
, uint8_t target_el
)
1932 System
*sys
= tc
->getSystemPtr();
1933 for (int x
= 0; x
< sys
->numContexts(); x
++) {
1934 ThreadContext
*oc
= sys
->getThreadContext(x
);
1935 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1936 oc
->getITBPtr()->flushAllSecurity(secure_lookup
, target_el
);
1937 oc
->getDTBPtr()->flushAllSecurity(secure_lookup
, target_el
);
1939 // If CheckerCPU is connected, need to notify it of a flush
1940 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1942 checker
->getITBPtr()->flushAllSecurity(secure_lookup
,
1944 checker
->getDTBPtr()->flushAllSecurity(secure_lookup
,
1951 ISA::tlbiALLN(ThreadContext
*tc
, bool hyp
, uint8_t target_el
)
1953 System
*sys
= tc
->getSystemPtr();
1954 for (int x
= 0; x
< sys
->numContexts(); x
++) {
1955 ThreadContext
*oc
= sys
->getThreadContext(x
);
1956 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1957 oc
->getITBPtr()->flushAllNs(hyp
, target_el
);
1958 oc
->getDTBPtr()->flushAllNs(hyp
, target_el
);
1960 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1962 checker
->getITBPtr()->flushAllNs(hyp
, target_el
);
1963 checker
->getDTBPtr()->flushAllNs(hyp
, target_el
);
1969 ISA::tlbiMVA(ThreadContext
*tc
, MiscReg newVal
, bool secure_lookup
, bool hyp
,
1972 System
*sys
= tc
->getSystemPtr();
1973 for (int x
= 0; x
< sys
->numContexts(); x
++) {
1974 ThreadContext
*oc
= sys
->getThreadContext(x
);
1975 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1976 oc
->getITBPtr()->flushMva(mbits(newVal
, 31,12),
1977 secure_lookup
, hyp
, target_el
);
1978 oc
->getDTBPtr()->flushMva(mbits(newVal
, 31,12),
1979 secure_lookup
, hyp
, target_el
);
1981 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1983 checker
->getITBPtr()->flushMva(mbits(newVal
, 31,12),
1984 secure_lookup
, hyp
, target_el
);
1985 checker
->getDTBPtr()->flushMva(mbits(newVal
, 31,12),
1986 secure_lookup
, hyp
, target_el
);
1991 ::GenericTimer::SystemCounter
*
1992 ISA::getSystemCounter(ThreadContext
*tc
)
1994 ::GenericTimer::SystemCounter
*cnt
= ((ArmSystem
*) tc
->getSystemPtr())->
1997 panic("System counter not available\n");
2002 ::GenericTimer::ArchTimer
*
2003 ISA::getArchTimer(ThreadContext
*tc
, int cpu_id
)
2005 ::GenericTimer::ArchTimer
*timer
= ((ArmSystem
*) tc
->getSystemPtr())->
2006 getArchTimer(cpu_id
);
2007 if (timer
== NULL
) {
2008 panic("Architected timer not available\n");
2016 ArmISAParams::create()
2018 return new ArmISA::ISA(this);