2 * Copyright (c) 2010-2013 ARM Limited
5 * The license below extends only to copyright in the software and shall
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41 #include "arch/arm/isa.hh"
42 #include "arch/arm/system.hh"
43 #include "cpu/checker/cpu.hh"
44 #include "debug/Arm.hh"
45 #include "debug/MiscRegs.hh"
46 #include "params/ArmISA.hh"
47 #include "sim/faults.hh"
48 #include "sim/stat_control.hh"
49 #include "sim/system.hh"
56 * Some registers aliase with others, and therefore need to be translated.
58 * The first value is the misc register that is to be looked up
59 * the second value is the lower part of the translation
60 * the third the upper part
62 const struct ISA::MiscRegInitializerEntry
63 ISA::MiscRegSwitch
[miscRegTranslateMax
] = {
64 {MISCREG_CSSELR_EL1
, {MISCREG_CSSELR
, 0}},
65 {MISCREG_SCTLR_EL1
, {MISCREG_SCTLR
, 0}},
66 {MISCREG_SCTLR_EL2
, {MISCREG_HSCTLR
, 0}},
67 {MISCREG_ACTLR_EL1
, {MISCREG_ACTLR
, 0}},
68 {MISCREG_ACTLR_EL2
, {MISCREG_HACTLR
, 0}},
69 {MISCREG_CPACR_EL1
, {MISCREG_CPACR
, 0}},
70 {MISCREG_CPTR_EL2
, {MISCREG_HCPTR
, 0}},
71 {MISCREG_HCR_EL2
, {MISCREG_HCR
, 0}},
72 {MISCREG_MDCR_EL2
, {MISCREG_HDCR
, 0}},
73 {MISCREG_HSTR_EL2
, {MISCREG_HSTR
, 0}},
74 {MISCREG_HACR_EL2
, {MISCREG_HACR
, 0}},
75 {MISCREG_TTBR0_EL1
, {MISCREG_TTBR0
, 0}},
76 {MISCREG_TTBR1_EL1
, {MISCREG_TTBR1
, 0}},
77 {MISCREG_TTBR0_EL2
, {MISCREG_HTTBR
, 0}},
78 {MISCREG_VTTBR_EL2
, {MISCREG_VTTBR
, 0}},
79 {MISCREG_TCR_EL1
, {MISCREG_TTBCR
, 0}},
80 {MISCREG_TCR_EL2
, {MISCREG_HTCR
, 0}},
81 {MISCREG_VTCR_EL2
, {MISCREG_VTCR
, 0}},
82 {MISCREG_AFSR0_EL1
, {MISCREG_ADFSR
, 0}},
83 {MISCREG_AFSR1_EL1
, {MISCREG_AIFSR
, 0}},
84 {MISCREG_AFSR0_EL2
, {MISCREG_HADFSR
, 0}},
85 {MISCREG_AFSR1_EL2
, {MISCREG_HAIFSR
, 0}},
86 {MISCREG_ESR_EL2
, {MISCREG_HSR
, 0}},
87 {MISCREG_FAR_EL1
, {MISCREG_DFAR
, MISCREG_IFAR
}},
88 {MISCREG_FAR_EL2
, {MISCREG_HDFAR
, MISCREG_HIFAR
}},
89 {MISCREG_HPFAR_EL2
, {MISCREG_HPFAR
, 0}},
90 {MISCREG_PAR_EL1
, {MISCREG_PAR
, 0}},
91 {MISCREG_MAIR_EL1
, {MISCREG_PRRR
, MISCREG_NMRR
}},
92 {MISCREG_MAIR_EL2
, {MISCREG_HMAIR0
, MISCREG_HMAIR1
}},
93 {MISCREG_AMAIR_EL1
, {MISCREG_AMAIR0
, MISCREG_AMAIR1
}},
94 {MISCREG_VBAR_EL1
, {MISCREG_VBAR
, 0}},
95 {MISCREG_VBAR_EL2
, {MISCREG_HVBAR
, 0}},
96 {MISCREG_CONTEXTIDR_EL1
, {MISCREG_CONTEXTIDR
, 0}},
97 {MISCREG_TPIDR_EL0
, {MISCREG_TPIDRURW
, 0}},
98 {MISCREG_TPIDRRO_EL0
, {MISCREG_TPIDRURO
, 0}},
99 {MISCREG_TPIDR_EL1
, {MISCREG_TPIDRPRW
, 0}},
100 {MISCREG_TPIDR_EL2
, {MISCREG_HTPIDR
, 0}},
101 {MISCREG_TEECR32_EL1
, {MISCREG_TEECR
, 0}},
102 {MISCREG_CNTFRQ_EL0
, {MISCREG_CNTFRQ
, 0}},
103 {MISCREG_CNTPCT_EL0
, {MISCREG_CNTPCT
, 0}},
104 {MISCREG_CNTVCT_EL0
, {MISCREG_CNTVCT
, 0}},
105 {MISCREG_CNTVOFF_EL2
, {MISCREG_CNTVOFF
, 0}},
106 {MISCREG_CNTKCTL_EL1
, {MISCREG_CNTKCTL
, 0}},
107 {MISCREG_CNTHCTL_EL2
, {MISCREG_CNTHCTL
, 0}},
108 {MISCREG_CNTP_TVAL_EL0
, {MISCREG_CNTP_TVAL
, 0}},
109 {MISCREG_CNTP_CTL_EL0
, {MISCREG_CNTP_CTL
, 0}},
110 {MISCREG_CNTP_CVAL_EL0
, {MISCREG_CNTP_CVAL
, 0}},
111 {MISCREG_CNTV_TVAL_EL0
, {MISCREG_CNTV_TVAL
, 0}},
112 {MISCREG_CNTV_CTL_EL0
, {MISCREG_CNTV_CTL
, 0}},
113 {MISCREG_CNTV_CVAL_EL0
, {MISCREG_CNTV_CVAL
, 0}},
114 {MISCREG_CNTHP_TVAL_EL2
, {MISCREG_CNTHP_TVAL
, 0}},
115 {MISCREG_CNTHP_CTL_EL2
, {MISCREG_CNTHP_CTL
, 0}},
116 {MISCREG_CNTHP_CVAL_EL2
, {MISCREG_CNTHP_CVAL
, 0}},
117 {MISCREG_DACR32_EL2
, {MISCREG_DACR
, 0}},
118 {MISCREG_IFSR32_EL2
, {MISCREG_IFSR
, 0}},
119 {MISCREG_TEEHBR32_EL1
, {MISCREG_TEEHBR
, 0}},
120 {MISCREG_SDER32_EL3
, {MISCREG_SDER
, 0}}
125 : SimObject(p
), system(NULL
), lookUpMiscReg(NUM_MISCREGS
, {0,0})
129 miscRegs
[MISCREG_SCTLR_RST
] = sctlr
;
131 system
= dynamic_cast<ArmSystem
*>(p
->system
);
132 DPRINTFN("ISA system set to: %p %p\n", system
, p
->system
);
134 // Cache system-level properties
135 if (FullSystem
&& system
) {
136 haveSecurity
= system
->haveSecurity();
137 haveLPAE
= system
->haveLPAE();
138 haveVirtualization
= system
->haveVirtualization();
139 haveLargeAsid64
= system
->haveLargeAsid64();
140 physAddrRange64
= system
->physAddrRange64();
142 haveSecurity
= haveLPAE
= haveVirtualization
= false;
143 haveLargeAsid64
= false;
144 physAddrRange64
= 32; // dummy value
147 /** Fill in the miscReg translation table */
148 for (uint32_t i
= 0; i
< miscRegTranslateMax
; i
++) {
149 struct MiscRegLUTEntry new_entry
;
151 uint32_t select
= MiscRegSwitch
[i
].index
;
152 new_entry
= MiscRegSwitch
[i
].entry
;
154 lookUpMiscReg
[select
] = new_entry
;
157 preUnflattenMiscReg();
165 return dynamic_cast<const Params
*>(_params
);
171 const Params
*p(params());
173 SCTLR sctlr_rst
= miscRegs
[MISCREG_SCTLR_RST
];
174 memset(miscRegs
, 0, sizeof(miscRegs
));
176 // Initialize configurable default values
177 miscRegs
[MISCREG_MIDR
] = p
->midr
;
178 miscRegs
[MISCREG_MIDR_EL1
] = p
->midr
;
179 miscRegs
[MISCREG_VPIDR
] = p
->midr
;
181 if (FullSystem
&& system
->highestELIs64()) {
182 // Initialize AArch64 state
187 // Initialize AArch32 state...
190 cpsr
.mode
= MODE_USER
;
191 miscRegs
[MISCREG_CPSR
] = cpsr
;
195 sctlr
.te
= (bool) sctlr_rst
.te
;
196 sctlr
.nmfi
= (bool) sctlr_rst
.nmfi
;
197 sctlr
.v
= (bool) sctlr_rst
.v
;
202 sctlr
.rao4
= 0xf; // SCTLR[6:3]
203 miscRegs
[MISCREG_SCTLR_NS
] = sctlr
;
204 miscRegs
[MISCREG_SCTLR_RST
] = sctlr_rst
;
205 miscRegs
[MISCREG_HCPTR
] = 0;
207 // Start with an event in the mailbox
208 miscRegs
[MISCREG_SEV_MAILBOX
] = 1;
210 // Separate Instruction and Data TLBs
211 miscRegs
[MISCREG_TLBTR
] = 1;
214 mvfr0
.advSimdRegisters
= 2;
215 mvfr0
.singlePrecision
= 2;
216 mvfr0
.doublePrecision
= 2;
217 mvfr0
.vfpExceptionTrapping
= 0;
219 mvfr0
.squareRoot
= 1;
220 mvfr0
.shortVectors
= 1;
221 mvfr0
.roundingModes
= 1;
222 miscRegs
[MISCREG_MVFR0
] = mvfr0
;
225 mvfr1
.flushToZero
= 1;
226 mvfr1
.defaultNaN
= 1;
227 mvfr1
.advSimdLoadStore
= 1;
228 mvfr1
.advSimdInteger
= 1;
229 mvfr1
.advSimdSinglePrecision
= 1;
230 mvfr1
.advSimdHalfPrecision
= 1;
231 mvfr1
.vfpHalfPrecision
= 1;
232 miscRegs
[MISCREG_MVFR1
] = mvfr1
;
234 // Reset values of PRRR and NMRR are implementation dependent
236 // @todo: PRRR and NMRR in secure state?
237 miscRegs
[MISCREG_PRRR_NS
] =
250 miscRegs
[MISCREG_NMRR_NS
] =
267 miscRegs
[MISCREG_CPACR
] = 0;
270 miscRegs
[MISCREG_ID_PFR0
] = p
->id_pfr0
;
271 miscRegs
[MISCREG_ID_PFR1
] = p
->id_pfr1
;
273 miscRegs
[MISCREG_ID_MMFR0
] = p
->id_mmfr0
;
274 miscRegs
[MISCREG_ID_MMFR1
] = p
->id_mmfr1
;
275 miscRegs
[MISCREG_ID_MMFR2
] = p
->id_mmfr2
;
276 miscRegs
[MISCREG_ID_MMFR3
] = p
->id_mmfr3
;
278 miscRegs
[MISCREG_ID_ISAR0
] = p
->id_isar0
;
279 miscRegs
[MISCREG_ID_ISAR1
] = p
->id_isar1
;
280 miscRegs
[MISCREG_ID_ISAR2
] = p
->id_isar2
;
281 miscRegs
[MISCREG_ID_ISAR3
] = p
->id_isar3
;
282 miscRegs
[MISCREG_ID_ISAR4
] = p
->id_isar4
;
283 miscRegs
[MISCREG_ID_ISAR5
] = p
->id_isar5
;
285 miscRegs
[MISCREG_FPSID
] = p
->fpsid
;
288 TTBCR ttbcr
= miscRegs
[MISCREG_TTBCR_NS
];
290 miscRegs
[MISCREG_TTBCR_NS
] = ttbcr
;
291 // Enforce consistency with system-level settings
292 miscRegs
[MISCREG_ID_MMFR0
] = (miscRegs
[MISCREG_ID_MMFR0
] & ~0xf) | 0x5;
296 miscRegs
[MISCREG_SCTLR_S
] = sctlr
;
297 miscRegs
[MISCREG_SCR
] = 0;
298 miscRegs
[MISCREG_VBAR_S
] = 0;
300 // we're always non-secure
301 miscRegs
[MISCREG_SCR
] = 1;
304 //XXX We need to initialize the rest of the state.
308 ISA::clear64(const ArmISAParams
*p
)
311 Addr rvbar
= system
->resetAddr64();
312 switch (system
->highestEL()) {
313 // Set initial EL to highest implemented EL using associated stack
314 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
317 cpsr
.mode
= MODE_EL3H
;
318 miscRegs
[MISCREG_RVBAR_EL3
] = rvbar
;
321 cpsr
.mode
= MODE_EL2H
;
322 miscRegs
[MISCREG_RVBAR_EL2
] = rvbar
;
325 cpsr
.mode
= MODE_EL1H
;
326 miscRegs
[MISCREG_RVBAR_EL1
] = rvbar
;
329 panic("Invalid highest implemented exception level");
333 // Initialize rest of CPSR
334 cpsr
.daif
= 0xf; // Mask all interrupts
337 miscRegs
[MISCREG_CPSR
] = cpsr
;
340 // Initialize other control registers
341 miscRegs
[MISCREG_MPIDR_EL1
] = 0x80000000;
343 miscRegs
[MISCREG_SCTLR_EL3
] = 0x30c50870;
344 miscRegs
[MISCREG_SCR_EL3
] = 0x00000030; // RES1 fields
345 // @todo: uncomment this to enable Virtualization
346 // } else if (haveVirtualization) {
347 // miscRegs[MISCREG_SCTLR_EL2] = 0x30c50870;
349 miscRegs
[MISCREG_SCTLR_EL1
] = 0x30c50870;
351 miscRegs
[MISCREG_SCR_EL3
] = 1;
354 // Initialize configurable id registers
355 miscRegs
[MISCREG_ID_AA64AFR0_EL1
] = p
->id_aa64afr0_el1
;
356 miscRegs
[MISCREG_ID_AA64AFR1_EL1
] = p
->id_aa64afr1_el1
;
357 miscRegs
[MISCREG_ID_AA64DFR0_EL1
] = p
->id_aa64dfr0_el1
;
358 miscRegs
[MISCREG_ID_AA64DFR1_EL1
] = p
->id_aa64dfr1_el1
;
359 miscRegs
[MISCREG_ID_AA64ISAR0_EL1
] = p
->id_aa64isar0_el1
;
360 miscRegs
[MISCREG_ID_AA64ISAR1_EL1
] = p
->id_aa64isar1_el1
;
361 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
] = p
->id_aa64mmfr0_el1
;
362 miscRegs
[MISCREG_ID_AA64MMFR1_EL1
] = p
->id_aa64mmfr1_el1
;
363 miscRegs
[MISCREG_ID_AA64PFR0_EL1
] = p
->id_aa64pfr0_el1
;
364 miscRegs
[MISCREG_ID_AA64PFR1_EL1
] = p
->id_aa64pfr1_el1
;
366 // Enforce consistency with system-level settings...
369 // (no AArch32/64 interprocessing support for now)
370 miscRegs
[MISCREG_ID_AA64PFR0_EL1
] = insertBits(
371 miscRegs
[MISCREG_ID_AA64PFR0_EL1
], 15, 12,
372 haveSecurity
? 0x1 : 0x0);
374 // (no AArch32/64 interprocessing support for now)
375 miscRegs
[MISCREG_ID_AA64PFR0_EL1
] = insertBits(
376 miscRegs
[MISCREG_ID_AA64PFR0_EL1
], 11, 8,
377 haveVirtualization
? 0x1 : 0x0);
378 // Large ASID support
379 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
] = insertBits(
380 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
], 7, 4,
381 haveLargeAsid64
? 0x2 : 0x0);
382 // Physical address size
383 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
] = insertBits(
384 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
], 3, 0,
385 encodePhysAddrRange64(physAddrRange64
));
389 ISA::readMiscRegNoEffect(int misc_reg
) const
391 assert(misc_reg
< NumMiscRegs
);
393 int flat_idx
= flattenMiscIndex(misc_reg
); // Note: indexes of AArch64
394 // registers are left unchanged
397 if (lookUpMiscReg
[flat_idx
].lower
== 0 || flat_idx
== MISCREG_SPSR
398 || flat_idx
== MISCREG_SCTLR_EL1
) {
399 if (flat_idx
== MISCREG_SPSR
)
400 flat_idx
= flattenMiscIndex(MISCREG_SPSR
);
401 if (flat_idx
== MISCREG_SCTLR_EL1
)
402 flat_idx
= flattenMiscIndex(MISCREG_SCTLR
);
403 val
= miscRegs
[flat_idx
];
405 if (lookUpMiscReg
[flat_idx
].upper
> 0)
406 val
= ((miscRegs
[lookUpMiscReg
[flat_idx
].lower
] & mask(32))
407 | (miscRegs
[lookUpMiscReg
[flat_idx
].upper
] << 32));
409 val
= miscRegs
[lookUpMiscReg
[flat_idx
].lower
];
416 ISA::readMiscReg(int misc_reg
, ThreadContext
*tc
)
422 if (misc_reg
== MISCREG_CPSR
) {
423 cpsr
= miscRegs
[misc_reg
];
425 cpsr
.j
= pc
.jazelle() ? 1 : 0;
426 cpsr
.t
= pc
.thumb() ? 1 : 0;
431 if (!miscRegInfo
[misc_reg
][MISCREG_IMPLEMENTED
]) {
432 if (miscRegInfo
[misc_reg
][MISCREG_WARN_NOT_FAIL
])
433 warn("Unimplemented system register %s read.\n",
434 miscRegName
[misc_reg
]);
436 panic("Unimplemented system register %s read.\n",
437 miscRegName
[misc_reg
]);
441 switch (unflattenMiscReg(misc_reg
)) {
444 if (!haveVirtualization
)
447 return readMiscRegNoEffect(MISCREG_HCR
);
451 const uint32_t ones
= (uint32_t)(-1);
453 // Only cp10, cp11, and ase are implemented, nothing else should
454 // be readable? (straight copy from the write code)
455 cpacrMask
.cp10
= ones
;
456 cpacrMask
.cp11
= ones
;
457 cpacrMask
.asedis
= ones
;
459 // Security Extensions may limit the readability of CPACR
461 scr
= readMiscRegNoEffect(MISCREG_SCR
);
462 cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
463 if (scr
.ns
&& (cpsr
.mode
!= MODE_MON
)) {
464 NSACR nsacr
= readMiscRegNoEffect(MISCREG_NSACR
);
465 // NB: Skipping the full loop, here
466 if (!nsacr
.cp10
) cpacrMask
.cp10
= 0;
467 if (!nsacr
.cp11
) cpacrMask
.cp11
= 0;
470 MiscReg val
= readMiscRegNoEffect(MISCREG_CPACR
);
472 DPRINTF(MiscRegs
, "Reading misc reg %s: %#x\n",
473 miscRegName
[misc_reg
], val
);
477 cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
478 scr
= readMiscRegNoEffect(MISCREG_SCR
);
479 if ((cpsr
.mode
== MODE_HYP
) || inSecureState(scr
, cpsr
)) {
480 return getMPIDR(system
, tc
);
482 return readMiscReg(MISCREG_VMPIDR
, tc
);
485 case MISCREG_MPIDR_EL1
:
486 // @todo in the absence of v8 virtualization support just return MPIDR_EL1
487 return getMPIDR(system
, tc
) & 0xffffffff;
489 // top bit defined as RES1
490 return readMiscRegNoEffect(misc_reg
) | 0x80000000;
491 case MISCREG_ID_AFR0
: // not implemented, so alias MIDR
492 case MISCREG_ID_DFR0
: // not implemented, so alias MIDR
493 case MISCREG_REVIDR
: // not implemented, so alias MIDR
495 cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
496 scr
= readMiscRegNoEffect(MISCREG_SCR
);
497 if ((cpsr
.mode
== MODE_HYP
) || inSecureState(scr
, cpsr
)) {
498 return readMiscRegNoEffect(misc_reg
);
500 return readMiscRegNoEffect(MISCREG_VPIDR
);
503 case MISCREG_JOSCR
: // Jazelle trivial implementation, RAZ/WI
504 case MISCREG_JMCR
: // Jazelle trivial implementation, RAZ/WI
505 case MISCREG_JIDR
: // Jazelle trivial implementation, RAZ/WI
506 case MISCREG_AIDR
: // AUX ID set to 0
507 case MISCREG_TCMTR
: // No TCM's
511 warn_once("The clidr register always reports 0 caches.\n");
512 warn_once("clidr LoUIS field of 0b001 to match current "
513 "ARM implementations.\n");
516 warn_once("The ccsidr register isn't implemented and "
517 "always reads as 0.\n");
521 //all caches have the same line size in gem5
522 //4 byte words in ARM
523 unsigned lineSizeWords
=
524 tc
->getSystemPtr()->cacheLineSize() / 4;
525 unsigned log2LineSizeWords
= 0;
527 while (lineSizeWords
>>= 1) {
532 //log2 of minimun i-cache line size (words)
533 ctr
.iCacheLineSize
= log2LineSizeWords
;
534 //b11 - gem5 uses pipt
535 ctr
.l1IndexPolicy
= 0x3;
536 //log2 of minimum d-cache line size (words)
537 ctr
.dCacheLineSize
= log2LineSizeWords
;
538 //log2 of max reservation size (words)
539 ctr
.erg
= log2LineSizeWords
;
540 //log2 of max writeback size (words)
541 ctr
.cwg
= log2LineSizeWords
;
542 //b100 - gem5 format is ARMv7
548 warn("Not doing anything for miscreg ACTLR\n");
551 case MISCREG_PMCCNTR
:
553 warn("Not doing anything for read to miscreg %s\n",
554 miscRegName
[misc_reg
]);
557 panic("shouldn't be reading this register seperately\n");
558 case MISCREG_FPSCR_QC
:
559 return readMiscRegNoEffect(MISCREG_FPSCR
) & ~FpscrQcMask
;
560 case MISCREG_FPSCR_EXC
:
561 return readMiscRegNoEffect(MISCREG_FPSCR
) & ~FpscrExcMask
;
564 const uint32_t ones
= (uint32_t)(-1);
566 fpscrMask
.ioc
= ones
;
567 fpscrMask
.dzc
= ones
;
568 fpscrMask
.ofc
= ones
;
569 fpscrMask
.ufc
= ones
;
570 fpscrMask
.ixc
= ones
;
571 fpscrMask
.idc
= ones
;
577 return readMiscRegNoEffect(MISCREG_FPSCR
) & (uint32_t)fpscrMask
;
581 const uint32_t ones
= (uint32_t)(-1);
583 fpscrMask
.ioe
= ones
;
584 fpscrMask
.dze
= ones
;
585 fpscrMask
.ofe
= ones
;
586 fpscrMask
.ufe
= ones
;
587 fpscrMask
.ixe
= ones
;
588 fpscrMask
.ide
= ones
;
589 fpscrMask
.len
= ones
;
590 fpscrMask
.stride
= ones
;
591 fpscrMask
.rMode
= ones
;
594 fpscrMask
.ahp
= ones
;
595 return readMiscRegNoEffect(MISCREG_FPSCR
) & (uint32_t)fpscrMask
;
600 cpsr
.nz
= tc
->readIntReg(INTREG_CONDCODES_NZ
);
601 cpsr
.c
= tc
->readIntReg(INTREG_CONDCODES_C
);
602 cpsr
.v
= tc
->readIntReg(INTREG_CONDCODES_V
);
608 cpsr
.daif
= (uint8_t) ((CPSR
) miscRegs
[MISCREG_CPSR
]).daif
;
613 return tc
->readIntReg(INTREG_SP0
);
617 return tc
->readIntReg(INTREG_SP1
);
621 return tc
->readIntReg(INTREG_SP2
);
625 return miscRegs
[MISCREG_CPSR
] & 0x1;
627 case MISCREG_CURRENTEL
:
629 return miscRegs
[MISCREG_CPSR
] & 0xc;
633 // mostly unimplemented, just set NumCPUs field from sim and return
635 // b00:1CPU to b11:4CPUs
636 l2ctlr
.numCPUs
= tc
->getSystemPtr()->numContexts() - 1;
639 case MISCREG_DBGDIDR
:
640 /* For now just implement the version number.
641 * Return 0 as we don't support debug architecture yet.
644 case MISCREG_DBGDSCRint
:
647 return tc
->getCpuPtr()->getInterruptController()->getISR(
648 readMiscRegNoEffect(MISCREG_HCR
),
649 readMiscRegNoEffect(MISCREG_CPSR
),
650 readMiscRegNoEffect(MISCREG_SCR
));
651 case MISCREG_ISR_EL1
:
652 return tc
->getCpuPtr()->getInterruptController()->getISR(
653 readMiscRegNoEffect(MISCREG_HCR_EL2
),
654 readMiscRegNoEffect(MISCREG_CPSR
),
655 readMiscRegNoEffect(MISCREG_SCR_EL3
));
656 case MISCREG_DCZID_EL0
:
657 return 0x04; // DC ZVA clear 64-byte chunks
660 MiscReg val
= readMiscRegNoEffect(misc_reg
);
661 // The trap bit associated with CP14 is defined as RAZ
663 // If a CP bit in NSACR is 0 then the corresponding bit in
665 bool secure_lookup
= haveSecurity
&&
666 inSecureState(readMiscRegNoEffect(MISCREG_SCR
),
667 readMiscRegNoEffect(MISCREG_CPSR
));
668 if (!secure_lookup
) {
669 MiscReg mask
= readMiscRegNoEffect(MISCREG_NSACR
);
670 val
|= (mask
^ 0x7FFF) & 0xBFFF;
672 // Set the bits for unimplemented coprocessors to RAO/WI
676 case MISCREG_HDFAR
: // alias for secure DFAR
677 return readMiscRegNoEffect(MISCREG_DFAR_S
);
678 case MISCREG_HIFAR
: // alias for secure IFAR
679 return readMiscRegNoEffect(MISCREG_IFAR_S
);
680 case MISCREG_HVBAR
: // bottom bits reserved
681 return readMiscRegNoEffect(MISCREG_HVBAR
) & 0xFFFFFFE0;
682 case MISCREG_SCTLR
: // Some bits hardwired
683 // The FI field (bit 21) is common between S/NS versions of the register
684 return (readMiscRegNoEffect(MISCREG_SCTLR_S
) & (1 << 21)) |
685 (readMiscRegNoEffect(misc_reg
) & 0x72DD39FF) | 0x00C00818; // V8 SCTLR
686 case MISCREG_SCTLR_EL1
:
687 // The FI field (bit 21) is common between S/NS versions of the register
688 return (readMiscRegNoEffect(MISCREG_SCTLR_S
) & (1 << 21)) |
689 (readMiscRegNoEffect(misc_reg
) & 0x37DDDBFF) | 0x30D00800; // V8 SCTLR_EL1
690 case MISCREG_SCTLR_EL3
:
691 // The FI field (bit 21) is common between S/NS versions of the register
692 return (readMiscRegNoEffect(MISCREG_SCTLR_S
) & (1 << 21)) |
693 (readMiscRegNoEffect(misc_reg
) & 0x32CD183F) | 0x30C50830; // V8 SCTLR_EL3
694 case MISCREG_HSCTLR
: // FI comes from SCTLR
696 uint32_t mask
= 1 << 27;
697 return (readMiscRegNoEffect(MISCREG_HSCTLR
) & ~mask
) |
698 (readMiscRegNoEffect(MISCREG_SCTLR
) & mask
);
702 CPSR cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
704 return readMiscRegNoEffect(MISCREG_SCR
);
706 return readMiscRegNoEffect(MISCREG_SCR_EL3
);
709 // Generic Timer registers
711 case MISCREG_CNTFRQ_EL0
:
712 inform_once("Read CNTFREQ_EL0 frequency\n");
713 return getSystemCounter(tc
)->freq();
715 case MISCREG_CNTPCT_EL0
:
716 return getSystemCounter(tc
)->value();
718 return getSystemCounter(tc
)->value();
719 case MISCREG_CNTVCT_EL0
:
720 return getSystemCounter(tc
)->value();
721 case MISCREG_CNTP_CVAL
:
722 case MISCREG_CNTP_CVAL_EL0
:
723 return getArchTimer(tc
, tc
->cpuId())->compareValue();
724 case MISCREG_CNTP_TVAL
:
725 case MISCREG_CNTP_TVAL_EL0
:
726 return getArchTimer(tc
, tc
->cpuId())->timerValue();
727 case MISCREG_CNTP_CTL
:
728 case MISCREG_CNTP_CTL_EL0
:
729 return getArchTimer(tc
, tc
->cpuId())->control();
730 // PL1 phys. timer, secure
732 // case MISCREG_CNTPS_CVAL_EL1:
733 // case MISCREG_CNTPS_TVAL_EL1:
734 // case MISCREG_CNTPS_CTL_EL1:
735 // PL2 phys. timer, non-secure
737 // case MISCREG_CNTHCTL:
738 // case MISCREG_CNTHP_CVAL:
739 // case MISCREG_CNTHP_TVAL:
740 // case MISCREG_CNTHP_CTL:
742 // case MISCREG_CNTHCTL_EL2:
743 // case MISCREG_CNTHP_CVAL_EL2:
744 // case MISCREG_CNTHP_TVAL_EL2:
745 // case MISCREG_CNTHP_CTL_EL2:
748 // case MISCREG_CNTV_CVAL:
749 // case MISCREG_CNTV_TVAL:
750 // case MISCREG_CNTV_CTL:
752 // case MISCREG_CNTV_CVAL_EL2:
753 // case MISCREG_CNTV_TVAL_EL2:
754 // case MISCREG_CNTV_CTL_EL2:
759 return readMiscRegNoEffect(misc_reg
);
763 ISA::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
)
765 assert(misc_reg
< NumMiscRegs
);
767 int flat_idx
= flattenMiscIndex(misc_reg
); // Note: indexes of AArch64
768 // registers are left unchanged
770 int flat_idx2
= lookUpMiscReg
[flat_idx
].upper
;
773 miscRegs
[lookUpMiscReg
[flat_idx
].lower
] = bits(val
, 31, 0);
774 miscRegs
[flat_idx2
] = bits(val
, 63, 32);
775 DPRINTF(MiscRegs
, "Writing to misc reg %d (%d:%d) : %#x\n",
776 misc_reg
, flat_idx
, flat_idx2
, val
);
778 if (flat_idx
== MISCREG_SPSR
)
779 flat_idx
= flattenMiscIndex(MISCREG_SPSR
);
780 else if (flat_idx
== MISCREG_SCTLR_EL1
)
781 flat_idx
= flattenMiscIndex(MISCREG_SCTLR
);
783 flat_idx
= (lookUpMiscReg
[flat_idx
].lower
> 0) ?
784 lookUpMiscReg
[flat_idx
].lower
: flat_idx
;
785 miscRegs
[flat_idx
] = val
;
786 DPRINTF(MiscRegs
, "Writing to misc reg %d (%d) : %#x\n",
787 misc_reg
, flat_idx
, val
);
792 ISA::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadContext
*tc
)
795 MiscReg newVal
= val
;
805 if (misc_reg
== MISCREG_CPSR
) {
809 CPSR old_cpsr
= miscRegs
[MISCREG_CPSR
];
810 int old_mode
= old_cpsr
.mode
;
812 if (old_mode
!= cpsr
.mode
) {
813 tc
->getITBPtr()->invalidateMiscReg();
814 tc
->getDTBPtr()->invalidateMiscReg();
817 DPRINTF(Arm
, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
818 miscRegs
[misc_reg
], cpsr
, cpsr
.f
, cpsr
.i
, cpsr
.a
, cpsr
.mode
);
819 PCState pc
= tc
->pcState();
820 pc
.nextThumb(cpsr
.t
);
821 pc
.nextJazelle(cpsr
.j
);
823 // Follow slightly different semantics if a CheckerCPU object
825 CheckerCPU
*checker
= tc
->getCheckerCpuPtr();
827 tc
->pcStateNoRecord(pc
);
833 if (!miscRegInfo
[misc_reg
][MISCREG_IMPLEMENTED
]) {
834 if (miscRegInfo
[misc_reg
][MISCREG_WARN_NOT_FAIL
])
835 warn("Unimplemented system register %s write with %#x.\n",
836 miscRegName
[misc_reg
], val
);
838 panic("Unimplemented system register %s write with %#x.\n",
839 miscRegName
[misc_reg
], val
);
842 switch (unflattenMiscReg(misc_reg
)) {
846 const uint32_t ones
= (uint32_t)(-1);
848 // Only cp10, cp11, and ase are implemented, nothing else should
850 cpacrMask
.cp10
= ones
;
851 cpacrMask
.cp11
= ones
;
852 cpacrMask
.asedis
= ones
;
854 // Security Extensions may limit the writability of CPACR
856 scr
= readMiscRegNoEffect(MISCREG_SCR
);
857 CPSR cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
858 if (scr
.ns
&& (cpsr
.mode
!= MODE_MON
)) {
859 NSACR nsacr
= readMiscRegNoEffect(MISCREG_NSACR
);
860 // NB: Skipping the full loop, here
861 if (!nsacr
.cp10
) cpacrMask
.cp10
= 0;
862 if (!nsacr
.cp11
) cpacrMask
.cp11
= 0;
866 MiscReg old_val
= readMiscRegNoEffect(MISCREG_CPACR
);
868 newVal
|= old_val
& ~cpacrMask
;
869 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
870 miscRegName
[misc_reg
], newVal
);
873 case MISCREG_CPACR_EL1
:
875 const uint32_t ones
= (uint32_t)(-1);
877 cpacrMask
.tta
= ones
;
878 cpacrMask
.fpen
= ones
;
880 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
881 miscRegName
[misc_reg
], newVal
);
884 case MISCREG_CPTR_EL2
:
886 const uint32_t ones
= (uint32_t)(-1);
888 cptrMask
.tcpac
= ones
;
893 cptrMask
.res1_13_12_el2
= ones
;
894 cptrMask
.res1_9_0_el2
= ones
;
896 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
897 miscRegName
[misc_reg
], newVal
);
900 case MISCREG_CPTR_EL3
:
902 const uint32_t ones
= (uint32_t)(-1);
904 cptrMask
.tcpac
= ones
;
908 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
909 miscRegName
[misc_reg
], newVal
);
913 warn_once("The csselr register isn't implemented.\n");
916 case MISCREG_DC_ZVA_Xt
:
917 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
922 const uint32_t ones
= (uint32_t)(-1);
924 fpscrMask
.ioc
= ones
;
925 fpscrMask
.dzc
= ones
;
926 fpscrMask
.ofc
= ones
;
927 fpscrMask
.ufc
= ones
;
928 fpscrMask
.ixc
= ones
;
929 fpscrMask
.idc
= ones
;
930 fpscrMask
.ioe
= ones
;
931 fpscrMask
.dze
= ones
;
932 fpscrMask
.ofe
= ones
;
933 fpscrMask
.ufe
= ones
;
934 fpscrMask
.ixe
= ones
;
935 fpscrMask
.ide
= ones
;
936 fpscrMask
.len
= ones
;
937 fpscrMask
.stride
= ones
;
938 fpscrMask
.rMode
= ones
;
941 fpscrMask
.ahp
= ones
;
947 newVal
= (newVal
& (uint32_t)fpscrMask
) |
948 (readMiscRegNoEffect(MISCREG_FPSCR
) &
949 ~(uint32_t)fpscrMask
);
950 tc
->getDecoderPtr()->setContext(newVal
);
955 const uint32_t ones
= (uint32_t)(-1);
957 fpscrMask
.ioc
= ones
;
958 fpscrMask
.dzc
= ones
;
959 fpscrMask
.ofc
= ones
;
960 fpscrMask
.ufc
= ones
;
961 fpscrMask
.ixc
= ones
;
962 fpscrMask
.idc
= ones
;
968 newVal
= (newVal
& (uint32_t)fpscrMask
) |
969 (readMiscRegNoEffect(MISCREG_FPSCR
) &
970 ~(uint32_t)fpscrMask
);
971 misc_reg
= MISCREG_FPSCR
;
976 const uint32_t ones
= (uint32_t)(-1);
978 fpscrMask
.ioe
= ones
;
979 fpscrMask
.dze
= ones
;
980 fpscrMask
.ofe
= ones
;
981 fpscrMask
.ufe
= ones
;
982 fpscrMask
.ixe
= ones
;
983 fpscrMask
.ide
= ones
;
984 fpscrMask
.len
= ones
;
985 fpscrMask
.stride
= ones
;
986 fpscrMask
.rMode
= ones
;
989 fpscrMask
.ahp
= ones
;
990 newVal
= (newVal
& (uint32_t)fpscrMask
) |
991 (readMiscRegNoEffect(MISCREG_FPSCR
) &
992 ~(uint32_t)fpscrMask
);
993 misc_reg
= MISCREG_FPSCR
;
998 assert(!(newVal
& ~CpsrMaskQ
));
999 newVal
= readMiscRegNoEffect(MISCREG_CPSR
) | newVal
;
1000 misc_reg
= MISCREG_CPSR
;
1003 case MISCREG_FPSCR_QC
:
1005 newVal
= readMiscRegNoEffect(MISCREG_FPSCR
) |
1006 (newVal
& FpscrQcMask
);
1007 misc_reg
= MISCREG_FPSCR
;
1010 case MISCREG_FPSCR_EXC
:
1012 newVal
= readMiscRegNoEffect(MISCREG_FPSCR
) |
1013 (newVal
& FpscrExcMask
);
1014 misc_reg
= MISCREG_FPSCR
;
1019 // vfpv3 architecture, section B.6.1 of DDI04068
1020 // bit 29 - valid only if fpexc[31] is 0
1021 const uint32_t fpexcMask
= 0x60000000;
1022 newVal
= (newVal
& fpexcMask
) |
1023 (readMiscRegNoEffect(MISCREG_FPEXC
) & ~fpexcMask
);
1028 if (!haveVirtualization
)
1034 // ARM ARM (ARM DDI 0406C.b) B4.1.96
1035 const uint32_t ifsrMask
=
1036 mask(31, 13) | mask(11, 11) | mask(8, 6);
1037 newVal
= newVal
& ~ifsrMask
;
1042 // ARM ARM (ARM DDI 0406C.b) B4.1.52
1043 const uint32_t dfsrMask
= mask(31, 14) | mask(8, 8);
1044 newVal
= newVal
& ~dfsrMask
;
1047 case MISCREG_AMAIR0
:
1048 case MISCREG_AMAIR1
:
1050 // ARM ARM (ARM DDI 0406C.b) B4.1.5
1051 // Valid only with LPAE
1054 DPRINTF(MiscRegs
, "Writing AMAIR: %#x\n", newVal
);
1058 tc
->getITBPtr()->invalidateMiscReg();
1059 tc
->getDTBPtr()->invalidateMiscReg();
1063 DPRINTF(MiscRegs
, "Writing SCTLR: %#x\n", newVal
);
1064 MiscRegIndex sctlr_idx
;
1065 scr
= readMiscRegNoEffect(MISCREG_SCR
);
1066 if (haveSecurity
&& !scr
.ns
) {
1067 sctlr_idx
= MISCREG_SCTLR_S
;
1069 sctlr_idx
= MISCREG_SCTLR_NS
;
1070 // The FI field (bit 21) is common between S/NS versions
1071 // of the register, we store this in the secure copy of
1073 miscRegs
[MISCREG_SCTLR_S
] &= ~(1 << 21);
1074 miscRegs
[MISCREG_SCTLR_S
] |= newVal
& (1 << 21);
1076 SCTLR sctlr
= miscRegs
[sctlr_idx
];
1077 SCTLR new_sctlr
= newVal
;
1078 new_sctlr
.nmfi
= ((bool)sctlr
.nmfi
) && !haveVirtualization
;
1079 miscRegs
[sctlr_idx
] = (MiscReg
)new_sctlr
;
1080 tc
->getITBPtr()->invalidateMiscReg();
1081 tc
->getDTBPtr()->invalidateMiscReg();
1083 // Check if all CPUs are booted with caches enabled
1084 // so we can stop enforcing coherency of some kernel
1085 // structures manually.
1086 sys
= tc
->getSystemPtr();
1087 for (x
= 0; x
< sys
->numContexts(); x
++) {
1088 oc
= sys
->getThreadContext(x
);
1089 // @todo: double check this for security
1090 SCTLR other_sctlr
= oc
->readMiscRegNoEffect(MISCREG_SCTLR
);
1091 if (!other_sctlr
.c
&& oc
->status() != ThreadContext::Halted
)
1095 for (x
= 0; x
< sys
->numContexts(); x
++) {
1096 oc
= sys
->getThreadContext(x
);
1097 oc
->getDTBPtr()->allCpusCaching();
1098 oc
->getITBPtr()->allCpusCaching();
1100 // If CheckerCPU is connected, need to notify it.
1101 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1103 checker
->getDTBPtr()->allCpusCaching();
1104 checker
->getITBPtr()->allCpusCaching();
1111 case MISCREG_ID_PFR0
:
1112 case MISCREG_ID_PFR1
:
1113 case MISCREG_ID_MMFR0
:
1114 case MISCREG_ID_MMFR1
:
1115 case MISCREG_ID_MMFR2
:
1116 case MISCREG_ID_MMFR3
:
1117 case MISCREG_ID_ISAR0
:
1118 case MISCREG_ID_ISAR1
:
1119 case MISCREG_ID_ISAR2
:
1120 case MISCREG_ID_ISAR3
:
1121 case MISCREG_ID_ISAR4
:
1122 case MISCREG_ID_ISAR5
:
1130 case MISCREG_ID_AA64AFR0_EL1
:
1131 case MISCREG_ID_AA64AFR1_EL1
:
1132 case MISCREG_ID_AA64DFR0_EL1
:
1133 case MISCREG_ID_AA64DFR1_EL1
:
1134 case MISCREG_ID_AA64ISAR0_EL1
:
1135 case MISCREG_ID_AA64ISAR1_EL1
:
1136 case MISCREG_ID_AA64MMFR0_EL1
:
1137 case MISCREG_ID_AA64MMFR1_EL1
:
1138 case MISCREG_ID_AA64PFR0_EL1
:
1139 case MISCREG_ID_AA64PFR1_EL1
:
1140 // ID registers are constants.
1143 // TLBI all entries, EL0&1 inner sharable (ignored)
1144 case MISCREG_TLBIALLIS
:
1145 case MISCREG_TLBIALL
: // TLBI all entries, EL0&1,
1147 target_el
= 1; // el 0 and 1 are handled together
1148 scr
= readMiscReg(MISCREG_SCR
, tc
);
1149 secure_lookup
= haveSecurity
&& !scr
.ns
;
1150 sys
= tc
->getSystemPtr();
1151 for (x
= 0; x
< sys
->numContexts(); x
++) {
1152 oc
= sys
->getThreadContext(x
);
1153 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1154 oc
->getITBPtr()->flushAllSecurity(secure_lookup
, target_el
);
1155 oc
->getDTBPtr()->flushAllSecurity(secure_lookup
, target_el
);
1157 // If CheckerCPU is connected, need to notify it of a flush
1158 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1160 checker
->getITBPtr()->flushAllSecurity(secure_lookup
,
1162 checker
->getDTBPtr()->flushAllSecurity(secure_lookup
,
1167 // TLBI all entries, EL0&1, instruction side
1168 case MISCREG_ITLBIALL
:
1170 target_el
= 1; // el 0 and 1 are handled together
1171 scr
= readMiscReg(MISCREG_SCR
, tc
);
1172 secure_lookup
= haveSecurity
&& !scr
.ns
;
1173 tc
->getITBPtr()->flushAllSecurity(secure_lookup
, target_el
);
1175 // TLBI all entries, EL0&1, data side
1176 case MISCREG_DTLBIALL
:
1178 target_el
= 1; // el 0 and 1 are handled together
1179 scr
= readMiscReg(MISCREG_SCR
, tc
);
1180 secure_lookup
= haveSecurity
&& !scr
.ns
;
1181 tc
->getDTBPtr()->flushAllSecurity(secure_lookup
, target_el
);
1183 // TLBI based on VA, EL0&1 inner sharable (ignored)
1184 case MISCREG_TLBIMVAIS
:
1185 case MISCREG_TLBIMVA
:
1187 target_el
= 1; // el 0 and 1 are handled together
1188 scr
= readMiscReg(MISCREG_SCR
, tc
);
1189 secure_lookup
= haveSecurity
&& !scr
.ns
;
1190 sys
= tc
->getSystemPtr();
1191 for (x
= 0; x
< sys
->numContexts(); x
++) {
1192 oc
= sys
->getThreadContext(x
);
1193 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1194 oc
->getITBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
1196 secure_lookup
, target_el
);
1197 oc
->getDTBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
1199 secure_lookup
, target_el
);
1201 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1203 checker
->getITBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
1204 bits(newVal
, 7,0), secure_lookup
, target_el
);
1205 checker
->getDTBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
1206 bits(newVal
, 7,0), secure_lookup
, target_el
);
1210 // TLBI by ASID, EL0&1, inner sharable
1211 case MISCREG_TLBIASIDIS
:
1212 case MISCREG_TLBIASID
:
1214 target_el
= 1; // el 0 and 1 are handled together
1215 scr
= readMiscReg(MISCREG_SCR
, tc
);
1216 secure_lookup
= haveSecurity
&& !scr
.ns
;
1217 sys
= tc
->getSystemPtr();
1218 for (x
= 0; x
< sys
->numContexts(); x
++) {
1219 oc
= sys
->getThreadContext(x
);
1220 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1221 oc
->getITBPtr()->flushAsid(bits(newVal
, 7,0),
1222 secure_lookup
, target_el
);
1223 oc
->getDTBPtr()->flushAsid(bits(newVal
, 7,0),
1224 secure_lookup
, target_el
);
1225 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1227 checker
->getITBPtr()->flushAsid(bits(newVal
, 7,0),
1228 secure_lookup
, target_el
);
1229 checker
->getDTBPtr()->flushAsid(bits(newVal
, 7,0),
1230 secure_lookup
, target_el
);
1234 // TLBI by address, EL0&1, inner sharable (ignored)
1235 case MISCREG_TLBIMVAAIS
:
1236 case MISCREG_TLBIMVAA
:
1238 target_el
= 1; // el 0 and 1 are handled together
1239 scr
= readMiscReg(MISCREG_SCR
, tc
);
1240 secure_lookup
= haveSecurity
&& !scr
.ns
;
1242 tlbiMVA(tc
, newVal
, secure_lookup
, hyp
, target_el
);
1244 // TLBI by address, EL2, hypervisor mode
1245 case MISCREG_TLBIMVAH
:
1246 case MISCREG_TLBIMVAHIS
:
1248 target_el
= 1; // aarch32, use hyp bit
1249 scr
= readMiscReg(MISCREG_SCR
, tc
);
1250 secure_lookup
= haveSecurity
&& !scr
.ns
;
1252 tlbiMVA(tc
, newVal
, secure_lookup
, hyp
, target_el
);
1254 // TLBI by address and asid, EL0&1, instruction side only
1255 case MISCREG_ITLBIMVA
:
1257 target_el
= 1; // el 0 and 1 are handled together
1258 scr
= readMiscReg(MISCREG_SCR
, tc
);
1259 secure_lookup
= haveSecurity
&& !scr
.ns
;
1260 tc
->getITBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
1261 bits(newVal
, 7,0), secure_lookup
, target_el
);
1263 // TLBI by address and asid, EL0&1, data side only
1264 case MISCREG_DTLBIMVA
:
1266 target_el
= 1; // el 0 and 1 are handled together
1267 scr
= readMiscReg(MISCREG_SCR
, tc
);
1268 secure_lookup
= haveSecurity
&& !scr
.ns
;
1269 tc
->getDTBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
1270 bits(newVal
, 7,0), secure_lookup
, target_el
);
1272 // TLBI by ASID, EL0&1, instrution side only
1273 case MISCREG_ITLBIASID
:
1275 target_el
= 1; // el 0 and 1 are handled together
1276 scr
= readMiscReg(MISCREG_SCR
, tc
);
1277 secure_lookup
= haveSecurity
&& !scr
.ns
;
1278 tc
->getITBPtr()->flushAsid(bits(newVal
, 7,0), secure_lookup
,
1281 // TLBI by ASID EL0&1 data size only
1282 case MISCREG_DTLBIASID
:
1284 target_el
= 1; // el 0 and 1 are handled together
1285 scr
= readMiscReg(MISCREG_SCR
, tc
);
1286 secure_lookup
= haveSecurity
&& !scr
.ns
;
1287 tc
->getDTBPtr()->flushAsid(bits(newVal
, 7,0), secure_lookup
,
1290 // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB
1291 case MISCREG_TLBIALLNSNH
:
1292 case MISCREG_TLBIALLNSNHIS
:
1294 target_el
= 1; // el 0 and 1 are handled together
1296 tlbiALLN(tc
, hyp
, target_el
);
1298 // TLBI all entries, EL2, hyp,
1299 case MISCREG_TLBIALLH
:
1300 case MISCREG_TLBIALLHIS
:
1302 target_el
= 1; // aarch32, use hyp bit
1304 tlbiALLN(tc
, hyp
, target_el
);
1306 // AArch64 TLBI: invalidate all entries EL3
1307 case MISCREG_TLBI_ALLE3IS
:
1308 case MISCREG_TLBI_ALLE3
:
1311 secure_lookup
= true;
1312 tlbiALL(tc
, secure_lookup
, target_el
);
1314 // @todo: uncomment this to enable Virtualization
1315 // case MISCREG_TLBI_ALLE2IS:
1316 // case MISCREG_TLBI_ALLE2:
1317 // TLBI all entries, EL0&1
1318 case MISCREG_TLBI_ALLE1IS
:
1319 case MISCREG_TLBI_ALLE1
:
1320 // AArch64 TLBI: invalidate all entries, stage 1, current VMID
1321 case MISCREG_TLBI_VMALLE1IS
:
1322 case MISCREG_TLBI_VMALLE1
:
1323 // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID
1324 case MISCREG_TLBI_VMALLS12E1IS
:
1325 case MISCREG_TLBI_VMALLS12E1
:
1326 // @todo: handle VMID and stage 2 to enable Virtualization
1328 target_el
= 1; // el 0 and 1 are handled together
1329 scr
= readMiscReg(MISCREG_SCR
, tc
);
1330 secure_lookup
= haveSecurity
&& !scr
.ns
;
1331 tlbiALL(tc
, secure_lookup
, target_el
);
1333 // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID
1334 // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries
1335 // from the last level of translation table walks
1336 // @todo: handle VMID to enable Virtualization
1337 // TLBI all entries, EL0&1
1338 case MISCREG_TLBI_VAE3IS_Xt
:
1339 case MISCREG_TLBI_VAE3_Xt
:
1340 // TLBI by VA, EL3 regime stage 1, last level walk
1341 case MISCREG_TLBI_VALE3IS_Xt
:
1342 case MISCREG_TLBI_VALE3_Xt
:
1345 asid
= 0xbeef; // does not matter, tlbi is global
1346 secure_lookup
= true;
1347 tlbiVA(tc
, newVal
, asid
, secure_lookup
, target_el
);
1350 case MISCREG_TLBI_VAE2IS_Xt
:
1351 case MISCREG_TLBI_VAE2_Xt
:
1352 // TLBI by VA, EL2, stage1 last level walk
1353 case MISCREG_TLBI_VALE2IS_Xt
:
1354 case MISCREG_TLBI_VALE2_Xt
:
1357 asid
= 0xbeef; // does not matter, tlbi is global
1358 scr
= readMiscReg(MISCREG_SCR
, tc
);
1359 secure_lookup
= haveSecurity
&& !scr
.ns
;
1360 tlbiVA(tc
, newVal
, asid
, secure_lookup
, target_el
);
1362 // TLBI by VA EL1 & 0, stage1, ASID, current VMID
1363 case MISCREG_TLBI_VAE1IS_Xt
:
1364 case MISCREG_TLBI_VAE1_Xt
:
1365 case MISCREG_TLBI_VALE1IS_Xt
:
1366 case MISCREG_TLBI_VALE1_Xt
:
1368 asid
= bits(newVal
, 63, 48);
1369 target_el
= 1; // el 0 and 1 are handled together
1370 scr
= readMiscReg(MISCREG_SCR
, tc
);
1371 secure_lookup
= haveSecurity
&& !scr
.ns
;
1372 tlbiVA(tc
, newVal
, asid
, secure_lookup
, target_el
);
1374 // AArch64 TLBI: invalidate by ASID, stage 1, current VMID
1375 // @todo: handle VMID to enable Virtualization
1376 case MISCREG_TLBI_ASIDE1IS_Xt
:
1377 case MISCREG_TLBI_ASIDE1_Xt
:
1379 target_el
= 1; // el 0 and 1 are handled together
1380 scr
= readMiscReg(MISCREG_SCR
, tc
);
1381 secure_lookup
= haveSecurity
&& !scr
.ns
;
1382 sys
= tc
->getSystemPtr();
1383 for (x
= 0; x
< sys
->numContexts(); x
++) {
1384 oc
= sys
->getThreadContext(x
);
1385 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1386 asid
= bits(newVal
, 63, 48);
1387 if (haveLargeAsid64
)
1389 oc
->getITBPtr()->flushAsid(asid
, secure_lookup
, target_el
);
1390 oc
->getDTBPtr()->flushAsid(asid
, secure_lookup
, target_el
);
1391 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1393 checker
->getITBPtr()->flushAsid(asid
,
1394 secure_lookup
, target_el
);
1395 checker
->getDTBPtr()->flushAsid(asid
,
1396 secure_lookup
, target_el
);
1400 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID
1401 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1402 // entries from the last level of translation table walks
1403 // @todo: handle VMID to enable Virtualization
1404 case MISCREG_TLBI_VAAE1IS_Xt
:
1405 case MISCREG_TLBI_VAAE1_Xt
:
1406 case MISCREG_TLBI_VAALE1IS_Xt
:
1407 case MISCREG_TLBI_VAALE1_Xt
:
1409 target_el
= 1; // el 0 and 1 are handled together
1410 scr
= readMiscReg(MISCREG_SCR
, tc
);
1411 secure_lookup
= haveSecurity
&& !scr
.ns
;
1412 sys
= tc
->getSystemPtr();
1413 for (x
= 0; x
< sys
->numContexts(); x
++) {
1414 // @todo: extra controls on TLBI broadcast?
1415 oc
= sys
->getThreadContext(x
);
1416 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1417 Addr va
= ((Addr
) bits(newVal
, 43, 0)) << 12;
1418 oc
->getITBPtr()->flushMva(va
,
1419 secure_lookup
, false, target_el
);
1420 oc
->getDTBPtr()->flushMva(va
,
1421 secure_lookup
, false, target_el
);
1423 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1425 checker
->getITBPtr()->flushMva(va
,
1426 secure_lookup
, false, target_el
);
1427 checker
->getDTBPtr()->flushMva(va
,
1428 secure_lookup
, false, target_el
);
1432 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID
1433 case MISCREG_TLBI_IPAS2LE1IS_Xt
:
1434 case MISCREG_TLBI_IPAS2LE1_Xt
:
1435 case MISCREG_TLBI_IPAS2E1IS_Xt
:
1436 case MISCREG_TLBI_IPAS2E1_Xt
:
1438 // @todo: implement these as part of Virtualization
1439 warn("Not doing anything for write of miscreg ITLB_IPAS2\n");
1442 warn("Not doing anything for write of miscreg ACTLR\n");
1446 // Performance counters not implemented. Instead, interpret
1447 // a reset command to this register to reset the simulator
1449 // PMCR_E | PMCR_P | PMCR_C
1450 const int ResetAndEnableCounters
= 0x7;
1451 if (newVal
== ResetAndEnableCounters
) {
1452 inform("Resetting all simobject stats\n");
1453 Stats::schedStatEvent(false, true);
1457 case MISCREG_PMCCNTR
:
1458 case MISCREG_PMSELR
:
1459 warn("Not doing anything for write to miscreg %s\n",
1460 miscRegName
[misc_reg
]);
1462 case MISCREG_HSTR
: // TJDBX, now redifined to be RES0
1466 newVal
&= ~((uint32_t) hstrMask
);
1471 // If a CP bit in NSACR is 0 then the corresponding bit in
1472 // HCPTR is RAO/WI. Same applies to NSASEDIS
1473 secure_lookup
= haveSecurity
&&
1474 inSecureState(readMiscRegNoEffect(MISCREG_SCR
),
1475 readMiscRegNoEffect(MISCREG_CPSR
));
1476 if (!secure_lookup
) {
1477 MiscReg oldValue
= readMiscRegNoEffect(MISCREG_HCPTR
);
1478 MiscReg mask
= (readMiscRegNoEffect(MISCREG_NSACR
) ^ 0x7FFF) & 0xBFFF;
1479 newVal
= (newVal
& ~mask
) | (oldValue
& mask
);
1483 case MISCREG_HDFAR
: // alias for secure DFAR
1484 misc_reg
= MISCREG_DFAR_S
;
1486 case MISCREG_HIFAR
: // alias for secure IFAR
1487 misc_reg
= MISCREG_IFAR_S
;
1489 case MISCREG_ATS1CPR
:
1490 case MISCREG_ATS1CPW
:
1491 case MISCREG_ATS1CUR
:
1492 case MISCREG_ATS1CUW
:
1493 case MISCREG_ATS12NSOPR
:
1494 case MISCREG_ATS12NSOPW
:
1495 case MISCREG_ATS12NSOUR
:
1496 case MISCREG_ATS12NSOUW
:
1497 case MISCREG_ATS1HR
:
1498 case MISCREG_ATS1HW
:
1500 RequestPtr req
= new Request
;
1502 BaseTLB::Mode mode
= BaseTLB::Read
;
1503 TLB::ArmTranslationType tranType
= TLB::NormalTran
;
1506 case MISCREG_ATS1CPR
:
1507 flags
= TLB::MustBeOne
;
1508 tranType
= TLB::S1CTran
;
1509 mode
= BaseTLB::Read
;
1511 case MISCREG_ATS1CPW
:
1512 flags
= TLB::MustBeOne
;
1513 tranType
= TLB::S1CTran
;
1514 mode
= BaseTLB::Write
;
1516 case MISCREG_ATS1CUR
:
1517 flags
= TLB::MustBeOne
| TLB::UserMode
;
1518 tranType
= TLB::S1CTran
;
1519 mode
= BaseTLB::Read
;
1521 case MISCREG_ATS1CUW
:
1522 flags
= TLB::MustBeOne
| TLB::UserMode
;
1523 tranType
= TLB::S1CTran
;
1524 mode
= BaseTLB::Write
;
1526 case MISCREG_ATS12NSOPR
:
1528 panic("Security Extensions required for ATS12NSOPR");
1529 flags
= TLB::MustBeOne
;
1530 tranType
= TLB::S1S2NsTran
;
1531 mode
= BaseTLB::Read
;
1533 case MISCREG_ATS12NSOPW
:
1535 panic("Security Extensions required for ATS12NSOPW");
1536 flags
= TLB::MustBeOne
;
1537 tranType
= TLB::S1S2NsTran
;
1538 mode
= BaseTLB::Write
;
1540 case MISCREG_ATS12NSOUR
:
1542 panic("Security Extensions required for ATS12NSOUR");
1543 flags
= TLB::MustBeOne
| TLB::UserMode
;
1544 tranType
= TLB::S1S2NsTran
;
1545 mode
= BaseTLB::Read
;
1547 case MISCREG_ATS12NSOUW
:
1549 panic("Security Extensions required for ATS12NSOUW");
1550 flags
= TLB::MustBeOne
| TLB::UserMode
;
1551 tranType
= TLB::S1S2NsTran
;
1552 mode
= BaseTLB::Write
;
1554 case MISCREG_ATS1HR
: // only really useful from secure mode.
1555 flags
= TLB::MustBeOne
;
1556 tranType
= TLB::HypMode
;
1557 mode
= BaseTLB::Read
;
1559 case MISCREG_ATS1HW
:
1560 flags
= TLB::MustBeOne
;
1561 tranType
= TLB::HypMode
;
1562 mode
= BaseTLB::Write
;
1565 // If we're in timing mode then doing the translation in
1566 // functional mode then we're slightly distorting performance
1567 // results obtained from simulations. The translation should be
1568 // done in the same mode the core is running in. NOTE: This
1569 // can't be an atomic translation because that causes problems
1570 // with unexpected atomic snoop requests.
1571 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg
);
1572 req
->setVirt(0, val
, 1, flags
, Request::funcMasterId
,
1573 tc
->pcState().pc());
1574 req
->setThreadContext(tc
->contextId(), tc
->threadId());
1575 fault
= tc
->getDTBPtr()->translateFunctional(req
, tc
, mode
, tranType
);
1576 TTBCR ttbcr
= readMiscRegNoEffect(MISCREG_TTBCR
);
1577 HCR hcr
= readMiscRegNoEffect(MISCREG_HCR
);
1580 if (fault
== NoFault
) {
1581 Addr paddr
= req
->getPaddr();
1582 if (haveLPAE
&& (ttbcr
.eae
|| tranType
& TLB::HypMode
||
1583 ((tranType
& TLB::S1S2NsTran
) && hcr
.vm
) )) {
1584 newVal
= (paddr
& mask(39, 12)) |
1585 (tc
->getDTBPtr()->getAttr());
1587 newVal
= (paddr
& 0xfffff000) |
1588 (tc
->getDTBPtr()->getAttr());
1591 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
1594 ArmFault
*armFault
= reinterpret_cast<ArmFault
*>(fault
.get());
1595 // Set fault bit and FSR
1596 FSR fsr
= armFault
->getFsr(tc
);
1598 newVal
= ((fsr
>> 9) & 1) << 11;
1600 // LPAE - rearange fault status
1601 newVal
|= ((fsr
>> 0) & 0x3f) << 1;
1603 // VMSA - rearange fault status
1604 newVal
|= ((fsr
>> 0) & 0xf) << 1;
1605 newVal
|= ((fsr
>> 10) & 0x1) << 5;
1606 newVal
|= ((fsr
>> 12) & 0x1) << 6;
1608 newVal
|= 0x1; // F bit
1609 newVal
|= ((armFault
->iss() >> 7) & 0x1) << 8;
1610 newVal
|= armFault
->isStage2() ? 0x200 : 0;
1612 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
1616 setMiscRegNoEffect(MISCREG_PAR
, newVal
);
1621 TTBCR ttbcr
= readMiscRegNoEffect(MISCREG_TTBCR
);
1622 const uint32_t ones
= (uint32_t)(-1);
1623 TTBCR ttbcrMask
= 0;
1624 TTBCR ttbcrNew
= newVal
;
1626 // ARM DDI 0406C.b, ARMv7-32
1627 ttbcrMask
.n
= ones
; // T0SZ
1629 ttbcrMask
.pd0
= ones
;
1630 ttbcrMask
.pd1
= ones
;
1632 ttbcrMask
.epd0
= ones
;
1633 ttbcrMask
.irgn0
= ones
;
1634 ttbcrMask
.orgn0
= ones
;
1635 ttbcrMask
.sh0
= ones
;
1636 ttbcrMask
.ps
= ones
; // T1SZ
1637 ttbcrMask
.a1
= ones
;
1638 ttbcrMask
.epd1
= ones
;
1639 ttbcrMask
.irgn1
= ones
;
1640 ttbcrMask
.orgn1
= ones
;
1641 ttbcrMask
.sh1
= ones
;
1643 ttbcrMask
.eae
= ones
;
1645 if (haveLPAE
&& ttbcrNew
.eae
) {
1646 newVal
= newVal
& ttbcrMask
;
1648 newVal
= (newVal
& ttbcrMask
) | (ttbcr
& (~ttbcrMask
));
1654 TTBCR ttbcr
= readMiscRegNoEffect(MISCREG_TTBCR
);
1657 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1658 // ARMv8 AArch32 bit 63-56 only
1659 uint64_t ttbrMask
= mask(63,56) | mask(47,40);
1660 newVal
= (newVal
& (~ttbrMask
));
1664 case MISCREG_CONTEXTIDR
:
1671 case MISCREG_SCR_EL3
:
1672 case MISCREG_SCTLR_EL1
:
1673 case MISCREG_SCTLR_EL2
:
1674 case MISCREG_SCTLR_EL3
:
1675 case MISCREG_TCR_EL1
:
1676 case MISCREG_TCR_EL2
:
1677 case MISCREG_TCR_EL3
:
1678 case MISCREG_TTBR0_EL1
:
1679 case MISCREG_TTBR1_EL1
:
1680 case MISCREG_TTBR0_EL2
:
1681 case MISCREG_TTBR0_EL3
:
1682 tc
->getITBPtr()->invalidateMiscReg();
1683 tc
->getDTBPtr()->invalidateMiscReg();
1689 tc
->setIntReg(INTREG_CONDCODES_NZ
, cpsr
.nz
);
1690 tc
->setIntReg(INTREG_CONDCODES_C
, cpsr
.c
);
1691 tc
->setIntReg(INTREG_CONDCODES_V
, cpsr
.v
);
1696 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1697 cpsr
.daif
= (uint8_t) ((CPSR
) newVal
).daif
;
1699 misc_reg
= MISCREG_CPSR
;
1702 case MISCREG_SP_EL0
:
1703 tc
->setIntReg(INTREG_SP0
, newVal
);
1705 case MISCREG_SP_EL1
:
1706 tc
->setIntReg(INTREG_SP1
, newVal
);
1708 case MISCREG_SP_EL2
:
1709 tc
->setIntReg(INTREG_SP2
, newVal
);
1713 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1714 cpsr
.sp
= (uint8_t) ((CPSR
) newVal
).sp
;
1716 misc_reg
= MISCREG_CPSR
;
1719 case MISCREG_CURRENTEL
:
1721 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1722 cpsr
.el
= (uint8_t) ((CPSR
) newVal
).el
;
1724 misc_reg
= MISCREG_CPSR
;
1727 case MISCREG_AT_S1E1R_Xt
:
1728 case MISCREG_AT_S1E1W_Xt
:
1729 case MISCREG_AT_S1E0R_Xt
:
1730 case MISCREG_AT_S1E0W_Xt
:
1731 case MISCREG_AT_S1E2R_Xt
:
1732 case MISCREG_AT_S1E2W_Xt
:
1733 case MISCREG_AT_S12E1R_Xt
:
1734 case MISCREG_AT_S12E1W_Xt
:
1735 case MISCREG_AT_S12E0R_Xt
:
1736 case MISCREG_AT_S12E0W_Xt
:
1737 case MISCREG_AT_S1E3R_Xt
:
1738 case MISCREG_AT_S1E3W_Xt
:
1740 RequestPtr req
= new Request
;
1742 BaseTLB::Mode mode
= BaseTLB::Read
;
1743 TLB::ArmTranslationType tranType
= TLB::NormalTran
;
1746 case MISCREG_AT_S1E1R_Xt
:
1747 flags
= TLB::MustBeOne
;
1748 tranType
= TLB::S1CTran
;
1749 mode
= BaseTLB::Read
;
1751 case MISCREG_AT_S1E1W_Xt
:
1752 flags
= TLB::MustBeOne
;
1753 tranType
= TLB::S1CTran
;
1754 mode
= BaseTLB::Write
;
1756 case MISCREG_AT_S1E0R_Xt
:
1757 flags
= TLB::MustBeOne
| TLB::UserMode
;
1758 tranType
= TLB::S1CTran
;
1759 mode
= BaseTLB::Read
;
1761 case MISCREG_AT_S1E0W_Xt
:
1762 flags
= TLB::MustBeOne
| TLB::UserMode
;
1763 tranType
= TLB::S1CTran
;
1764 mode
= BaseTLB::Write
;
1766 case MISCREG_AT_S1E2R_Xt
:
1767 flags
= TLB::MustBeOne
;
1768 tranType
= TLB::HypMode
;
1769 mode
= BaseTLB::Read
;
1771 case MISCREG_AT_S1E2W_Xt
:
1772 flags
= TLB::MustBeOne
;
1773 tranType
= TLB::HypMode
;
1774 mode
= BaseTLB::Write
;
1776 case MISCREG_AT_S12E0R_Xt
:
1777 flags
= TLB::MustBeOne
| TLB::UserMode
;
1778 tranType
= TLB::S1S2NsTran
;
1779 mode
= BaseTLB::Read
;
1781 case MISCREG_AT_S12E0W_Xt
:
1782 flags
= TLB::MustBeOne
| TLB::UserMode
;
1783 tranType
= TLB::S1S2NsTran
;
1784 mode
= BaseTLB::Write
;
1786 case MISCREG_AT_S12E1R_Xt
:
1787 flags
= TLB::MustBeOne
;
1788 tranType
= TLB::S1S2NsTran
;
1789 mode
= BaseTLB::Read
;
1791 case MISCREG_AT_S12E1W_Xt
:
1792 flags
= TLB::MustBeOne
;
1793 tranType
= TLB::S1S2NsTran
;
1794 mode
= BaseTLB::Write
;
1796 case MISCREG_AT_S1E3R_Xt
:
1797 flags
= TLB::MustBeOne
;
1798 tranType
= TLB::HypMode
; // There is no TZ mode defined.
1799 mode
= BaseTLB::Read
;
1801 case MISCREG_AT_S1E3W_Xt
:
1802 flags
= TLB::MustBeOne
;
1803 tranType
= TLB::HypMode
; // There is no TZ mode defined.
1804 mode
= BaseTLB::Write
;
1807 // If we're in timing mode then doing the translation in
1808 // functional mode then we're slightly distorting performance
1809 // results obtained from simulations. The translation should be
1810 // done in the same mode the core is running in. NOTE: This
1811 // can't be an atomic translation because that causes problems
1812 // with unexpected atomic snoop requests.
1813 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg
);
1814 req
->setVirt(0, val
, 1, flags
, Request::funcMasterId
,
1815 tc
->pcState().pc());
1816 req
->setThreadContext(tc
->contextId(), tc
->threadId());
1817 fault
= tc
->getDTBPtr()->translateFunctional(req
, tc
, mode
,
1821 if (fault
== NoFault
) {
1822 Addr paddr
= req
->getPaddr();
1823 uint64_t attr
= tc
->getDTBPtr()->getAttr();
1824 uint64_t attr1
= attr
>> 56;
1825 if (!attr1
|| attr1
==0x44) {
1827 attr
&= ~ uint64_t(0x80);
1829 newVal
= (paddr
& mask(47, 12)) | attr
;
1831 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
1834 ArmFault
*armFault
= reinterpret_cast<ArmFault
*>(fault
.get());
1835 // Set fault bit and FSR
1836 FSR fsr
= armFault
->getFsr(tc
);
1838 newVal
= ((fsr
>> 9) & 1) << 11;
1839 // rearange fault status
1840 newVal
|= ((fsr
>> 0) & 0x3f) << 1;
1841 newVal
|= 0x1; // F bit
1842 newVal
|= ((armFault
->iss() >> 7) & 0x1) << 8;
1843 newVal
|= armFault
->isStage2() ? 0x200 : 0;
1845 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
1849 setMiscRegNoEffect(MISCREG_PAR_EL1
, newVal
);
1852 case MISCREG_SPSR_EL3
:
1853 case MISCREG_SPSR_EL2
:
1854 case MISCREG_SPSR_EL1
:
1855 // Force bits 23:21 to 0
1856 newVal
= val
& ~(0x7 << 21);
1858 case MISCREG_L2CTLR
:
1859 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
1860 miscRegName
[misc_reg
], uint32_t(val
));
1863 // Generic Timer registers
1864 case MISCREG_CNTFRQ
:
1865 case MISCREG_CNTFRQ_EL0
:
1866 getSystemCounter(tc
)->setFreq(val
);
1868 case MISCREG_CNTP_CVAL
:
1869 case MISCREG_CNTP_CVAL_EL0
:
1870 getArchTimer(tc
, tc
->cpuId())->setCompareValue(val
);
1872 case MISCREG_CNTP_TVAL
:
1873 case MISCREG_CNTP_TVAL_EL0
:
1874 getArchTimer(tc
, tc
->cpuId())->setTimerValue(val
);
1876 case MISCREG_CNTP_CTL
:
1877 case MISCREG_CNTP_CTL_EL0
:
1878 getArchTimer(tc
, tc
->cpuId())->setControl(val
);
1880 // PL1 phys. timer, secure
1882 case MISCREG_CNTPS_CVAL_EL1
:
1883 case MISCREG_CNTPS_TVAL_EL1
:
1884 case MISCREG_CNTPS_CTL_EL1
:
1885 // PL2 phys. timer, non-secure
1887 case MISCREG_CNTHCTL
:
1888 case MISCREG_CNTHP_CVAL
:
1889 case MISCREG_CNTHP_TVAL
:
1890 case MISCREG_CNTHP_CTL
:
1892 case MISCREG_CNTHCTL_EL2
:
1893 case MISCREG_CNTHP_CVAL_EL2
:
1894 case MISCREG_CNTHP_TVAL_EL2
:
1895 case MISCREG_CNTHP_CTL_EL2
:
1898 case MISCREG_CNTV_CVAL
:
1899 case MISCREG_CNTV_TVAL
:
1900 case MISCREG_CNTV_CTL
:
1902 // case MISCREG_CNTV_CVAL_EL2:
1903 // case MISCREG_CNTV_TVAL_EL2:
1904 // case MISCREG_CNTV_CTL_EL2:
1908 setMiscRegNoEffect(misc_reg
, newVal
);
1912 ISA::tlbiVA(ThreadContext
*tc
, MiscReg newVal
, uint8_t asid
, bool secure_lookup
,
1915 if (haveLargeAsid64
)
1917 Addr va
= ((Addr
) bits(newVal
, 43, 0)) << 12;
1918 System
*sys
= tc
->getSystemPtr();
1919 for (int x
= 0; x
< sys
->numContexts(); x
++) {
1920 ThreadContext
*oc
= sys
->getThreadContext(x
);
1921 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1922 oc
->getITBPtr()->flushMvaAsid(va
, asid
,
1923 secure_lookup
, target_el
);
1924 oc
->getDTBPtr()->flushMvaAsid(va
, asid
,
1925 secure_lookup
, target_el
);
1927 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1929 checker
->getITBPtr()->flushMvaAsid(
1930 va
, asid
, secure_lookup
, target_el
);
1931 checker
->getDTBPtr()->flushMvaAsid(
1932 va
, asid
, secure_lookup
, target_el
);
1938 ISA::tlbiALL(ThreadContext
*tc
, bool secure_lookup
, uint8_t target_el
)
1940 System
*sys
= tc
->getSystemPtr();
1941 for (int x
= 0; x
< sys
->numContexts(); x
++) {
1942 ThreadContext
*oc
= sys
->getThreadContext(x
);
1943 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1944 oc
->getITBPtr()->flushAllSecurity(secure_lookup
, target_el
);
1945 oc
->getDTBPtr()->flushAllSecurity(secure_lookup
, target_el
);
1947 // If CheckerCPU is connected, need to notify it of a flush
1948 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1950 checker
->getITBPtr()->flushAllSecurity(secure_lookup
,
1952 checker
->getDTBPtr()->flushAllSecurity(secure_lookup
,
1959 ISA::tlbiALLN(ThreadContext
*tc
, bool hyp
, uint8_t target_el
)
1961 System
*sys
= tc
->getSystemPtr();
1962 for (int x
= 0; x
< sys
->numContexts(); x
++) {
1963 ThreadContext
*oc
= sys
->getThreadContext(x
);
1964 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1965 oc
->getITBPtr()->flushAllNs(hyp
, target_el
);
1966 oc
->getDTBPtr()->flushAllNs(hyp
, target_el
);
1968 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1970 checker
->getITBPtr()->flushAllNs(hyp
, target_el
);
1971 checker
->getDTBPtr()->flushAllNs(hyp
, target_el
);
1977 ISA::tlbiMVA(ThreadContext
*tc
, MiscReg newVal
, bool secure_lookup
, bool hyp
,
1980 System
*sys
= tc
->getSystemPtr();
1981 for (int x
= 0; x
< sys
->numContexts(); x
++) {
1982 ThreadContext
*oc
= sys
->getThreadContext(x
);
1983 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1984 oc
->getITBPtr()->flushMva(mbits(newVal
, 31,12),
1985 secure_lookup
, hyp
, target_el
);
1986 oc
->getDTBPtr()->flushMva(mbits(newVal
, 31,12),
1987 secure_lookup
, hyp
, target_el
);
1989 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1991 checker
->getITBPtr()->flushMva(mbits(newVal
, 31,12),
1992 secure_lookup
, hyp
, target_el
);
1993 checker
->getDTBPtr()->flushMva(mbits(newVal
, 31,12),
1994 secure_lookup
, hyp
, target_el
);
1999 ::GenericTimer::SystemCounter
*
2000 ISA::getSystemCounter(ThreadContext
*tc
)
2002 ::GenericTimer::SystemCounter
*cnt
= ((ArmSystem
*) tc
->getSystemPtr())->
2005 panic("System counter not available\n");
2010 ::GenericTimer::ArchTimer
*
2011 ISA::getArchTimer(ThreadContext
*tc
, int cpu_id
)
2013 ::GenericTimer::ArchTimer
*timer
= ((ArmSystem
*) tc
->getSystemPtr())->
2014 getArchTimer(cpu_id
);
2015 if (timer
== NULL
) {
2016 panic("Architected timer not available\n");
2024 ArmISAParams::create()
2026 return new ArmISA::ISA(this);