2 * Copyright (c) 2010-2014 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
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41 #include "arch/arm/isa.hh"
42 #include "arch/arm/pmu.hh"
43 #include "arch/arm/system.hh"
44 #include "cpu/checker/cpu.hh"
45 #include "cpu/base.hh"
46 #include "debug/Arm.hh"
47 #include "debug/MiscRegs.hh"
48 #include "params/ArmISA.hh"
49 #include "sim/faults.hh"
50 #include "sim/stat_control.hh"
51 #include "sim/system.hh"
58 * Some registers aliase with others, and therefore need to be translated.
60 * The first value is the misc register that is to be looked up
61 * the second value is the lower part of the translation
62 * the third the upper part
64 const struct ISA::MiscRegInitializerEntry
65 ISA::MiscRegSwitch
[miscRegTranslateMax
] = {
66 {MISCREG_CSSELR_EL1
, {MISCREG_CSSELR
, 0}},
67 {MISCREG_SCTLR_EL1
, {MISCREG_SCTLR
, 0}},
68 {MISCREG_SCTLR_EL2
, {MISCREG_HSCTLR
, 0}},
69 {MISCREG_ACTLR_EL1
, {MISCREG_ACTLR
, 0}},
70 {MISCREG_ACTLR_EL2
, {MISCREG_HACTLR
, 0}},
71 {MISCREG_CPACR_EL1
, {MISCREG_CPACR
, 0}},
72 {MISCREG_CPTR_EL2
, {MISCREG_HCPTR
, 0}},
73 {MISCREG_HCR_EL2
, {MISCREG_HCR
, 0}},
74 {MISCREG_MDCR_EL2
, {MISCREG_HDCR
, 0}},
75 {MISCREG_HSTR_EL2
, {MISCREG_HSTR
, 0}},
76 {MISCREG_HACR_EL2
, {MISCREG_HACR
, 0}},
77 {MISCREG_TTBR0_EL1
, {MISCREG_TTBR0
, 0}},
78 {MISCREG_TTBR1_EL1
, {MISCREG_TTBR1
, 0}},
79 {MISCREG_TTBR0_EL2
, {MISCREG_HTTBR
, 0}},
80 {MISCREG_VTTBR_EL2
, {MISCREG_VTTBR
, 0}},
81 {MISCREG_TCR_EL1
, {MISCREG_TTBCR
, 0}},
82 {MISCREG_TCR_EL2
, {MISCREG_HTCR
, 0}},
83 {MISCREG_VTCR_EL2
, {MISCREG_VTCR
, 0}},
84 {MISCREG_AFSR0_EL1
, {MISCREG_ADFSR
, 0}},
85 {MISCREG_AFSR1_EL1
, {MISCREG_AIFSR
, 0}},
86 {MISCREG_AFSR0_EL2
, {MISCREG_HADFSR
, 0}},
87 {MISCREG_AFSR1_EL2
, {MISCREG_HAIFSR
, 0}},
88 {MISCREG_ESR_EL2
, {MISCREG_HSR
, 0}},
89 {MISCREG_FAR_EL1
, {MISCREG_DFAR
, MISCREG_IFAR
}},
90 {MISCREG_FAR_EL2
, {MISCREG_HDFAR
, MISCREG_HIFAR
}},
91 {MISCREG_HPFAR_EL2
, {MISCREG_HPFAR
, 0}},
92 {MISCREG_PAR_EL1
, {MISCREG_PAR
, 0}},
93 {MISCREG_MAIR_EL1
, {MISCREG_PRRR
, MISCREG_NMRR
}},
94 {MISCREG_MAIR_EL2
, {MISCREG_HMAIR0
, MISCREG_HMAIR1
}},
95 {MISCREG_AMAIR_EL1
, {MISCREG_AMAIR0
, MISCREG_AMAIR1
}},
96 {MISCREG_VBAR_EL1
, {MISCREG_VBAR
, 0}},
97 {MISCREG_VBAR_EL2
, {MISCREG_HVBAR
, 0}},
98 {MISCREG_CONTEXTIDR_EL1
, {MISCREG_CONTEXTIDR
, 0}},
99 {MISCREG_TPIDR_EL0
, {MISCREG_TPIDRURW
, 0}},
100 {MISCREG_TPIDRRO_EL0
, {MISCREG_TPIDRURO
, 0}},
101 {MISCREG_TPIDR_EL1
, {MISCREG_TPIDRPRW
, 0}},
102 {MISCREG_TPIDR_EL2
, {MISCREG_HTPIDR
, 0}},
103 {MISCREG_TEECR32_EL1
, {MISCREG_TEECR
, 0}},
104 {MISCREG_CNTFRQ_EL0
, {MISCREG_CNTFRQ
, 0}},
105 {MISCREG_CNTPCT_EL0
, {MISCREG_CNTPCT
, 0}},
106 {MISCREG_CNTVCT_EL0
, {MISCREG_CNTVCT
, 0}},
107 {MISCREG_CNTVOFF_EL2
, {MISCREG_CNTVOFF
, 0}},
108 {MISCREG_CNTKCTL_EL1
, {MISCREG_CNTKCTL
, 0}},
109 {MISCREG_CNTHCTL_EL2
, {MISCREG_CNTHCTL
, 0}},
110 {MISCREG_CNTP_TVAL_EL0
, {MISCREG_CNTP_TVAL
, 0}},
111 {MISCREG_CNTP_CTL_EL0
, {MISCREG_CNTP_CTL
, 0}},
112 {MISCREG_CNTP_CVAL_EL0
, {MISCREG_CNTP_CVAL
, 0}},
113 {MISCREG_CNTV_TVAL_EL0
, {MISCREG_CNTV_TVAL
, 0}},
114 {MISCREG_CNTV_CTL_EL0
, {MISCREG_CNTV_CTL
, 0}},
115 {MISCREG_CNTV_CVAL_EL0
, {MISCREG_CNTV_CVAL
, 0}},
116 {MISCREG_CNTHP_TVAL_EL2
, {MISCREG_CNTHP_TVAL
, 0}},
117 {MISCREG_CNTHP_CTL_EL2
, {MISCREG_CNTHP_CTL
, 0}},
118 {MISCREG_CNTHP_CVAL_EL2
, {MISCREG_CNTHP_CVAL
, 0}},
119 {MISCREG_DACR32_EL2
, {MISCREG_DACR
, 0}},
120 {MISCREG_IFSR32_EL2
, {MISCREG_IFSR
, 0}},
121 {MISCREG_TEEHBR32_EL1
, {MISCREG_TEEHBR
, 0}},
122 {MISCREG_SDER32_EL3
, {MISCREG_SDER
, 0}}
130 lookUpMiscReg(NUM_MISCREGS
, {0,0})
134 miscRegs
[MISCREG_SCTLR_RST
] = sctlr
;
136 // Hook up a dummy device if we haven't been configured with a
137 // real PMU. By using a dummy device, we don't need to check that
138 // the PMU exist every time we try to access a PMU register.
142 system
= dynamic_cast<ArmSystem
*>(p
->system
);
143 DPRINTFN("ISA system set to: %p %p\n", system
, p
->system
);
145 // Cache system-level properties
146 if (FullSystem
&& system
) {
147 haveSecurity
= system
->haveSecurity();
148 haveLPAE
= system
->haveLPAE();
149 haveVirtualization
= system
->haveVirtualization();
150 haveLargeAsid64
= system
->haveLargeAsid64();
151 physAddrRange64
= system
->physAddrRange64();
153 haveSecurity
= haveLPAE
= haveVirtualization
= false;
154 haveLargeAsid64
= false;
155 physAddrRange64
= 32; // dummy value
158 /** Fill in the miscReg translation table */
159 for (uint32_t i
= 0; i
< miscRegTranslateMax
; i
++) {
160 struct MiscRegLUTEntry new_entry
;
162 uint32_t select
= MiscRegSwitch
[i
].index
;
163 new_entry
= MiscRegSwitch
[i
].entry
;
165 lookUpMiscReg
[select
] = new_entry
;
168 preUnflattenMiscReg();
176 return dynamic_cast<const Params
*>(_params
);
182 const Params
*p(params());
184 SCTLR sctlr_rst
= miscRegs
[MISCREG_SCTLR_RST
];
185 memset(miscRegs
, 0, sizeof(miscRegs
));
187 // Initialize configurable default values
188 miscRegs
[MISCREG_MIDR
] = p
->midr
;
189 miscRegs
[MISCREG_MIDR_EL1
] = p
->midr
;
190 miscRegs
[MISCREG_VPIDR
] = p
->midr
;
192 if (FullSystem
&& system
->highestELIs64()) {
193 // Initialize AArch64 state
198 // Initialize AArch32 state...
201 cpsr
.mode
= MODE_USER
;
202 miscRegs
[MISCREG_CPSR
] = cpsr
;
206 sctlr
.te
= (bool) sctlr_rst
.te
;
207 sctlr
.nmfi
= (bool) sctlr_rst
.nmfi
;
208 sctlr
.v
= (bool) sctlr_rst
.v
;
213 sctlr
.rao4
= 0xf; // SCTLR[6:3]
216 miscRegs
[MISCREG_SCTLR_NS
] = sctlr
;
217 miscRegs
[MISCREG_SCTLR_RST
] = sctlr_rst
;
218 miscRegs
[MISCREG_HCPTR
] = 0;
220 // Start with an event in the mailbox
221 miscRegs
[MISCREG_SEV_MAILBOX
] = 1;
223 // Separate Instruction and Data TLBs
224 miscRegs
[MISCREG_TLBTR
] = 1;
227 mvfr0
.advSimdRegisters
= 2;
228 mvfr0
.singlePrecision
= 2;
229 mvfr0
.doublePrecision
= 2;
230 mvfr0
.vfpExceptionTrapping
= 0;
232 mvfr0
.squareRoot
= 1;
233 mvfr0
.shortVectors
= 1;
234 mvfr0
.roundingModes
= 1;
235 miscRegs
[MISCREG_MVFR0
] = mvfr0
;
238 mvfr1
.flushToZero
= 1;
239 mvfr1
.defaultNaN
= 1;
240 mvfr1
.advSimdLoadStore
= 1;
241 mvfr1
.advSimdInteger
= 1;
242 mvfr1
.advSimdSinglePrecision
= 1;
243 mvfr1
.advSimdHalfPrecision
= 1;
244 mvfr1
.vfpHalfPrecision
= 1;
245 miscRegs
[MISCREG_MVFR1
] = mvfr1
;
247 // Reset values of PRRR and NMRR are implementation dependent
249 // @todo: PRRR and NMRR in secure state?
250 miscRegs
[MISCREG_PRRR_NS
] =
263 miscRegs
[MISCREG_NMRR_NS
] =
280 miscRegs
[MISCREG_CPACR
] = 0;
283 miscRegs
[MISCREG_ID_PFR0
] = p
->id_pfr0
;
284 miscRegs
[MISCREG_ID_PFR1
] = p
->id_pfr1
;
286 miscRegs
[MISCREG_ID_MMFR0
] = p
->id_mmfr0
;
287 miscRegs
[MISCREG_ID_MMFR1
] = p
->id_mmfr1
;
288 miscRegs
[MISCREG_ID_MMFR2
] = p
->id_mmfr2
;
289 miscRegs
[MISCREG_ID_MMFR3
] = p
->id_mmfr3
;
291 miscRegs
[MISCREG_ID_ISAR0
] = p
->id_isar0
;
292 miscRegs
[MISCREG_ID_ISAR1
] = p
->id_isar1
;
293 miscRegs
[MISCREG_ID_ISAR2
] = p
->id_isar2
;
294 miscRegs
[MISCREG_ID_ISAR3
] = p
->id_isar3
;
295 miscRegs
[MISCREG_ID_ISAR4
] = p
->id_isar4
;
296 miscRegs
[MISCREG_ID_ISAR5
] = p
->id_isar5
;
298 miscRegs
[MISCREG_FPSID
] = p
->fpsid
;
301 TTBCR ttbcr
= miscRegs
[MISCREG_TTBCR_NS
];
303 miscRegs
[MISCREG_TTBCR_NS
] = ttbcr
;
304 // Enforce consistency with system-level settings
305 miscRegs
[MISCREG_ID_MMFR0
] = (miscRegs
[MISCREG_ID_MMFR0
] & ~0xf) | 0x5;
309 miscRegs
[MISCREG_SCTLR_S
] = sctlr
;
310 miscRegs
[MISCREG_SCR
] = 0;
311 miscRegs
[MISCREG_VBAR_S
] = 0;
313 // we're always non-secure
314 miscRegs
[MISCREG_SCR
] = 1;
317 //XXX We need to initialize the rest of the state.
321 ISA::clear64(const ArmISAParams
*p
)
324 Addr rvbar
= system
->resetAddr64();
325 switch (system
->highestEL()) {
326 // Set initial EL to highest implemented EL using associated stack
327 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
330 cpsr
.mode
= MODE_EL3H
;
331 miscRegs
[MISCREG_RVBAR_EL3
] = rvbar
;
334 cpsr
.mode
= MODE_EL2H
;
335 miscRegs
[MISCREG_RVBAR_EL2
] = rvbar
;
338 cpsr
.mode
= MODE_EL1H
;
339 miscRegs
[MISCREG_RVBAR_EL1
] = rvbar
;
342 panic("Invalid highest implemented exception level");
346 // Initialize rest of CPSR
347 cpsr
.daif
= 0xf; // Mask all interrupts
350 miscRegs
[MISCREG_CPSR
] = cpsr
;
353 // Initialize other control registers
354 miscRegs
[MISCREG_MPIDR_EL1
] = 0x80000000;
356 miscRegs
[MISCREG_SCTLR_EL3
] = 0x30c50870;
357 miscRegs
[MISCREG_SCR_EL3
] = 0x00000030; // RES1 fields
358 // @todo: uncomment this to enable Virtualization
359 // } else if (haveVirtualization) {
360 // miscRegs[MISCREG_SCTLR_EL2] = 0x30c50870;
362 miscRegs
[MISCREG_SCTLR_EL1
] = 0x30c50870;
364 miscRegs
[MISCREG_SCR_EL3
] = 1;
367 // Initialize configurable id registers
368 miscRegs
[MISCREG_ID_AA64AFR0_EL1
] = p
->id_aa64afr0_el1
;
369 miscRegs
[MISCREG_ID_AA64AFR1_EL1
] = p
->id_aa64afr1_el1
;
370 miscRegs
[MISCREG_ID_AA64DFR0_EL1
] =
371 (p
->id_aa64dfr0_el1
& 0xfffffffffffff0ffULL
) |
372 (p
->pmu
? 0x0000000000000100ULL
: 0); // Enable PMUv3
374 miscRegs
[MISCREG_ID_AA64DFR1_EL1
] = p
->id_aa64dfr1_el1
;
375 miscRegs
[MISCREG_ID_AA64ISAR0_EL1
] = p
->id_aa64isar0_el1
;
376 miscRegs
[MISCREG_ID_AA64ISAR1_EL1
] = p
->id_aa64isar1_el1
;
377 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
] = p
->id_aa64mmfr0_el1
;
378 miscRegs
[MISCREG_ID_AA64MMFR1_EL1
] = p
->id_aa64mmfr1_el1
;
379 miscRegs
[MISCREG_ID_AA64PFR0_EL1
] = p
->id_aa64pfr0_el1
;
380 miscRegs
[MISCREG_ID_AA64PFR1_EL1
] = p
->id_aa64pfr1_el1
;
382 miscRegs
[MISCREG_ID_DFR0_EL1
] =
383 (p
->pmu
? 0x03000000ULL
: 0); // Enable PMUv3
385 miscRegs
[MISCREG_ID_DFR0
] = miscRegs
[MISCREG_ID_DFR0_EL1
];
387 // Enforce consistency with system-level settings...
390 // (no AArch32/64 interprocessing support for now)
391 miscRegs
[MISCREG_ID_AA64PFR0_EL1
] = insertBits(
392 miscRegs
[MISCREG_ID_AA64PFR0_EL1
], 15, 12,
393 haveSecurity
? 0x1 : 0x0);
395 // (no AArch32/64 interprocessing support for now)
396 miscRegs
[MISCREG_ID_AA64PFR0_EL1
] = insertBits(
397 miscRegs
[MISCREG_ID_AA64PFR0_EL1
], 11, 8,
398 haveVirtualization
? 0x1 : 0x0);
399 // Large ASID support
400 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
] = insertBits(
401 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
], 7, 4,
402 haveLargeAsid64
? 0x2 : 0x0);
403 // Physical address size
404 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
] = insertBits(
405 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
], 3, 0,
406 encodePhysAddrRange64(physAddrRange64
));
410 ISA::readMiscRegNoEffect(int misc_reg
) const
412 assert(misc_reg
< NumMiscRegs
);
414 int flat_idx
= flattenMiscIndex(misc_reg
); // Note: indexes of AArch64
415 // registers are left unchanged
418 if (lookUpMiscReg
[flat_idx
].lower
== 0 || flat_idx
== MISCREG_SPSR
419 || flat_idx
== MISCREG_SCTLR_EL1
) {
420 if (flat_idx
== MISCREG_SPSR
)
421 flat_idx
= flattenMiscIndex(MISCREG_SPSR
);
422 if (flat_idx
== MISCREG_SCTLR_EL1
)
423 flat_idx
= flattenMiscIndex(MISCREG_SCTLR
);
424 val
= miscRegs
[flat_idx
];
426 if (lookUpMiscReg
[flat_idx
].upper
> 0)
427 val
= ((miscRegs
[lookUpMiscReg
[flat_idx
].lower
] & mask(32))
428 | (miscRegs
[lookUpMiscReg
[flat_idx
].upper
] << 32));
430 val
= miscRegs
[lookUpMiscReg
[flat_idx
].lower
];
437 ISA::readMiscReg(int misc_reg
, ThreadContext
*tc
)
443 if (misc_reg
== MISCREG_CPSR
) {
444 cpsr
= miscRegs
[misc_reg
];
446 cpsr
.j
= pc
.jazelle() ? 1 : 0;
447 cpsr
.t
= pc
.thumb() ? 1 : 0;
452 if (!miscRegInfo
[misc_reg
][MISCREG_IMPLEMENTED
]) {
453 if (miscRegInfo
[misc_reg
][MISCREG_WARN_NOT_FAIL
])
454 warn("Unimplemented system register %s read.\n",
455 miscRegName
[misc_reg
]);
457 panic("Unimplemented system register %s read.\n",
458 miscRegName
[misc_reg
]);
462 switch (unflattenMiscReg(misc_reg
)) {
465 if (!haveVirtualization
)
468 return readMiscRegNoEffect(MISCREG_HCR
);
472 const uint32_t ones
= (uint32_t)(-1);
474 // Only cp10, cp11, and ase are implemented, nothing else should
475 // be readable? (straight copy from the write code)
476 cpacrMask
.cp10
= ones
;
477 cpacrMask
.cp11
= ones
;
478 cpacrMask
.asedis
= ones
;
480 // Security Extensions may limit the readability of CPACR
482 scr
= readMiscRegNoEffect(MISCREG_SCR
);
483 cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
484 if (scr
.ns
&& (cpsr
.mode
!= MODE_MON
)) {
485 NSACR nsacr
= readMiscRegNoEffect(MISCREG_NSACR
);
486 // NB: Skipping the full loop, here
487 if (!nsacr
.cp10
) cpacrMask
.cp10
= 0;
488 if (!nsacr
.cp11
) cpacrMask
.cp11
= 0;
491 MiscReg val
= readMiscRegNoEffect(MISCREG_CPACR
);
493 DPRINTF(MiscRegs
, "Reading misc reg %s: %#x\n",
494 miscRegName
[misc_reg
], val
);
498 cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
499 scr
= readMiscRegNoEffect(MISCREG_SCR
);
500 if ((cpsr
.mode
== MODE_HYP
) || inSecureState(scr
, cpsr
)) {
501 return getMPIDR(system
, tc
);
503 return readMiscReg(MISCREG_VMPIDR
, tc
);
506 case MISCREG_MPIDR_EL1
:
507 // @todo in the absence of v8 virtualization support just return MPIDR_EL1
508 return getMPIDR(system
, tc
) & 0xffffffff;
510 // top bit defined as RES1
511 return readMiscRegNoEffect(misc_reg
) | 0x80000000;
512 case MISCREG_ID_AFR0
: // not implemented, so alias MIDR
513 case MISCREG_REVIDR
: // not implemented, so alias MIDR
515 cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
516 scr
= readMiscRegNoEffect(MISCREG_SCR
);
517 if ((cpsr
.mode
== MODE_HYP
) || inSecureState(scr
, cpsr
)) {
518 return readMiscRegNoEffect(misc_reg
);
520 return readMiscRegNoEffect(MISCREG_VPIDR
);
523 case MISCREG_JOSCR
: // Jazelle trivial implementation, RAZ/WI
524 case MISCREG_JMCR
: // Jazelle trivial implementation, RAZ/WI
525 case MISCREG_JIDR
: // Jazelle trivial implementation, RAZ/WI
526 case MISCREG_AIDR
: // AUX ID set to 0
527 case MISCREG_TCMTR
: // No TCM's
531 warn_once("The clidr register always reports 0 caches.\n");
532 warn_once("clidr LoUIS field of 0b001 to match current "
533 "ARM implementations.\n");
536 warn_once("The ccsidr register isn't implemented and "
537 "always reads as 0.\n");
541 //all caches have the same line size in gem5
542 //4 byte words in ARM
543 unsigned lineSizeWords
=
544 tc
->getSystemPtr()->cacheLineSize() / 4;
545 unsigned log2LineSizeWords
= 0;
547 while (lineSizeWords
>>= 1) {
552 //log2 of minimun i-cache line size (words)
553 ctr
.iCacheLineSize
= log2LineSizeWords
;
554 //b11 - gem5 uses pipt
555 ctr
.l1IndexPolicy
= 0x3;
556 //log2 of minimum d-cache line size (words)
557 ctr
.dCacheLineSize
= log2LineSizeWords
;
558 //log2 of max reservation size (words)
559 ctr
.erg
= log2LineSizeWords
;
560 //log2 of max writeback size (words)
561 ctr
.cwg
= log2LineSizeWords
;
562 //b100 - gem5 format is ARMv7
568 warn("Not doing anything for miscreg ACTLR\n");
571 case MISCREG_PMXEVTYPER_PMCCFILTR
:
572 case MISCREG_PMINTENSET_EL1
... MISCREG_PMOVSSET_EL0
:
573 case MISCREG_PMEVCNTR0_EL0
... MISCREG_PMEVTYPER5_EL0
:
574 case MISCREG_PMCR
... MISCREG_PMOVSSET
:
575 return pmu
->readMiscReg(misc_reg
);
578 panic("shouldn't be reading this register seperately\n");
579 case MISCREG_FPSCR_QC
:
580 return readMiscRegNoEffect(MISCREG_FPSCR
) & ~FpscrQcMask
;
581 case MISCREG_FPSCR_EXC
:
582 return readMiscRegNoEffect(MISCREG_FPSCR
) & ~FpscrExcMask
;
585 const uint32_t ones
= (uint32_t)(-1);
587 fpscrMask
.ioc
= ones
;
588 fpscrMask
.dzc
= ones
;
589 fpscrMask
.ofc
= ones
;
590 fpscrMask
.ufc
= ones
;
591 fpscrMask
.ixc
= ones
;
592 fpscrMask
.idc
= ones
;
598 return readMiscRegNoEffect(MISCREG_FPSCR
) & (uint32_t)fpscrMask
;
602 const uint32_t ones
= (uint32_t)(-1);
604 fpscrMask
.ioe
= ones
;
605 fpscrMask
.dze
= ones
;
606 fpscrMask
.ofe
= ones
;
607 fpscrMask
.ufe
= ones
;
608 fpscrMask
.ixe
= ones
;
609 fpscrMask
.ide
= ones
;
610 fpscrMask
.len
= ones
;
611 fpscrMask
.stride
= ones
;
612 fpscrMask
.rMode
= ones
;
615 fpscrMask
.ahp
= ones
;
616 return readMiscRegNoEffect(MISCREG_FPSCR
) & (uint32_t)fpscrMask
;
621 cpsr
.nz
= tc
->readCCReg(CCREG_NZ
);
622 cpsr
.c
= tc
->readCCReg(CCREG_C
);
623 cpsr
.v
= tc
->readCCReg(CCREG_V
);
629 cpsr
.daif
= (uint8_t) ((CPSR
) miscRegs
[MISCREG_CPSR
]).daif
;
634 return tc
->readIntReg(INTREG_SP0
);
638 return tc
->readIntReg(INTREG_SP1
);
642 return tc
->readIntReg(INTREG_SP2
);
646 return miscRegs
[MISCREG_CPSR
] & 0x1;
648 case MISCREG_CURRENTEL
:
650 return miscRegs
[MISCREG_CPSR
] & 0xc;
654 // mostly unimplemented, just set NumCPUs field from sim and return
656 // b00:1CPU to b11:4CPUs
657 l2ctlr
.numCPUs
= tc
->getSystemPtr()->numContexts() - 1;
660 case MISCREG_DBGDIDR
:
661 /* For now just implement the version number.
662 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
665 case MISCREG_DBGDSCRint
:
668 return tc
->getCpuPtr()->getInterruptController()->getISR(
669 readMiscRegNoEffect(MISCREG_HCR
),
670 readMiscRegNoEffect(MISCREG_CPSR
),
671 readMiscRegNoEffect(MISCREG_SCR
));
672 case MISCREG_ISR_EL1
:
673 return tc
->getCpuPtr()->getInterruptController()->getISR(
674 readMiscRegNoEffect(MISCREG_HCR_EL2
),
675 readMiscRegNoEffect(MISCREG_CPSR
),
676 readMiscRegNoEffect(MISCREG_SCR_EL3
));
677 case MISCREG_DCZID_EL0
:
678 return 0x04; // DC ZVA clear 64-byte chunks
681 MiscReg val
= readMiscRegNoEffect(misc_reg
);
682 // The trap bit associated with CP14 is defined as RAZ
684 // If a CP bit in NSACR is 0 then the corresponding bit in
686 bool secure_lookup
= haveSecurity
&&
687 inSecureState(readMiscRegNoEffect(MISCREG_SCR
),
688 readMiscRegNoEffect(MISCREG_CPSR
));
689 if (!secure_lookup
) {
690 MiscReg mask
= readMiscRegNoEffect(MISCREG_NSACR
);
691 val
|= (mask
^ 0x7FFF) & 0xBFFF;
693 // Set the bits for unimplemented coprocessors to RAO/WI
697 case MISCREG_HDFAR
: // alias for secure DFAR
698 return readMiscRegNoEffect(MISCREG_DFAR_S
);
699 case MISCREG_HIFAR
: // alias for secure IFAR
700 return readMiscRegNoEffect(MISCREG_IFAR_S
);
701 case MISCREG_HVBAR
: // bottom bits reserved
702 return readMiscRegNoEffect(MISCREG_HVBAR
) & 0xFFFFFFE0;
703 case MISCREG_SCTLR
: // Some bits hardwired
704 // The FI field (bit 21) is common between S/NS versions of the register
705 return (readMiscRegNoEffect(MISCREG_SCTLR_S
) & (1 << 21)) |
706 (readMiscRegNoEffect(misc_reg
) & 0x72DD39FF) | 0x00C00818; // V8 SCTLR
707 case MISCREG_SCTLR_EL1
:
708 // The FI field (bit 21) is common between S/NS versions of the register
709 return (readMiscRegNoEffect(MISCREG_SCTLR_S
) & (1 << 21)) |
710 (readMiscRegNoEffect(misc_reg
) & 0x37DDDBFF) | 0x30D00800; // V8 SCTLR_EL1
711 case MISCREG_SCTLR_EL3
:
712 // The FI field (bit 21) is common between S/NS versions of the register
713 return (readMiscRegNoEffect(MISCREG_SCTLR_S
) & (1 << 21)) |
714 (readMiscRegNoEffect(misc_reg
) & 0x32CD183F) | 0x30C50830; // V8 SCTLR_EL3
715 case MISCREG_HSCTLR
: // FI comes from SCTLR
717 uint32_t mask
= 1 << 27;
718 return (readMiscRegNoEffect(MISCREG_HSCTLR
) & ~mask
) |
719 (readMiscRegNoEffect(MISCREG_SCTLR
) & mask
);
723 CPSR cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
725 return readMiscRegNoEffect(MISCREG_SCR
);
727 return readMiscRegNoEffect(MISCREG_SCR_EL3
);
730 // Generic Timer registers
732 case MISCREG_CNTFRQ_EL0
:
733 inform_once("Read CNTFREQ_EL0 frequency\n");
734 return getSystemCounter(tc
)->freq();
736 case MISCREG_CNTPCT_EL0
:
737 return getSystemCounter(tc
)->value();
739 return getSystemCounter(tc
)->value();
740 case MISCREG_CNTVCT_EL0
:
741 return getSystemCounter(tc
)->value();
742 case MISCREG_CNTP_CVAL
:
743 case MISCREG_CNTP_CVAL_EL0
:
744 return getArchTimer(tc
, tc
->cpuId())->compareValue();
745 case MISCREG_CNTP_TVAL
:
746 case MISCREG_CNTP_TVAL_EL0
:
747 return getArchTimer(tc
, tc
->cpuId())->timerValue();
748 case MISCREG_CNTP_CTL
:
749 case MISCREG_CNTP_CTL_EL0
:
750 return getArchTimer(tc
, tc
->cpuId())->control();
751 // PL1 phys. timer, secure
753 // case MISCREG_CNTPS_CVAL_EL1:
754 // case MISCREG_CNTPS_TVAL_EL1:
755 // case MISCREG_CNTPS_CTL_EL1:
756 // PL2 phys. timer, non-secure
758 // case MISCREG_CNTHCTL:
759 // case MISCREG_CNTHP_CVAL:
760 // case MISCREG_CNTHP_TVAL:
761 // case MISCREG_CNTHP_CTL:
763 // case MISCREG_CNTHCTL_EL2:
764 // case MISCREG_CNTHP_CVAL_EL2:
765 // case MISCREG_CNTHP_TVAL_EL2:
766 // case MISCREG_CNTHP_CTL_EL2:
769 // case MISCREG_CNTV_CVAL:
770 // case MISCREG_CNTV_TVAL:
771 // case MISCREG_CNTV_CTL:
773 // case MISCREG_CNTV_CVAL_EL2:
774 // case MISCREG_CNTV_TVAL_EL2:
775 // case MISCREG_CNTV_CTL_EL2:
780 return readMiscRegNoEffect(misc_reg
);
784 ISA::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
)
786 assert(misc_reg
< NumMiscRegs
);
788 int flat_idx
= flattenMiscIndex(misc_reg
); // Note: indexes of AArch64
789 // registers are left unchanged
791 int flat_idx2
= lookUpMiscReg
[flat_idx
].upper
;
794 miscRegs
[lookUpMiscReg
[flat_idx
].lower
] = bits(val
, 31, 0);
795 miscRegs
[flat_idx2
] = bits(val
, 63, 32);
796 DPRINTF(MiscRegs
, "Writing to misc reg %d (%d:%d) : %#x\n",
797 misc_reg
, flat_idx
, flat_idx2
, val
);
799 if (flat_idx
== MISCREG_SPSR
)
800 flat_idx
= flattenMiscIndex(MISCREG_SPSR
);
801 else if (flat_idx
== MISCREG_SCTLR_EL1
)
802 flat_idx
= flattenMiscIndex(MISCREG_SCTLR
);
804 flat_idx
= (lookUpMiscReg
[flat_idx
].lower
> 0) ?
805 lookUpMiscReg
[flat_idx
].lower
: flat_idx
;
806 miscRegs
[flat_idx
] = val
;
807 DPRINTF(MiscRegs
, "Writing to misc reg %d (%d) : %#x\n",
808 misc_reg
, flat_idx
, val
);
813 ISA::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadContext
*tc
)
816 MiscReg newVal
= val
;
826 if (misc_reg
== MISCREG_CPSR
) {
830 CPSR old_cpsr
= miscRegs
[MISCREG_CPSR
];
831 int old_mode
= old_cpsr
.mode
;
833 if (old_mode
!= cpsr
.mode
) {
834 tc
->getITBPtr()->invalidateMiscReg();
835 tc
->getDTBPtr()->invalidateMiscReg();
838 DPRINTF(Arm
, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
839 miscRegs
[misc_reg
], cpsr
, cpsr
.f
, cpsr
.i
, cpsr
.a
, cpsr
.mode
);
840 PCState pc
= tc
->pcState();
841 pc
.nextThumb(cpsr
.t
);
842 pc
.nextJazelle(cpsr
.j
);
844 // Follow slightly different semantics if a CheckerCPU object
846 CheckerCPU
*checker
= tc
->getCheckerCpuPtr();
848 tc
->pcStateNoRecord(pc
);
854 if (!miscRegInfo
[misc_reg
][MISCREG_IMPLEMENTED
]) {
855 if (miscRegInfo
[misc_reg
][MISCREG_WARN_NOT_FAIL
])
856 warn("Unimplemented system register %s write with %#x.\n",
857 miscRegName
[misc_reg
], val
);
859 panic("Unimplemented system register %s write with %#x.\n",
860 miscRegName
[misc_reg
], val
);
863 switch (unflattenMiscReg(misc_reg
)) {
867 const uint32_t ones
= (uint32_t)(-1);
869 // Only cp10, cp11, and ase are implemented, nothing else should
871 cpacrMask
.cp10
= ones
;
872 cpacrMask
.cp11
= ones
;
873 cpacrMask
.asedis
= ones
;
875 // Security Extensions may limit the writability of CPACR
877 scr
= readMiscRegNoEffect(MISCREG_SCR
);
878 CPSR cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
879 if (scr
.ns
&& (cpsr
.mode
!= MODE_MON
)) {
880 NSACR nsacr
= readMiscRegNoEffect(MISCREG_NSACR
);
881 // NB: Skipping the full loop, here
882 if (!nsacr
.cp10
) cpacrMask
.cp10
= 0;
883 if (!nsacr
.cp11
) cpacrMask
.cp11
= 0;
887 MiscReg old_val
= readMiscRegNoEffect(MISCREG_CPACR
);
889 newVal
|= old_val
& ~cpacrMask
;
890 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
891 miscRegName
[misc_reg
], newVal
);
894 case MISCREG_CPACR_EL1
:
896 const uint32_t ones
= (uint32_t)(-1);
898 cpacrMask
.tta
= ones
;
899 cpacrMask
.fpen
= ones
;
901 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
902 miscRegName
[misc_reg
], newVal
);
905 case MISCREG_CPTR_EL2
:
907 const uint32_t ones
= (uint32_t)(-1);
909 cptrMask
.tcpac
= ones
;
914 cptrMask
.res1_13_12_el2
= ones
;
915 cptrMask
.res1_9_0_el2
= ones
;
917 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
918 miscRegName
[misc_reg
], newVal
);
921 case MISCREG_CPTR_EL3
:
923 const uint32_t ones
= (uint32_t)(-1);
925 cptrMask
.tcpac
= ones
;
929 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
930 miscRegName
[misc_reg
], newVal
);
934 warn_once("The csselr register isn't implemented.\n");
937 case MISCREG_DC_ZVA_Xt
:
938 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
943 const uint32_t ones
= (uint32_t)(-1);
945 fpscrMask
.ioc
= ones
;
946 fpscrMask
.dzc
= ones
;
947 fpscrMask
.ofc
= ones
;
948 fpscrMask
.ufc
= ones
;
949 fpscrMask
.ixc
= ones
;
950 fpscrMask
.idc
= ones
;
951 fpscrMask
.ioe
= ones
;
952 fpscrMask
.dze
= ones
;
953 fpscrMask
.ofe
= ones
;
954 fpscrMask
.ufe
= ones
;
955 fpscrMask
.ixe
= ones
;
956 fpscrMask
.ide
= ones
;
957 fpscrMask
.len
= ones
;
958 fpscrMask
.stride
= ones
;
959 fpscrMask
.rMode
= ones
;
962 fpscrMask
.ahp
= ones
;
968 newVal
= (newVal
& (uint32_t)fpscrMask
) |
969 (readMiscRegNoEffect(MISCREG_FPSCR
) &
970 ~(uint32_t)fpscrMask
);
971 tc
->getDecoderPtr()->setContext(newVal
);
976 const uint32_t ones
= (uint32_t)(-1);
978 fpscrMask
.ioc
= ones
;
979 fpscrMask
.dzc
= ones
;
980 fpscrMask
.ofc
= ones
;
981 fpscrMask
.ufc
= ones
;
982 fpscrMask
.ixc
= ones
;
983 fpscrMask
.idc
= ones
;
989 newVal
= (newVal
& (uint32_t)fpscrMask
) |
990 (readMiscRegNoEffect(MISCREG_FPSCR
) &
991 ~(uint32_t)fpscrMask
);
992 misc_reg
= MISCREG_FPSCR
;
997 const uint32_t ones
= (uint32_t)(-1);
999 fpscrMask
.ioe
= ones
;
1000 fpscrMask
.dze
= ones
;
1001 fpscrMask
.ofe
= ones
;
1002 fpscrMask
.ufe
= ones
;
1003 fpscrMask
.ixe
= ones
;
1004 fpscrMask
.ide
= ones
;
1005 fpscrMask
.len
= ones
;
1006 fpscrMask
.stride
= ones
;
1007 fpscrMask
.rMode
= ones
;
1008 fpscrMask
.fz
= ones
;
1009 fpscrMask
.dn
= ones
;
1010 fpscrMask
.ahp
= ones
;
1011 newVal
= (newVal
& (uint32_t)fpscrMask
) |
1012 (readMiscRegNoEffect(MISCREG_FPSCR
) &
1013 ~(uint32_t)fpscrMask
);
1014 misc_reg
= MISCREG_FPSCR
;
1017 case MISCREG_CPSR_Q
:
1019 assert(!(newVal
& ~CpsrMaskQ
));
1020 newVal
= readMiscRegNoEffect(MISCREG_CPSR
) | newVal
;
1021 misc_reg
= MISCREG_CPSR
;
1024 case MISCREG_FPSCR_QC
:
1026 newVal
= readMiscRegNoEffect(MISCREG_FPSCR
) |
1027 (newVal
& FpscrQcMask
);
1028 misc_reg
= MISCREG_FPSCR
;
1031 case MISCREG_FPSCR_EXC
:
1033 newVal
= readMiscRegNoEffect(MISCREG_FPSCR
) |
1034 (newVal
& FpscrExcMask
);
1035 misc_reg
= MISCREG_FPSCR
;
1040 // vfpv3 architecture, section B.6.1 of DDI04068
1041 // bit 29 - valid only if fpexc[31] is 0
1042 const uint32_t fpexcMask
= 0x60000000;
1043 newVal
= (newVal
& fpexcMask
) |
1044 (readMiscRegNoEffect(MISCREG_FPEXC
) & ~fpexcMask
);
1049 if (!haveVirtualization
)
1055 // ARM ARM (ARM DDI 0406C.b) B4.1.96
1056 const uint32_t ifsrMask
=
1057 mask(31, 13) | mask(11, 11) | mask(8, 6);
1058 newVal
= newVal
& ~ifsrMask
;
1063 // ARM ARM (ARM DDI 0406C.b) B4.1.52
1064 const uint32_t dfsrMask
= mask(31, 14) | mask(8, 8);
1065 newVal
= newVal
& ~dfsrMask
;
1068 case MISCREG_AMAIR0
:
1069 case MISCREG_AMAIR1
:
1071 // ARM ARM (ARM DDI 0406C.b) B4.1.5
1072 // Valid only with LPAE
1075 DPRINTF(MiscRegs
, "Writing AMAIR: %#x\n", newVal
);
1079 tc
->getITBPtr()->invalidateMiscReg();
1080 tc
->getDTBPtr()->invalidateMiscReg();
1084 DPRINTF(MiscRegs
, "Writing SCTLR: %#x\n", newVal
);
1085 MiscRegIndex sctlr_idx
;
1086 scr
= readMiscRegNoEffect(MISCREG_SCR
);
1087 if (haveSecurity
&& !scr
.ns
) {
1088 sctlr_idx
= MISCREG_SCTLR_S
;
1090 sctlr_idx
= MISCREG_SCTLR_NS
;
1091 // The FI field (bit 21) is common between S/NS versions
1092 // of the register, we store this in the secure copy of
1094 miscRegs
[MISCREG_SCTLR_S
] &= ~(1 << 21);
1095 miscRegs
[MISCREG_SCTLR_S
] |= newVal
& (1 << 21);
1097 SCTLR sctlr
= miscRegs
[sctlr_idx
];
1098 SCTLR new_sctlr
= newVal
;
1099 new_sctlr
.nmfi
= ((bool)sctlr
.nmfi
) && !haveVirtualization
;
1100 miscRegs
[sctlr_idx
] = (MiscReg
)new_sctlr
;
1101 tc
->getITBPtr()->invalidateMiscReg();
1102 tc
->getDTBPtr()->invalidateMiscReg();
1104 // Check if all CPUs are booted with caches enabled
1105 // so we can stop enforcing coherency of some kernel
1106 // structures manually.
1107 sys
= tc
->getSystemPtr();
1108 for (x
= 0; x
< sys
->numContexts(); x
++) {
1109 oc
= sys
->getThreadContext(x
);
1110 // @todo: double check this for security
1111 SCTLR other_sctlr
= oc
->readMiscRegNoEffect(MISCREG_SCTLR
);
1112 if (!other_sctlr
.c
&& oc
->status() != ThreadContext::Halted
)
1116 for (x
= 0; x
< sys
->numContexts(); x
++) {
1117 oc
= sys
->getThreadContext(x
);
1118 oc
->getDTBPtr()->allCpusCaching();
1119 oc
->getITBPtr()->allCpusCaching();
1121 // If CheckerCPU is connected, need to notify it.
1122 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1124 checker
->getDTBPtr()->allCpusCaching();
1125 checker
->getITBPtr()->allCpusCaching();
1132 case MISCREG_ID_PFR0
:
1133 case MISCREG_ID_PFR1
:
1134 case MISCREG_ID_DFR0
:
1135 case MISCREG_ID_MMFR0
:
1136 case MISCREG_ID_MMFR1
:
1137 case MISCREG_ID_MMFR2
:
1138 case MISCREG_ID_MMFR3
:
1139 case MISCREG_ID_ISAR0
:
1140 case MISCREG_ID_ISAR1
:
1141 case MISCREG_ID_ISAR2
:
1142 case MISCREG_ID_ISAR3
:
1143 case MISCREG_ID_ISAR4
:
1144 case MISCREG_ID_ISAR5
:
1152 case MISCREG_ID_AA64AFR0_EL1
:
1153 case MISCREG_ID_AA64AFR1_EL1
:
1154 case MISCREG_ID_AA64DFR0_EL1
:
1155 case MISCREG_ID_AA64DFR1_EL1
:
1156 case MISCREG_ID_AA64ISAR0_EL1
:
1157 case MISCREG_ID_AA64ISAR1_EL1
:
1158 case MISCREG_ID_AA64MMFR0_EL1
:
1159 case MISCREG_ID_AA64MMFR1_EL1
:
1160 case MISCREG_ID_AA64PFR0_EL1
:
1161 case MISCREG_ID_AA64PFR1_EL1
:
1162 // ID registers are constants.
1165 // TLBI all entries, EL0&1 inner sharable (ignored)
1166 case MISCREG_TLBIALLIS
:
1167 case MISCREG_TLBIALL
: // TLBI all entries, EL0&1,
1169 target_el
= 1; // el 0 and 1 are handled together
1170 scr
= readMiscReg(MISCREG_SCR
, tc
);
1171 secure_lookup
= haveSecurity
&& !scr
.ns
;
1172 sys
= tc
->getSystemPtr();
1173 for (x
= 0; x
< sys
->numContexts(); x
++) {
1174 oc
= sys
->getThreadContext(x
);
1175 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1176 oc
->getITBPtr()->flushAllSecurity(secure_lookup
, target_el
);
1177 oc
->getDTBPtr()->flushAllSecurity(secure_lookup
, target_el
);
1179 // If CheckerCPU is connected, need to notify it of a flush
1180 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1182 checker
->getITBPtr()->flushAllSecurity(secure_lookup
,
1184 checker
->getDTBPtr()->flushAllSecurity(secure_lookup
,
1189 // TLBI all entries, EL0&1, instruction side
1190 case MISCREG_ITLBIALL
:
1192 target_el
= 1; // el 0 and 1 are handled together
1193 scr
= readMiscReg(MISCREG_SCR
, tc
);
1194 secure_lookup
= haveSecurity
&& !scr
.ns
;
1195 tc
->getITBPtr()->flushAllSecurity(secure_lookup
, target_el
);
1197 // TLBI all entries, EL0&1, data side
1198 case MISCREG_DTLBIALL
:
1200 target_el
= 1; // el 0 and 1 are handled together
1201 scr
= readMiscReg(MISCREG_SCR
, tc
);
1202 secure_lookup
= haveSecurity
&& !scr
.ns
;
1203 tc
->getDTBPtr()->flushAllSecurity(secure_lookup
, target_el
);
1205 // TLBI based on VA, EL0&1 inner sharable (ignored)
1206 case MISCREG_TLBIMVAIS
:
1207 case MISCREG_TLBIMVA
:
1209 target_el
= 1; // el 0 and 1 are handled together
1210 scr
= readMiscReg(MISCREG_SCR
, tc
);
1211 secure_lookup
= haveSecurity
&& !scr
.ns
;
1212 sys
= tc
->getSystemPtr();
1213 for (x
= 0; x
< sys
->numContexts(); x
++) {
1214 oc
= sys
->getThreadContext(x
);
1215 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1216 oc
->getITBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
1218 secure_lookup
, target_el
);
1219 oc
->getDTBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
1221 secure_lookup
, target_el
);
1223 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1225 checker
->getITBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
1226 bits(newVal
, 7,0), secure_lookup
, target_el
);
1227 checker
->getDTBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
1228 bits(newVal
, 7,0), secure_lookup
, target_el
);
1232 // TLBI by ASID, EL0&1, inner sharable
1233 case MISCREG_TLBIASIDIS
:
1234 case MISCREG_TLBIASID
:
1236 target_el
= 1; // el 0 and 1 are handled together
1237 scr
= readMiscReg(MISCREG_SCR
, tc
);
1238 secure_lookup
= haveSecurity
&& !scr
.ns
;
1239 sys
= tc
->getSystemPtr();
1240 for (x
= 0; x
< sys
->numContexts(); x
++) {
1241 oc
= sys
->getThreadContext(x
);
1242 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1243 oc
->getITBPtr()->flushAsid(bits(newVal
, 7,0),
1244 secure_lookup
, target_el
);
1245 oc
->getDTBPtr()->flushAsid(bits(newVal
, 7,0),
1246 secure_lookup
, target_el
);
1247 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1249 checker
->getITBPtr()->flushAsid(bits(newVal
, 7,0),
1250 secure_lookup
, target_el
);
1251 checker
->getDTBPtr()->flushAsid(bits(newVal
, 7,0),
1252 secure_lookup
, target_el
);
1256 // TLBI by address, EL0&1, inner sharable (ignored)
1257 case MISCREG_TLBIMVAAIS
:
1258 case MISCREG_TLBIMVAA
:
1260 target_el
= 1; // el 0 and 1 are handled together
1261 scr
= readMiscReg(MISCREG_SCR
, tc
);
1262 secure_lookup
= haveSecurity
&& !scr
.ns
;
1264 tlbiMVA(tc
, newVal
, secure_lookup
, hyp
, target_el
);
1266 // TLBI by address, EL2, hypervisor mode
1267 case MISCREG_TLBIMVAH
:
1268 case MISCREG_TLBIMVAHIS
:
1270 target_el
= 1; // aarch32, use hyp bit
1271 scr
= readMiscReg(MISCREG_SCR
, tc
);
1272 secure_lookup
= haveSecurity
&& !scr
.ns
;
1274 tlbiMVA(tc
, newVal
, secure_lookup
, hyp
, target_el
);
1276 // TLBI by address and asid, EL0&1, instruction side only
1277 case MISCREG_ITLBIMVA
:
1279 target_el
= 1; // el 0 and 1 are handled together
1280 scr
= readMiscReg(MISCREG_SCR
, tc
);
1281 secure_lookup
= haveSecurity
&& !scr
.ns
;
1282 tc
->getITBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
1283 bits(newVal
, 7,0), secure_lookup
, target_el
);
1285 // TLBI by address and asid, EL0&1, data side only
1286 case MISCREG_DTLBIMVA
:
1288 target_el
= 1; // el 0 and 1 are handled together
1289 scr
= readMiscReg(MISCREG_SCR
, tc
);
1290 secure_lookup
= haveSecurity
&& !scr
.ns
;
1291 tc
->getDTBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
1292 bits(newVal
, 7,0), secure_lookup
, target_el
);
1294 // TLBI by ASID, EL0&1, instrution side only
1295 case MISCREG_ITLBIASID
:
1297 target_el
= 1; // el 0 and 1 are handled together
1298 scr
= readMiscReg(MISCREG_SCR
, tc
);
1299 secure_lookup
= haveSecurity
&& !scr
.ns
;
1300 tc
->getITBPtr()->flushAsid(bits(newVal
, 7,0), secure_lookup
,
1303 // TLBI by ASID EL0&1 data size only
1304 case MISCREG_DTLBIASID
:
1306 target_el
= 1; // el 0 and 1 are handled together
1307 scr
= readMiscReg(MISCREG_SCR
, tc
);
1308 secure_lookup
= haveSecurity
&& !scr
.ns
;
1309 tc
->getDTBPtr()->flushAsid(bits(newVal
, 7,0), secure_lookup
,
1312 // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB
1313 case MISCREG_TLBIALLNSNH
:
1314 case MISCREG_TLBIALLNSNHIS
:
1316 target_el
= 1; // el 0 and 1 are handled together
1318 tlbiALLN(tc
, hyp
, target_el
);
1320 // TLBI all entries, EL2, hyp,
1321 case MISCREG_TLBIALLH
:
1322 case MISCREG_TLBIALLHIS
:
1324 target_el
= 1; // aarch32, use hyp bit
1326 tlbiALLN(tc
, hyp
, target_el
);
1328 // AArch64 TLBI: invalidate all entries EL3
1329 case MISCREG_TLBI_ALLE3IS
:
1330 case MISCREG_TLBI_ALLE3
:
1333 secure_lookup
= true;
1334 tlbiALL(tc
, secure_lookup
, target_el
);
1336 // @todo: uncomment this to enable Virtualization
1337 // case MISCREG_TLBI_ALLE2IS:
1338 // case MISCREG_TLBI_ALLE2:
1339 // TLBI all entries, EL0&1
1340 case MISCREG_TLBI_ALLE1IS
:
1341 case MISCREG_TLBI_ALLE1
:
1342 // AArch64 TLBI: invalidate all entries, stage 1, current VMID
1343 case MISCREG_TLBI_VMALLE1IS
:
1344 case MISCREG_TLBI_VMALLE1
:
1345 // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID
1346 case MISCREG_TLBI_VMALLS12E1IS
:
1347 case MISCREG_TLBI_VMALLS12E1
:
1348 // @todo: handle VMID and stage 2 to enable Virtualization
1350 target_el
= 1; // el 0 and 1 are handled together
1351 scr
= readMiscReg(MISCREG_SCR
, tc
);
1352 secure_lookup
= haveSecurity
&& !scr
.ns
;
1353 tlbiALL(tc
, secure_lookup
, target_el
);
1355 // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID
1356 // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries
1357 // from the last level of translation table walks
1358 // @todo: handle VMID to enable Virtualization
1359 // TLBI all entries, EL0&1
1360 case MISCREG_TLBI_VAE3IS_Xt
:
1361 case MISCREG_TLBI_VAE3_Xt
:
1362 // TLBI by VA, EL3 regime stage 1, last level walk
1363 case MISCREG_TLBI_VALE3IS_Xt
:
1364 case MISCREG_TLBI_VALE3_Xt
:
1367 asid
= 0xbeef; // does not matter, tlbi is global
1368 secure_lookup
= true;
1369 tlbiVA(tc
, newVal
, asid
, secure_lookup
, target_el
);
1372 case MISCREG_TLBI_VAE2IS_Xt
:
1373 case MISCREG_TLBI_VAE2_Xt
:
1374 // TLBI by VA, EL2, stage1 last level walk
1375 case MISCREG_TLBI_VALE2IS_Xt
:
1376 case MISCREG_TLBI_VALE2_Xt
:
1379 asid
= 0xbeef; // does not matter, tlbi is global
1380 scr
= readMiscReg(MISCREG_SCR
, tc
);
1381 secure_lookup
= haveSecurity
&& !scr
.ns
;
1382 tlbiVA(tc
, newVal
, asid
, secure_lookup
, target_el
);
1384 // TLBI by VA EL1 & 0, stage1, ASID, current VMID
1385 case MISCREG_TLBI_VAE1IS_Xt
:
1386 case MISCREG_TLBI_VAE1_Xt
:
1387 case MISCREG_TLBI_VALE1IS_Xt
:
1388 case MISCREG_TLBI_VALE1_Xt
:
1390 asid
= bits(newVal
, 63, 48);
1391 target_el
= 1; // el 0 and 1 are handled together
1392 scr
= readMiscReg(MISCREG_SCR
, tc
);
1393 secure_lookup
= haveSecurity
&& !scr
.ns
;
1394 tlbiVA(tc
, newVal
, asid
, secure_lookup
, target_el
);
1396 // AArch64 TLBI: invalidate by ASID, stage 1, current VMID
1397 // @todo: handle VMID to enable Virtualization
1398 case MISCREG_TLBI_ASIDE1IS_Xt
:
1399 case MISCREG_TLBI_ASIDE1_Xt
:
1401 target_el
= 1; // el 0 and 1 are handled together
1402 scr
= readMiscReg(MISCREG_SCR
, tc
);
1403 secure_lookup
= haveSecurity
&& !scr
.ns
;
1404 sys
= tc
->getSystemPtr();
1405 for (x
= 0; x
< sys
->numContexts(); x
++) {
1406 oc
= sys
->getThreadContext(x
);
1407 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1408 asid
= bits(newVal
, 63, 48);
1409 if (haveLargeAsid64
)
1411 oc
->getITBPtr()->flushAsid(asid
, secure_lookup
, target_el
);
1412 oc
->getDTBPtr()->flushAsid(asid
, secure_lookup
, target_el
);
1413 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1415 checker
->getITBPtr()->flushAsid(asid
,
1416 secure_lookup
, target_el
);
1417 checker
->getDTBPtr()->flushAsid(asid
,
1418 secure_lookup
, target_el
);
1422 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID
1423 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1424 // entries from the last level of translation table walks
1425 // @todo: handle VMID to enable Virtualization
1426 case MISCREG_TLBI_VAAE1IS_Xt
:
1427 case MISCREG_TLBI_VAAE1_Xt
:
1428 case MISCREG_TLBI_VAALE1IS_Xt
:
1429 case MISCREG_TLBI_VAALE1_Xt
:
1431 target_el
= 1; // el 0 and 1 are handled together
1432 scr
= readMiscReg(MISCREG_SCR
, tc
);
1433 secure_lookup
= haveSecurity
&& !scr
.ns
;
1434 sys
= tc
->getSystemPtr();
1435 for (x
= 0; x
< sys
->numContexts(); x
++) {
1436 // @todo: extra controls on TLBI broadcast?
1437 oc
= sys
->getThreadContext(x
);
1438 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1439 Addr va
= ((Addr
) bits(newVal
, 43, 0)) << 12;
1440 oc
->getITBPtr()->flushMva(va
,
1441 secure_lookup
, false, target_el
);
1442 oc
->getDTBPtr()->flushMva(va
,
1443 secure_lookup
, false, target_el
);
1445 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1447 checker
->getITBPtr()->flushMva(va
,
1448 secure_lookup
, false, target_el
);
1449 checker
->getDTBPtr()->flushMva(va
,
1450 secure_lookup
, false, target_el
);
1454 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID
1455 case MISCREG_TLBI_IPAS2LE1IS_Xt
:
1456 case MISCREG_TLBI_IPAS2LE1_Xt
:
1457 case MISCREG_TLBI_IPAS2E1IS_Xt
:
1458 case MISCREG_TLBI_IPAS2E1_Xt
:
1460 // @todo: implement these as part of Virtualization
1461 warn("Not doing anything for write of miscreg ITLB_IPAS2\n");
1464 warn("Not doing anything for write of miscreg ACTLR\n");
1467 case MISCREG_PMXEVTYPER_PMCCFILTR
:
1468 case MISCREG_PMINTENSET_EL1
... MISCREG_PMOVSSET_EL0
:
1469 case MISCREG_PMEVCNTR0_EL0
... MISCREG_PMEVTYPER5_EL0
:
1470 case MISCREG_PMCR
... MISCREG_PMOVSSET
:
1471 pmu
->setMiscReg(misc_reg
, newVal
);
1475 case MISCREG_HSTR
: // TJDBX, now redifined to be RES0
1479 newVal
&= ~((uint32_t) hstrMask
);
1484 // If a CP bit in NSACR is 0 then the corresponding bit in
1485 // HCPTR is RAO/WI. Same applies to NSASEDIS
1486 secure_lookup
= haveSecurity
&&
1487 inSecureState(readMiscRegNoEffect(MISCREG_SCR
),
1488 readMiscRegNoEffect(MISCREG_CPSR
));
1489 if (!secure_lookup
) {
1490 MiscReg oldValue
= readMiscRegNoEffect(MISCREG_HCPTR
);
1491 MiscReg mask
= (readMiscRegNoEffect(MISCREG_NSACR
) ^ 0x7FFF) & 0xBFFF;
1492 newVal
= (newVal
& ~mask
) | (oldValue
& mask
);
1496 case MISCREG_HDFAR
: // alias for secure DFAR
1497 misc_reg
= MISCREG_DFAR_S
;
1499 case MISCREG_HIFAR
: // alias for secure IFAR
1500 misc_reg
= MISCREG_IFAR_S
;
1502 case MISCREG_ATS1CPR
:
1503 case MISCREG_ATS1CPW
:
1504 case MISCREG_ATS1CUR
:
1505 case MISCREG_ATS1CUW
:
1506 case MISCREG_ATS12NSOPR
:
1507 case MISCREG_ATS12NSOPW
:
1508 case MISCREG_ATS12NSOUR
:
1509 case MISCREG_ATS12NSOUW
:
1510 case MISCREG_ATS1HR
:
1511 case MISCREG_ATS1HW
:
1513 RequestPtr req
= new Request
;
1515 BaseTLB::Mode mode
= BaseTLB::Read
;
1516 TLB::ArmTranslationType tranType
= TLB::NormalTran
;
1519 case MISCREG_ATS1CPR
:
1520 flags
= TLB::MustBeOne
;
1521 tranType
= TLB::S1CTran
;
1522 mode
= BaseTLB::Read
;
1524 case MISCREG_ATS1CPW
:
1525 flags
= TLB::MustBeOne
;
1526 tranType
= TLB::S1CTran
;
1527 mode
= BaseTLB::Write
;
1529 case MISCREG_ATS1CUR
:
1530 flags
= TLB::MustBeOne
| TLB::UserMode
;
1531 tranType
= TLB::S1CTran
;
1532 mode
= BaseTLB::Read
;
1534 case MISCREG_ATS1CUW
:
1535 flags
= TLB::MustBeOne
| TLB::UserMode
;
1536 tranType
= TLB::S1CTran
;
1537 mode
= BaseTLB::Write
;
1539 case MISCREG_ATS12NSOPR
:
1541 panic("Security Extensions required for ATS12NSOPR");
1542 flags
= TLB::MustBeOne
;
1543 tranType
= TLB::S1S2NsTran
;
1544 mode
= BaseTLB::Read
;
1546 case MISCREG_ATS12NSOPW
:
1548 panic("Security Extensions required for ATS12NSOPW");
1549 flags
= TLB::MustBeOne
;
1550 tranType
= TLB::S1S2NsTran
;
1551 mode
= BaseTLB::Write
;
1553 case MISCREG_ATS12NSOUR
:
1555 panic("Security Extensions required for ATS12NSOUR");
1556 flags
= TLB::MustBeOne
| TLB::UserMode
;
1557 tranType
= TLB::S1S2NsTran
;
1558 mode
= BaseTLB::Read
;
1560 case MISCREG_ATS12NSOUW
:
1562 panic("Security Extensions required for ATS12NSOUW");
1563 flags
= TLB::MustBeOne
| TLB::UserMode
;
1564 tranType
= TLB::S1S2NsTran
;
1565 mode
= BaseTLB::Write
;
1567 case MISCREG_ATS1HR
: // only really useful from secure mode.
1568 flags
= TLB::MustBeOne
;
1569 tranType
= TLB::HypMode
;
1570 mode
= BaseTLB::Read
;
1572 case MISCREG_ATS1HW
:
1573 flags
= TLB::MustBeOne
;
1574 tranType
= TLB::HypMode
;
1575 mode
= BaseTLB::Write
;
1578 // If we're in timing mode then doing the translation in
1579 // functional mode then we're slightly distorting performance
1580 // results obtained from simulations. The translation should be
1581 // done in the same mode the core is running in. NOTE: This
1582 // can't be an atomic translation because that causes problems
1583 // with unexpected atomic snoop requests.
1584 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg
);
1585 req
->setVirt(0, val
, 1, flags
, Request::funcMasterId
,
1586 tc
->pcState().pc());
1587 req
->setThreadContext(tc
->contextId(), tc
->threadId());
1588 fault
= tc
->getDTBPtr()->translateFunctional(req
, tc
, mode
, tranType
);
1589 TTBCR ttbcr
= readMiscRegNoEffect(MISCREG_TTBCR
);
1590 HCR hcr
= readMiscRegNoEffect(MISCREG_HCR
);
1593 if (fault
== NoFault
) {
1594 Addr paddr
= req
->getPaddr();
1595 if (haveLPAE
&& (ttbcr
.eae
|| tranType
& TLB::HypMode
||
1596 ((tranType
& TLB::S1S2NsTran
) && hcr
.vm
) )) {
1597 newVal
= (paddr
& mask(39, 12)) |
1598 (tc
->getDTBPtr()->getAttr());
1600 newVal
= (paddr
& 0xfffff000) |
1601 (tc
->getDTBPtr()->getAttr());
1604 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
1607 ArmFault
*armFault
= reinterpret_cast<ArmFault
*>(fault
.get());
1608 // Set fault bit and FSR
1609 FSR fsr
= armFault
->getFsr(tc
);
1611 newVal
= ((fsr
>> 9) & 1) << 11;
1613 // LPAE - rearange fault status
1614 newVal
|= ((fsr
>> 0) & 0x3f) << 1;
1616 // VMSA - rearange fault status
1617 newVal
|= ((fsr
>> 0) & 0xf) << 1;
1618 newVal
|= ((fsr
>> 10) & 0x1) << 5;
1619 newVal
|= ((fsr
>> 12) & 0x1) << 6;
1621 newVal
|= 0x1; // F bit
1622 newVal
|= ((armFault
->iss() >> 7) & 0x1) << 8;
1623 newVal
|= armFault
->isStage2() ? 0x200 : 0;
1625 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
1629 setMiscRegNoEffect(MISCREG_PAR
, newVal
);
1634 TTBCR ttbcr
= readMiscRegNoEffect(MISCREG_TTBCR
);
1635 const uint32_t ones
= (uint32_t)(-1);
1636 TTBCR ttbcrMask
= 0;
1637 TTBCR ttbcrNew
= newVal
;
1639 // ARM DDI 0406C.b, ARMv7-32
1640 ttbcrMask
.n
= ones
; // T0SZ
1642 ttbcrMask
.pd0
= ones
;
1643 ttbcrMask
.pd1
= ones
;
1645 ttbcrMask
.epd0
= ones
;
1646 ttbcrMask
.irgn0
= ones
;
1647 ttbcrMask
.orgn0
= ones
;
1648 ttbcrMask
.sh0
= ones
;
1649 ttbcrMask
.ps
= ones
; // T1SZ
1650 ttbcrMask
.a1
= ones
;
1651 ttbcrMask
.epd1
= ones
;
1652 ttbcrMask
.irgn1
= ones
;
1653 ttbcrMask
.orgn1
= ones
;
1654 ttbcrMask
.sh1
= ones
;
1656 ttbcrMask
.eae
= ones
;
1658 if (haveLPAE
&& ttbcrNew
.eae
) {
1659 newVal
= newVal
& ttbcrMask
;
1661 newVal
= (newVal
& ttbcrMask
) | (ttbcr
& (~ttbcrMask
));
1667 TTBCR ttbcr
= readMiscRegNoEffect(MISCREG_TTBCR
);
1670 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1671 // ARMv8 AArch32 bit 63-56 only
1672 uint64_t ttbrMask
= mask(63,56) | mask(47,40);
1673 newVal
= (newVal
& (~ttbrMask
));
1677 case MISCREG_CONTEXTIDR
:
1684 case MISCREG_SCR_EL3
:
1685 case MISCREG_SCTLR_EL1
:
1686 case MISCREG_SCTLR_EL2
:
1687 case MISCREG_SCTLR_EL3
:
1688 case MISCREG_TCR_EL1
:
1689 case MISCREG_TCR_EL2
:
1690 case MISCREG_TCR_EL3
:
1691 case MISCREG_TTBR0_EL1
:
1692 case MISCREG_TTBR1_EL1
:
1693 case MISCREG_TTBR0_EL2
:
1694 case MISCREG_TTBR0_EL3
:
1695 tc
->getITBPtr()->invalidateMiscReg();
1696 tc
->getDTBPtr()->invalidateMiscReg();
1702 tc
->setCCReg(CCREG_NZ
, cpsr
.nz
);
1703 tc
->setCCReg(CCREG_C
, cpsr
.c
);
1704 tc
->setCCReg(CCREG_V
, cpsr
.v
);
1709 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1710 cpsr
.daif
= (uint8_t) ((CPSR
) newVal
).daif
;
1712 misc_reg
= MISCREG_CPSR
;
1715 case MISCREG_SP_EL0
:
1716 tc
->setIntReg(INTREG_SP0
, newVal
);
1718 case MISCREG_SP_EL1
:
1719 tc
->setIntReg(INTREG_SP1
, newVal
);
1721 case MISCREG_SP_EL2
:
1722 tc
->setIntReg(INTREG_SP2
, newVal
);
1726 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1727 cpsr
.sp
= (uint8_t) ((CPSR
) newVal
).sp
;
1729 misc_reg
= MISCREG_CPSR
;
1732 case MISCREG_CURRENTEL
:
1734 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1735 cpsr
.el
= (uint8_t) ((CPSR
) newVal
).el
;
1737 misc_reg
= MISCREG_CPSR
;
1740 case MISCREG_AT_S1E1R_Xt
:
1741 case MISCREG_AT_S1E1W_Xt
:
1742 case MISCREG_AT_S1E0R_Xt
:
1743 case MISCREG_AT_S1E0W_Xt
:
1744 case MISCREG_AT_S1E2R_Xt
:
1745 case MISCREG_AT_S1E2W_Xt
:
1746 case MISCREG_AT_S12E1R_Xt
:
1747 case MISCREG_AT_S12E1W_Xt
:
1748 case MISCREG_AT_S12E0R_Xt
:
1749 case MISCREG_AT_S12E0W_Xt
:
1750 case MISCREG_AT_S1E3R_Xt
:
1751 case MISCREG_AT_S1E3W_Xt
:
1753 RequestPtr req
= new Request
;
1755 BaseTLB::Mode mode
= BaseTLB::Read
;
1756 TLB::ArmTranslationType tranType
= TLB::NormalTran
;
1759 case MISCREG_AT_S1E1R_Xt
:
1760 flags
= TLB::MustBeOne
;
1761 tranType
= TLB::S1CTran
;
1762 mode
= BaseTLB::Read
;
1764 case MISCREG_AT_S1E1W_Xt
:
1765 flags
= TLB::MustBeOne
;
1766 tranType
= TLB::S1CTran
;
1767 mode
= BaseTLB::Write
;
1769 case MISCREG_AT_S1E0R_Xt
:
1770 flags
= TLB::MustBeOne
| TLB::UserMode
;
1771 tranType
= TLB::S1CTran
;
1772 mode
= BaseTLB::Read
;
1774 case MISCREG_AT_S1E0W_Xt
:
1775 flags
= TLB::MustBeOne
| TLB::UserMode
;
1776 tranType
= TLB::S1CTran
;
1777 mode
= BaseTLB::Write
;
1779 case MISCREG_AT_S1E2R_Xt
:
1780 flags
= TLB::MustBeOne
;
1781 tranType
= TLB::HypMode
;
1782 mode
= BaseTLB::Read
;
1784 case MISCREG_AT_S1E2W_Xt
:
1785 flags
= TLB::MustBeOne
;
1786 tranType
= TLB::HypMode
;
1787 mode
= BaseTLB::Write
;
1789 case MISCREG_AT_S12E0R_Xt
:
1790 flags
= TLB::MustBeOne
| TLB::UserMode
;
1791 tranType
= TLB::S1S2NsTran
;
1792 mode
= BaseTLB::Read
;
1794 case MISCREG_AT_S12E0W_Xt
:
1795 flags
= TLB::MustBeOne
| TLB::UserMode
;
1796 tranType
= TLB::S1S2NsTran
;
1797 mode
= BaseTLB::Write
;
1799 case MISCREG_AT_S12E1R_Xt
:
1800 flags
= TLB::MustBeOne
;
1801 tranType
= TLB::S1S2NsTran
;
1802 mode
= BaseTLB::Read
;
1804 case MISCREG_AT_S12E1W_Xt
:
1805 flags
= TLB::MustBeOne
;
1806 tranType
= TLB::S1S2NsTran
;
1807 mode
= BaseTLB::Write
;
1809 case MISCREG_AT_S1E3R_Xt
:
1810 flags
= TLB::MustBeOne
;
1811 tranType
= TLB::HypMode
; // There is no TZ mode defined.
1812 mode
= BaseTLB::Read
;
1814 case MISCREG_AT_S1E3W_Xt
:
1815 flags
= TLB::MustBeOne
;
1816 tranType
= TLB::HypMode
; // There is no TZ mode defined.
1817 mode
= BaseTLB::Write
;
1820 // If we're in timing mode then doing the translation in
1821 // functional mode then we're slightly distorting performance
1822 // results obtained from simulations. The translation should be
1823 // done in the same mode the core is running in. NOTE: This
1824 // can't be an atomic translation because that causes problems
1825 // with unexpected atomic snoop requests.
1826 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg
);
1827 req
->setVirt(0, val
, 1, flags
, Request::funcMasterId
,
1828 tc
->pcState().pc());
1829 req
->setThreadContext(tc
->contextId(), tc
->threadId());
1830 fault
= tc
->getDTBPtr()->translateFunctional(req
, tc
, mode
,
1834 if (fault
== NoFault
) {
1835 Addr paddr
= req
->getPaddr();
1836 uint64_t attr
= tc
->getDTBPtr()->getAttr();
1837 uint64_t attr1
= attr
>> 56;
1838 if (!attr1
|| attr1
==0x44) {
1840 attr
&= ~ uint64_t(0x80);
1842 newVal
= (paddr
& mask(47, 12)) | attr
;
1844 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
1847 ArmFault
*armFault
= reinterpret_cast<ArmFault
*>(fault
.get());
1848 // Set fault bit and FSR
1849 FSR fsr
= armFault
->getFsr(tc
);
1851 newVal
= ((fsr
>> 9) & 1) << 11;
1852 // rearange fault status
1853 newVal
|= ((fsr
>> 0) & 0x3f) << 1;
1854 newVal
|= 0x1; // F bit
1855 newVal
|= ((armFault
->iss() >> 7) & 0x1) << 8;
1856 newVal
|= armFault
->isStage2() ? 0x200 : 0;
1858 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
1862 setMiscRegNoEffect(MISCREG_PAR_EL1
, newVal
);
1865 case MISCREG_SPSR_EL3
:
1866 case MISCREG_SPSR_EL2
:
1867 case MISCREG_SPSR_EL1
:
1868 // Force bits 23:21 to 0
1869 newVal
= val
& ~(0x7 << 21);
1871 case MISCREG_L2CTLR
:
1872 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
1873 miscRegName
[misc_reg
], uint32_t(val
));
1876 // Generic Timer registers
1877 case MISCREG_CNTFRQ
:
1878 case MISCREG_CNTFRQ_EL0
:
1879 getSystemCounter(tc
)->setFreq(val
);
1881 case MISCREG_CNTP_CVAL
:
1882 case MISCREG_CNTP_CVAL_EL0
:
1883 getArchTimer(tc
, tc
->cpuId())->setCompareValue(val
);
1885 case MISCREG_CNTP_TVAL
:
1886 case MISCREG_CNTP_TVAL_EL0
:
1887 getArchTimer(tc
, tc
->cpuId())->setTimerValue(val
);
1889 case MISCREG_CNTP_CTL
:
1890 case MISCREG_CNTP_CTL_EL0
:
1891 getArchTimer(tc
, tc
->cpuId())->setControl(val
);
1893 // PL1 phys. timer, secure
1895 case MISCREG_CNTPS_CVAL_EL1
:
1896 case MISCREG_CNTPS_TVAL_EL1
:
1897 case MISCREG_CNTPS_CTL_EL1
:
1898 // PL2 phys. timer, non-secure
1900 case MISCREG_CNTHCTL
:
1901 case MISCREG_CNTHP_CVAL
:
1902 case MISCREG_CNTHP_TVAL
:
1903 case MISCREG_CNTHP_CTL
:
1905 case MISCREG_CNTHCTL_EL2
:
1906 case MISCREG_CNTHP_CVAL_EL2
:
1907 case MISCREG_CNTHP_TVAL_EL2
:
1908 case MISCREG_CNTHP_CTL_EL2
:
1911 case MISCREG_CNTV_CVAL
:
1912 case MISCREG_CNTV_TVAL
:
1913 case MISCREG_CNTV_CTL
:
1915 // case MISCREG_CNTV_CVAL_EL2:
1916 // case MISCREG_CNTV_TVAL_EL2:
1917 // case MISCREG_CNTV_CTL_EL2:
1921 setMiscRegNoEffect(misc_reg
, newVal
);
1925 ISA::tlbiVA(ThreadContext
*tc
, MiscReg newVal
, uint8_t asid
, bool secure_lookup
,
1928 if (haveLargeAsid64
)
1930 Addr va
= ((Addr
) bits(newVal
, 43, 0)) << 12;
1931 System
*sys
= tc
->getSystemPtr();
1932 for (int x
= 0; x
< sys
->numContexts(); x
++) {
1933 ThreadContext
*oc
= sys
->getThreadContext(x
);
1934 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1935 oc
->getITBPtr()->flushMvaAsid(va
, asid
,
1936 secure_lookup
, target_el
);
1937 oc
->getDTBPtr()->flushMvaAsid(va
, asid
,
1938 secure_lookup
, target_el
);
1940 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1942 checker
->getITBPtr()->flushMvaAsid(
1943 va
, asid
, secure_lookup
, target_el
);
1944 checker
->getDTBPtr()->flushMvaAsid(
1945 va
, asid
, secure_lookup
, target_el
);
1951 ISA::tlbiALL(ThreadContext
*tc
, bool secure_lookup
, uint8_t target_el
)
1953 System
*sys
= tc
->getSystemPtr();
1954 for (int x
= 0; x
< sys
->numContexts(); x
++) {
1955 ThreadContext
*oc
= sys
->getThreadContext(x
);
1956 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1957 oc
->getITBPtr()->flushAllSecurity(secure_lookup
, target_el
);
1958 oc
->getDTBPtr()->flushAllSecurity(secure_lookup
, target_el
);
1960 // If CheckerCPU is connected, need to notify it of a flush
1961 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1963 checker
->getITBPtr()->flushAllSecurity(secure_lookup
,
1965 checker
->getDTBPtr()->flushAllSecurity(secure_lookup
,
1972 ISA::tlbiALLN(ThreadContext
*tc
, bool hyp
, uint8_t target_el
)
1974 System
*sys
= tc
->getSystemPtr();
1975 for (int x
= 0; x
< sys
->numContexts(); x
++) {
1976 ThreadContext
*oc
= sys
->getThreadContext(x
);
1977 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1978 oc
->getITBPtr()->flushAllNs(hyp
, target_el
);
1979 oc
->getDTBPtr()->flushAllNs(hyp
, target_el
);
1981 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1983 checker
->getITBPtr()->flushAllNs(hyp
, target_el
);
1984 checker
->getDTBPtr()->flushAllNs(hyp
, target_el
);
1990 ISA::tlbiMVA(ThreadContext
*tc
, MiscReg newVal
, bool secure_lookup
, bool hyp
,
1993 System
*sys
= tc
->getSystemPtr();
1994 for (int x
= 0; x
< sys
->numContexts(); x
++) {
1995 ThreadContext
*oc
= sys
->getThreadContext(x
);
1996 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1997 oc
->getITBPtr()->flushMva(mbits(newVal
, 31,12),
1998 secure_lookup
, hyp
, target_el
);
1999 oc
->getDTBPtr()->flushMva(mbits(newVal
, 31,12),
2000 secure_lookup
, hyp
, target_el
);
2002 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
2004 checker
->getITBPtr()->flushMva(mbits(newVal
, 31,12),
2005 secure_lookup
, hyp
, target_el
);
2006 checker
->getDTBPtr()->flushMva(mbits(newVal
, 31,12),
2007 secure_lookup
, hyp
, target_el
);
2012 ::GenericTimer::SystemCounter
*
2013 ISA::getSystemCounter(ThreadContext
*tc
)
2015 ::GenericTimer::SystemCounter
*cnt
= ((ArmSystem
*) tc
->getSystemPtr())->
2018 panic("System counter not available\n");
2023 ::GenericTimer::ArchTimer
*
2024 ISA::getArchTimer(ThreadContext
*tc
, int cpu_id
)
2026 ::GenericTimer::ArchTimer
*timer
= ((ArmSystem
*) tc
->getSystemPtr())->
2027 getArchTimer(cpu_id
);
2028 if (timer
== NULL
) {
2029 panic("Architected timer not available\n");
2037 ArmISAParams::create()
2039 return new ArmISA::ISA(this);