2 * Copyright (c) 2010-2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
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15 * modification, are permitted provided that the following conditions are
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17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
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23 * this software without specific prior written permission.
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 #include "arch/arm/isa.hh"
42 #include "arch/arm/system.hh"
43 #include "cpu/checker/cpu.hh"
44 #include "debug/Arm.hh"
45 #include "debug/MiscRegs.hh"
46 #include "params/ArmISA.hh"
47 #include "sim/faults.hh"
48 #include "sim/stat_control.hh"
49 #include "sim/system.hh"
59 miscRegs
[MISCREG_SCTLR_RST
] = sctlr
;
66 return dynamic_cast<const Params
*>(_params
);
72 SCTLR sctlr_rst
= miscRegs
[MISCREG_SCTLR_RST
];
73 uint32_t midr
= miscRegs
[MISCREG_MIDR
];
74 memset(miscRegs
, 0, sizeof(miscRegs
));
76 cpsr
.mode
= MODE_USER
;
77 miscRegs
[MISCREG_CPSR
] = cpsr
;
81 sctlr
.te
= (bool)sctlr_rst
.te
;
82 sctlr
.nmfi
= (bool)sctlr_rst
.nmfi
;
83 sctlr
.v
= (bool)sctlr_rst
.v
;
89 miscRegs
[MISCREG_SCTLR
] = sctlr
;
90 miscRegs
[MISCREG_SCTLR_RST
] = sctlr_rst
;
92 // Preserve MIDR across reset
93 miscRegs
[MISCREG_MIDR
] = midr
;
95 /* Start with an event in the mailbox */
96 miscRegs
[MISCREG_SEV_MAILBOX
] = 1;
98 // Separate Instruction and Data TLBs.
99 miscRegs
[MISCREG_TLBTR
] = 1;
102 mvfr0
.advSimdRegisters
= 2;
103 mvfr0
.singlePrecision
= 2;
104 mvfr0
.doublePrecision
= 2;
105 mvfr0
.vfpExceptionTrapping
= 0;
107 mvfr0
.squareRoot
= 1;
108 mvfr0
.shortVectors
= 1;
109 mvfr0
.roundingModes
= 1;
110 miscRegs
[MISCREG_MVFR0
] = mvfr0
;
113 mvfr1
.flushToZero
= 1;
114 mvfr1
.defaultNaN
= 1;
115 mvfr1
.advSimdLoadStore
= 1;
116 mvfr1
.advSimdInteger
= 1;
117 mvfr1
.advSimdSinglePrecision
= 1;
118 mvfr1
.advSimdHalfPrecision
= 1;
119 mvfr1
.vfpHalfPrecision
= 1;
120 miscRegs
[MISCREG_MVFR1
] = mvfr1
;
122 // Reset values of PRRR and NMRR are implementation dependent
124 miscRegs
[MISCREG_PRRR
] =
137 miscRegs
[MISCREG_NMRR
] =
154 miscRegs
[MISCREG_CPACR
] = 0;
155 miscRegs
[MISCREG_FPSID
] = 0x410430A0;
157 // See section B4.1.84 of ARM ARM
158 // All values are latest for ARMv7-A profile
159 miscRegs
[MISCREG_ID_ISAR0
] = 0x02101111;
160 miscRegs
[MISCREG_ID_ISAR1
] = 0x02112111;
161 miscRegs
[MISCREG_ID_ISAR2
] = 0x21232141;
162 miscRegs
[MISCREG_ID_ISAR3
] = 0x01112131;
163 miscRegs
[MISCREG_ID_ISAR4
] = 0x10010142;
164 miscRegs
[MISCREG_ID_ISAR5
] = 0x00000000;
166 //XXX We need to initialize the rest of the state.
170 ISA::readMiscRegNoEffect(int misc_reg
)
172 assert(misc_reg
< NumMiscRegs
);
175 if (misc_reg
== MISCREG_SPSR
)
176 flat_idx
= flattenMiscIndex(misc_reg
);
179 MiscReg val
= miscRegs
[flat_idx
];
181 DPRINTF(MiscRegs
, "Reading From misc reg %d (%d) : %#x\n",
182 misc_reg
, flat_idx
, val
);
188 ISA::readMiscReg(int misc_reg
, ThreadContext
*tc
)
192 if (misc_reg
== MISCREG_CPSR
) {
193 CPSR cpsr
= miscRegs
[misc_reg
];
194 PCState pc
= tc
->pcState();
195 cpsr
.j
= pc
.jazelle() ? 1 : 0;
196 cpsr
.t
= pc
.thumb() ? 1 : 0;
199 if (misc_reg
>= MISCREG_CP15_UNIMP_START
)
200 panic("Unimplemented CP15 register %s read.\n",
201 miscRegName
[misc_reg
]);
205 arm_sys
= dynamic_cast<ArmSystem
*>(tc
->getSystemPtr());
208 if (arm_sys
->multiProc
) {
209 return 0x80000000 | // multiprocessor extensions available
212 return 0x80000000 | // multiprocessor extensions available
213 0x40000000 | // in up system
217 case MISCREG_ID_MMFR0
:
218 return 0x03; // VMSAv7 support
219 case MISCREG_ID_MMFR2
:
220 return 0x01230000; // no HW access | WFI stalling | ISB and DSB
221 // | all TLB maintenance | no Harvard
222 case MISCREG_ID_MMFR3
:
223 return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint |
224 // BP Maint | Cache Maint Set/way | Cache Maint MVA
226 warn_once("The clidr register always reports 0 caches.\n");
227 warn_once("clidr LoUIS field of 0b001 to match current "
228 "ARM implementations.\n");
231 warn_once("The ccsidr register isn't implemented and "
232 "always reads as 0.\n");
234 case MISCREG_ID_PFR0
:
235 warn("Returning thumbEE disabled for now since we don't support CP14"
236 "config registers and jumping to ThumbEE vectors\n");
237 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
238 case MISCREG_ID_PFR1
:
239 return 0x00001; // !Timer | !Virti | !M Profile | !TrustZone | ARMv4
242 //all caches have the same line size in gem5
243 //4 byte words in ARM
244 unsigned lineSizeWords
=
245 tc
->getCpuPtr()->getInstPort().peerBlockSize() / 4;
246 unsigned log2LineSizeWords
= 0;
248 while (lineSizeWords
>>= 1) {
253 //log2 of minimun i-cache line size (words)
254 ctr
.iCacheLineSize
= log2LineSizeWords
;
255 //b11 - gem5 uses pipt
256 ctr
.l1IndexPolicy
= 0x3;
257 //log2 of minimum d-cache line size (words)
258 ctr
.dCacheLineSize
= log2LineSizeWords
;
259 //log2 of max reservation size (words)
260 ctr
.erg
= log2LineSizeWords
;
261 //log2 of max writeback size (words)
262 ctr
.cwg
= log2LineSizeWords
;
263 //b100 - gem5 format is ARMv7
269 warn("Not doing anything for miscreg ACTLR\n");
272 case MISCREG_PMCCNTR
:
274 warn("Not doing anything for read to miscreg %s\n",
275 miscRegName
[misc_reg
]);
278 panic("shouldn't be reading this register seperately\n");
279 case MISCREG_FPSCR_QC
:
280 return readMiscRegNoEffect(MISCREG_FPSCR
) & ~FpscrQcMask
;
281 case MISCREG_FPSCR_EXC
:
282 return readMiscRegNoEffect(MISCREG_FPSCR
) & ~FpscrExcMask
;
285 // mostly unimplemented, just set NumCPUs field from sim and return
287 // b00:1CPU to b11:4CPUs
288 l2ctlr
.numCPUs
= tc
->getSystemPtr()->numContexts() - 1;
291 case MISCREG_DBGDIDR
:
292 /* For now just implement the version number.
293 * Return 0 as we don't support debug architecture yet.
296 case MISCREG_DBGDSCR_INT
:
299 return readMiscRegNoEffect(misc_reg
);
303 ISA::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
)
305 assert(misc_reg
< NumMiscRegs
);
308 if (misc_reg
== MISCREG_SPSR
)
309 flat_idx
= flattenMiscIndex(misc_reg
);
312 miscRegs
[flat_idx
] = val
;
314 DPRINTF(MiscRegs
, "Writing to misc reg %d (%d) : %#x\n", misc_reg
,
319 ISA::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadContext
*tc
)
322 MiscReg newVal
= val
;
327 if (misc_reg
== MISCREG_CPSR
) {
331 CPSR old_cpsr
= miscRegs
[MISCREG_CPSR
];
332 int old_mode
= old_cpsr
.mode
;
334 if (old_mode
!= cpsr
.mode
) {
335 tc
->getITBPtr()->invalidateMiscReg();
336 tc
->getDTBPtr()->invalidateMiscReg();
339 DPRINTF(Arm
, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
340 miscRegs
[misc_reg
], cpsr
, cpsr
.f
, cpsr
.i
, cpsr
.a
, cpsr
.mode
);
341 PCState pc
= tc
->pcState();
342 pc
.nextThumb(cpsr
.t
);
343 pc
.nextJazelle(cpsr
.j
);
345 // Follow slightly different semantics if a CheckerCPU object
347 CheckerCPU
*checker
= tc
->getCheckerCpuPtr();
349 tc
->pcStateNoRecord(pc
);
353 } else if (misc_reg
>= MISCREG_CP15_UNIMP_START
&&
354 misc_reg
< MISCREG_CP15_END
) {
355 panic("Unimplemented CP15 register %s wrote with %#x.\n",
356 miscRegName
[misc_reg
], val
);
362 const uint32_t ones
= (uint32_t)(-1);
364 // Only cp10, cp11, and ase are implemented, nothing else should
366 cpacrMask
.cp10
= ones
;
367 cpacrMask
.cp11
= ones
;
368 cpacrMask
.asedis
= ones
;
370 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
371 miscRegName
[misc_reg
], newVal
);
375 warn_once("The csselr register isn't implemented.\n");
379 const uint32_t ones
= (uint32_t)(-1);
381 fpscrMask
.ioc
= ones
;
382 fpscrMask
.dzc
= ones
;
383 fpscrMask
.ofc
= ones
;
384 fpscrMask
.ufc
= ones
;
385 fpscrMask
.ixc
= ones
;
386 fpscrMask
.idc
= ones
;
387 fpscrMask
.len
= ones
;
388 fpscrMask
.stride
= ones
;
389 fpscrMask
.rMode
= ones
;
392 fpscrMask
.ahp
= ones
;
398 newVal
= (newVal
& (uint32_t)fpscrMask
) |
399 (miscRegs
[MISCREG_FPSCR
] & ~(uint32_t)fpscrMask
);
400 tc
->getDecoderPtr()->setContext(newVal
);
405 assert(!(newVal
& ~CpsrMaskQ
));
406 newVal
= miscRegs
[MISCREG_CPSR
] | newVal
;
407 misc_reg
= MISCREG_CPSR
;
410 case MISCREG_FPSCR_QC
:
412 newVal
= miscRegs
[MISCREG_FPSCR
] | (newVal
& FpscrQcMask
);
413 misc_reg
= MISCREG_FPSCR
;
416 case MISCREG_FPSCR_EXC
:
418 newVal
= miscRegs
[MISCREG_FPSCR
] | (newVal
& FpscrExcMask
);
419 misc_reg
= MISCREG_FPSCR
;
424 // vfpv3 architecture, section B.6.1 of DDI04068
425 // bit 29 - valid only if fpexc[31] is 0
426 const uint32_t fpexcMask
= 0x60000000;
427 newVal
= (newVal
& fpexcMask
) |
428 (miscRegs
[MISCREG_FPEXC
] & ~fpexcMask
);
433 DPRINTF(MiscRegs
, "Writing SCTLR: %#x\n", newVal
);
434 SCTLR sctlr
= miscRegs
[MISCREG_SCTLR
];
435 SCTLR new_sctlr
= newVal
;
436 new_sctlr
.nmfi
= (bool)sctlr
.nmfi
;
437 miscRegs
[MISCREG_SCTLR
] = (MiscReg
)new_sctlr
;
438 tc
->getITBPtr()->invalidateMiscReg();
439 tc
->getDTBPtr()->invalidateMiscReg();
441 // Check if all CPUs are booted with caches enabled
442 // so we can stop enforcing coherency of some kernel
443 // structures manually.
444 sys
= tc
->getSystemPtr();
445 for (x
= 0; x
< sys
->numContexts(); x
++) {
446 oc
= sys
->getThreadContext(x
);
447 SCTLR other_sctlr
= oc
->readMiscRegNoEffect(MISCREG_SCTLR
);
448 if (!other_sctlr
.c
&& oc
->status() != ThreadContext::Halted
)
452 for (x
= 0; x
< sys
->numContexts(); x
++) {
453 oc
= sys
->getThreadContext(x
);
454 oc
->getDTBPtr()->allCpusCaching();
455 oc
->getITBPtr()->allCpusCaching();
457 // If CheckerCPU is connected, need to notify it.
458 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
460 checker
->getDTBPtr()->allCpusCaching();
461 checker
->getITBPtr()->allCpusCaching();
472 case MISCREG_TLBIALLIS
:
473 case MISCREG_TLBIALL
:
474 sys
= tc
->getSystemPtr();
475 for (x
= 0; x
< sys
->numContexts(); x
++) {
476 oc
= sys
->getThreadContext(x
);
477 assert(oc
->getITBPtr() && oc
->getDTBPtr());
478 oc
->getITBPtr()->flushAll();
479 oc
->getDTBPtr()->flushAll();
481 // If CheckerCPU is connected, need to notify it of a flush
482 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
484 checker
->getITBPtr()->flushAll();
485 checker
->getDTBPtr()->flushAll();
489 case MISCREG_ITLBIALL
:
490 tc
->getITBPtr()->flushAll();
492 case MISCREG_DTLBIALL
:
493 tc
->getDTBPtr()->flushAll();
495 case MISCREG_TLBIMVAIS
:
496 case MISCREG_TLBIMVA
:
497 sys
= tc
->getSystemPtr();
498 for (x
= 0; x
< sys
->numContexts(); x
++) {
499 oc
= sys
->getThreadContext(x
);
500 assert(oc
->getITBPtr() && oc
->getDTBPtr());
501 oc
->getITBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
503 oc
->getDTBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
506 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
508 checker
->getITBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
510 checker
->getDTBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
515 case MISCREG_TLBIASIDIS
:
516 case MISCREG_TLBIASID
:
517 sys
= tc
->getSystemPtr();
518 for (x
= 0; x
< sys
->numContexts(); x
++) {
519 oc
= sys
->getThreadContext(x
);
520 assert(oc
->getITBPtr() && oc
->getDTBPtr());
521 oc
->getITBPtr()->flushAsid(bits(newVal
, 7,0));
522 oc
->getDTBPtr()->flushAsid(bits(newVal
, 7,0));
523 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
525 checker
->getITBPtr()->flushAsid(bits(newVal
, 7,0));
526 checker
->getDTBPtr()->flushAsid(bits(newVal
, 7,0));
530 case MISCREG_TLBIMVAAIS
:
531 case MISCREG_TLBIMVAA
:
532 sys
= tc
->getSystemPtr();
533 for (x
= 0; x
< sys
->numContexts(); x
++) {
534 oc
= sys
->getThreadContext(x
);
535 assert(oc
->getITBPtr() && oc
->getDTBPtr());
536 oc
->getITBPtr()->flushMva(mbits(newVal
, 31,12));
537 oc
->getDTBPtr()->flushMva(mbits(newVal
, 31,12));
539 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
541 checker
->getITBPtr()->flushMva(mbits(newVal
, 31,12));
542 checker
->getDTBPtr()->flushMva(mbits(newVal
, 31,12));
546 case MISCREG_ITLBIMVA
:
547 tc
->getITBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
550 case MISCREG_DTLBIMVA
:
551 tc
->getDTBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
554 case MISCREG_ITLBIASID
:
555 tc
->getITBPtr()->flushAsid(bits(newVal
, 7,0));
557 case MISCREG_DTLBIASID
:
558 tc
->getDTBPtr()->flushAsid(bits(newVal
, 7,0));
561 warn("Not doing anything for write of miscreg ACTLR\n");
565 // Performance counters not implemented. Instead, interpret
566 // a reset command to this register to reset the simulator
568 // PMCR_E | PMCR_P | PMCR_C
569 const int ResetAndEnableCounters
= 0x7;
570 if (newVal
== ResetAndEnableCounters
) {
571 inform("Resetting all simobject stats\n");
572 Stats::schedStatEvent(false, true);
576 case MISCREG_PMCCNTR
:
578 warn("Not doing anything for write to miscreg %s\n",
579 miscRegName
[misc_reg
]);
581 case MISCREG_V2PCWPR
:
582 case MISCREG_V2PCWPW
:
583 case MISCREG_V2PCWUR
:
584 case MISCREG_V2PCWUW
:
585 case MISCREG_V2POWPR
:
586 case MISCREG_V2POWPW
:
587 case MISCREG_V2POWUR
:
588 case MISCREG_V2POWUW
:
590 RequestPtr req
= new Request
;
595 case MISCREG_V2PCWPR
:
596 flags
= TLB::MustBeOne
;
597 mode
= BaseTLB::Read
;
599 case MISCREG_V2PCWPW
:
600 flags
= TLB::MustBeOne
;
601 mode
= BaseTLB::Write
;
603 case MISCREG_V2PCWUR
:
604 flags
= TLB::MustBeOne
| TLB::UserMode
;
605 mode
= BaseTLB::Read
;
607 case MISCREG_V2PCWUW
:
608 flags
= TLB::MustBeOne
| TLB::UserMode
;
609 mode
= BaseTLB::Write
;
612 panic("Security Extensions not implemented!");
614 warn("Translating via MISCREG in atomic mode! Fix Me!\n");
615 req
->setVirt(0, val
, 1, flags
, tc
->pcState().pc(),
616 Request::funcMasterId
);
617 fault
= tc
->getDTBPtr()->translateAtomic(req
, tc
, mode
);
618 if (fault
== NoFault
) {
619 miscRegs
[MISCREG_PAR
] =
620 (req
->getPaddr() & 0xfffff000) |
621 (tc
->getDTBPtr()->getAttr() );
623 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
624 val
, miscRegs
[MISCREG_PAR
]);
627 // Set fault bit and FSR
628 FSR fsr
= miscRegs
[MISCREG_DFSR
];
629 miscRegs
[MISCREG_PAR
] =
637 case MISCREG_CONTEXTIDR
:
641 tc
->getITBPtr()->invalidateMiscReg();
642 tc
->getDTBPtr()->invalidateMiscReg();
644 case MISCREG_CPSR_MODE
:
645 // This miscreg is used by copy*Regs to set the CPSR mode
646 // without updating other CPSR variables. It's used to
647 // make sure the register map is in such a state that we can
648 // see all of the registers for the copy.
652 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
653 miscRegName
[misc_reg
], uint32_t(val
));
656 setMiscRegNoEffect(misc_reg
, newVal
);
662 ArmISAParams::create()
664 return new ArmISA::ISA(this);