2 * Copyright (c) 2010-2014 ARM Limited
5 * The license below extends only to copyright in the software and shall
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41 #include "arch/arm/isa.hh"
42 #include "arch/arm/system.hh"
43 #include "cpu/checker/cpu.hh"
44 #include "debug/Arm.hh"
45 #include "debug/MiscRegs.hh"
46 #include "params/ArmISA.hh"
47 #include "sim/faults.hh"
48 #include "sim/stat_control.hh"
49 #include "sim/system.hh"
56 * Some registers aliase with others, and therefore need to be translated.
58 * The first value is the misc register that is to be looked up
59 * the second value is the lower part of the translation
60 * the third the upper part
62 const struct ISA::MiscRegInitializerEntry
63 ISA::MiscRegSwitch
[miscRegTranslateMax
] = {
64 {MISCREG_CSSELR_EL1
, {MISCREG_CSSELR
, 0}},
65 {MISCREG_SCTLR_EL1
, {MISCREG_SCTLR
, 0}},
66 {MISCREG_SCTLR_EL2
, {MISCREG_HSCTLR
, 0}},
67 {MISCREG_ACTLR_EL1
, {MISCREG_ACTLR
, 0}},
68 {MISCREG_ACTLR_EL2
, {MISCREG_HACTLR
, 0}},
69 {MISCREG_CPACR_EL1
, {MISCREG_CPACR
, 0}},
70 {MISCREG_CPTR_EL2
, {MISCREG_HCPTR
, 0}},
71 {MISCREG_HCR_EL2
, {MISCREG_HCR
, 0}},
72 {MISCREG_MDCR_EL2
, {MISCREG_HDCR
, 0}},
73 {MISCREG_HSTR_EL2
, {MISCREG_HSTR
, 0}},
74 {MISCREG_HACR_EL2
, {MISCREG_HACR
, 0}},
75 {MISCREG_TTBR0_EL1
, {MISCREG_TTBR0
, 0}},
76 {MISCREG_TTBR1_EL1
, {MISCREG_TTBR1
, 0}},
77 {MISCREG_TTBR0_EL2
, {MISCREG_HTTBR
, 0}},
78 {MISCREG_VTTBR_EL2
, {MISCREG_VTTBR
, 0}},
79 {MISCREG_TCR_EL1
, {MISCREG_TTBCR
, 0}},
80 {MISCREG_TCR_EL2
, {MISCREG_HTCR
, 0}},
81 {MISCREG_VTCR_EL2
, {MISCREG_VTCR
, 0}},
82 {MISCREG_AFSR0_EL1
, {MISCREG_ADFSR
, 0}},
83 {MISCREG_AFSR1_EL1
, {MISCREG_AIFSR
, 0}},
84 {MISCREG_AFSR0_EL2
, {MISCREG_HADFSR
, 0}},
85 {MISCREG_AFSR1_EL2
, {MISCREG_HAIFSR
, 0}},
86 {MISCREG_ESR_EL2
, {MISCREG_HSR
, 0}},
87 {MISCREG_FAR_EL1
, {MISCREG_DFAR
, MISCREG_IFAR
}},
88 {MISCREG_FAR_EL2
, {MISCREG_HDFAR
, MISCREG_HIFAR
}},
89 {MISCREG_HPFAR_EL2
, {MISCREG_HPFAR
, 0}},
90 {MISCREG_PAR_EL1
, {MISCREG_PAR
, 0}},
91 {MISCREG_MAIR_EL1
, {MISCREG_PRRR
, MISCREG_NMRR
}},
92 {MISCREG_MAIR_EL2
, {MISCREG_HMAIR0
, MISCREG_HMAIR1
}},
93 {MISCREG_AMAIR_EL1
, {MISCREG_AMAIR0
, MISCREG_AMAIR1
}},
94 {MISCREG_VBAR_EL1
, {MISCREG_VBAR
, 0}},
95 {MISCREG_VBAR_EL2
, {MISCREG_HVBAR
, 0}},
96 {MISCREG_CONTEXTIDR_EL1
, {MISCREG_CONTEXTIDR
, 0}},
97 {MISCREG_TPIDR_EL0
, {MISCREG_TPIDRURW
, 0}},
98 {MISCREG_TPIDRRO_EL0
, {MISCREG_TPIDRURO
, 0}},
99 {MISCREG_TPIDR_EL1
, {MISCREG_TPIDRPRW
, 0}},
100 {MISCREG_TPIDR_EL2
, {MISCREG_HTPIDR
, 0}},
101 {MISCREG_TEECR32_EL1
, {MISCREG_TEECR
, 0}},
102 {MISCREG_CNTFRQ_EL0
, {MISCREG_CNTFRQ
, 0}},
103 {MISCREG_CNTPCT_EL0
, {MISCREG_CNTPCT
, 0}},
104 {MISCREG_CNTVCT_EL0
, {MISCREG_CNTVCT
, 0}},
105 {MISCREG_CNTVOFF_EL2
, {MISCREG_CNTVOFF
, 0}},
106 {MISCREG_CNTKCTL_EL1
, {MISCREG_CNTKCTL
, 0}},
107 {MISCREG_CNTHCTL_EL2
, {MISCREG_CNTHCTL
, 0}},
108 {MISCREG_CNTP_TVAL_EL0
, {MISCREG_CNTP_TVAL
, 0}},
109 {MISCREG_CNTP_CTL_EL0
, {MISCREG_CNTP_CTL
, 0}},
110 {MISCREG_CNTP_CVAL_EL0
, {MISCREG_CNTP_CVAL
, 0}},
111 {MISCREG_CNTV_TVAL_EL0
, {MISCREG_CNTV_TVAL
, 0}},
112 {MISCREG_CNTV_CTL_EL0
, {MISCREG_CNTV_CTL
, 0}},
113 {MISCREG_CNTV_CVAL_EL0
, {MISCREG_CNTV_CVAL
, 0}},
114 {MISCREG_CNTHP_TVAL_EL2
, {MISCREG_CNTHP_TVAL
, 0}},
115 {MISCREG_CNTHP_CTL_EL2
, {MISCREG_CNTHP_CTL
, 0}},
116 {MISCREG_CNTHP_CVAL_EL2
, {MISCREG_CNTHP_CVAL
, 0}},
117 {MISCREG_DACR32_EL2
, {MISCREG_DACR
, 0}},
118 {MISCREG_IFSR32_EL2
, {MISCREG_IFSR
, 0}},
119 {MISCREG_TEEHBR32_EL1
, {MISCREG_TEEHBR
, 0}},
120 {MISCREG_SDER32_EL3
, {MISCREG_SDER
, 0}}
125 : SimObject(p
), system(NULL
), lookUpMiscReg(NUM_MISCREGS
, {0,0})
129 miscRegs
[MISCREG_SCTLR_RST
] = sctlr
;
131 system
= dynamic_cast<ArmSystem
*>(p
->system
);
132 DPRINTFN("ISA system set to: %p %p\n", system
, p
->system
);
134 // Cache system-level properties
135 if (FullSystem
&& system
) {
136 haveSecurity
= system
->haveSecurity();
137 haveLPAE
= system
->haveLPAE();
138 haveVirtualization
= system
->haveVirtualization();
139 haveLargeAsid64
= system
->haveLargeAsid64();
140 physAddrRange64
= system
->physAddrRange64();
142 haveSecurity
= haveLPAE
= haveVirtualization
= false;
143 haveLargeAsid64
= false;
144 physAddrRange64
= 32; // dummy value
147 /** Fill in the miscReg translation table */
148 for (uint32_t i
= 0; i
< miscRegTranslateMax
; i
++) {
149 struct MiscRegLUTEntry new_entry
;
151 uint32_t select
= MiscRegSwitch
[i
].index
;
152 new_entry
= MiscRegSwitch
[i
].entry
;
154 lookUpMiscReg
[select
] = new_entry
;
157 preUnflattenMiscReg();
165 return dynamic_cast<const Params
*>(_params
);
171 const Params
*p(params());
173 SCTLR sctlr_rst
= miscRegs
[MISCREG_SCTLR_RST
];
174 memset(miscRegs
, 0, sizeof(miscRegs
));
176 // Initialize configurable default values
177 miscRegs
[MISCREG_MIDR
] = p
->midr
;
178 miscRegs
[MISCREG_MIDR_EL1
] = p
->midr
;
179 miscRegs
[MISCREG_VPIDR
] = p
->midr
;
181 if (FullSystem
&& system
->highestELIs64()) {
182 // Initialize AArch64 state
187 // Initialize AArch32 state...
190 cpsr
.mode
= MODE_USER
;
191 miscRegs
[MISCREG_CPSR
] = cpsr
;
195 sctlr
.te
= (bool) sctlr_rst
.te
;
196 sctlr
.nmfi
= (bool) sctlr_rst
.nmfi
;
197 sctlr
.v
= (bool) sctlr_rst
.v
;
202 sctlr
.rao4
= 0xf; // SCTLR[6:3]
205 miscRegs
[MISCREG_SCTLR_NS
] = sctlr
;
206 miscRegs
[MISCREG_SCTLR_RST
] = sctlr_rst
;
207 miscRegs
[MISCREG_HCPTR
] = 0;
209 // Start with an event in the mailbox
210 miscRegs
[MISCREG_SEV_MAILBOX
] = 1;
212 // Separate Instruction and Data TLBs
213 miscRegs
[MISCREG_TLBTR
] = 1;
216 mvfr0
.advSimdRegisters
= 2;
217 mvfr0
.singlePrecision
= 2;
218 mvfr0
.doublePrecision
= 2;
219 mvfr0
.vfpExceptionTrapping
= 0;
221 mvfr0
.squareRoot
= 1;
222 mvfr0
.shortVectors
= 1;
223 mvfr0
.roundingModes
= 1;
224 miscRegs
[MISCREG_MVFR0
] = mvfr0
;
227 mvfr1
.flushToZero
= 1;
228 mvfr1
.defaultNaN
= 1;
229 mvfr1
.advSimdLoadStore
= 1;
230 mvfr1
.advSimdInteger
= 1;
231 mvfr1
.advSimdSinglePrecision
= 1;
232 mvfr1
.advSimdHalfPrecision
= 1;
233 mvfr1
.vfpHalfPrecision
= 1;
234 miscRegs
[MISCREG_MVFR1
] = mvfr1
;
236 // Reset values of PRRR and NMRR are implementation dependent
238 // @todo: PRRR and NMRR in secure state?
239 miscRegs
[MISCREG_PRRR_NS
] =
252 miscRegs
[MISCREG_NMRR_NS
] =
269 miscRegs
[MISCREG_CPACR
] = 0;
272 miscRegs
[MISCREG_ID_PFR0
] = p
->id_pfr0
;
273 miscRegs
[MISCREG_ID_PFR1
] = p
->id_pfr1
;
275 miscRegs
[MISCREG_ID_MMFR0
] = p
->id_mmfr0
;
276 miscRegs
[MISCREG_ID_MMFR1
] = p
->id_mmfr1
;
277 miscRegs
[MISCREG_ID_MMFR2
] = p
->id_mmfr2
;
278 miscRegs
[MISCREG_ID_MMFR3
] = p
->id_mmfr3
;
280 miscRegs
[MISCREG_ID_ISAR0
] = p
->id_isar0
;
281 miscRegs
[MISCREG_ID_ISAR1
] = p
->id_isar1
;
282 miscRegs
[MISCREG_ID_ISAR2
] = p
->id_isar2
;
283 miscRegs
[MISCREG_ID_ISAR3
] = p
->id_isar3
;
284 miscRegs
[MISCREG_ID_ISAR4
] = p
->id_isar4
;
285 miscRegs
[MISCREG_ID_ISAR5
] = p
->id_isar5
;
287 miscRegs
[MISCREG_FPSID
] = p
->fpsid
;
290 TTBCR ttbcr
= miscRegs
[MISCREG_TTBCR_NS
];
292 miscRegs
[MISCREG_TTBCR_NS
] = ttbcr
;
293 // Enforce consistency with system-level settings
294 miscRegs
[MISCREG_ID_MMFR0
] = (miscRegs
[MISCREG_ID_MMFR0
] & ~0xf) | 0x5;
298 miscRegs
[MISCREG_SCTLR_S
] = sctlr
;
299 miscRegs
[MISCREG_SCR
] = 0;
300 miscRegs
[MISCREG_VBAR_S
] = 0;
302 // we're always non-secure
303 miscRegs
[MISCREG_SCR
] = 1;
306 //XXX We need to initialize the rest of the state.
310 ISA::clear64(const ArmISAParams
*p
)
313 Addr rvbar
= system
->resetAddr64();
314 switch (system
->highestEL()) {
315 // Set initial EL to highest implemented EL using associated stack
316 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
319 cpsr
.mode
= MODE_EL3H
;
320 miscRegs
[MISCREG_RVBAR_EL3
] = rvbar
;
323 cpsr
.mode
= MODE_EL2H
;
324 miscRegs
[MISCREG_RVBAR_EL2
] = rvbar
;
327 cpsr
.mode
= MODE_EL1H
;
328 miscRegs
[MISCREG_RVBAR_EL1
] = rvbar
;
331 panic("Invalid highest implemented exception level");
335 // Initialize rest of CPSR
336 cpsr
.daif
= 0xf; // Mask all interrupts
339 miscRegs
[MISCREG_CPSR
] = cpsr
;
342 // Initialize other control registers
343 miscRegs
[MISCREG_MPIDR_EL1
] = 0x80000000;
345 miscRegs
[MISCREG_SCTLR_EL3
] = 0x30c50870;
346 miscRegs
[MISCREG_SCR_EL3
] = 0x00000030; // RES1 fields
347 // @todo: uncomment this to enable Virtualization
348 // } else if (haveVirtualization) {
349 // miscRegs[MISCREG_SCTLR_EL2] = 0x30c50870;
351 miscRegs
[MISCREG_SCTLR_EL1
] = 0x30c50870;
353 miscRegs
[MISCREG_SCR_EL3
] = 1;
356 // Initialize configurable id registers
357 miscRegs
[MISCREG_ID_AA64AFR0_EL1
] = p
->id_aa64afr0_el1
;
358 miscRegs
[MISCREG_ID_AA64AFR1_EL1
] = p
->id_aa64afr1_el1
;
359 miscRegs
[MISCREG_ID_AA64DFR0_EL1
] = p
->id_aa64dfr0_el1
;
360 miscRegs
[MISCREG_ID_AA64DFR1_EL1
] = p
->id_aa64dfr1_el1
;
361 miscRegs
[MISCREG_ID_AA64ISAR0_EL1
] = p
->id_aa64isar0_el1
;
362 miscRegs
[MISCREG_ID_AA64ISAR1_EL1
] = p
->id_aa64isar1_el1
;
363 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
] = p
->id_aa64mmfr0_el1
;
364 miscRegs
[MISCREG_ID_AA64MMFR1_EL1
] = p
->id_aa64mmfr1_el1
;
365 miscRegs
[MISCREG_ID_AA64PFR0_EL1
] = p
->id_aa64pfr0_el1
;
366 miscRegs
[MISCREG_ID_AA64PFR1_EL1
] = p
->id_aa64pfr1_el1
;
368 // Enforce consistency with system-level settings...
371 // (no AArch32/64 interprocessing support for now)
372 miscRegs
[MISCREG_ID_AA64PFR0_EL1
] = insertBits(
373 miscRegs
[MISCREG_ID_AA64PFR0_EL1
], 15, 12,
374 haveSecurity
? 0x1 : 0x0);
376 // (no AArch32/64 interprocessing support for now)
377 miscRegs
[MISCREG_ID_AA64PFR0_EL1
] = insertBits(
378 miscRegs
[MISCREG_ID_AA64PFR0_EL1
], 11, 8,
379 haveVirtualization
? 0x1 : 0x0);
380 // Large ASID support
381 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
] = insertBits(
382 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
], 7, 4,
383 haveLargeAsid64
? 0x2 : 0x0);
384 // Physical address size
385 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
] = insertBits(
386 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
], 3, 0,
387 encodePhysAddrRange64(physAddrRange64
));
391 ISA::readMiscRegNoEffect(int misc_reg
) const
393 assert(misc_reg
< NumMiscRegs
);
395 int flat_idx
= flattenMiscIndex(misc_reg
); // Note: indexes of AArch64
396 // registers are left unchanged
399 if (lookUpMiscReg
[flat_idx
].lower
== 0 || flat_idx
== MISCREG_SPSR
400 || flat_idx
== MISCREG_SCTLR_EL1
) {
401 if (flat_idx
== MISCREG_SPSR
)
402 flat_idx
= flattenMiscIndex(MISCREG_SPSR
);
403 if (flat_idx
== MISCREG_SCTLR_EL1
)
404 flat_idx
= flattenMiscIndex(MISCREG_SCTLR
);
405 val
= miscRegs
[flat_idx
];
407 if (lookUpMiscReg
[flat_idx
].upper
> 0)
408 val
= ((miscRegs
[lookUpMiscReg
[flat_idx
].lower
] & mask(32))
409 | (miscRegs
[lookUpMiscReg
[flat_idx
].upper
] << 32));
411 val
= miscRegs
[lookUpMiscReg
[flat_idx
].lower
];
418 ISA::readMiscReg(int misc_reg
, ThreadContext
*tc
)
424 if (misc_reg
== MISCREG_CPSR
) {
425 cpsr
= miscRegs
[misc_reg
];
427 cpsr
.j
= pc
.jazelle() ? 1 : 0;
428 cpsr
.t
= pc
.thumb() ? 1 : 0;
433 if (!miscRegInfo
[misc_reg
][MISCREG_IMPLEMENTED
]) {
434 if (miscRegInfo
[misc_reg
][MISCREG_WARN_NOT_FAIL
])
435 warn("Unimplemented system register %s read.\n",
436 miscRegName
[misc_reg
]);
438 panic("Unimplemented system register %s read.\n",
439 miscRegName
[misc_reg
]);
443 switch (unflattenMiscReg(misc_reg
)) {
446 if (!haveVirtualization
)
449 return readMiscRegNoEffect(MISCREG_HCR
);
453 const uint32_t ones
= (uint32_t)(-1);
455 // Only cp10, cp11, and ase are implemented, nothing else should
456 // be readable? (straight copy from the write code)
457 cpacrMask
.cp10
= ones
;
458 cpacrMask
.cp11
= ones
;
459 cpacrMask
.asedis
= ones
;
461 // Security Extensions may limit the readability of CPACR
463 scr
= readMiscRegNoEffect(MISCREG_SCR
);
464 cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
465 if (scr
.ns
&& (cpsr
.mode
!= MODE_MON
)) {
466 NSACR nsacr
= readMiscRegNoEffect(MISCREG_NSACR
);
467 // NB: Skipping the full loop, here
468 if (!nsacr
.cp10
) cpacrMask
.cp10
= 0;
469 if (!nsacr
.cp11
) cpacrMask
.cp11
= 0;
472 MiscReg val
= readMiscRegNoEffect(MISCREG_CPACR
);
474 DPRINTF(MiscRegs
, "Reading misc reg %s: %#x\n",
475 miscRegName
[misc_reg
], val
);
479 cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
480 scr
= readMiscRegNoEffect(MISCREG_SCR
);
481 if ((cpsr
.mode
== MODE_HYP
) || inSecureState(scr
, cpsr
)) {
482 return getMPIDR(system
, tc
);
484 return readMiscReg(MISCREG_VMPIDR
, tc
);
487 case MISCREG_MPIDR_EL1
:
488 // @todo in the absence of v8 virtualization support just return MPIDR_EL1
489 return getMPIDR(system
, tc
) & 0xffffffff;
491 // top bit defined as RES1
492 return readMiscRegNoEffect(misc_reg
) | 0x80000000;
493 case MISCREG_ID_AFR0
: // not implemented, so alias MIDR
494 case MISCREG_ID_DFR0
: // not implemented, so alias MIDR
495 case MISCREG_REVIDR
: // not implemented, so alias MIDR
497 cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
498 scr
= readMiscRegNoEffect(MISCREG_SCR
);
499 if ((cpsr
.mode
== MODE_HYP
) || inSecureState(scr
, cpsr
)) {
500 return readMiscRegNoEffect(misc_reg
);
502 return readMiscRegNoEffect(MISCREG_VPIDR
);
505 case MISCREG_JOSCR
: // Jazelle trivial implementation, RAZ/WI
506 case MISCREG_JMCR
: // Jazelle trivial implementation, RAZ/WI
507 case MISCREG_JIDR
: // Jazelle trivial implementation, RAZ/WI
508 case MISCREG_AIDR
: // AUX ID set to 0
509 case MISCREG_TCMTR
: // No TCM's
513 warn_once("The clidr register always reports 0 caches.\n");
514 warn_once("clidr LoUIS field of 0b001 to match current "
515 "ARM implementations.\n");
518 warn_once("The ccsidr register isn't implemented and "
519 "always reads as 0.\n");
523 //all caches have the same line size in gem5
524 //4 byte words in ARM
525 unsigned lineSizeWords
=
526 tc
->getSystemPtr()->cacheLineSize() / 4;
527 unsigned log2LineSizeWords
= 0;
529 while (lineSizeWords
>>= 1) {
534 //log2 of minimun i-cache line size (words)
535 ctr
.iCacheLineSize
= log2LineSizeWords
;
536 //b11 - gem5 uses pipt
537 ctr
.l1IndexPolicy
= 0x3;
538 //log2 of minimum d-cache line size (words)
539 ctr
.dCacheLineSize
= log2LineSizeWords
;
540 //log2 of max reservation size (words)
541 ctr
.erg
= log2LineSizeWords
;
542 //log2 of max writeback size (words)
543 ctr
.cwg
= log2LineSizeWords
;
544 //b100 - gem5 format is ARMv7
550 warn("Not doing anything for miscreg ACTLR\n");
553 case MISCREG_PMCCNTR
:
555 warn("Not doing anything for read to miscreg %s\n",
556 miscRegName
[misc_reg
]);
559 panic("shouldn't be reading this register seperately\n");
560 case MISCREG_FPSCR_QC
:
561 return readMiscRegNoEffect(MISCREG_FPSCR
) & ~FpscrQcMask
;
562 case MISCREG_FPSCR_EXC
:
563 return readMiscRegNoEffect(MISCREG_FPSCR
) & ~FpscrExcMask
;
566 const uint32_t ones
= (uint32_t)(-1);
568 fpscrMask
.ioc
= ones
;
569 fpscrMask
.dzc
= ones
;
570 fpscrMask
.ofc
= ones
;
571 fpscrMask
.ufc
= ones
;
572 fpscrMask
.ixc
= ones
;
573 fpscrMask
.idc
= ones
;
579 return readMiscRegNoEffect(MISCREG_FPSCR
) & (uint32_t)fpscrMask
;
583 const uint32_t ones
= (uint32_t)(-1);
585 fpscrMask
.ioe
= ones
;
586 fpscrMask
.dze
= ones
;
587 fpscrMask
.ofe
= ones
;
588 fpscrMask
.ufe
= ones
;
589 fpscrMask
.ixe
= ones
;
590 fpscrMask
.ide
= ones
;
591 fpscrMask
.len
= ones
;
592 fpscrMask
.stride
= ones
;
593 fpscrMask
.rMode
= ones
;
596 fpscrMask
.ahp
= ones
;
597 return readMiscRegNoEffect(MISCREG_FPSCR
) & (uint32_t)fpscrMask
;
602 cpsr
.nz
= tc
->readCCReg(CCREG_NZ
);
603 cpsr
.c
= tc
->readCCReg(CCREG_C
);
604 cpsr
.v
= tc
->readCCReg(CCREG_V
);
610 cpsr
.daif
= (uint8_t) ((CPSR
) miscRegs
[MISCREG_CPSR
]).daif
;
615 return tc
->readIntReg(INTREG_SP0
);
619 return tc
->readIntReg(INTREG_SP1
);
623 return tc
->readIntReg(INTREG_SP2
);
627 return miscRegs
[MISCREG_CPSR
] & 0x1;
629 case MISCREG_CURRENTEL
:
631 return miscRegs
[MISCREG_CPSR
] & 0xc;
635 // mostly unimplemented, just set NumCPUs field from sim and return
637 // b00:1CPU to b11:4CPUs
638 l2ctlr
.numCPUs
= tc
->getSystemPtr()->numContexts() - 1;
641 case MISCREG_DBGDIDR
:
642 /* For now just implement the version number.
643 * Return 0 as we don't support debug architecture yet.
646 case MISCREG_DBGDSCRint
:
649 return tc
->getCpuPtr()->getInterruptController()->getISR(
650 readMiscRegNoEffect(MISCREG_HCR
),
651 readMiscRegNoEffect(MISCREG_CPSR
),
652 readMiscRegNoEffect(MISCREG_SCR
));
653 case MISCREG_ISR_EL1
:
654 return tc
->getCpuPtr()->getInterruptController()->getISR(
655 readMiscRegNoEffect(MISCREG_HCR_EL2
),
656 readMiscRegNoEffect(MISCREG_CPSR
),
657 readMiscRegNoEffect(MISCREG_SCR_EL3
));
658 case MISCREG_DCZID_EL0
:
659 return 0x04; // DC ZVA clear 64-byte chunks
662 MiscReg val
= readMiscRegNoEffect(misc_reg
);
663 // The trap bit associated with CP14 is defined as RAZ
665 // If a CP bit in NSACR is 0 then the corresponding bit in
667 bool secure_lookup
= haveSecurity
&&
668 inSecureState(readMiscRegNoEffect(MISCREG_SCR
),
669 readMiscRegNoEffect(MISCREG_CPSR
));
670 if (!secure_lookup
) {
671 MiscReg mask
= readMiscRegNoEffect(MISCREG_NSACR
);
672 val
|= (mask
^ 0x7FFF) & 0xBFFF;
674 // Set the bits for unimplemented coprocessors to RAO/WI
678 case MISCREG_HDFAR
: // alias for secure DFAR
679 return readMiscRegNoEffect(MISCREG_DFAR_S
);
680 case MISCREG_HIFAR
: // alias for secure IFAR
681 return readMiscRegNoEffect(MISCREG_IFAR_S
);
682 case MISCREG_HVBAR
: // bottom bits reserved
683 return readMiscRegNoEffect(MISCREG_HVBAR
) & 0xFFFFFFE0;
684 case MISCREG_SCTLR
: // Some bits hardwired
685 // The FI field (bit 21) is common between S/NS versions of the register
686 return (readMiscRegNoEffect(MISCREG_SCTLR_S
) & (1 << 21)) |
687 (readMiscRegNoEffect(misc_reg
) & 0x72DD39FF) | 0x00C00818; // V8 SCTLR
688 case MISCREG_SCTLR_EL1
:
689 // The FI field (bit 21) is common between S/NS versions of the register
690 return (readMiscRegNoEffect(MISCREG_SCTLR_S
) & (1 << 21)) |
691 (readMiscRegNoEffect(misc_reg
) & 0x37DDDBFF) | 0x30D00800; // V8 SCTLR_EL1
692 case MISCREG_SCTLR_EL3
:
693 // The FI field (bit 21) is common between S/NS versions of the register
694 return (readMiscRegNoEffect(MISCREG_SCTLR_S
) & (1 << 21)) |
695 (readMiscRegNoEffect(misc_reg
) & 0x32CD183F) | 0x30C50830; // V8 SCTLR_EL3
696 case MISCREG_HSCTLR
: // FI comes from SCTLR
698 uint32_t mask
= 1 << 27;
699 return (readMiscRegNoEffect(MISCREG_HSCTLR
) & ~mask
) |
700 (readMiscRegNoEffect(MISCREG_SCTLR
) & mask
);
704 CPSR cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
706 return readMiscRegNoEffect(MISCREG_SCR
);
708 return readMiscRegNoEffect(MISCREG_SCR_EL3
);
711 // Generic Timer registers
713 case MISCREG_CNTFRQ_EL0
:
714 inform_once("Read CNTFREQ_EL0 frequency\n");
715 return getSystemCounter(tc
)->freq();
717 case MISCREG_CNTPCT_EL0
:
718 return getSystemCounter(tc
)->value();
720 return getSystemCounter(tc
)->value();
721 case MISCREG_CNTVCT_EL0
:
722 return getSystemCounter(tc
)->value();
723 case MISCREG_CNTP_CVAL
:
724 case MISCREG_CNTP_CVAL_EL0
:
725 return getArchTimer(tc
, tc
->cpuId())->compareValue();
726 case MISCREG_CNTP_TVAL
:
727 case MISCREG_CNTP_TVAL_EL0
:
728 return getArchTimer(tc
, tc
->cpuId())->timerValue();
729 case MISCREG_CNTP_CTL
:
730 case MISCREG_CNTP_CTL_EL0
:
731 return getArchTimer(tc
, tc
->cpuId())->control();
732 // PL1 phys. timer, secure
734 // case MISCREG_CNTPS_CVAL_EL1:
735 // case MISCREG_CNTPS_TVAL_EL1:
736 // case MISCREG_CNTPS_CTL_EL1:
737 // PL2 phys. timer, non-secure
739 // case MISCREG_CNTHCTL:
740 // case MISCREG_CNTHP_CVAL:
741 // case MISCREG_CNTHP_TVAL:
742 // case MISCREG_CNTHP_CTL:
744 // case MISCREG_CNTHCTL_EL2:
745 // case MISCREG_CNTHP_CVAL_EL2:
746 // case MISCREG_CNTHP_TVAL_EL2:
747 // case MISCREG_CNTHP_CTL_EL2:
750 // case MISCREG_CNTV_CVAL:
751 // case MISCREG_CNTV_TVAL:
752 // case MISCREG_CNTV_CTL:
754 // case MISCREG_CNTV_CVAL_EL2:
755 // case MISCREG_CNTV_TVAL_EL2:
756 // case MISCREG_CNTV_CTL_EL2:
761 return readMiscRegNoEffect(misc_reg
);
765 ISA::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
)
767 assert(misc_reg
< NumMiscRegs
);
769 int flat_idx
= flattenMiscIndex(misc_reg
); // Note: indexes of AArch64
770 // registers are left unchanged
772 int flat_idx2
= lookUpMiscReg
[flat_idx
].upper
;
775 miscRegs
[lookUpMiscReg
[flat_idx
].lower
] = bits(val
, 31, 0);
776 miscRegs
[flat_idx2
] = bits(val
, 63, 32);
777 DPRINTF(MiscRegs
, "Writing to misc reg %d (%d:%d) : %#x\n",
778 misc_reg
, flat_idx
, flat_idx2
, val
);
780 if (flat_idx
== MISCREG_SPSR
)
781 flat_idx
= flattenMiscIndex(MISCREG_SPSR
);
782 else if (flat_idx
== MISCREG_SCTLR_EL1
)
783 flat_idx
= flattenMiscIndex(MISCREG_SCTLR
);
785 flat_idx
= (lookUpMiscReg
[flat_idx
].lower
> 0) ?
786 lookUpMiscReg
[flat_idx
].lower
: flat_idx
;
787 miscRegs
[flat_idx
] = val
;
788 DPRINTF(MiscRegs
, "Writing to misc reg %d (%d) : %#x\n",
789 misc_reg
, flat_idx
, val
);
794 ISA::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadContext
*tc
)
797 MiscReg newVal
= val
;
807 if (misc_reg
== MISCREG_CPSR
) {
811 CPSR old_cpsr
= miscRegs
[MISCREG_CPSR
];
812 int old_mode
= old_cpsr
.mode
;
814 if (old_mode
!= cpsr
.mode
) {
815 tc
->getITBPtr()->invalidateMiscReg();
816 tc
->getDTBPtr()->invalidateMiscReg();
819 DPRINTF(Arm
, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
820 miscRegs
[misc_reg
], cpsr
, cpsr
.f
, cpsr
.i
, cpsr
.a
, cpsr
.mode
);
821 PCState pc
= tc
->pcState();
822 pc
.nextThumb(cpsr
.t
);
823 pc
.nextJazelle(cpsr
.j
);
825 // Follow slightly different semantics if a CheckerCPU object
827 CheckerCPU
*checker
= tc
->getCheckerCpuPtr();
829 tc
->pcStateNoRecord(pc
);
835 if (!miscRegInfo
[misc_reg
][MISCREG_IMPLEMENTED
]) {
836 if (miscRegInfo
[misc_reg
][MISCREG_WARN_NOT_FAIL
])
837 warn("Unimplemented system register %s write with %#x.\n",
838 miscRegName
[misc_reg
], val
);
840 panic("Unimplemented system register %s write with %#x.\n",
841 miscRegName
[misc_reg
], val
);
844 switch (unflattenMiscReg(misc_reg
)) {
848 const uint32_t ones
= (uint32_t)(-1);
850 // Only cp10, cp11, and ase are implemented, nothing else should
852 cpacrMask
.cp10
= ones
;
853 cpacrMask
.cp11
= ones
;
854 cpacrMask
.asedis
= ones
;
856 // Security Extensions may limit the writability of CPACR
858 scr
= readMiscRegNoEffect(MISCREG_SCR
);
859 CPSR cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
860 if (scr
.ns
&& (cpsr
.mode
!= MODE_MON
)) {
861 NSACR nsacr
= readMiscRegNoEffect(MISCREG_NSACR
);
862 // NB: Skipping the full loop, here
863 if (!nsacr
.cp10
) cpacrMask
.cp10
= 0;
864 if (!nsacr
.cp11
) cpacrMask
.cp11
= 0;
868 MiscReg old_val
= readMiscRegNoEffect(MISCREG_CPACR
);
870 newVal
|= old_val
& ~cpacrMask
;
871 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
872 miscRegName
[misc_reg
], newVal
);
875 case MISCREG_CPACR_EL1
:
877 const uint32_t ones
= (uint32_t)(-1);
879 cpacrMask
.tta
= ones
;
880 cpacrMask
.fpen
= ones
;
882 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
883 miscRegName
[misc_reg
], newVal
);
886 case MISCREG_CPTR_EL2
:
888 const uint32_t ones
= (uint32_t)(-1);
890 cptrMask
.tcpac
= ones
;
895 cptrMask
.res1_13_12_el2
= ones
;
896 cptrMask
.res1_9_0_el2
= ones
;
898 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
899 miscRegName
[misc_reg
], newVal
);
902 case MISCREG_CPTR_EL3
:
904 const uint32_t ones
= (uint32_t)(-1);
906 cptrMask
.tcpac
= ones
;
910 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
911 miscRegName
[misc_reg
], newVal
);
915 warn_once("The csselr register isn't implemented.\n");
918 case MISCREG_DC_ZVA_Xt
:
919 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
924 const uint32_t ones
= (uint32_t)(-1);
926 fpscrMask
.ioc
= ones
;
927 fpscrMask
.dzc
= ones
;
928 fpscrMask
.ofc
= ones
;
929 fpscrMask
.ufc
= ones
;
930 fpscrMask
.ixc
= ones
;
931 fpscrMask
.idc
= ones
;
932 fpscrMask
.ioe
= ones
;
933 fpscrMask
.dze
= ones
;
934 fpscrMask
.ofe
= ones
;
935 fpscrMask
.ufe
= ones
;
936 fpscrMask
.ixe
= ones
;
937 fpscrMask
.ide
= ones
;
938 fpscrMask
.len
= ones
;
939 fpscrMask
.stride
= ones
;
940 fpscrMask
.rMode
= ones
;
943 fpscrMask
.ahp
= ones
;
949 newVal
= (newVal
& (uint32_t)fpscrMask
) |
950 (readMiscRegNoEffect(MISCREG_FPSCR
) &
951 ~(uint32_t)fpscrMask
);
952 tc
->getDecoderPtr()->setContext(newVal
);
957 const uint32_t ones
= (uint32_t)(-1);
959 fpscrMask
.ioc
= ones
;
960 fpscrMask
.dzc
= ones
;
961 fpscrMask
.ofc
= ones
;
962 fpscrMask
.ufc
= ones
;
963 fpscrMask
.ixc
= ones
;
964 fpscrMask
.idc
= ones
;
970 newVal
= (newVal
& (uint32_t)fpscrMask
) |
971 (readMiscRegNoEffect(MISCREG_FPSCR
) &
972 ~(uint32_t)fpscrMask
);
973 misc_reg
= MISCREG_FPSCR
;
978 const uint32_t ones
= (uint32_t)(-1);
980 fpscrMask
.ioe
= ones
;
981 fpscrMask
.dze
= ones
;
982 fpscrMask
.ofe
= ones
;
983 fpscrMask
.ufe
= ones
;
984 fpscrMask
.ixe
= ones
;
985 fpscrMask
.ide
= ones
;
986 fpscrMask
.len
= ones
;
987 fpscrMask
.stride
= ones
;
988 fpscrMask
.rMode
= ones
;
991 fpscrMask
.ahp
= ones
;
992 newVal
= (newVal
& (uint32_t)fpscrMask
) |
993 (readMiscRegNoEffect(MISCREG_FPSCR
) &
994 ~(uint32_t)fpscrMask
);
995 misc_reg
= MISCREG_FPSCR
;
1000 assert(!(newVal
& ~CpsrMaskQ
));
1001 newVal
= readMiscRegNoEffect(MISCREG_CPSR
) | newVal
;
1002 misc_reg
= MISCREG_CPSR
;
1005 case MISCREG_FPSCR_QC
:
1007 newVal
= readMiscRegNoEffect(MISCREG_FPSCR
) |
1008 (newVal
& FpscrQcMask
);
1009 misc_reg
= MISCREG_FPSCR
;
1012 case MISCREG_FPSCR_EXC
:
1014 newVal
= readMiscRegNoEffect(MISCREG_FPSCR
) |
1015 (newVal
& FpscrExcMask
);
1016 misc_reg
= MISCREG_FPSCR
;
1021 // vfpv3 architecture, section B.6.1 of DDI04068
1022 // bit 29 - valid only if fpexc[31] is 0
1023 const uint32_t fpexcMask
= 0x60000000;
1024 newVal
= (newVal
& fpexcMask
) |
1025 (readMiscRegNoEffect(MISCREG_FPEXC
) & ~fpexcMask
);
1030 if (!haveVirtualization
)
1036 // ARM ARM (ARM DDI 0406C.b) B4.1.96
1037 const uint32_t ifsrMask
=
1038 mask(31, 13) | mask(11, 11) | mask(8, 6);
1039 newVal
= newVal
& ~ifsrMask
;
1044 // ARM ARM (ARM DDI 0406C.b) B4.1.52
1045 const uint32_t dfsrMask
= mask(31, 14) | mask(8, 8);
1046 newVal
= newVal
& ~dfsrMask
;
1049 case MISCREG_AMAIR0
:
1050 case MISCREG_AMAIR1
:
1052 // ARM ARM (ARM DDI 0406C.b) B4.1.5
1053 // Valid only with LPAE
1056 DPRINTF(MiscRegs
, "Writing AMAIR: %#x\n", newVal
);
1060 tc
->getITBPtr()->invalidateMiscReg();
1061 tc
->getDTBPtr()->invalidateMiscReg();
1065 DPRINTF(MiscRegs
, "Writing SCTLR: %#x\n", newVal
);
1066 MiscRegIndex sctlr_idx
;
1067 scr
= readMiscRegNoEffect(MISCREG_SCR
);
1068 if (haveSecurity
&& !scr
.ns
) {
1069 sctlr_idx
= MISCREG_SCTLR_S
;
1071 sctlr_idx
= MISCREG_SCTLR_NS
;
1072 // The FI field (bit 21) is common between S/NS versions
1073 // of the register, we store this in the secure copy of
1075 miscRegs
[MISCREG_SCTLR_S
] &= ~(1 << 21);
1076 miscRegs
[MISCREG_SCTLR_S
] |= newVal
& (1 << 21);
1078 SCTLR sctlr
= miscRegs
[sctlr_idx
];
1079 SCTLR new_sctlr
= newVal
;
1080 new_sctlr
.nmfi
= ((bool)sctlr
.nmfi
) && !haveVirtualization
;
1081 miscRegs
[sctlr_idx
] = (MiscReg
)new_sctlr
;
1082 tc
->getITBPtr()->invalidateMiscReg();
1083 tc
->getDTBPtr()->invalidateMiscReg();
1085 // Check if all CPUs are booted with caches enabled
1086 // so we can stop enforcing coherency of some kernel
1087 // structures manually.
1088 sys
= tc
->getSystemPtr();
1089 for (x
= 0; x
< sys
->numContexts(); x
++) {
1090 oc
= sys
->getThreadContext(x
);
1091 // @todo: double check this for security
1092 SCTLR other_sctlr
= oc
->readMiscRegNoEffect(MISCREG_SCTLR
);
1093 if (!other_sctlr
.c
&& oc
->status() != ThreadContext::Halted
)
1097 for (x
= 0; x
< sys
->numContexts(); x
++) {
1098 oc
= sys
->getThreadContext(x
);
1099 oc
->getDTBPtr()->allCpusCaching();
1100 oc
->getITBPtr()->allCpusCaching();
1102 // If CheckerCPU is connected, need to notify it.
1103 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1105 checker
->getDTBPtr()->allCpusCaching();
1106 checker
->getITBPtr()->allCpusCaching();
1113 case MISCREG_ID_PFR0
:
1114 case MISCREG_ID_PFR1
:
1115 case MISCREG_ID_MMFR0
:
1116 case MISCREG_ID_MMFR1
:
1117 case MISCREG_ID_MMFR2
:
1118 case MISCREG_ID_MMFR3
:
1119 case MISCREG_ID_ISAR0
:
1120 case MISCREG_ID_ISAR1
:
1121 case MISCREG_ID_ISAR2
:
1122 case MISCREG_ID_ISAR3
:
1123 case MISCREG_ID_ISAR4
:
1124 case MISCREG_ID_ISAR5
:
1132 case MISCREG_ID_AA64AFR0_EL1
:
1133 case MISCREG_ID_AA64AFR1_EL1
:
1134 case MISCREG_ID_AA64DFR0_EL1
:
1135 case MISCREG_ID_AA64DFR1_EL1
:
1136 case MISCREG_ID_AA64ISAR0_EL1
:
1137 case MISCREG_ID_AA64ISAR1_EL1
:
1138 case MISCREG_ID_AA64MMFR0_EL1
:
1139 case MISCREG_ID_AA64MMFR1_EL1
:
1140 case MISCREG_ID_AA64PFR0_EL1
:
1141 case MISCREG_ID_AA64PFR1_EL1
:
1142 // ID registers are constants.
1145 // TLBI all entries, EL0&1 inner sharable (ignored)
1146 case MISCREG_TLBIALLIS
:
1147 case MISCREG_TLBIALL
: // TLBI all entries, EL0&1,
1149 target_el
= 1; // el 0 and 1 are handled together
1150 scr
= readMiscReg(MISCREG_SCR
, tc
);
1151 secure_lookup
= haveSecurity
&& !scr
.ns
;
1152 sys
= tc
->getSystemPtr();
1153 for (x
= 0; x
< sys
->numContexts(); x
++) {
1154 oc
= sys
->getThreadContext(x
);
1155 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1156 oc
->getITBPtr()->flushAllSecurity(secure_lookup
, target_el
);
1157 oc
->getDTBPtr()->flushAllSecurity(secure_lookup
, target_el
);
1159 // If CheckerCPU is connected, need to notify it of a flush
1160 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1162 checker
->getITBPtr()->flushAllSecurity(secure_lookup
,
1164 checker
->getDTBPtr()->flushAllSecurity(secure_lookup
,
1169 // TLBI all entries, EL0&1, instruction side
1170 case MISCREG_ITLBIALL
:
1172 target_el
= 1; // el 0 and 1 are handled together
1173 scr
= readMiscReg(MISCREG_SCR
, tc
);
1174 secure_lookup
= haveSecurity
&& !scr
.ns
;
1175 tc
->getITBPtr()->flushAllSecurity(secure_lookup
, target_el
);
1177 // TLBI all entries, EL0&1, data side
1178 case MISCREG_DTLBIALL
:
1180 target_el
= 1; // el 0 and 1 are handled together
1181 scr
= readMiscReg(MISCREG_SCR
, tc
);
1182 secure_lookup
= haveSecurity
&& !scr
.ns
;
1183 tc
->getDTBPtr()->flushAllSecurity(secure_lookup
, target_el
);
1185 // TLBI based on VA, EL0&1 inner sharable (ignored)
1186 case MISCREG_TLBIMVAIS
:
1187 case MISCREG_TLBIMVA
:
1189 target_el
= 1; // el 0 and 1 are handled together
1190 scr
= readMiscReg(MISCREG_SCR
, tc
);
1191 secure_lookup
= haveSecurity
&& !scr
.ns
;
1192 sys
= tc
->getSystemPtr();
1193 for (x
= 0; x
< sys
->numContexts(); x
++) {
1194 oc
= sys
->getThreadContext(x
);
1195 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1196 oc
->getITBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
1198 secure_lookup
, target_el
);
1199 oc
->getDTBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
1201 secure_lookup
, target_el
);
1203 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1205 checker
->getITBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
1206 bits(newVal
, 7,0), secure_lookup
, target_el
);
1207 checker
->getDTBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
1208 bits(newVal
, 7,0), secure_lookup
, target_el
);
1212 // TLBI by ASID, EL0&1, inner sharable
1213 case MISCREG_TLBIASIDIS
:
1214 case MISCREG_TLBIASID
:
1216 target_el
= 1; // el 0 and 1 are handled together
1217 scr
= readMiscReg(MISCREG_SCR
, tc
);
1218 secure_lookup
= haveSecurity
&& !scr
.ns
;
1219 sys
= tc
->getSystemPtr();
1220 for (x
= 0; x
< sys
->numContexts(); x
++) {
1221 oc
= sys
->getThreadContext(x
);
1222 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1223 oc
->getITBPtr()->flushAsid(bits(newVal
, 7,0),
1224 secure_lookup
, target_el
);
1225 oc
->getDTBPtr()->flushAsid(bits(newVal
, 7,0),
1226 secure_lookup
, target_el
);
1227 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1229 checker
->getITBPtr()->flushAsid(bits(newVal
, 7,0),
1230 secure_lookup
, target_el
);
1231 checker
->getDTBPtr()->flushAsid(bits(newVal
, 7,0),
1232 secure_lookup
, target_el
);
1236 // TLBI by address, EL0&1, inner sharable (ignored)
1237 case MISCREG_TLBIMVAAIS
:
1238 case MISCREG_TLBIMVAA
:
1240 target_el
= 1; // el 0 and 1 are handled together
1241 scr
= readMiscReg(MISCREG_SCR
, tc
);
1242 secure_lookup
= haveSecurity
&& !scr
.ns
;
1244 tlbiMVA(tc
, newVal
, secure_lookup
, hyp
, target_el
);
1246 // TLBI by address, EL2, hypervisor mode
1247 case MISCREG_TLBIMVAH
:
1248 case MISCREG_TLBIMVAHIS
:
1250 target_el
= 1; // aarch32, use hyp bit
1251 scr
= readMiscReg(MISCREG_SCR
, tc
);
1252 secure_lookup
= haveSecurity
&& !scr
.ns
;
1254 tlbiMVA(tc
, newVal
, secure_lookup
, hyp
, target_el
);
1256 // TLBI by address and asid, EL0&1, instruction side only
1257 case MISCREG_ITLBIMVA
:
1259 target_el
= 1; // el 0 and 1 are handled together
1260 scr
= readMiscReg(MISCREG_SCR
, tc
);
1261 secure_lookup
= haveSecurity
&& !scr
.ns
;
1262 tc
->getITBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
1263 bits(newVal
, 7,0), secure_lookup
, target_el
);
1265 // TLBI by address and asid, EL0&1, data side only
1266 case MISCREG_DTLBIMVA
:
1268 target_el
= 1; // el 0 and 1 are handled together
1269 scr
= readMiscReg(MISCREG_SCR
, tc
);
1270 secure_lookup
= haveSecurity
&& !scr
.ns
;
1271 tc
->getDTBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
1272 bits(newVal
, 7,0), secure_lookup
, target_el
);
1274 // TLBI by ASID, EL0&1, instrution side only
1275 case MISCREG_ITLBIASID
:
1277 target_el
= 1; // el 0 and 1 are handled together
1278 scr
= readMiscReg(MISCREG_SCR
, tc
);
1279 secure_lookup
= haveSecurity
&& !scr
.ns
;
1280 tc
->getITBPtr()->flushAsid(bits(newVal
, 7,0), secure_lookup
,
1283 // TLBI by ASID EL0&1 data size only
1284 case MISCREG_DTLBIASID
:
1286 target_el
= 1; // el 0 and 1 are handled together
1287 scr
= readMiscReg(MISCREG_SCR
, tc
);
1288 secure_lookup
= haveSecurity
&& !scr
.ns
;
1289 tc
->getDTBPtr()->flushAsid(bits(newVal
, 7,0), secure_lookup
,
1292 // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB
1293 case MISCREG_TLBIALLNSNH
:
1294 case MISCREG_TLBIALLNSNHIS
:
1296 target_el
= 1; // el 0 and 1 are handled together
1298 tlbiALLN(tc
, hyp
, target_el
);
1300 // TLBI all entries, EL2, hyp,
1301 case MISCREG_TLBIALLH
:
1302 case MISCREG_TLBIALLHIS
:
1304 target_el
= 1; // aarch32, use hyp bit
1306 tlbiALLN(tc
, hyp
, target_el
);
1308 // AArch64 TLBI: invalidate all entries EL3
1309 case MISCREG_TLBI_ALLE3IS
:
1310 case MISCREG_TLBI_ALLE3
:
1313 secure_lookup
= true;
1314 tlbiALL(tc
, secure_lookup
, target_el
);
1316 // @todo: uncomment this to enable Virtualization
1317 // case MISCREG_TLBI_ALLE2IS:
1318 // case MISCREG_TLBI_ALLE2:
1319 // TLBI all entries, EL0&1
1320 case MISCREG_TLBI_ALLE1IS
:
1321 case MISCREG_TLBI_ALLE1
:
1322 // AArch64 TLBI: invalidate all entries, stage 1, current VMID
1323 case MISCREG_TLBI_VMALLE1IS
:
1324 case MISCREG_TLBI_VMALLE1
:
1325 // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID
1326 case MISCREG_TLBI_VMALLS12E1IS
:
1327 case MISCREG_TLBI_VMALLS12E1
:
1328 // @todo: handle VMID and stage 2 to enable Virtualization
1330 target_el
= 1; // el 0 and 1 are handled together
1331 scr
= readMiscReg(MISCREG_SCR
, tc
);
1332 secure_lookup
= haveSecurity
&& !scr
.ns
;
1333 tlbiALL(tc
, secure_lookup
, target_el
);
1335 // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID
1336 // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries
1337 // from the last level of translation table walks
1338 // @todo: handle VMID to enable Virtualization
1339 // TLBI all entries, EL0&1
1340 case MISCREG_TLBI_VAE3IS_Xt
:
1341 case MISCREG_TLBI_VAE3_Xt
:
1342 // TLBI by VA, EL3 regime stage 1, last level walk
1343 case MISCREG_TLBI_VALE3IS_Xt
:
1344 case MISCREG_TLBI_VALE3_Xt
:
1347 asid
= 0xbeef; // does not matter, tlbi is global
1348 secure_lookup
= true;
1349 tlbiVA(tc
, newVal
, asid
, secure_lookup
, target_el
);
1352 case MISCREG_TLBI_VAE2IS_Xt
:
1353 case MISCREG_TLBI_VAE2_Xt
:
1354 // TLBI by VA, EL2, stage1 last level walk
1355 case MISCREG_TLBI_VALE2IS_Xt
:
1356 case MISCREG_TLBI_VALE2_Xt
:
1359 asid
= 0xbeef; // does not matter, tlbi is global
1360 scr
= readMiscReg(MISCREG_SCR
, tc
);
1361 secure_lookup
= haveSecurity
&& !scr
.ns
;
1362 tlbiVA(tc
, newVal
, asid
, secure_lookup
, target_el
);
1364 // TLBI by VA EL1 & 0, stage1, ASID, current VMID
1365 case MISCREG_TLBI_VAE1IS_Xt
:
1366 case MISCREG_TLBI_VAE1_Xt
:
1367 case MISCREG_TLBI_VALE1IS_Xt
:
1368 case MISCREG_TLBI_VALE1_Xt
:
1370 asid
= bits(newVal
, 63, 48);
1371 target_el
= 1; // el 0 and 1 are handled together
1372 scr
= readMiscReg(MISCREG_SCR
, tc
);
1373 secure_lookup
= haveSecurity
&& !scr
.ns
;
1374 tlbiVA(tc
, newVal
, asid
, secure_lookup
, target_el
);
1376 // AArch64 TLBI: invalidate by ASID, stage 1, current VMID
1377 // @todo: handle VMID to enable Virtualization
1378 case MISCREG_TLBI_ASIDE1IS_Xt
:
1379 case MISCREG_TLBI_ASIDE1_Xt
:
1381 target_el
= 1; // el 0 and 1 are handled together
1382 scr
= readMiscReg(MISCREG_SCR
, tc
);
1383 secure_lookup
= haveSecurity
&& !scr
.ns
;
1384 sys
= tc
->getSystemPtr();
1385 for (x
= 0; x
< sys
->numContexts(); x
++) {
1386 oc
= sys
->getThreadContext(x
);
1387 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1388 asid
= bits(newVal
, 63, 48);
1389 if (haveLargeAsid64
)
1391 oc
->getITBPtr()->flushAsid(asid
, secure_lookup
, target_el
);
1392 oc
->getDTBPtr()->flushAsid(asid
, secure_lookup
, target_el
);
1393 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1395 checker
->getITBPtr()->flushAsid(asid
,
1396 secure_lookup
, target_el
);
1397 checker
->getDTBPtr()->flushAsid(asid
,
1398 secure_lookup
, target_el
);
1402 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID
1403 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1404 // entries from the last level of translation table walks
1405 // @todo: handle VMID to enable Virtualization
1406 case MISCREG_TLBI_VAAE1IS_Xt
:
1407 case MISCREG_TLBI_VAAE1_Xt
:
1408 case MISCREG_TLBI_VAALE1IS_Xt
:
1409 case MISCREG_TLBI_VAALE1_Xt
:
1411 target_el
= 1; // el 0 and 1 are handled together
1412 scr
= readMiscReg(MISCREG_SCR
, tc
);
1413 secure_lookup
= haveSecurity
&& !scr
.ns
;
1414 sys
= tc
->getSystemPtr();
1415 for (x
= 0; x
< sys
->numContexts(); x
++) {
1416 // @todo: extra controls on TLBI broadcast?
1417 oc
= sys
->getThreadContext(x
);
1418 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1419 Addr va
= ((Addr
) bits(newVal
, 43, 0)) << 12;
1420 oc
->getITBPtr()->flushMva(va
,
1421 secure_lookup
, false, target_el
);
1422 oc
->getDTBPtr()->flushMva(va
,
1423 secure_lookup
, false, target_el
);
1425 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1427 checker
->getITBPtr()->flushMva(va
,
1428 secure_lookup
, false, target_el
);
1429 checker
->getDTBPtr()->flushMva(va
,
1430 secure_lookup
, false, target_el
);
1434 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID
1435 case MISCREG_TLBI_IPAS2LE1IS_Xt
:
1436 case MISCREG_TLBI_IPAS2LE1_Xt
:
1437 case MISCREG_TLBI_IPAS2E1IS_Xt
:
1438 case MISCREG_TLBI_IPAS2E1_Xt
:
1440 // @todo: implement these as part of Virtualization
1441 warn("Not doing anything for write of miscreg ITLB_IPAS2\n");
1444 warn("Not doing anything for write of miscreg ACTLR\n");
1448 // Performance counters not implemented. Instead, interpret
1449 // a reset command to this register to reset the simulator
1451 // PMCR_E | PMCR_P | PMCR_C
1452 const int ResetAndEnableCounters
= 0x7;
1453 if (newVal
== ResetAndEnableCounters
) {
1454 inform("Resetting all simobject stats\n");
1455 Stats::schedStatEvent(false, true);
1459 case MISCREG_PMCCNTR
:
1460 case MISCREG_PMSELR
:
1461 warn("Not doing anything for write to miscreg %s\n",
1462 miscRegName
[misc_reg
]);
1464 case MISCREG_HSTR
: // TJDBX, now redifined to be RES0
1468 newVal
&= ~((uint32_t) hstrMask
);
1473 // If a CP bit in NSACR is 0 then the corresponding bit in
1474 // HCPTR is RAO/WI. Same applies to NSASEDIS
1475 secure_lookup
= haveSecurity
&&
1476 inSecureState(readMiscRegNoEffect(MISCREG_SCR
),
1477 readMiscRegNoEffect(MISCREG_CPSR
));
1478 if (!secure_lookup
) {
1479 MiscReg oldValue
= readMiscRegNoEffect(MISCREG_HCPTR
);
1480 MiscReg mask
= (readMiscRegNoEffect(MISCREG_NSACR
) ^ 0x7FFF) & 0xBFFF;
1481 newVal
= (newVal
& ~mask
) | (oldValue
& mask
);
1485 case MISCREG_HDFAR
: // alias for secure DFAR
1486 misc_reg
= MISCREG_DFAR_S
;
1488 case MISCREG_HIFAR
: // alias for secure IFAR
1489 misc_reg
= MISCREG_IFAR_S
;
1491 case MISCREG_ATS1CPR
:
1492 case MISCREG_ATS1CPW
:
1493 case MISCREG_ATS1CUR
:
1494 case MISCREG_ATS1CUW
:
1495 case MISCREG_ATS12NSOPR
:
1496 case MISCREG_ATS12NSOPW
:
1497 case MISCREG_ATS12NSOUR
:
1498 case MISCREG_ATS12NSOUW
:
1499 case MISCREG_ATS1HR
:
1500 case MISCREG_ATS1HW
:
1502 RequestPtr req
= new Request
;
1504 BaseTLB::Mode mode
= BaseTLB::Read
;
1505 TLB::ArmTranslationType tranType
= TLB::NormalTran
;
1508 case MISCREG_ATS1CPR
:
1509 flags
= TLB::MustBeOne
;
1510 tranType
= TLB::S1CTran
;
1511 mode
= BaseTLB::Read
;
1513 case MISCREG_ATS1CPW
:
1514 flags
= TLB::MustBeOne
;
1515 tranType
= TLB::S1CTran
;
1516 mode
= BaseTLB::Write
;
1518 case MISCREG_ATS1CUR
:
1519 flags
= TLB::MustBeOne
| TLB::UserMode
;
1520 tranType
= TLB::S1CTran
;
1521 mode
= BaseTLB::Read
;
1523 case MISCREG_ATS1CUW
:
1524 flags
= TLB::MustBeOne
| TLB::UserMode
;
1525 tranType
= TLB::S1CTran
;
1526 mode
= BaseTLB::Write
;
1528 case MISCREG_ATS12NSOPR
:
1530 panic("Security Extensions required for ATS12NSOPR");
1531 flags
= TLB::MustBeOne
;
1532 tranType
= TLB::S1S2NsTran
;
1533 mode
= BaseTLB::Read
;
1535 case MISCREG_ATS12NSOPW
:
1537 panic("Security Extensions required for ATS12NSOPW");
1538 flags
= TLB::MustBeOne
;
1539 tranType
= TLB::S1S2NsTran
;
1540 mode
= BaseTLB::Write
;
1542 case MISCREG_ATS12NSOUR
:
1544 panic("Security Extensions required for ATS12NSOUR");
1545 flags
= TLB::MustBeOne
| TLB::UserMode
;
1546 tranType
= TLB::S1S2NsTran
;
1547 mode
= BaseTLB::Read
;
1549 case MISCREG_ATS12NSOUW
:
1551 panic("Security Extensions required for ATS12NSOUW");
1552 flags
= TLB::MustBeOne
| TLB::UserMode
;
1553 tranType
= TLB::S1S2NsTran
;
1554 mode
= BaseTLB::Write
;
1556 case MISCREG_ATS1HR
: // only really useful from secure mode.
1557 flags
= TLB::MustBeOne
;
1558 tranType
= TLB::HypMode
;
1559 mode
= BaseTLB::Read
;
1561 case MISCREG_ATS1HW
:
1562 flags
= TLB::MustBeOne
;
1563 tranType
= TLB::HypMode
;
1564 mode
= BaseTLB::Write
;
1567 // If we're in timing mode then doing the translation in
1568 // functional mode then we're slightly distorting performance
1569 // results obtained from simulations. The translation should be
1570 // done in the same mode the core is running in. NOTE: This
1571 // can't be an atomic translation because that causes problems
1572 // with unexpected atomic snoop requests.
1573 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg
);
1574 req
->setVirt(0, val
, 1, flags
, Request::funcMasterId
,
1575 tc
->pcState().pc());
1576 req
->setThreadContext(tc
->contextId(), tc
->threadId());
1577 fault
= tc
->getDTBPtr()->translateFunctional(req
, tc
, mode
, tranType
);
1578 TTBCR ttbcr
= readMiscRegNoEffect(MISCREG_TTBCR
);
1579 HCR hcr
= readMiscRegNoEffect(MISCREG_HCR
);
1582 if (fault
== NoFault
) {
1583 Addr paddr
= req
->getPaddr();
1584 if (haveLPAE
&& (ttbcr
.eae
|| tranType
& TLB::HypMode
||
1585 ((tranType
& TLB::S1S2NsTran
) && hcr
.vm
) )) {
1586 newVal
= (paddr
& mask(39, 12)) |
1587 (tc
->getDTBPtr()->getAttr());
1589 newVal
= (paddr
& 0xfffff000) |
1590 (tc
->getDTBPtr()->getAttr());
1593 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
1596 ArmFault
*armFault
= reinterpret_cast<ArmFault
*>(fault
.get());
1597 // Set fault bit and FSR
1598 FSR fsr
= armFault
->getFsr(tc
);
1600 newVal
= ((fsr
>> 9) & 1) << 11;
1602 // LPAE - rearange fault status
1603 newVal
|= ((fsr
>> 0) & 0x3f) << 1;
1605 // VMSA - rearange fault status
1606 newVal
|= ((fsr
>> 0) & 0xf) << 1;
1607 newVal
|= ((fsr
>> 10) & 0x1) << 5;
1608 newVal
|= ((fsr
>> 12) & 0x1) << 6;
1610 newVal
|= 0x1; // F bit
1611 newVal
|= ((armFault
->iss() >> 7) & 0x1) << 8;
1612 newVal
|= armFault
->isStage2() ? 0x200 : 0;
1614 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
1618 setMiscRegNoEffect(MISCREG_PAR
, newVal
);
1623 TTBCR ttbcr
= readMiscRegNoEffect(MISCREG_TTBCR
);
1624 const uint32_t ones
= (uint32_t)(-1);
1625 TTBCR ttbcrMask
= 0;
1626 TTBCR ttbcrNew
= newVal
;
1628 // ARM DDI 0406C.b, ARMv7-32
1629 ttbcrMask
.n
= ones
; // T0SZ
1631 ttbcrMask
.pd0
= ones
;
1632 ttbcrMask
.pd1
= ones
;
1634 ttbcrMask
.epd0
= ones
;
1635 ttbcrMask
.irgn0
= ones
;
1636 ttbcrMask
.orgn0
= ones
;
1637 ttbcrMask
.sh0
= ones
;
1638 ttbcrMask
.ps
= ones
; // T1SZ
1639 ttbcrMask
.a1
= ones
;
1640 ttbcrMask
.epd1
= ones
;
1641 ttbcrMask
.irgn1
= ones
;
1642 ttbcrMask
.orgn1
= ones
;
1643 ttbcrMask
.sh1
= ones
;
1645 ttbcrMask
.eae
= ones
;
1647 if (haveLPAE
&& ttbcrNew
.eae
) {
1648 newVal
= newVal
& ttbcrMask
;
1650 newVal
= (newVal
& ttbcrMask
) | (ttbcr
& (~ttbcrMask
));
1656 TTBCR ttbcr
= readMiscRegNoEffect(MISCREG_TTBCR
);
1659 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1660 // ARMv8 AArch32 bit 63-56 only
1661 uint64_t ttbrMask
= mask(63,56) | mask(47,40);
1662 newVal
= (newVal
& (~ttbrMask
));
1666 case MISCREG_CONTEXTIDR
:
1673 case MISCREG_SCR_EL3
:
1674 case MISCREG_SCTLR_EL1
:
1675 case MISCREG_SCTLR_EL2
:
1676 case MISCREG_SCTLR_EL3
:
1677 case MISCREG_TCR_EL1
:
1678 case MISCREG_TCR_EL2
:
1679 case MISCREG_TCR_EL3
:
1680 case MISCREG_TTBR0_EL1
:
1681 case MISCREG_TTBR1_EL1
:
1682 case MISCREG_TTBR0_EL2
:
1683 case MISCREG_TTBR0_EL3
:
1684 tc
->getITBPtr()->invalidateMiscReg();
1685 tc
->getDTBPtr()->invalidateMiscReg();
1691 tc
->setCCReg(CCREG_NZ
, cpsr
.nz
);
1692 tc
->setCCReg(CCREG_C
, cpsr
.c
);
1693 tc
->setCCReg(CCREG_V
, cpsr
.v
);
1698 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1699 cpsr
.daif
= (uint8_t) ((CPSR
) newVal
).daif
;
1701 misc_reg
= MISCREG_CPSR
;
1704 case MISCREG_SP_EL0
:
1705 tc
->setIntReg(INTREG_SP0
, newVal
);
1707 case MISCREG_SP_EL1
:
1708 tc
->setIntReg(INTREG_SP1
, newVal
);
1710 case MISCREG_SP_EL2
:
1711 tc
->setIntReg(INTREG_SP2
, newVal
);
1715 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1716 cpsr
.sp
= (uint8_t) ((CPSR
) newVal
).sp
;
1718 misc_reg
= MISCREG_CPSR
;
1721 case MISCREG_CURRENTEL
:
1723 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1724 cpsr
.el
= (uint8_t) ((CPSR
) newVal
).el
;
1726 misc_reg
= MISCREG_CPSR
;
1729 case MISCREG_AT_S1E1R_Xt
:
1730 case MISCREG_AT_S1E1W_Xt
:
1731 case MISCREG_AT_S1E0R_Xt
:
1732 case MISCREG_AT_S1E0W_Xt
:
1733 case MISCREG_AT_S1E2R_Xt
:
1734 case MISCREG_AT_S1E2W_Xt
:
1735 case MISCREG_AT_S12E1R_Xt
:
1736 case MISCREG_AT_S12E1W_Xt
:
1737 case MISCREG_AT_S12E0R_Xt
:
1738 case MISCREG_AT_S12E0W_Xt
:
1739 case MISCREG_AT_S1E3R_Xt
:
1740 case MISCREG_AT_S1E3W_Xt
:
1742 RequestPtr req
= new Request
;
1744 BaseTLB::Mode mode
= BaseTLB::Read
;
1745 TLB::ArmTranslationType tranType
= TLB::NormalTran
;
1748 case MISCREG_AT_S1E1R_Xt
:
1749 flags
= TLB::MustBeOne
;
1750 tranType
= TLB::S1CTran
;
1751 mode
= BaseTLB::Read
;
1753 case MISCREG_AT_S1E1W_Xt
:
1754 flags
= TLB::MustBeOne
;
1755 tranType
= TLB::S1CTran
;
1756 mode
= BaseTLB::Write
;
1758 case MISCREG_AT_S1E0R_Xt
:
1759 flags
= TLB::MustBeOne
| TLB::UserMode
;
1760 tranType
= TLB::S1CTran
;
1761 mode
= BaseTLB::Read
;
1763 case MISCREG_AT_S1E0W_Xt
:
1764 flags
= TLB::MustBeOne
| TLB::UserMode
;
1765 tranType
= TLB::S1CTran
;
1766 mode
= BaseTLB::Write
;
1768 case MISCREG_AT_S1E2R_Xt
:
1769 flags
= TLB::MustBeOne
;
1770 tranType
= TLB::HypMode
;
1771 mode
= BaseTLB::Read
;
1773 case MISCREG_AT_S1E2W_Xt
:
1774 flags
= TLB::MustBeOne
;
1775 tranType
= TLB::HypMode
;
1776 mode
= BaseTLB::Write
;
1778 case MISCREG_AT_S12E0R_Xt
:
1779 flags
= TLB::MustBeOne
| TLB::UserMode
;
1780 tranType
= TLB::S1S2NsTran
;
1781 mode
= BaseTLB::Read
;
1783 case MISCREG_AT_S12E0W_Xt
:
1784 flags
= TLB::MustBeOne
| TLB::UserMode
;
1785 tranType
= TLB::S1S2NsTran
;
1786 mode
= BaseTLB::Write
;
1788 case MISCREG_AT_S12E1R_Xt
:
1789 flags
= TLB::MustBeOne
;
1790 tranType
= TLB::S1S2NsTran
;
1791 mode
= BaseTLB::Read
;
1793 case MISCREG_AT_S12E1W_Xt
:
1794 flags
= TLB::MustBeOne
;
1795 tranType
= TLB::S1S2NsTran
;
1796 mode
= BaseTLB::Write
;
1798 case MISCREG_AT_S1E3R_Xt
:
1799 flags
= TLB::MustBeOne
;
1800 tranType
= TLB::HypMode
; // There is no TZ mode defined.
1801 mode
= BaseTLB::Read
;
1803 case MISCREG_AT_S1E3W_Xt
:
1804 flags
= TLB::MustBeOne
;
1805 tranType
= TLB::HypMode
; // There is no TZ mode defined.
1806 mode
= BaseTLB::Write
;
1809 // If we're in timing mode then doing the translation in
1810 // functional mode then we're slightly distorting performance
1811 // results obtained from simulations. The translation should be
1812 // done in the same mode the core is running in. NOTE: This
1813 // can't be an atomic translation because that causes problems
1814 // with unexpected atomic snoop requests.
1815 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg
);
1816 req
->setVirt(0, val
, 1, flags
, Request::funcMasterId
,
1817 tc
->pcState().pc());
1818 req
->setThreadContext(tc
->contextId(), tc
->threadId());
1819 fault
= tc
->getDTBPtr()->translateFunctional(req
, tc
, mode
,
1823 if (fault
== NoFault
) {
1824 Addr paddr
= req
->getPaddr();
1825 uint64_t attr
= tc
->getDTBPtr()->getAttr();
1826 uint64_t attr1
= attr
>> 56;
1827 if (!attr1
|| attr1
==0x44) {
1829 attr
&= ~ uint64_t(0x80);
1831 newVal
= (paddr
& mask(47, 12)) | attr
;
1833 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
1836 ArmFault
*armFault
= reinterpret_cast<ArmFault
*>(fault
.get());
1837 // Set fault bit and FSR
1838 FSR fsr
= armFault
->getFsr(tc
);
1840 newVal
= ((fsr
>> 9) & 1) << 11;
1841 // rearange fault status
1842 newVal
|= ((fsr
>> 0) & 0x3f) << 1;
1843 newVal
|= 0x1; // F bit
1844 newVal
|= ((armFault
->iss() >> 7) & 0x1) << 8;
1845 newVal
|= armFault
->isStage2() ? 0x200 : 0;
1847 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
1851 setMiscRegNoEffect(MISCREG_PAR_EL1
, newVal
);
1854 case MISCREG_SPSR_EL3
:
1855 case MISCREG_SPSR_EL2
:
1856 case MISCREG_SPSR_EL1
:
1857 // Force bits 23:21 to 0
1858 newVal
= val
& ~(0x7 << 21);
1860 case MISCREG_L2CTLR
:
1861 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
1862 miscRegName
[misc_reg
], uint32_t(val
));
1865 // Generic Timer registers
1866 case MISCREG_CNTFRQ
:
1867 case MISCREG_CNTFRQ_EL0
:
1868 getSystemCounter(tc
)->setFreq(val
);
1870 case MISCREG_CNTP_CVAL
:
1871 case MISCREG_CNTP_CVAL_EL0
:
1872 getArchTimer(tc
, tc
->cpuId())->setCompareValue(val
);
1874 case MISCREG_CNTP_TVAL
:
1875 case MISCREG_CNTP_TVAL_EL0
:
1876 getArchTimer(tc
, tc
->cpuId())->setTimerValue(val
);
1878 case MISCREG_CNTP_CTL
:
1879 case MISCREG_CNTP_CTL_EL0
:
1880 getArchTimer(tc
, tc
->cpuId())->setControl(val
);
1882 // PL1 phys. timer, secure
1884 case MISCREG_CNTPS_CVAL_EL1
:
1885 case MISCREG_CNTPS_TVAL_EL1
:
1886 case MISCREG_CNTPS_CTL_EL1
:
1887 // PL2 phys. timer, non-secure
1889 case MISCREG_CNTHCTL
:
1890 case MISCREG_CNTHP_CVAL
:
1891 case MISCREG_CNTHP_TVAL
:
1892 case MISCREG_CNTHP_CTL
:
1894 case MISCREG_CNTHCTL_EL2
:
1895 case MISCREG_CNTHP_CVAL_EL2
:
1896 case MISCREG_CNTHP_TVAL_EL2
:
1897 case MISCREG_CNTHP_CTL_EL2
:
1900 case MISCREG_CNTV_CVAL
:
1901 case MISCREG_CNTV_TVAL
:
1902 case MISCREG_CNTV_CTL
:
1904 // case MISCREG_CNTV_CVAL_EL2:
1905 // case MISCREG_CNTV_TVAL_EL2:
1906 // case MISCREG_CNTV_CTL_EL2:
1910 setMiscRegNoEffect(misc_reg
, newVal
);
1914 ISA::tlbiVA(ThreadContext
*tc
, MiscReg newVal
, uint8_t asid
, bool secure_lookup
,
1917 if (haveLargeAsid64
)
1919 Addr va
= ((Addr
) bits(newVal
, 43, 0)) << 12;
1920 System
*sys
= tc
->getSystemPtr();
1921 for (int x
= 0; x
< sys
->numContexts(); x
++) {
1922 ThreadContext
*oc
= sys
->getThreadContext(x
);
1923 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1924 oc
->getITBPtr()->flushMvaAsid(va
, asid
,
1925 secure_lookup
, target_el
);
1926 oc
->getDTBPtr()->flushMvaAsid(va
, asid
,
1927 secure_lookup
, target_el
);
1929 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1931 checker
->getITBPtr()->flushMvaAsid(
1932 va
, asid
, secure_lookup
, target_el
);
1933 checker
->getDTBPtr()->flushMvaAsid(
1934 va
, asid
, secure_lookup
, target_el
);
1940 ISA::tlbiALL(ThreadContext
*tc
, bool secure_lookup
, uint8_t target_el
)
1942 System
*sys
= tc
->getSystemPtr();
1943 for (int x
= 0; x
< sys
->numContexts(); x
++) {
1944 ThreadContext
*oc
= sys
->getThreadContext(x
);
1945 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1946 oc
->getITBPtr()->flushAllSecurity(secure_lookup
, target_el
);
1947 oc
->getDTBPtr()->flushAllSecurity(secure_lookup
, target_el
);
1949 // If CheckerCPU is connected, need to notify it of a flush
1950 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1952 checker
->getITBPtr()->flushAllSecurity(secure_lookup
,
1954 checker
->getDTBPtr()->flushAllSecurity(secure_lookup
,
1961 ISA::tlbiALLN(ThreadContext
*tc
, bool hyp
, uint8_t target_el
)
1963 System
*sys
= tc
->getSystemPtr();
1964 for (int x
= 0; x
< sys
->numContexts(); x
++) {
1965 ThreadContext
*oc
= sys
->getThreadContext(x
);
1966 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1967 oc
->getITBPtr()->flushAllNs(hyp
, target_el
);
1968 oc
->getDTBPtr()->flushAllNs(hyp
, target_el
);
1970 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1972 checker
->getITBPtr()->flushAllNs(hyp
, target_el
);
1973 checker
->getDTBPtr()->flushAllNs(hyp
, target_el
);
1979 ISA::tlbiMVA(ThreadContext
*tc
, MiscReg newVal
, bool secure_lookup
, bool hyp
,
1982 System
*sys
= tc
->getSystemPtr();
1983 for (int x
= 0; x
< sys
->numContexts(); x
++) {
1984 ThreadContext
*oc
= sys
->getThreadContext(x
);
1985 assert(oc
->getITBPtr() && oc
->getDTBPtr());
1986 oc
->getITBPtr()->flushMva(mbits(newVal
, 31,12),
1987 secure_lookup
, hyp
, target_el
);
1988 oc
->getDTBPtr()->flushMva(mbits(newVal
, 31,12),
1989 secure_lookup
, hyp
, target_el
);
1991 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1993 checker
->getITBPtr()->flushMva(mbits(newVal
, 31,12),
1994 secure_lookup
, hyp
, target_el
);
1995 checker
->getDTBPtr()->flushMva(mbits(newVal
, 31,12),
1996 secure_lookup
, hyp
, target_el
);
2001 ::GenericTimer::SystemCounter
*
2002 ISA::getSystemCounter(ThreadContext
*tc
)
2004 ::GenericTimer::SystemCounter
*cnt
= ((ArmSystem
*) tc
->getSystemPtr())->
2007 panic("System counter not available\n");
2012 ::GenericTimer::ArchTimer
*
2013 ISA::getArchTimer(ThreadContext
*tc
, int cpu_id
)
2015 ::GenericTimer::ArchTimer
*timer
= ((ArmSystem
*) tc
->getSystemPtr())->
2016 getArchTimer(cpu_id
);
2017 if (timer
== NULL
) {
2018 panic("Architected timer not available\n");
2026 ArmISAParams::create()
2028 return new ArmISA::ISA(this);