2 * Copyright (c) 2010-2018 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
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22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 #include "arch/arm/isa.hh"
42 #include "arch/arm/pmu.hh"
43 #include "arch/arm/system.hh"
44 #include "arch/arm/tlb.hh"
45 #include "arch/arm/tlbi_op.hh"
46 #include "cpu/base.hh"
47 #include "cpu/checker/cpu.hh"
48 #include "debug/Arm.hh"
49 #include "debug/MiscRegs.hh"
50 #include "dev/arm/generic_timer.hh"
51 #include "params/ArmISA.hh"
52 #include "sim/faults.hh"
53 #include "sim/stat_control.hh"
54 #include "sim/system.hh"
62 _decoderFlavour(p
->decoderFlavour
),
63 _vecRegRenameMode(p
->vecRegRenameMode
),
65 impdefAsNop(p
->impdef_nop
)
67 miscRegs
[MISCREG_SCTLR_RST
] = 0;
69 // Hook up a dummy device if we haven't been configured with a
70 // real PMU. By using a dummy device, we don't need to check that
71 // the PMU exist every time we try to access a PMU register.
75 // Give all ISA devices a pointer to this ISA
78 system
= dynamic_cast<ArmSystem
*>(p
->system
);
80 // Cache system-level properties
81 if (FullSystem
&& system
) {
82 highestELIs64
= system
->highestELIs64();
83 haveSecurity
= system
->haveSecurity();
84 haveLPAE
= system
->haveLPAE();
85 haveCrypto
= system
->haveCrypto();
86 haveVirtualization
= system
->haveVirtualization();
87 haveLargeAsid64
= system
->haveLargeAsid64();
88 physAddrRange
= system
->physAddrRange();
90 highestELIs64
= true; // ArmSystem::highestELIs64 does the same
91 haveSecurity
= haveLPAE
= haveVirtualization
= false;
93 haveLargeAsid64
= false;
94 physAddrRange
= 32; // dummy value
97 initializeMiscRegMetadata();
98 preUnflattenMiscReg();
103 std::vector
<struct ISA::MiscRegLUTEntry
> ISA::lookUpMiscReg(NUM_MISCREGS
);
108 return dynamic_cast<const Params
*>(_params
);
114 const Params
*p(params());
116 SCTLR sctlr_rst
= miscRegs
[MISCREG_SCTLR_RST
];
117 memset(miscRegs
, 0, sizeof(miscRegs
));
121 // We always initialize AArch64 ID registers even
122 // if we are in AArch32. This is done since if we
123 // are in SE mode we don't know if our ArmProcess is
124 // AArch32 or AArch64
127 // Start with an event in the mailbox
128 miscRegs
[MISCREG_SEV_MAILBOX
] = 1;
130 // Separate Instruction and Data TLBs
131 miscRegs
[MISCREG_TLBTR
] = 1;
134 mvfr0
.advSimdRegisters
= 2;
135 mvfr0
.singlePrecision
= 2;
136 mvfr0
.doublePrecision
= 2;
137 mvfr0
.vfpExceptionTrapping
= 0;
139 mvfr0
.squareRoot
= 1;
140 mvfr0
.shortVectors
= 1;
141 mvfr0
.roundingModes
= 1;
142 miscRegs
[MISCREG_MVFR0
] = mvfr0
;
145 mvfr1
.flushToZero
= 1;
146 mvfr1
.defaultNaN
= 1;
147 mvfr1
.advSimdLoadStore
= 1;
148 mvfr1
.advSimdInteger
= 1;
149 mvfr1
.advSimdSinglePrecision
= 1;
150 mvfr1
.advSimdHalfPrecision
= 1;
151 mvfr1
.vfpHalfPrecision
= 1;
152 miscRegs
[MISCREG_MVFR1
] = mvfr1
;
154 // Reset values of PRRR and NMRR are implementation dependent
156 // @todo: PRRR and NMRR in secure state?
157 miscRegs
[MISCREG_PRRR_NS
] =
171 miscRegs
[MISCREG_NMRR_NS
] =
188 if (FullSystem
&& system
->highestELIs64()) {
189 // Initialize AArch64 state
194 // Initialize AArch32 state...
195 clear32(p
, sctlr_rst
);
199 ISA::clear32(const ArmISAParams
*p
, const SCTLR
&sctlr_rst
)
202 cpsr
.mode
= MODE_USER
;
205 miscRegs
[MISCREG_MVBAR
] = system
->resetAddr();
208 miscRegs
[MISCREG_CPSR
] = cpsr
;
212 sctlr
.te
= (bool) sctlr_rst
.te
;
213 sctlr
.nmfi
= (bool) sctlr_rst
.nmfi
;
214 sctlr
.v
= (bool) sctlr_rst
.v
;
219 sctlr
.rao4
= 0xf; // SCTLR[6:3]
222 miscRegs
[MISCREG_SCTLR_NS
] = sctlr
;
223 miscRegs
[MISCREG_SCTLR_RST
] = sctlr_rst
;
224 miscRegs
[MISCREG_HCPTR
] = 0;
226 miscRegs
[MISCREG_CPACR
] = 0;
228 miscRegs
[MISCREG_FPSID
] = p
->fpsid
;
231 TTBCR ttbcr
= miscRegs
[MISCREG_TTBCR_NS
];
233 miscRegs
[MISCREG_TTBCR_NS
] = ttbcr
;
234 // Enforce consistency with system-level settings
235 miscRegs
[MISCREG_ID_MMFR0
] = (miscRegs
[MISCREG_ID_MMFR0
] & ~0xf) | 0x5;
239 miscRegs
[MISCREG_SCTLR_S
] = sctlr
;
240 miscRegs
[MISCREG_SCR
] = 0;
241 miscRegs
[MISCREG_VBAR_S
] = 0;
243 // we're always non-secure
244 miscRegs
[MISCREG_SCR
] = 1;
247 //XXX We need to initialize the rest of the state.
251 ISA::clear64(const ArmISAParams
*p
)
254 Addr rvbar
= system
->resetAddr();
255 switch (system
->highestEL()) {
256 // Set initial EL to highest implemented EL using associated stack
257 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
260 cpsr
.mode
= MODE_EL3H
;
261 miscRegs
[MISCREG_RVBAR_EL3
] = rvbar
;
264 cpsr
.mode
= MODE_EL2H
;
265 miscRegs
[MISCREG_RVBAR_EL2
] = rvbar
;
268 cpsr
.mode
= MODE_EL1H
;
269 miscRegs
[MISCREG_RVBAR_EL1
] = rvbar
;
272 panic("Invalid highest implemented exception level");
276 // Initialize rest of CPSR
277 cpsr
.daif
= 0xf; // Mask all interrupts
280 miscRegs
[MISCREG_CPSR
] = cpsr
;
283 // Initialize other control registers
284 miscRegs
[MISCREG_MPIDR_EL1
] = 0x80000000;
286 miscRegs
[MISCREG_SCTLR_EL3
] = 0x30c50830;
287 miscRegs
[MISCREG_SCR_EL3
] = 0x00000030; // RES1 fields
288 } else if (haveVirtualization
) {
289 // also MISCREG_SCTLR_EL2 (by mapping)
290 miscRegs
[MISCREG_HSCTLR
] = 0x30c50830;
292 // also MISCREG_SCTLR_EL1 (by mapping)
293 miscRegs
[MISCREG_SCTLR_NS
] = 0x30d00800 | 0x00050030; // RES1 | init
295 miscRegs
[MISCREG_SCR_EL3
] = 1;
300 ISA::initID32(const ArmISAParams
*p
)
302 // Initialize configurable default values
303 miscRegs
[MISCREG_MIDR
] = p
->midr
;
304 miscRegs
[MISCREG_MIDR_EL1
] = p
->midr
;
305 miscRegs
[MISCREG_VPIDR
] = p
->midr
;
307 miscRegs
[MISCREG_ID_ISAR0
] = p
->id_isar0
;
308 miscRegs
[MISCREG_ID_ISAR1
] = p
->id_isar1
;
309 miscRegs
[MISCREG_ID_ISAR2
] = p
->id_isar2
;
310 miscRegs
[MISCREG_ID_ISAR3
] = p
->id_isar3
;
311 miscRegs
[MISCREG_ID_ISAR4
] = p
->id_isar4
;
312 miscRegs
[MISCREG_ID_ISAR5
] = p
->id_isar5
;
314 miscRegs
[MISCREG_ID_MMFR0
] = p
->id_mmfr0
;
315 miscRegs
[MISCREG_ID_MMFR1
] = p
->id_mmfr1
;
316 miscRegs
[MISCREG_ID_MMFR2
] = p
->id_mmfr2
;
317 miscRegs
[MISCREG_ID_MMFR3
] = p
->id_mmfr3
;
321 ISA::initID64(const ArmISAParams
*p
)
323 // Initialize configurable id registers
324 miscRegs
[MISCREG_ID_AA64AFR0_EL1
] = p
->id_aa64afr0_el1
;
325 miscRegs
[MISCREG_ID_AA64AFR1_EL1
] = p
->id_aa64afr1_el1
;
326 miscRegs
[MISCREG_ID_AA64DFR0_EL1
] =
327 (p
->id_aa64dfr0_el1
& 0xfffffffffffff0ffULL
) |
328 (p
->pmu
? 0x0000000000000100ULL
: 0); // Enable PMUv3
330 miscRegs
[MISCREG_ID_AA64DFR1_EL1
] = p
->id_aa64dfr1_el1
;
331 miscRegs
[MISCREG_ID_AA64ISAR0_EL1
] = p
->id_aa64isar0_el1
;
332 miscRegs
[MISCREG_ID_AA64ISAR1_EL1
] = p
->id_aa64isar1_el1
;
333 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
] = p
->id_aa64mmfr0_el1
;
334 miscRegs
[MISCREG_ID_AA64MMFR1_EL1
] = p
->id_aa64mmfr1_el1
;
335 miscRegs
[MISCREG_ID_AA64MMFR2_EL1
] = p
->id_aa64mmfr2_el1
;
337 miscRegs
[MISCREG_ID_DFR0_EL1
] =
338 (p
->pmu
? 0x03000000ULL
: 0); // Enable PMUv3
340 miscRegs
[MISCREG_ID_DFR0
] = miscRegs
[MISCREG_ID_DFR0_EL1
];
342 // Enforce consistency with system-level settings...
345 miscRegs
[MISCREG_ID_AA64PFR0_EL1
] = insertBits(
346 miscRegs
[MISCREG_ID_AA64PFR0_EL1
], 15, 12,
347 haveSecurity
? 0x2 : 0x0);
349 miscRegs
[MISCREG_ID_AA64PFR0_EL1
] = insertBits(
350 miscRegs
[MISCREG_ID_AA64PFR0_EL1
], 11, 8,
351 haveVirtualization
? 0x2 : 0x0);
352 // Large ASID support
353 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
] = insertBits(
354 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
], 7, 4,
355 haveLargeAsid64
? 0x2 : 0x0);
356 // Physical address size
357 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
] = insertBits(
358 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
], 3, 0,
359 encodePhysAddrRange64(physAddrRange
));
361 miscRegs
[MISCREG_ID_AA64ISAR0_EL1
] = insertBits(
362 miscRegs
[MISCREG_ID_AA64ISAR0_EL1
], 19, 4,
363 haveCrypto
? 0x1112 : 0x0);
367 ISA::startup(ThreadContext
*tc
)
369 pmu
->setThreadContext(tc
);
375 ISA::readMiscRegNoEffect(int misc_reg
) const
377 assert(misc_reg
< NumMiscRegs
);
379 const auto ®
= lookUpMiscReg
[misc_reg
]; // bit masks
380 const auto &map
= getMiscIndices(misc_reg
);
381 int lower
= map
.first
, upper
= map
.second
;
382 // NB!: apply architectural masks according to desired register,
383 // despite possibly getting value from different (mapped) register.
384 auto val
= !upper
? miscRegs
[lower
] : ((miscRegs
[lower
] & mask(32))
385 |(miscRegs
[upper
] << 32));
386 if (val
& reg
.res0()) {
387 DPRINTF(MiscRegs
, "Reading MiscReg %s with set res0 bits: %#x\n",
388 miscRegName
[misc_reg
], val
& reg
.res0());
390 if ((val
& reg
.res1()) != reg
.res1()) {
391 DPRINTF(MiscRegs
, "Reading MiscReg %s with clear res1 bits: %#x\n",
392 miscRegName
[misc_reg
], (val
& reg
.res1()) ^ reg
.res1());
394 return (val
& ~reg
.raz()) | reg
.rao(); // enforce raz/rao
399 ISA::readMiscReg(int misc_reg
, ThreadContext
*tc
)
405 if (misc_reg
== MISCREG_CPSR
) {
406 cpsr
= miscRegs
[misc_reg
];
408 cpsr
.j
= pc
.jazelle() ? 1 : 0;
409 cpsr
.t
= pc
.thumb() ? 1 : 0;
414 if (!miscRegInfo
[misc_reg
][MISCREG_IMPLEMENTED
]) {
415 if (miscRegInfo
[misc_reg
][MISCREG_WARN_NOT_FAIL
])
416 warn("Unimplemented system register %s read.\n",
417 miscRegName
[misc_reg
]);
419 panic("Unimplemented system register %s read.\n",
420 miscRegName
[misc_reg
]);
424 switch (unflattenMiscReg(misc_reg
)) {
427 if (!haveVirtualization
)
430 return readMiscRegNoEffect(MISCREG_HCR
);
434 const uint32_t ones
= (uint32_t)(-1);
436 // Only cp10, cp11, and ase are implemented, nothing else should
437 // be readable? (straight copy from the write code)
438 cpacrMask
.cp10
= ones
;
439 cpacrMask
.cp11
= ones
;
440 cpacrMask
.asedis
= ones
;
442 // Security Extensions may limit the readability of CPACR
444 scr
= readMiscRegNoEffect(MISCREG_SCR
);
445 cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
446 if (scr
.ns
&& (cpsr
.mode
!= MODE_MON
) && ELIs32(tc
, EL3
)) {
447 NSACR nsacr
= readMiscRegNoEffect(MISCREG_NSACR
);
448 // NB: Skipping the full loop, here
449 if (!nsacr
.cp10
) cpacrMask
.cp10
= 0;
450 if (!nsacr
.cp11
) cpacrMask
.cp11
= 0;
453 MiscReg val
= readMiscRegNoEffect(MISCREG_CPACR
);
455 DPRINTF(MiscRegs
, "Reading misc reg %s: %#x\n",
456 miscRegName
[misc_reg
], val
);
460 cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
461 scr
= readMiscRegNoEffect(MISCREG_SCR
);
462 if ((cpsr
.mode
== MODE_HYP
) || inSecureState(scr
, cpsr
)) {
463 return getMPIDR(system
, tc
);
465 return readMiscReg(MISCREG_VMPIDR
, tc
);
468 case MISCREG_MPIDR_EL1
:
469 // @todo in the absence of v8 virtualization support just return MPIDR_EL1
470 return getMPIDR(system
, tc
) & 0xffffffff;
472 // top bit defined as RES1
473 return readMiscRegNoEffect(misc_reg
) | 0x80000000;
474 case MISCREG_ID_AFR0
: // not implemented, so alias MIDR
475 case MISCREG_REVIDR
: // not implemented, so alias MIDR
477 cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
478 scr
= readMiscRegNoEffect(MISCREG_SCR
);
479 if ((cpsr
.mode
== MODE_HYP
) || inSecureState(scr
, cpsr
)) {
480 return readMiscRegNoEffect(misc_reg
);
482 return readMiscRegNoEffect(MISCREG_VPIDR
);
485 case MISCREG_JOSCR
: // Jazelle trivial implementation, RAZ/WI
486 case MISCREG_JMCR
: // Jazelle trivial implementation, RAZ/WI
487 case MISCREG_JIDR
: // Jazelle trivial implementation, RAZ/WI
488 case MISCREG_AIDR
: // AUX ID set to 0
489 case MISCREG_TCMTR
: // No TCM's
493 warn_once("The clidr register always reports 0 caches.\n");
494 warn_once("clidr LoUIS field of 0b001 to match current "
495 "ARM implementations.\n");
498 warn_once("The ccsidr register isn't implemented and "
499 "always reads as 0.\n");
501 case MISCREG_CTR
: // AArch32, ARMv7, top bit set
502 case MISCREG_CTR_EL0
: // AArch64
504 //all caches have the same line size in gem5
505 //4 byte words in ARM
506 unsigned lineSizeWords
=
507 tc
->getSystemPtr()->cacheLineSize() / 4;
508 unsigned log2LineSizeWords
= 0;
510 while (lineSizeWords
>>= 1) {
515 //log2 of minimun i-cache line size (words)
516 ctr
.iCacheLineSize
= log2LineSizeWords
;
517 //b11 - gem5 uses pipt
518 ctr
.l1IndexPolicy
= 0x3;
519 //log2 of minimum d-cache line size (words)
520 ctr
.dCacheLineSize
= log2LineSizeWords
;
521 //log2 of max reservation size (words)
522 ctr
.erg
= log2LineSizeWords
;
523 //log2 of max writeback size (words)
524 ctr
.cwg
= log2LineSizeWords
;
525 //b100 - gem5 format is ARMv7
531 warn("Not doing anything for miscreg ACTLR\n");
534 case MISCREG_PMXEVTYPER_PMCCFILTR
:
535 case MISCREG_PMINTENSET_EL1
... MISCREG_PMOVSSET_EL0
:
536 case MISCREG_PMEVCNTR0_EL0
... MISCREG_PMEVTYPER5_EL0
:
537 case MISCREG_PMCR
... MISCREG_PMOVSSET
:
538 return pmu
->readMiscReg(misc_reg
);
541 panic("shouldn't be reading this register seperately\n");
542 case MISCREG_FPSCR_QC
:
543 return readMiscRegNoEffect(MISCREG_FPSCR
) & ~FpscrQcMask
;
544 case MISCREG_FPSCR_EXC
:
545 return readMiscRegNoEffect(MISCREG_FPSCR
) & ~FpscrExcMask
;
548 const uint32_t ones
= (uint32_t)(-1);
550 fpscrMask
.ioc
= ones
;
551 fpscrMask
.dzc
= ones
;
552 fpscrMask
.ofc
= ones
;
553 fpscrMask
.ufc
= ones
;
554 fpscrMask
.ixc
= ones
;
555 fpscrMask
.idc
= ones
;
561 return readMiscRegNoEffect(MISCREG_FPSCR
) & (uint32_t)fpscrMask
;
565 const uint32_t ones
= (uint32_t)(-1);
567 fpscrMask
.len
= ones
;
568 fpscrMask
.stride
= ones
;
569 fpscrMask
.rMode
= ones
;
572 fpscrMask
.ahp
= ones
;
573 return readMiscRegNoEffect(MISCREG_FPSCR
) & (uint32_t)fpscrMask
;
578 cpsr
.nz
= tc
->readCCReg(CCREG_NZ
);
579 cpsr
.c
= tc
->readCCReg(CCREG_C
);
580 cpsr
.v
= tc
->readCCReg(CCREG_V
);
586 cpsr
.daif
= (uint8_t) ((CPSR
) miscRegs
[MISCREG_CPSR
]).daif
;
591 return tc
->readIntReg(INTREG_SP0
);
595 return tc
->readIntReg(INTREG_SP1
);
599 return tc
->readIntReg(INTREG_SP2
);
603 return miscRegs
[MISCREG_CPSR
] & 0x1;
605 case MISCREG_CURRENTEL
:
607 return miscRegs
[MISCREG_CPSR
] & 0xc;
611 // mostly unimplemented, just set NumCPUs field from sim and return
613 // b00:1CPU to b11:4CPUs
614 l2ctlr
.numCPUs
= tc
->getSystemPtr()->numContexts() - 1;
617 case MISCREG_DBGDIDR
:
618 /* For now just implement the version number.
619 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
622 case MISCREG_DBGDSCRint
:
625 return tc
->getCpuPtr()->getInterruptController(tc
->threadId())->getISR(
626 readMiscRegNoEffect(MISCREG_HCR
),
627 readMiscRegNoEffect(MISCREG_CPSR
),
628 readMiscRegNoEffect(MISCREG_SCR
));
629 case MISCREG_ISR_EL1
:
630 return tc
->getCpuPtr()->getInterruptController(tc
->threadId())->getISR(
631 readMiscRegNoEffect(MISCREG_HCR_EL2
),
632 readMiscRegNoEffect(MISCREG_CPSR
),
633 readMiscRegNoEffect(MISCREG_SCR_EL3
));
634 case MISCREG_DCZID_EL0
:
635 return 0x04; // DC ZVA clear 64-byte chunks
638 MiscReg val
= readMiscRegNoEffect(misc_reg
);
639 // The trap bit associated with CP14 is defined as RAZ
641 // If a CP bit in NSACR is 0 then the corresponding bit in
643 bool secure_lookup
= haveSecurity
&&
644 inSecureState(readMiscRegNoEffect(MISCREG_SCR
),
645 readMiscRegNoEffect(MISCREG_CPSR
));
646 if (!secure_lookup
) {
647 MiscReg mask
= readMiscRegNoEffect(MISCREG_NSACR
);
648 val
|= (mask
^ 0x7FFF) & 0xBFFF;
650 // Set the bits for unimplemented coprocessors to RAO/WI
654 case MISCREG_HDFAR
: // alias for secure DFAR
655 return readMiscRegNoEffect(MISCREG_DFAR_S
);
656 case MISCREG_HIFAR
: // alias for secure IFAR
657 return readMiscRegNoEffect(MISCREG_IFAR_S
);
658 case MISCREG_HVBAR
: // bottom bits reserved
659 return readMiscRegNoEffect(MISCREG_HVBAR
) & 0xFFFFFFE0;
661 return (readMiscRegNoEffect(misc_reg
) & 0x72DD39FF) | 0x00C00818;
662 case MISCREG_SCTLR_EL1
:
663 return (readMiscRegNoEffect(misc_reg
) & 0x37DDDBBF) | 0x30D00800;
664 case MISCREG_SCTLR_EL2
:
665 case MISCREG_SCTLR_EL3
:
667 return (readMiscRegNoEffect(misc_reg
) & 0x32CD183F) | 0x30C50830;
669 case MISCREG_ID_PFR0
:
670 // !ThumbEE | !Jazelle | Thumb | ARM
672 case MISCREG_ID_PFR1
:
673 { // Timer | Virti | !M Profile | TrustZone | ARMv4
674 bool haveTimer
= (system
->getGenericTimer() != NULL
);
676 | (haveSecurity
? 0x00000010 : 0x0)
677 | (haveVirtualization
? 0x00001000 : 0x0)
678 | (haveTimer
? 0x00010000 : 0x0);
680 case MISCREG_ID_AA64PFR0_EL1
:
681 return 0x0000000000000002 // AArch{64,32} supported at EL0
682 | 0x0000000000000020 // EL1
683 | (haveVirtualization
? 0x0000000000000200 : 0) // EL2
684 | (haveSecurity
? 0x0000000000002000 : 0); // EL3
685 case MISCREG_ID_AA64PFR1_EL1
:
686 return 0; // bits [63:0] RES0 (reserved for future use)
688 // Generic Timer registers
689 case MISCREG_CNTHV_CTL_EL2
:
690 case MISCREG_CNTHV_CVAL_EL2
:
691 case MISCREG_CNTHV_TVAL_EL2
:
692 case MISCREG_CNTFRQ
... MISCREG_CNTHP_CTL
:
693 case MISCREG_CNTPCT
... MISCREG_CNTHP_CVAL
:
694 case MISCREG_CNTKCTL_EL1
... MISCREG_CNTV_CVAL_EL0
:
695 case MISCREG_CNTVOFF_EL2
... MISCREG_CNTPS_CVAL_EL1
:
696 return getGenericTimer(tc
).readMiscReg(misc_reg
);
702 return readMiscRegNoEffect(misc_reg
);
706 ISA::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
)
708 assert(misc_reg
< NumMiscRegs
);
710 const auto ®
= lookUpMiscReg
[misc_reg
]; // bit masks
711 const auto &map
= getMiscIndices(misc_reg
);
712 int lower
= map
.first
, upper
= map
.second
;
714 auto v
= (val
& ~reg
.wi()) | reg
.rao();
716 miscRegs
[lower
] = bits(v
, 31, 0);
717 miscRegs
[upper
] = bits(v
, 63, 32);
718 DPRINTF(MiscRegs
, "Writing to misc reg %d (%d:%d) : %#x\n",
719 misc_reg
, lower
, upper
, v
);
722 DPRINTF(MiscRegs
, "Writing to misc reg %d (%d) : %#x\n",
728 ISA::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadContext
*tc
)
731 MiscReg newVal
= val
;
735 if (misc_reg
== MISCREG_CPSR
) {
739 CPSR old_cpsr
= miscRegs
[MISCREG_CPSR
];
740 int old_mode
= old_cpsr
.mode
;
742 if (old_mode
!= cpsr
.mode
|| cpsr
.il
!= old_cpsr
.il
) {
743 getITBPtr(tc
)->invalidateMiscReg();
744 getDTBPtr(tc
)->invalidateMiscReg();
747 DPRINTF(Arm
, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
748 miscRegs
[misc_reg
], cpsr
, cpsr
.f
, cpsr
.i
, cpsr
.a
, cpsr
.mode
);
749 PCState pc
= tc
->pcState();
750 pc
.nextThumb(cpsr
.t
);
751 pc
.nextJazelle(cpsr
.j
);
752 pc
.illegalExec(cpsr
.il
== 1);
754 // Follow slightly different semantics if a CheckerCPU object
756 CheckerCPU
*checker
= tc
->getCheckerCpuPtr();
758 tc
->pcStateNoRecord(pc
);
764 if (!miscRegInfo
[misc_reg
][MISCREG_IMPLEMENTED
]) {
765 if (miscRegInfo
[misc_reg
][MISCREG_WARN_NOT_FAIL
])
766 warn("Unimplemented system register %s write with %#x.\n",
767 miscRegName
[misc_reg
], val
);
769 panic("Unimplemented system register %s write with %#x.\n",
770 miscRegName
[misc_reg
], val
);
773 switch (unflattenMiscReg(misc_reg
)) {
777 const uint32_t ones
= (uint32_t)(-1);
779 // Only cp10, cp11, and ase are implemented, nothing else should
781 cpacrMask
.cp10
= ones
;
782 cpacrMask
.cp11
= ones
;
783 cpacrMask
.asedis
= ones
;
785 // Security Extensions may limit the writability of CPACR
787 scr
= readMiscRegNoEffect(MISCREG_SCR
);
788 CPSR cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
789 if (scr
.ns
&& (cpsr
.mode
!= MODE_MON
) && ELIs32(tc
, EL3
)) {
790 NSACR nsacr
= readMiscRegNoEffect(MISCREG_NSACR
);
791 // NB: Skipping the full loop, here
792 if (!nsacr
.cp10
) cpacrMask
.cp10
= 0;
793 if (!nsacr
.cp11
) cpacrMask
.cp11
= 0;
797 MiscReg old_val
= readMiscRegNoEffect(MISCREG_CPACR
);
799 newVal
|= old_val
& ~cpacrMask
;
800 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
801 miscRegName
[misc_reg
], newVal
);
804 case MISCREG_CPTR_EL2
:
806 const uint32_t ones
= (uint32_t)(-1);
808 cptrMask
.tcpac
= ones
;
813 cptrMask
.res1_13_12_el2
= ones
;
814 cptrMask
.res1_9_0_el2
= ones
;
816 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
817 miscRegName
[misc_reg
], newVal
);
820 case MISCREG_CPTR_EL3
:
822 const uint32_t ones
= (uint32_t)(-1);
824 cptrMask
.tcpac
= ones
;
828 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
829 miscRegName
[misc_reg
], newVal
);
833 warn_once("The csselr register isn't implemented.\n");
836 case MISCREG_DC_ZVA_Xt
:
837 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
842 const uint32_t ones
= (uint32_t)(-1);
844 fpscrMask
.ioc
= ones
;
845 fpscrMask
.dzc
= ones
;
846 fpscrMask
.ofc
= ones
;
847 fpscrMask
.ufc
= ones
;
848 fpscrMask
.ixc
= ones
;
849 fpscrMask
.idc
= ones
;
850 fpscrMask
.ioe
= ones
;
851 fpscrMask
.dze
= ones
;
852 fpscrMask
.ofe
= ones
;
853 fpscrMask
.ufe
= ones
;
854 fpscrMask
.ixe
= ones
;
855 fpscrMask
.ide
= ones
;
856 fpscrMask
.len
= ones
;
857 fpscrMask
.stride
= ones
;
858 fpscrMask
.rMode
= ones
;
861 fpscrMask
.ahp
= ones
;
867 newVal
= (newVal
& (uint32_t)fpscrMask
) |
868 (readMiscRegNoEffect(MISCREG_FPSCR
) &
869 ~(uint32_t)fpscrMask
);
870 tc
->getDecoderPtr()->setContext(newVal
);
875 const uint32_t ones
= (uint32_t)(-1);
877 fpscrMask
.ioc
= ones
;
878 fpscrMask
.dzc
= ones
;
879 fpscrMask
.ofc
= ones
;
880 fpscrMask
.ufc
= ones
;
881 fpscrMask
.ixc
= ones
;
882 fpscrMask
.idc
= ones
;
888 newVal
= (newVal
& (uint32_t)fpscrMask
) |
889 (readMiscRegNoEffect(MISCREG_FPSCR
) &
890 ~(uint32_t)fpscrMask
);
891 misc_reg
= MISCREG_FPSCR
;
896 const uint32_t ones
= (uint32_t)(-1);
898 fpscrMask
.len
= ones
;
899 fpscrMask
.stride
= ones
;
900 fpscrMask
.rMode
= ones
;
903 fpscrMask
.ahp
= ones
;
904 newVal
= (newVal
& (uint32_t)fpscrMask
) |
905 (readMiscRegNoEffect(MISCREG_FPSCR
) &
906 ~(uint32_t)fpscrMask
);
907 misc_reg
= MISCREG_FPSCR
;
912 assert(!(newVal
& ~CpsrMaskQ
));
913 newVal
= readMiscRegNoEffect(MISCREG_CPSR
) | newVal
;
914 misc_reg
= MISCREG_CPSR
;
917 case MISCREG_FPSCR_QC
:
919 newVal
= readMiscRegNoEffect(MISCREG_FPSCR
) |
920 (newVal
& FpscrQcMask
);
921 misc_reg
= MISCREG_FPSCR
;
924 case MISCREG_FPSCR_EXC
:
926 newVal
= readMiscRegNoEffect(MISCREG_FPSCR
) |
927 (newVal
& FpscrExcMask
);
928 misc_reg
= MISCREG_FPSCR
;
933 // vfpv3 architecture, section B.6.1 of DDI04068
934 // bit 29 - valid only if fpexc[31] is 0
935 const uint32_t fpexcMask
= 0x60000000;
936 newVal
= (newVal
& fpexcMask
) |
937 (readMiscRegNoEffect(MISCREG_FPEXC
) & ~fpexcMask
);
942 if (!haveVirtualization
)
948 // ARM ARM (ARM DDI 0406C.b) B4.1.96
949 const uint32_t ifsrMask
=
950 mask(31, 13) | mask(11, 11) | mask(8, 6);
951 newVal
= newVal
& ~ifsrMask
;
956 // ARM ARM (ARM DDI 0406C.b) B4.1.52
957 const uint32_t dfsrMask
= mask(31, 14) | mask(8, 8);
958 newVal
= newVal
& ~dfsrMask
;
964 // ARM ARM (ARM DDI 0406C.b) B4.1.5
965 // Valid only with LPAE
968 DPRINTF(MiscRegs
, "Writing AMAIR: %#x\n", newVal
);
972 getITBPtr(tc
)->invalidateMiscReg();
973 getDTBPtr(tc
)->invalidateMiscReg();
977 DPRINTF(MiscRegs
, "Writing SCTLR: %#x\n", newVal
);
978 scr
= readMiscRegNoEffect(MISCREG_SCR
);
980 MiscRegIndex sctlr_idx
;
981 if (haveSecurity
&& !highestELIs64
&& !scr
.ns
) {
982 sctlr_idx
= MISCREG_SCTLR_S
;
984 sctlr_idx
= MISCREG_SCTLR_NS
;
987 SCTLR sctlr
= miscRegs
[sctlr_idx
];
988 SCTLR new_sctlr
= newVal
;
989 new_sctlr
.nmfi
= ((bool)sctlr
.nmfi
) && !haveVirtualization
;
990 miscRegs
[sctlr_idx
] = (MiscReg
)new_sctlr
;
991 getITBPtr(tc
)->invalidateMiscReg();
992 getDTBPtr(tc
)->invalidateMiscReg();
995 case MISCREG_ID_PFR0
:
996 case MISCREG_ID_PFR1
:
997 case MISCREG_ID_DFR0
:
998 case MISCREG_ID_MMFR0
:
999 case MISCREG_ID_MMFR1
:
1000 case MISCREG_ID_MMFR2
:
1001 case MISCREG_ID_MMFR3
:
1002 case MISCREG_ID_ISAR0
:
1003 case MISCREG_ID_ISAR1
:
1004 case MISCREG_ID_ISAR2
:
1005 case MISCREG_ID_ISAR3
:
1006 case MISCREG_ID_ISAR4
:
1007 case MISCREG_ID_ISAR5
:
1015 case MISCREG_ID_AA64AFR0_EL1
:
1016 case MISCREG_ID_AA64AFR1_EL1
:
1017 case MISCREG_ID_AA64DFR0_EL1
:
1018 case MISCREG_ID_AA64DFR1_EL1
:
1019 case MISCREG_ID_AA64ISAR0_EL1
:
1020 case MISCREG_ID_AA64ISAR1_EL1
:
1021 case MISCREG_ID_AA64MMFR0_EL1
:
1022 case MISCREG_ID_AA64MMFR1_EL1
:
1023 case MISCREG_ID_AA64MMFR2_EL1
:
1024 case MISCREG_ID_AA64PFR0_EL1
:
1025 case MISCREG_ID_AA64PFR1_EL1
:
1026 // ID registers are constants.
1029 // TLB Invalidate All
1030 case MISCREG_TLBIALL
: // TLBI all entries, EL0&1,
1033 scr
= readMiscReg(MISCREG_SCR
, tc
);
1035 TLBIALL
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
);
1039 // TLB Invalidate All, Inner Shareable
1040 case MISCREG_TLBIALLIS
:
1043 scr
= readMiscReg(MISCREG_SCR
, tc
);
1045 TLBIALL
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
);
1046 tlbiOp
.broadcast(tc
);
1049 // Instruction TLB Invalidate All
1050 case MISCREG_ITLBIALL
:
1053 scr
= readMiscReg(MISCREG_SCR
, tc
);
1055 ITLBIALL
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
);
1059 // Data TLB Invalidate All
1060 case MISCREG_DTLBIALL
:
1063 scr
= readMiscReg(MISCREG_SCR
, tc
);
1065 DTLBIALL
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
);
1069 // TLB Invalidate by VA
1070 // mcr tlbimval(is) is invalidating all matching entries
1071 // regardless of the level of lookup, since in gem5 we cache
1072 // in the tlb the last level of lookup only.
1073 case MISCREG_TLBIMVA
:
1074 case MISCREG_TLBIMVAL
:
1077 scr
= readMiscReg(MISCREG_SCR
, tc
);
1080 haveSecurity
&& !scr
.ns
,
1081 mbits(newVal
, 31, 12),
1087 // TLB Invalidate by VA, Inner Shareable
1088 case MISCREG_TLBIMVAIS
:
1089 case MISCREG_TLBIMVALIS
:
1092 scr
= readMiscReg(MISCREG_SCR
, tc
);
1095 haveSecurity
&& !scr
.ns
,
1096 mbits(newVal
, 31, 12),
1099 tlbiOp
.broadcast(tc
);
1102 // TLB Invalidate by ASID match
1103 case MISCREG_TLBIASID
:
1106 scr
= readMiscReg(MISCREG_SCR
, tc
);
1108 TLBIASID
tlbiOp(EL1
,
1109 haveSecurity
&& !scr
.ns
,
1115 // TLB Invalidate by ASID match, Inner Shareable
1116 case MISCREG_TLBIASIDIS
:
1119 scr
= readMiscReg(MISCREG_SCR
, tc
);
1121 TLBIASID
tlbiOp(EL1
,
1122 haveSecurity
&& !scr
.ns
,
1125 tlbiOp
.broadcast(tc
);
1128 // mcr tlbimvaal(is) is invalidating all matching entries
1129 // regardless of the level of lookup, since in gem5 we cache
1130 // in the tlb the last level of lookup only.
1131 // TLB Invalidate by VA, All ASID
1132 case MISCREG_TLBIMVAA
:
1133 case MISCREG_TLBIMVAAL
:
1136 scr
= readMiscReg(MISCREG_SCR
, tc
);
1138 TLBIMVAA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1139 mbits(newVal
, 31,12), false);
1144 // TLB Invalidate by VA, All ASID, Inner Shareable
1145 case MISCREG_TLBIMVAAIS
:
1146 case MISCREG_TLBIMVAALIS
:
1149 scr
= readMiscReg(MISCREG_SCR
, tc
);
1151 TLBIMVAA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1152 mbits(newVal
, 31,12), false);
1154 tlbiOp
.broadcast(tc
);
1157 // mcr tlbimvalh(is) is invalidating all matching entries
1158 // regardless of the level of lookup, since in gem5 we cache
1159 // in the tlb the last level of lookup only.
1160 // TLB Invalidate by VA, Hyp mode
1161 case MISCREG_TLBIMVAH
:
1162 case MISCREG_TLBIMVALH
:
1165 scr
= readMiscReg(MISCREG_SCR
, tc
);
1167 TLBIMVAA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1168 mbits(newVal
, 31,12), true);
1173 // TLB Invalidate by VA, Hyp mode, Inner Shareable
1174 case MISCREG_TLBIMVAHIS
:
1175 case MISCREG_TLBIMVALHIS
:
1178 scr
= readMiscReg(MISCREG_SCR
, tc
);
1180 TLBIMVAA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1181 mbits(newVal
, 31,12), true);
1183 tlbiOp
.broadcast(tc
);
1186 // mcr tlbiipas2l(is) is invalidating all matching entries
1187 // regardless of the level of lookup, since in gem5 we cache
1188 // in the tlb the last level of lookup only.
1189 // TLB Invalidate by Intermediate Physical Address, Stage 2
1190 case MISCREG_TLBIIPAS2
:
1191 case MISCREG_TLBIIPAS2L
:
1194 scr
= readMiscReg(MISCREG_SCR
, tc
);
1197 haveSecurity
&& !scr
.ns
,
1198 static_cast<Addr
>(bits(newVal
, 35, 0)) << 12);
1203 // TLB Invalidate by Intermediate Physical Address, Stage 2,
1205 case MISCREG_TLBIIPAS2IS
:
1206 case MISCREG_TLBIIPAS2LIS
:
1209 scr
= readMiscReg(MISCREG_SCR
, tc
);
1212 haveSecurity
&& !scr
.ns
,
1213 static_cast<Addr
>(bits(newVal
, 35, 0)) << 12);
1215 tlbiOp
.broadcast(tc
);
1218 // Instruction TLB Invalidate by VA
1219 case MISCREG_ITLBIMVA
:
1222 scr
= readMiscReg(MISCREG_SCR
, tc
);
1224 ITLBIMVA
tlbiOp(EL1
,
1225 haveSecurity
&& !scr
.ns
,
1226 mbits(newVal
, 31, 12),
1232 // Data TLB Invalidate by VA
1233 case MISCREG_DTLBIMVA
:
1236 scr
= readMiscReg(MISCREG_SCR
, tc
);
1238 DTLBIMVA
tlbiOp(EL1
,
1239 haveSecurity
&& !scr
.ns
,
1240 mbits(newVal
, 31, 12),
1246 // Instruction TLB Invalidate by ASID match
1247 case MISCREG_ITLBIASID
:
1250 scr
= readMiscReg(MISCREG_SCR
, tc
);
1252 ITLBIASID
tlbiOp(EL1
,
1253 haveSecurity
&& !scr
.ns
,
1259 // Data TLB Invalidate by ASID match
1260 case MISCREG_DTLBIASID
:
1263 scr
= readMiscReg(MISCREG_SCR
, tc
);
1265 DTLBIASID
tlbiOp(EL1
,
1266 haveSecurity
&& !scr
.ns
,
1272 // TLB Invalidate All, Non-Secure Non-Hyp
1273 case MISCREG_TLBIALLNSNH
:
1277 TLBIALLN
tlbiOp(EL1
, false);
1281 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
1282 case MISCREG_TLBIALLNSNHIS
:
1286 TLBIALLN
tlbiOp(EL1
, false);
1287 tlbiOp
.broadcast(tc
);
1290 // TLB Invalidate All, Hyp mode
1291 case MISCREG_TLBIALLH
:
1295 TLBIALLN
tlbiOp(EL1
, true);
1299 // TLB Invalidate All, Hyp mode, Inner Shareable
1300 case MISCREG_TLBIALLHIS
:
1304 TLBIALLN
tlbiOp(EL1
, true);
1305 tlbiOp
.broadcast(tc
);
1308 // AArch64 TLB Invalidate All, EL3
1309 case MISCREG_TLBI_ALLE3
:
1313 TLBIALL
tlbiOp(EL3
, true);
1317 // AArch64 TLB Invalidate All, EL3, Inner Shareable
1318 case MISCREG_TLBI_ALLE3IS
:
1322 TLBIALL
tlbiOp(EL3
, true);
1323 tlbiOp
.broadcast(tc
);
1326 // @todo: uncomment this to enable Virtualization
1327 // case MISCREG_TLBI_ALLE2IS:
1328 // case MISCREG_TLBI_ALLE2:
1329 // AArch64 TLB Invalidate All, EL1
1330 case MISCREG_TLBI_ALLE1
:
1331 case MISCREG_TLBI_VMALLE1
:
1332 case MISCREG_TLBI_VMALLS12E1
:
1333 // @todo: handle VMID and stage 2 to enable Virtualization
1336 scr
= readMiscReg(MISCREG_SCR
, tc
);
1338 TLBIALL
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
);
1342 // AArch64 TLB Invalidate All, EL1, Inner Shareable
1343 case MISCREG_TLBI_ALLE1IS
:
1344 case MISCREG_TLBI_VMALLE1IS
:
1345 case MISCREG_TLBI_VMALLS12E1IS
:
1346 // @todo: handle VMID and stage 2 to enable Virtualization
1349 scr
= readMiscReg(MISCREG_SCR
, tc
);
1351 TLBIALL
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
);
1352 tlbiOp
.broadcast(tc
);
1355 // VAEx(IS) and VALEx(IS) are the same because TLBs
1356 // only store entries
1357 // from the last level of translation table walks
1358 // @todo: handle VMID to enable Virtualization
1359 // AArch64 TLB Invalidate by VA, EL3
1360 case MISCREG_TLBI_VAE3_Xt
:
1361 case MISCREG_TLBI_VALE3_Xt
:
1365 TLBIMVA
tlbiOp(EL3
, true,
1366 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12,
1371 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable
1372 case MISCREG_TLBI_VAE3IS_Xt
:
1373 case MISCREG_TLBI_VALE3IS_Xt
:
1377 TLBIMVA
tlbiOp(EL3
, true,
1378 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12,
1381 tlbiOp
.broadcast(tc
);
1384 // AArch64 TLB Invalidate by VA, EL2
1385 case MISCREG_TLBI_VAE2_Xt
:
1386 case MISCREG_TLBI_VALE2_Xt
:
1389 scr
= readMiscReg(MISCREG_SCR
, tc
);
1391 TLBIMVA
tlbiOp(EL2
, haveSecurity
&& !scr
.ns
,
1392 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12,
1397 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable
1398 case MISCREG_TLBI_VAE2IS_Xt
:
1399 case MISCREG_TLBI_VALE2IS_Xt
:
1402 scr
= readMiscReg(MISCREG_SCR
, tc
);
1404 TLBIMVA
tlbiOp(EL2
, haveSecurity
&& !scr
.ns
,
1405 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12,
1408 tlbiOp
.broadcast(tc
);
1411 // AArch64 TLB Invalidate by VA, EL1
1412 case MISCREG_TLBI_VAE1_Xt
:
1413 case MISCREG_TLBI_VALE1_Xt
:
1416 scr
= readMiscReg(MISCREG_SCR
, tc
);
1417 auto asid
= haveLargeAsid64
? bits(newVal
, 63, 48) :
1418 bits(newVal
, 55, 48);
1420 TLBIMVA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1421 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12,
1427 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable
1428 case MISCREG_TLBI_VAE1IS_Xt
:
1429 case MISCREG_TLBI_VALE1IS_Xt
:
1432 scr
= readMiscReg(MISCREG_SCR
, tc
);
1433 auto asid
= haveLargeAsid64
? bits(newVal
, 63, 48) :
1434 bits(newVal
, 55, 48);
1436 TLBIMVA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1437 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12,
1440 tlbiOp
.broadcast(tc
);
1443 // AArch64 TLB Invalidate by ASID, EL1
1444 // @todo: handle VMID to enable Virtualization
1445 case MISCREG_TLBI_ASIDE1_Xt
:
1448 scr
= readMiscReg(MISCREG_SCR
, tc
);
1449 auto asid
= haveLargeAsid64
? bits(newVal
, 63, 48) :
1450 bits(newVal
, 55, 48);
1452 TLBIASID
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
, asid
);
1456 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable
1457 case MISCREG_TLBI_ASIDE1IS_Xt
:
1460 scr
= readMiscReg(MISCREG_SCR
, tc
);
1461 auto asid
= haveLargeAsid64
? bits(newVal
, 63, 48) :
1462 bits(newVal
, 55, 48);
1464 TLBIASID
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
, asid
);
1465 tlbiOp
.broadcast(tc
);
1468 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1469 // entries from the last level of translation table walks
1470 // AArch64 TLB Invalidate by VA, All ASID, EL1
1471 case MISCREG_TLBI_VAAE1_Xt
:
1472 case MISCREG_TLBI_VAALE1_Xt
:
1475 scr
= readMiscReg(MISCREG_SCR
, tc
);
1477 TLBIMVAA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1478 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12, false);
1483 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable
1484 case MISCREG_TLBI_VAAE1IS_Xt
:
1485 case MISCREG_TLBI_VAALE1IS_Xt
:
1488 scr
= readMiscReg(MISCREG_SCR
, tc
);
1490 TLBIMVAA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1491 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12, false);
1493 tlbiOp
.broadcast(tc
);
1496 // AArch64 TLB Invalidate by Intermediate Physical Address,
1498 case MISCREG_TLBI_IPAS2E1_Xt
:
1499 case MISCREG_TLBI_IPAS2LE1_Xt
:
1502 scr
= readMiscReg(MISCREG_SCR
, tc
);
1504 TLBIIPA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1505 static_cast<Addr
>(bits(newVal
, 35, 0)) << 12);
1510 // AArch64 TLB Invalidate by Intermediate Physical Address,
1511 // Stage 2, EL1, Inner Shareable
1512 case MISCREG_TLBI_IPAS2E1IS_Xt
:
1513 case MISCREG_TLBI_IPAS2LE1IS_Xt
:
1516 scr
= readMiscReg(MISCREG_SCR
, tc
);
1518 TLBIIPA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1519 static_cast<Addr
>(bits(newVal
, 35, 0)) << 12);
1521 tlbiOp
.broadcast(tc
);
1525 warn("Not doing anything for write of miscreg ACTLR\n");
1528 case MISCREG_PMXEVTYPER_PMCCFILTR
:
1529 case MISCREG_PMINTENSET_EL1
... MISCREG_PMOVSSET_EL0
:
1530 case MISCREG_PMEVCNTR0_EL0
... MISCREG_PMEVTYPER5_EL0
:
1531 case MISCREG_PMCR
... MISCREG_PMOVSSET
:
1532 pmu
->setMiscReg(misc_reg
, newVal
);
1536 case MISCREG_HSTR
: // TJDBX, now redifined to be RES0
1540 newVal
&= ~((uint32_t) hstrMask
);
1545 // If a CP bit in NSACR is 0 then the corresponding bit in
1546 // HCPTR is RAO/WI. Same applies to NSASEDIS
1547 secure_lookup
= haveSecurity
&&
1548 inSecureState(readMiscRegNoEffect(MISCREG_SCR
),
1549 readMiscRegNoEffect(MISCREG_CPSR
));
1550 if (!secure_lookup
) {
1551 MiscReg oldValue
= readMiscRegNoEffect(MISCREG_HCPTR
);
1552 MiscReg mask
= (readMiscRegNoEffect(MISCREG_NSACR
) ^ 0x7FFF) & 0xBFFF;
1553 newVal
= (newVal
& ~mask
) | (oldValue
& mask
);
1557 case MISCREG_HDFAR
: // alias for secure DFAR
1558 misc_reg
= MISCREG_DFAR_S
;
1560 case MISCREG_HIFAR
: // alias for secure IFAR
1561 misc_reg
= MISCREG_IFAR_S
;
1563 case MISCREG_ATS1CPR
:
1564 case MISCREG_ATS1CPW
:
1565 case MISCREG_ATS1CUR
:
1566 case MISCREG_ATS1CUW
:
1567 case MISCREG_ATS12NSOPR
:
1568 case MISCREG_ATS12NSOPW
:
1569 case MISCREG_ATS12NSOUR
:
1570 case MISCREG_ATS12NSOUW
:
1571 case MISCREG_ATS1HR
:
1572 case MISCREG_ATS1HW
:
1574 Request::Flags flags
= 0;
1575 BaseTLB::Mode mode
= BaseTLB::Read
;
1576 TLB::ArmTranslationType tranType
= TLB::NormalTran
;
1579 case MISCREG_ATS1CPR
:
1580 flags
= TLB::MustBeOne
;
1581 tranType
= TLB::S1CTran
;
1582 mode
= BaseTLB::Read
;
1584 case MISCREG_ATS1CPW
:
1585 flags
= TLB::MustBeOne
;
1586 tranType
= TLB::S1CTran
;
1587 mode
= BaseTLB::Write
;
1589 case MISCREG_ATS1CUR
:
1590 flags
= TLB::MustBeOne
| TLB::UserMode
;
1591 tranType
= TLB::S1CTran
;
1592 mode
= BaseTLB::Read
;
1594 case MISCREG_ATS1CUW
:
1595 flags
= TLB::MustBeOne
| TLB::UserMode
;
1596 tranType
= TLB::S1CTran
;
1597 mode
= BaseTLB::Write
;
1599 case MISCREG_ATS12NSOPR
:
1601 panic("Security Extensions required for ATS12NSOPR");
1602 flags
= TLB::MustBeOne
;
1603 tranType
= TLB::S1S2NsTran
;
1604 mode
= BaseTLB::Read
;
1606 case MISCREG_ATS12NSOPW
:
1608 panic("Security Extensions required for ATS12NSOPW");
1609 flags
= TLB::MustBeOne
;
1610 tranType
= TLB::S1S2NsTran
;
1611 mode
= BaseTLB::Write
;
1613 case MISCREG_ATS12NSOUR
:
1615 panic("Security Extensions required for ATS12NSOUR");
1616 flags
= TLB::MustBeOne
| TLB::UserMode
;
1617 tranType
= TLB::S1S2NsTran
;
1618 mode
= BaseTLB::Read
;
1620 case MISCREG_ATS12NSOUW
:
1622 panic("Security Extensions required for ATS12NSOUW");
1623 flags
= TLB::MustBeOne
| TLB::UserMode
;
1624 tranType
= TLB::S1S2NsTran
;
1625 mode
= BaseTLB::Write
;
1627 case MISCREG_ATS1HR
: // only really useful from secure mode.
1628 flags
= TLB::MustBeOne
;
1629 tranType
= TLB::HypMode
;
1630 mode
= BaseTLB::Read
;
1632 case MISCREG_ATS1HW
:
1633 flags
= TLB::MustBeOne
;
1634 tranType
= TLB::HypMode
;
1635 mode
= BaseTLB::Write
;
1638 // If we're in timing mode then doing the translation in
1639 // functional mode then we're slightly distorting performance
1640 // results obtained from simulations. The translation should be
1641 // done in the same mode the core is running in. NOTE: This
1642 // can't be an atomic translation because that causes problems
1643 // with unexpected atomic snoop requests.
1644 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg
);
1646 auto req
= std::make_shared
<Request
>(
1647 0, val
, 0, flags
, Request::funcMasterId
,
1648 tc
->pcState().pc(), tc
->contextId());
1650 fault
= getDTBPtr(tc
)->translateFunctional(
1651 req
, tc
, mode
, tranType
);
1653 TTBCR ttbcr
= readMiscRegNoEffect(MISCREG_TTBCR
);
1654 HCR hcr
= readMiscRegNoEffect(MISCREG_HCR
);
1657 if (fault
== NoFault
) {
1658 Addr paddr
= req
->getPaddr();
1659 if (haveLPAE
&& (ttbcr
.eae
|| tranType
& TLB::HypMode
||
1660 ((tranType
& TLB::S1S2NsTran
) && hcr
.vm
) )) {
1661 newVal
= (paddr
& mask(39, 12)) |
1662 (getDTBPtr(tc
)->getAttr());
1664 newVal
= (paddr
& 0xfffff000) |
1665 (getDTBPtr(tc
)->getAttr());
1668 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
1671 ArmFault
*armFault
= static_cast<ArmFault
*>(fault
.get());
1672 armFault
->update(tc
);
1673 // Set fault bit and FSR
1674 FSR fsr
= armFault
->getFsr(tc
);
1676 newVal
= ((fsr
>> 9) & 1) << 11;
1678 // LPAE - rearange fault status
1679 newVal
|= ((fsr
>> 0) & 0x3f) << 1;
1681 // VMSA - rearange fault status
1682 newVal
|= ((fsr
>> 0) & 0xf) << 1;
1683 newVal
|= ((fsr
>> 10) & 0x1) << 5;
1684 newVal
|= ((fsr
>> 12) & 0x1) << 6;
1686 newVal
|= 0x1; // F bit
1687 newVal
|= ((armFault
->iss() >> 7) & 0x1) << 8;
1688 newVal
|= armFault
->isStage2() ? 0x200 : 0;
1690 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
1693 setMiscRegNoEffect(MISCREG_PAR
, newVal
);
1698 TTBCR ttbcr
= readMiscRegNoEffect(MISCREG_TTBCR
);
1699 const uint32_t ones
= (uint32_t)(-1);
1700 TTBCR ttbcrMask
= 0;
1701 TTBCR ttbcrNew
= newVal
;
1703 // ARM DDI 0406C.b, ARMv7-32
1704 ttbcrMask
.n
= ones
; // T0SZ
1706 ttbcrMask
.pd0
= ones
;
1707 ttbcrMask
.pd1
= ones
;
1709 ttbcrMask
.epd0
= ones
;
1710 ttbcrMask
.irgn0
= ones
;
1711 ttbcrMask
.orgn0
= ones
;
1712 ttbcrMask
.sh0
= ones
;
1713 ttbcrMask
.ps
= ones
; // T1SZ
1714 ttbcrMask
.a1
= ones
;
1715 ttbcrMask
.epd1
= ones
;
1716 ttbcrMask
.irgn1
= ones
;
1717 ttbcrMask
.orgn1
= ones
;
1718 ttbcrMask
.sh1
= ones
;
1720 ttbcrMask
.eae
= ones
;
1722 if (haveLPAE
&& ttbcrNew
.eae
) {
1723 newVal
= newVal
& ttbcrMask
;
1725 newVal
= (newVal
& ttbcrMask
) | (ttbcr
& (~ttbcrMask
));
1727 // Invalidate TLB MiscReg
1728 getITBPtr(tc
)->invalidateMiscReg();
1729 getDTBPtr(tc
)->invalidateMiscReg();
1735 TTBCR ttbcr
= readMiscRegNoEffect(MISCREG_TTBCR
);
1738 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1739 // ARMv8 AArch32 bit 63-56 only
1740 uint64_t ttbrMask
= mask(63,56) | mask(47,40);
1741 newVal
= (newVal
& (~ttbrMask
));
1744 // Invalidate TLB MiscReg
1745 getITBPtr(tc
)->invalidateMiscReg();
1746 getDTBPtr(tc
)->invalidateMiscReg();
1749 case MISCREG_SCTLR_EL1
:
1750 case MISCREG_CONTEXTIDR
:
1757 case MISCREG_SCR_EL3
:
1758 case MISCREG_HCR_EL2
:
1759 case MISCREG_TCR_EL1
:
1760 case MISCREG_TCR_EL2
:
1761 case MISCREG_TCR_EL3
:
1762 case MISCREG_SCTLR_EL2
:
1763 case MISCREG_SCTLR_EL3
:
1764 case MISCREG_HSCTLR
:
1765 case MISCREG_TTBR0_EL1
:
1766 case MISCREG_TTBR1_EL1
:
1767 case MISCREG_TTBR0_EL2
:
1768 case MISCREG_TTBR1_EL2
:
1769 case MISCREG_TTBR0_EL3
:
1770 getITBPtr(tc
)->invalidateMiscReg();
1771 getDTBPtr(tc
)->invalidateMiscReg();
1777 tc
->setCCReg(CCREG_NZ
, cpsr
.nz
);
1778 tc
->setCCReg(CCREG_C
, cpsr
.c
);
1779 tc
->setCCReg(CCREG_V
, cpsr
.v
);
1784 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1785 cpsr
.daif
= (uint8_t) ((CPSR
) newVal
).daif
;
1787 misc_reg
= MISCREG_CPSR
;
1790 case MISCREG_SP_EL0
:
1791 tc
->setIntReg(INTREG_SP0
, newVal
);
1793 case MISCREG_SP_EL1
:
1794 tc
->setIntReg(INTREG_SP1
, newVal
);
1796 case MISCREG_SP_EL2
:
1797 tc
->setIntReg(INTREG_SP2
, newVal
);
1801 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1802 cpsr
.sp
= (uint8_t) ((CPSR
) newVal
).sp
;
1804 misc_reg
= MISCREG_CPSR
;
1807 case MISCREG_CURRENTEL
:
1809 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1810 cpsr
.el
= (uint8_t) ((CPSR
) newVal
).el
;
1812 misc_reg
= MISCREG_CPSR
;
1815 case MISCREG_AT_S1E1R_Xt
:
1816 case MISCREG_AT_S1E1W_Xt
:
1817 case MISCREG_AT_S1E0R_Xt
:
1818 case MISCREG_AT_S1E0W_Xt
:
1819 case MISCREG_AT_S1E2R_Xt
:
1820 case MISCREG_AT_S1E2W_Xt
:
1821 case MISCREG_AT_S12E1R_Xt
:
1822 case MISCREG_AT_S12E1W_Xt
:
1823 case MISCREG_AT_S12E0R_Xt
:
1824 case MISCREG_AT_S12E0W_Xt
:
1825 case MISCREG_AT_S1E3R_Xt
:
1826 case MISCREG_AT_S1E3W_Xt
:
1828 RequestPtr req
= std::make_shared
<Request
>();
1829 Request::Flags flags
= 0;
1830 BaseTLB::Mode mode
= BaseTLB::Read
;
1831 TLB::ArmTranslationType tranType
= TLB::NormalTran
;
1834 case MISCREG_AT_S1E1R_Xt
:
1835 flags
= TLB::MustBeOne
;
1836 tranType
= TLB::S1E1Tran
;
1837 mode
= BaseTLB::Read
;
1839 case MISCREG_AT_S1E1W_Xt
:
1840 flags
= TLB::MustBeOne
;
1841 tranType
= TLB::S1E1Tran
;
1842 mode
= BaseTLB::Write
;
1844 case MISCREG_AT_S1E0R_Xt
:
1845 flags
= TLB::MustBeOne
| TLB::UserMode
;
1846 tranType
= TLB::S1E0Tran
;
1847 mode
= BaseTLB::Read
;
1849 case MISCREG_AT_S1E0W_Xt
:
1850 flags
= TLB::MustBeOne
| TLB::UserMode
;
1851 tranType
= TLB::S1E0Tran
;
1852 mode
= BaseTLB::Write
;
1854 case MISCREG_AT_S1E2R_Xt
:
1855 flags
= TLB::MustBeOne
;
1856 tranType
= TLB::S1E2Tran
;
1857 mode
= BaseTLB::Read
;
1859 case MISCREG_AT_S1E2W_Xt
:
1860 flags
= TLB::MustBeOne
;
1861 tranType
= TLB::S1E2Tran
;
1862 mode
= BaseTLB::Write
;
1864 case MISCREG_AT_S12E0R_Xt
:
1865 flags
= TLB::MustBeOne
| TLB::UserMode
;
1866 tranType
= TLB::S12E0Tran
;
1867 mode
= BaseTLB::Read
;
1869 case MISCREG_AT_S12E0W_Xt
:
1870 flags
= TLB::MustBeOne
| TLB::UserMode
;
1871 tranType
= TLB::S12E0Tran
;
1872 mode
= BaseTLB::Write
;
1874 case MISCREG_AT_S12E1R_Xt
:
1875 flags
= TLB::MustBeOne
;
1876 tranType
= TLB::S12E1Tran
;
1877 mode
= BaseTLB::Read
;
1879 case MISCREG_AT_S12E1W_Xt
:
1880 flags
= TLB::MustBeOne
;
1881 tranType
= TLB::S12E1Tran
;
1882 mode
= BaseTLB::Write
;
1884 case MISCREG_AT_S1E3R_Xt
:
1885 flags
= TLB::MustBeOne
;
1886 tranType
= TLB::S1E3Tran
;
1887 mode
= BaseTLB::Read
;
1889 case MISCREG_AT_S1E3W_Xt
:
1890 flags
= TLB::MustBeOne
;
1891 tranType
= TLB::S1E3Tran
;
1892 mode
= BaseTLB::Write
;
1895 // If we're in timing mode then doing the translation in
1896 // functional mode then we're slightly distorting performance
1897 // results obtained from simulations. The translation should be
1898 // done in the same mode the core is running in. NOTE: This
1899 // can't be an atomic translation because that causes problems
1900 // with unexpected atomic snoop requests.
1901 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg
);
1902 req
->setVirt(0, val
, 0, flags
, Request::funcMasterId
,
1903 tc
->pcState().pc());
1904 req
->setContext(tc
->contextId());
1905 fault
= getDTBPtr(tc
)->translateFunctional(req
, tc
, mode
,
1909 if (fault
== NoFault
) {
1910 Addr paddr
= req
->getPaddr();
1911 uint64_t attr
= getDTBPtr(tc
)->getAttr();
1912 uint64_t attr1
= attr
>> 56;
1913 if (!attr1
|| attr1
==0x44) {
1915 attr
&= ~ uint64_t(0x80);
1917 newVal
= (paddr
& mask(47, 12)) | attr
;
1919 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
1922 ArmFault
*armFault
= static_cast<ArmFault
*>(fault
.get());
1923 armFault
->update(tc
);
1924 // Set fault bit and FSR
1925 FSR fsr
= armFault
->getFsr(tc
);
1927 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
1928 if (cpsr
.width
) { // AArch32
1929 newVal
= ((fsr
>> 9) & 1) << 11;
1930 // rearrange fault status
1931 newVal
|= ((fsr
>> 0) & 0x3f) << 1;
1932 newVal
|= 0x1; // F bit
1933 newVal
|= ((armFault
->iss() >> 7) & 0x1) << 8;
1934 newVal
|= armFault
->isStage2() ? 0x200 : 0;
1936 newVal
= 1; // F bit
1937 newVal
|= fsr
<< 1; // FST
1938 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
1939 newVal
|= armFault
->isStage2() ? 1 << 8 : 0; // PTW
1940 newVal
|= armFault
->isStage2() ? 1 << 9 : 0; // S
1941 newVal
|= 1 << 11; // RES1
1944 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
1947 setMiscRegNoEffect(MISCREG_PAR_EL1
, newVal
);
1950 case MISCREG_SPSR_EL3
:
1951 case MISCREG_SPSR_EL2
:
1952 case MISCREG_SPSR_EL1
:
1953 // Force bits 23:21 to 0
1954 newVal
= val
& ~(0x7 << 21);
1956 case MISCREG_L2CTLR
:
1957 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
1958 miscRegName
[misc_reg
], uint32_t(val
));
1961 // Generic Timer registers
1962 case MISCREG_CNTHV_CTL_EL2
:
1963 case MISCREG_CNTHV_CVAL_EL2
:
1964 case MISCREG_CNTHV_TVAL_EL2
:
1965 case MISCREG_CNTFRQ
... MISCREG_CNTHP_CTL
:
1966 case MISCREG_CNTPCT
... MISCREG_CNTHP_CVAL
:
1967 case MISCREG_CNTKCTL_EL1
... MISCREG_CNTV_CVAL_EL0
:
1968 case MISCREG_CNTVOFF_EL2
... MISCREG_CNTPS_CVAL_EL1
:
1969 getGenericTimer(tc
).setMiscReg(misc_reg
, newVal
);
1973 setMiscRegNoEffect(misc_reg
, newVal
);
1977 ISA::getGenericTimer(ThreadContext
*tc
)
1979 // We only need to create an ISA interface the first time we try
1980 // to access the timer.
1982 return *timer
.get();
1985 GenericTimer
*generic_timer(system
->getGenericTimer());
1986 if (!generic_timer
) {
1987 panic("Trying to get a generic timer from a system that hasn't "
1988 "been configured to use a generic timer.\n");
1991 timer
.reset(new GenericTimerISA(*generic_timer
, tc
->contextId()));
1992 timer
->setThreadContext(tc
);
1994 return *timer
.get();
2000 ArmISAParams::create()
2002 return new ArmISA::ISA(this);