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arch-arm: Implementation of SelfHosted Debug Software step
[gem5.git] / src / arch / arm / isa.cc
1 /*
2 * Copyright (c) 2010-2020 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 #include "arch/arm/isa.hh"
39
40 #include "arch/arm/faults.hh"
41 #include "arch/arm/interrupts.hh"
42 #include "arch/arm/pmu.hh"
43 #include "arch/arm/self_debug.hh"
44 #include "arch/arm/system.hh"
45 #include "arch/arm/tlb.hh"
46 #include "arch/arm/tlbi_op.hh"
47 #include "cpu/base.hh"
48 #include "cpu/checker/cpu.hh"
49 #include "debug/Arm.hh"
50 #include "debug/MiscRegs.hh"
51 #include "dev/arm/generic_timer.hh"
52 #include "dev/arm/gic_v3.hh"
53 #include "dev/arm/gic_v3_cpu_interface.hh"
54 #include "params/ArmISA.hh"
55 #include "sim/faults.hh"
56 #include "sim/stat_control.hh"
57 #include "sim/system.hh"
58
59 namespace ArmISA
60 {
61
62 ISA::ISA(Params *p) : BaseISA(p), system(NULL),
63 _decoderFlavor(p->decoderFlavor), _vecRegRenameMode(Enums::Full),
64 pmu(p->pmu), impdefAsNop(p->impdef_nop),
65 afterStartup(false)
66 {
67 miscRegs[MISCREG_SCTLR_RST] = 0;
68
69 // Hook up a dummy device if we haven't been configured with a
70 // real PMU. By using a dummy device, we don't need to check that
71 // the PMU exist every time we try to access a PMU register.
72 if (!pmu)
73 pmu = &dummyDevice;
74
75 // Give all ISA devices a pointer to this ISA
76 pmu->setISA(this);
77
78 system = dynamic_cast<ArmSystem *>(p->system);
79
80 // Cache system-level properties
81 if (FullSystem && system) {
82 highestELIs64 = system->highestELIs64();
83 haveSecurity = system->haveSecurity();
84 haveLPAE = system->haveLPAE();
85 haveCrypto = system->haveCrypto();
86 haveVirtualization = system->haveVirtualization();
87 haveLargeAsid64 = system->haveLargeAsid64();
88 physAddrRange = system->physAddrRange();
89 haveSVE = system->haveSVE();
90 havePAN = system->havePAN();
91 sveVL = system->sveVL();
92 haveLSE = system->haveLSE();
93 } else {
94 highestELIs64 = true; // ArmSystem::highestELIs64 does the same
95 haveSecurity = haveLPAE = haveVirtualization = false;
96 haveCrypto = true;
97 haveLargeAsid64 = false;
98 physAddrRange = 32; // dummy value
99 haveSVE = true;
100 havePAN = false;
101 sveVL = p->sve_vl_se;
102 haveLSE = true;
103 }
104
105 // Initial rename mode depends on highestEL
106 const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) =
107 highestELIs64 ? Enums::Full : Enums::Elem;
108
109 selfDebug = new SelfDebug();
110 initializeMiscRegMetadata();
111 preUnflattenMiscReg();
112
113 clear();
114 }
115
116 std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS);
117
118 const ArmISAParams *
119 ISA::params() const
120 {
121 return dynamic_cast<const Params *>(_params);
122 }
123
124 void
125 ISA::clear()
126 {
127 const Params *p(params());
128
129 // Invalidate cached copies of miscregs in the TLBs
130 if (tc) {
131 getITBPtr(tc)->invalidateMiscReg();
132 getDTBPtr(tc)->invalidateMiscReg();
133 }
134
135 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
136 memset(miscRegs, 0, sizeof(miscRegs));
137
138 initID32(p);
139
140 // We always initialize AArch64 ID registers even
141 // if we are in AArch32. This is done since if we
142 // are in SE mode we don't know if our ArmProcess is
143 // AArch32 or AArch64
144 initID64(p);
145
146 // Start with an event in the mailbox
147 miscRegs[MISCREG_SEV_MAILBOX] = 1;
148
149 // Separate Instruction and Data TLBs
150 miscRegs[MISCREG_TLBTR] = 1;
151
152 MVFR0 mvfr0 = 0;
153 mvfr0.advSimdRegisters = 2;
154 mvfr0.singlePrecision = 2;
155 mvfr0.doublePrecision = 2;
156 mvfr0.vfpExceptionTrapping = 0;
157 mvfr0.divide = 1;
158 mvfr0.squareRoot = 1;
159 mvfr0.shortVectors = 1;
160 mvfr0.roundingModes = 1;
161 miscRegs[MISCREG_MVFR0] = mvfr0;
162
163 MVFR1 mvfr1 = 0;
164 mvfr1.flushToZero = 1;
165 mvfr1.defaultNaN = 1;
166 mvfr1.advSimdLoadStore = 1;
167 mvfr1.advSimdInteger = 1;
168 mvfr1.advSimdSinglePrecision = 1;
169 mvfr1.advSimdHalfPrecision = 1;
170 mvfr1.vfpHalfPrecision = 1;
171 miscRegs[MISCREG_MVFR1] = mvfr1;
172
173 // Reset values of PRRR and NMRR are implementation dependent
174
175 // @todo: PRRR and NMRR in secure state?
176 miscRegs[MISCREG_PRRR_NS] =
177 (1 << 19) | // 19
178 (0 << 18) | // 18
179 (0 << 17) | // 17
180 (1 << 16) | // 16
181 (2 << 14) | // 15:14
182 (0 << 12) | // 13:12
183 (2 << 10) | // 11:10
184 (2 << 8) | // 9:8
185 (2 << 6) | // 7:6
186 (2 << 4) | // 5:4
187 (1 << 2) | // 3:2
188 0; // 1:0
189
190 miscRegs[MISCREG_NMRR_NS] =
191 (1 << 30) | // 31:30
192 (0 << 26) | // 27:26
193 (0 << 24) | // 25:24
194 (3 << 22) | // 23:22
195 (2 << 20) | // 21:20
196 (0 << 18) | // 19:18
197 (0 << 16) | // 17:16
198 (1 << 14) | // 15:14
199 (0 << 12) | // 13:12
200 (2 << 10) | // 11:10
201 (0 << 8) | // 9:8
202 (3 << 6) | // 7:6
203 (2 << 4) | // 5:4
204 (0 << 2) | // 3:2
205 0; // 1:0
206
207 if (FullSystem && system->highestELIs64()) {
208 // Initialize AArch64 state
209 clear64(p);
210 return;
211 }
212
213 // Initialize AArch32 state...
214 clear32(p, sctlr_rst);
215 }
216
217 void
218 ISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst)
219 {
220 CPSR cpsr = 0;
221 cpsr.mode = MODE_USER;
222
223 if (FullSystem) {
224 miscRegs[MISCREG_MVBAR] = system->resetAddr();
225 }
226
227 miscRegs[MISCREG_CPSR] = cpsr;
228 updateRegMap(cpsr);
229
230 SCTLR sctlr = 0;
231 sctlr.te = (bool) sctlr_rst.te;
232 sctlr.nmfi = (bool) sctlr_rst.nmfi;
233 sctlr.v = (bool) sctlr_rst.v;
234 sctlr.u = 1;
235 sctlr.xp = 1;
236 sctlr.rao2 = 1;
237 sctlr.rao3 = 1;
238 sctlr.rao4 = 0xf; // SCTLR[6:3]
239 sctlr.uci = 1;
240 sctlr.dze = 1;
241 miscRegs[MISCREG_SCTLR_NS] = sctlr;
242 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
243 miscRegs[MISCREG_HCPTR] = 0;
244
245 miscRegs[MISCREG_CPACR] = 0;
246
247 miscRegs[MISCREG_FPSID] = p->fpsid;
248
249 if (haveLPAE) {
250 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
251 ttbcr.eae = 0;
252 miscRegs[MISCREG_TTBCR_NS] = ttbcr;
253 // Enforce consistency with system-level settings
254 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
255 }
256
257 if (haveSecurity) {
258 miscRegs[MISCREG_SCTLR_S] = sctlr;
259 miscRegs[MISCREG_SCR] = 0;
260 miscRegs[MISCREG_VBAR_S] = 0;
261 } else {
262 // we're always non-secure
263 miscRegs[MISCREG_SCR] = 1;
264 }
265
266 //XXX We need to initialize the rest of the state.
267 }
268
269 void
270 ISA::clear64(const ArmISAParams *p)
271 {
272 CPSR cpsr = 0;
273 Addr rvbar = system->resetAddr();
274 switch (system->highestEL()) {
275 // Set initial EL to highest implemented EL using associated stack
276 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
277 // value
278 case EL3:
279 cpsr.mode = MODE_EL3H;
280 miscRegs[MISCREG_RVBAR_EL3] = rvbar;
281 break;
282 case EL2:
283 cpsr.mode = MODE_EL2H;
284 miscRegs[MISCREG_RVBAR_EL2] = rvbar;
285 break;
286 case EL1:
287 cpsr.mode = MODE_EL1H;
288 miscRegs[MISCREG_RVBAR_EL1] = rvbar;
289 break;
290 default:
291 panic("Invalid highest implemented exception level");
292 break;
293 }
294
295 // Initialize rest of CPSR
296 cpsr.daif = 0xf; // Mask all interrupts
297 cpsr.ss = 0;
298 cpsr.il = 0;
299 miscRegs[MISCREG_CPSR] = cpsr;
300 updateRegMap(cpsr);
301
302 // Initialize other control registers
303 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
304 if (haveSecurity) {
305 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
306 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
307 } else if (haveVirtualization) {
308 // also MISCREG_SCTLR_EL2 (by mapping)
309 miscRegs[MISCREG_HSCTLR] = 0x30c50830;
310 } else {
311 // also MISCREG_SCTLR_EL1 (by mapping)
312 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
313 // Always non-secure
314 miscRegs[MISCREG_SCR_EL3] = 1;
315 }
316 }
317
318 void
319 ISA::initID32(const ArmISAParams *p)
320 {
321 // Initialize configurable default values
322
323 uint32_t midr;
324 if (p->midr != 0x0)
325 midr = p->midr;
326 else if (highestELIs64)
327 // Cortex-A57 TRM r0p0 MIDR
328 midr = 0x410fd070;
329 else
330 // Cortex-A15 TRM r0p0 MIDR
331 midr = 0x410fc0f0;
332
333 miscRegs[MISCREG_MIDR] = midr;
334 miscRegs[MISCREG_MIDR_EL1] = midr;
335 miscRegs[MISCREG_VPIDR] = midr;
336
337 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
338 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
339 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
340 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
341 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
342 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
343
344 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
345 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
346 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
347 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
348
349 miscRegs[MISCREG_ID_ISAR5] = insertBits(
350 miscRegs[MISCREG_ID_ISAR5], 19, 4,
351 haveCrypto ? 0x1112 : 0x0);
352 }
353
354 void
355 ISA::initID64(const ArmISAParams *p)
356 {
357 // Initialize configurable id registers
358 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
359 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
360 miscRegs[MISCREG_ID_AA64DFR0_EL1] =
361 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
362 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3
363
364 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
365 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
366 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
367 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
368 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
369 miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1;
370
371 miscRegs[MISCREG_ID_DFR0_EL1] =
372 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3
373
374 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
375
376 // SVE
377 miscRegs[MISCREG_ID_AA64ZFR0_EL1] = 0; // SVEver 0
378 if (haveSecurity) {
379 miscRegs[MISCREG_ZCR_EL3] = sveVL - 1;
380 } else if (haveVirtualization) {
381 miscRegs[MISCREG_ZCR_EL2] = sveVL - 1;
382 } else {
383 miscRegs[MISCREG_ZCR_EL1] = sveVL - 1;
384 }
385
386 // Enforce consistency with system-level settings...
387
388 // EL3
389 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
390 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
391 haveSecurity ? 0x2 : 0x0);
392 // EL2
393 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
394 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
395 haveVirtualization ? 0x2 : 0x0);
396 // SVE
397 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
398 miscRegs[MISCREG_ID_AA64PFR0_EL1], 35, 32,
399 haveSVE ? 0x1 : 0x0);
400 // Large ASID support
401 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
402 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
403 haveLargeAsid64 ? 0x2 : 0x0);
404 // Physical address size
405 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
406 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
407 encodePhysAddrRange64(physAddrRange));
408 // Crypto
409 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
410 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4,
411 haveCrypto ? 0x1112 : 0x0);
412 // LSE
413 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
414 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20,
415 haveLSE ? 0x2 : 0x0);
416 // PAN
417 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
418 miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,
419 havePAN ? 0x1 : 0x0);
420 }
421
422 void
423 ISA::startup()
424 {
425 BaseISA::startup();
426
427 if (tc)
428 setupThreadContext();
429
430 afterStartup = true;
431 }
432
433 void
434 ISA::setupThreadContext()
435 {
436 pmu->setThreadContext(tc);
437
438 if (!system)
439 return;
440
441 selfDebug->init(tc);
442
443 Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
444 if (!gicv3)
445 return;
446
447 if (!gicv3CpuInterface)
448 gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
449
450 gicv3CpuInterface->setISA(this);
451 gicv3CpuInterface->setThreadContext(tc);
452 }
453
454 void
455 ISA::takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
456 {
457 tc = new_tc;
458 setupThreadContext();
459 }
460
461 RegVal
462 ISA::readMiscRegNoEffect(int misc_reg) const
463 {
464 assert(misc_reg < NumMiscRegs);
465
466 const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
467 const auto &map = getMiscIndices(misc_reg);
468 int lower = map.first, upper = map.second;
469 // NB!: apply architectural masks according to desired register,
470 // despite possibly getting value from different (mapped) register.
471 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
472 |(miscRegs[upper] << 32));
473 if (val & reg.res0()) {
474 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n",
475 miscRegName[misc_reg], val & reg.res0());
476 }
477 if ((val & reg.res1()) != reg.res1()) {
478 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n",
479 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1());
480 }
481 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao
482 }
483
484
485 RegVal
486 ISA::readMiscReg(int misc_reg)
487 {
488 CPSR cpsr = 0;
489 PCState pc = 0;
490 SCR scr = 0;
491
492 if (misc_reg == MISCREG_CPSR) {
493 cpsr = miscRegs[misc_reg];
494 pc = tc->pcState();
495 cpsr.j = pc.jazelle() ? 1 : 0;
496 cpsr.t = pc.thumb() ? 1 : 0;
497 return cpsr;
498 }
499
500 #ifndef NDEBUG
501 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
502 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
503 warn("Unimplemented system register %s read.\n",
504 miscRegName[misc_reg]);
505 else
506 panic("Unimplemented system register %s read.\n",
507 miscRegName[misc_reg]);
508 }
509 #endif
510
511 switch (unflattenMiscReg(misc_reg)) {
512 case MISCREG_HCR:
513 case MISCREG_HCR2:
514 if (!haveVirtualization)
515 return 0;
516 break;
517 case MISCREG_CPACR:
518 {
519 const uint32_t ones = (uint32_t)(-1);
520 CPACR cpacrMask = 0;
521 // Only cp10, cp11, and ase are implemented, nothing else should
522 // be readable? (straight copy from the write code)
523 cpacrMask.cp10 = ones;
524 cpacrMask.cp11 = ones;
525 cpacrMask.asedis = ones;
526
527 // Security Extensions may limit the readability of CPACR
528 if (haveSecurity) {
529 scr = readMiscRegNoEffect(MISCREG_SCR);
530 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
531 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
532 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
533 // NB: Skipping the full loop, here
534 if (!nsacr.cp10) cpacrMask.cp10 = 0;
535 if (!nsacr.cp11) cpacrMask.cp11 = 0;
536 }
537 }
538 RegVal val = readMiscRegNoEffect(MISCREG_CPACR);
539 val &= cpacrMask;
540 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
541 miscRegName[misc_reg], val);
542 return val;
543 }
544 case MISCREG_MPIDR:
545 case MISCREG_MPIDR_EL1:
546 return readMPIDR(system, tc);
547 case MISCREG_VMPIDR:
548 case MISCREG_VMPIDR_EL2:
549 // top bit defined as RES1
550 return readMiscRegNoEffect(misc_reg) | 0x80000000;
551 case MISCREG_ID_AFR0: // not implemented, so alias MIDR
552 case MISCREG_REVIDR: // not implemented, so alias MIDR
553 case MISCREG_MIDR:
554 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
555 scr = readMiscRegNoEffect(MISCREG_SCR);
556 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
557 return readMiscRegNoEffect(misc_reg);
558 } else {
559 return readMiscRegNoEffect(MISCREG_VPIDR);
560 }
561 break;
562 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
563 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI
564 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI
565 case MISCREG_AIDR: // AUX ID set to 0
566 case MISCREG_TCMTR: // No TCM's
567 return 0;
568
569 case MISCREG_CLIDR:
570 warn_once("The clidr register always reports 0 caches.\n");
571 warn_once("clidr LoUIS field of 0b001 to match current "
572 "ARM implementations.\n");
573 return 0x00200000;
574 case MISCREG_CCSIDR:
575 warn_once("The ccsidr register isn't implemented and "
576 "always reads as 0.\n");
577 break;
578 case MISCREG_CTR: // AArch32, ARMv7, top bit set
579 case MISCREG_CTR_EL0: // AArch64
580 {
581 //all caches have the same line size in gem5
582 //4 byte words in ARM
583 unsigned lineSizeWords =
584 tc->getSystemPtr()->cacheLineSize() / 4;
585 unsigned log2LineSizeWords = 0;
586
587 while (lineSizeWords >>= 1) {
588 ++log2LineSizeWords;
589 }
590
591 CTR ctr = 0;
592 //log2 of minimun i-cache line size (words)
593 ctr.iCacheLineSize = log2LineSizeWords;
594 //b11 - gem5 uses pipt
595 ctr.l1IndexPolicy = 0x3;
596 //log2 of minimum d-cache line size (words)
597 ctr.dCacheLineSize = log2LineSizeWords;
598 //log2 of max reservation size (words)
599 ctr.erg = log2LineSizeWords;
600 //log2 of max writeback size (words)
601 ctr.cwg = log2LineSizeWords;
602 //b100 - gem5 format is ARMv7
603 ctr.format = 0x4;
604
605 return ctr;
606 }
607 case MISCREG_ACTLR:
608 warn("Not doing anything for miscreg ACTLR\n");
609 break;
610
611 case MISCREG_PMXEVTYPER_PMCCFILTR:
612 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
613 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
614 case MISCREG_PMCR ... MISCREG_PMOVSSET:
615 return pmu->readMiscReg(misc_reg);
616
617 case MISCREG_CPSR_Q:
618 panic("shouldn't be reading this register seperately\n");
619 case MISCREG_FPSCR_QC:
620 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
621 case MISCREG_FPSCR_EXC:
622 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
623 case MISCREG_FPSR:
624 {
625 const uint32_t ones = (uint32_t)(-1);
626 FPSCR fpscrMask = 0;
627 fpscrMask.ioc = ones;
628 fpscrMask.dzc = ones;
629 fpscrMask.ofc = ones;
630 fpscrMask.ufc = ones;
631 fpscrMask.ixc = ones;
632 fpscrMask.idc = ones;
633 fpscrMask.qc = ones;
634 fpscrMask.v = ones;
635 fpscrMask.c = ones;
636 fpscrMask.z = ones;
637 fpscrMask.n = ones;
638 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
639 }
640 case MISCREG_FPCR:
641 {
642 const uint32_t ones = (uint32_t)(-1);
643 FPSCR fpscrMask = 0;
644 fpscrMask.len = ones;
645 fpscrMask.fz16 = ones;
646 fpscrMask.stride = ones;
647 fpscrMask.rMode = ones;
648 fpscrMask.fz = ones;
649 fpscrMask.dn = ones;
650 fpscrMask.ahp = ones;
651 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
652 }
653 case MISCREG_NZCV:
654 {
655 CPSR cpsr = 0;
656 cpsr.nz = tc->readCCReg(CCREG_NZ);
657 cpsr.c = tc->readCCReg(CCREG_C);
658 cpsr.v = tc->readCCReg(CCREG_V);
659 return cpsr;
660 }
661 case MISCREG_DAIF:
662 {
663 CPSR cpsr = 0;
664 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
665 return cpsr;
666 }
667 case MISCREG_SP_EL0:
668 {
669 return tc->readIntReg(INTREG_SP0);
670 }
671 case MISCREG_SP_EL1:
672 {
673 return tc->readIntReg(INTREG_SP1);
674 }
675 case MISCREG_SP_EL2:
676 {
677 return tc->readIntReg(INTREG_SP2);
678 }
679 case MISCREG_SPSEL:
680 {
681 return miscRegs[MISCREG_CPSR] & 0x1;
682 }
683 case MISCREG_CURRENTEL:
684 {
685 return miscRegs[MISCREG_CPSR] & 0xc;
686 }
687 case MISCREG_PAN:
688 {
689 return miscRegs[MISCREG_CPSR] & 0x400000;
690 }
691 case MISCREG_L2CTLR:
692 {
693 // mostly unimplemented, just set NumCPUs field from sim and return
694 L2CTLR l2ctlr = 0;
695 // b00:1CPU to b11:4CPUs
696 l2ctlr.numCPUs = tc->getSystemPtr()->threads.size() - 1;
697 return l2ctlr;
698 }
699 case MISCREG_DBGDIDR:
700 /* For now just implement the version number.
701 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
702 */
703 return 0x5 << 16;
704 case MISCREG_DBGDSCRint:
705 return readMiscRegNoEffect(MISCREG_DBGDSCRint);
706 case MISCREG_ISR:
707 {
708 auto ic = dynamic_cast<ArmISA::Interrupts *>(
709 tc->getCpuPtr()->getInterruptController(tc->threadId()));
710 return ic->getISR(
711 readMiscRegNoEffect(MISCREG_HCR),
712 readMiscRegNoEffect(MISCREG_CPSR),
713 readMiscRegNoEffect(MISCREG_SCR));
714 }
715 case MISCREG_ISR_EL1:
716 {
717 auto ic = dynamic_cast<ArmISA::Interrupts *>(
718 tc->getCpuPtr()->getInterruptController(tc->threadId()));
719 return ic->getISR(
720 readMiscRegNoEffect(MISCREG_HCR_EL2),
721 readMiscRegNoEffect(MISCREG_CPSR),
722 readMiscRegNoEffect(MISCREG_SCR_EL3));
723 }
724 case MISCREG_DCZID_EL0:
725 return 0x04; // DC ZVA clear 64-byte chunks
726 case MISCREG_HCPTR:
727 {
728 RegVal val = readMiscRegNoEffect(misc_reg);
729 // The trap bit associated with CP14 is defined as RAZ
730 val &= ~(1 << 14);
731 // If a CP bit in NSACR is 0 then the corresponding bit in
732 // HCPTR is RAO/WI
733 bool secure_lookup = haveSecurity &&
734 inSecureState(readMiscRegNoEffect(MISCREG_SCR),
735 readMiscRegNoEffect(MISCREG_CPSR));
736 if (!secure_lookup) {
737 RegVal mask = readMiscRegNoEffect(MISCREG_NSACR);
738 val |= (mask ^ 0x7FFF) & 0xBFFF;
739 }
740 // Set the bits for unimplemented coprocessors to RAO/WI
741 val |= 0x33FF;
742 return (val);
743 }
744 case MISCREG_HDFAR: // alias for secure DFAR
745 return readMiscRegNoEffect(MISCREG_DFAR_S);
746 case MISCREG_HIFAR: // alias for secure IFAR
747 return readMiscRegNoEffect(MISCREG_IFAR_S);
748
749 case MISCREG_ID_PFR0:
750 // !ThumbEE | !Jazelle | Thumb | ARM
751 return 0x00000031;
752 case MISCREG_ID_PFR1:
753 { // Timer | Virti | !M Profile | TrustZone | ARMv4
754 bool haveTimer = (system->getGenericTimer() != NULL);
755 return 0x00000001
756 | (haveSecurity ? 0x00000010 : 0x0)
757 | (haveVirtualization ? 0x00001000 : 0x0)
758 | (haveTimer ? 0x00010000 : 0x0);
759 }
760 case MISCREG_ID_AA64PFR0_EL1:
761 return 0x0000000000000002 | // AArch{64,32} supported at EL0
762 0x0000000000000020 | // EL1
763 (haveVirtualization ? 0x0000000000000200 : 0) | // EL2
764 (haveSecurity ? 0x0000000000002000 : 0) | // EL3
765 (haveSVE ? 0x0000000100000000 : 0) | // SVE
766 (gicv3CpuInterface ? 0x0000000001000000 : 0);
767 case MISCREG_ID_AA64PFR1_EL1:
768 return 0; // bits [63:0] RES0 (reserved for future use)
769
770 // Generic Timer registers
771 case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
772 case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
773 return getGenericTimer().readMiscReg(misc_reg);
774
775 case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15:
776 case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
777 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
778 return getGICv3CPUInterface().readMiscReg(misc_reg);
779
780 default:
781 break;
782
783 }
784 return readMiscRegNoEffect(misc_reg);
785 }
786
787 void
788 ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
789 {
790 assert(misc_reg < NumMiscRegs);
791
792 const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
793 const auto &map = getMiscIndices(misc_reg);
794 int lower = map.first, upper = map.second;
795
796 auto v = (val & ~reg.wi()) | reg.rao();
797 if (upper > 0) {
798 miscRegs[lower] = bits(v, 31, 0);
799 miscRegs[upper] = bits(v, 63, 32);
800 DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d:%d) : %#x\n",
801 miscRegName[misc_reg], misc_reg, lower, upper, v);
802 } else {
803 miscRegs[lower] = v;
804 DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d) : %#x\n",
805 miscRegName[misc_reg], misc_reg, lower, v);
806 }
807 }
808
809 void
810 ISA::setMiscReg(int misc_reg, RegVal val)
811 {
812
813 RegVal newVal = val;
814 bool secure_lookup;
815 SCR scr;
816
817 if (misc_reg == MISCREG_CPSR) {
818 updateRegMap(val);
819
820
821 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
822 int old_mode = old_cpsr.mode;
823 CPSR cpsr = val;
824 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) {
825 getITBPtr(tc)->invalidateMiscReg();
826 getDTBPtr(tc)->invalidateMiscReg();
827 }
828
829 if (cpsr.pan != old_cpsr.pan) {
830 getDTBPtr(tc)->invalidateMiscReg();
831 }
832
833 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
834 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
835 PCState pc = tc->pcState();
836 pc.nextThumb(cpsr.t);
837 pc.nextJazelle(cpsr.j);
838 pc.illegalExec(cpsr.il == 1);
839 selfDebug->setDebugMask(cpsr.d == 1);
840
841 tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits() >> 7) - 1);
842
843 // Follow slightly different semantics if a CheckerCPU object
844 // is connected
845 CheckerCPU *checker = tc->getCheckerCpuPtr();
846 if (checker) {
847 tc->pcStateNoRecord(pc);
848 } else {
849 tc->pcState(pc);
850 }
851 } else {
852 #ifndef NDEBUG
853 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
854 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
855 warn("Unimplemented system register %s write with %#x.\n",
856 miscRegName[misc_reg], val);
857 else
858 panic("Unimplemented system register %s write with %#x.\n",
859 miscRegName[misc_reg], val);
860 }
861 #endif
862 switch (unflattenMiscReg(misc_reg)) {
863 case MISCREG_CPACR:
864 {
865
866 const uint32_t ones = (uint32_t)(-1);
867 CPACR cpacrMask = 0;
868 // Only cp10, cp11, and ase are implemented, nothing else should
869 // be writable
870 cpacrMask.cp10 = ones;
871 cpacrMask.cp11 = ones;
872 cpacrMask.asedis = ones;
873
874 // Security Extensions may limit the writability of CPACR
875 if (haveSecurity) {
876 scr = readMiscRegNoEffect(MISCREG_SCR);
877 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
878 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
879 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
880 // NB: Skipping the full loop, here
881 if (!nsacr.cp10) cpacrMask.cp10 = 0;
882 if (!nsacr.cp11) cpacrMask.cp11 = 0;
883 }
884 }
885
886 RegVal old_val = readMiscRegNoEffect(MISCREG_CPACR);
887 newVal &= cpacrMask;
888 newVal |= old_val & ~cpacrMask;
889 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
890 miscRegName[misc_reg], newVal);
891 }
892 break;
893 case MISCREG_CPACR_EL1:
894 {
895 const uint32_t ones = (uint32_t)(-1);
896 CPACR cpacrMask = 0;
897 cpacrMask.tta = ones;
898 cpacrMask.fpen = ones;
899 if (haveSVE) {
900 cpacrMask.zen = ones;
901 }
902 newVal &= cpacrMask;
903 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
904 miscRegName[misc_reg], newVal);
905 }
906 break;
907 case MISCREG_CPTR_EL2:
908 {
909 const uint32_t ones = (uint32_t)(-1);
910 CPTR cptrMask = 0;
911 cptrMask.tcpac = ones;
912 cptrMask.tta = ones;
913 cptrMask.tfp = ones;
914 if (haveSVE) {
915 cptrMask.tz = ones;
916 }
917 newVal &= cptrMask;
918 cptrMask = 0;
919 cptrMask.res1_13_12_el2 = ones;
920 cptrMask.res1_7_0_el2 = ones;
921 if (!haveSVE) {
922 cptrMask.res1_8_el2 = ones;
923 }
924 cptrMask.res1_9_el2 = ones;
925 newVal |= cptrMask;
926 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
927 miscRegName[misc_reg], newVal);
928 }
929 break;
930 case MISCREG_CPTR_EL3:
931 {
932 const uint32_t ones = (uint32_t)(-1);
933 CPTR cptrMask = 0;
934 cptrMask.tcpac = ones;
935 cptrMask.tta = ones;
936 cptrMask.tfp = ones;
937 if (haveSVE) {
938 cptrMask.ez = ones;
939 }
940 newVal &= cptrMask;
941 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
942 miscRegName[misc_reg], newVal);
943 }
944 break;
945 case MISCREG_CSSELR:
946 warn_once("The csselr register isn't implemented.\n");
947 return;
948
949 case MISCREG_DC_ZVA_Xt:
950 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
951 return;
952
953 case MISCREG_FPSCR:
954 {
955 const uint32_t ones = (uint32_t)(-1);
956 FPSCR fpscrMask = 0;
957 fpscrMask.ioc = ones;
958 fpscrMask.dzc = ones;
959 fpscrMask.ofc = ones;
960 fpscrMask.ufc = ones;
961 fpscrMask.ixc = ones;
962 fpscrMask.idc = ones;
963 fpscrMask.ioe = ones;
964 fpscrMask.dze = ones;
965 fpscrMask.ofe = ones;
966 fpscrMask.ufe = ones;
967 fpscrMask.ixe = ones;
968 fpscrMask.ide = ones;
969 fpscrMask.len = ones;
970 fpscrMask.fz16 = ones;
971 fpscrMask.stride = ones;
972 fpscrMask.rMode = ones;
973 fpscrMask.fz = ones;
974 fpscrMask.dn = ones;
975 fpscrMask.ahp = ones;
976 fpscrMask.qc = ones;
977 fpscrMask.v = ones;
978 fpscrMask.c = ones;
979 fpscrMask.z = ones;
980 fpscrMask.n = ones;
981 newVal = (newVal & (uint32_t)fpscrMask) |
982 (readMiscRegNoEffect(MISCREG_FPSCR) &
983 ~(uint32_t)fpscrMask);
984 tc->getDecoderPtr()->setContext(newVal);
985 }
986 break;
987 case MISCREG_FPSR:
988 {
989 const uint32_t ones = (uint32_t)(-1);
990 FPSCR fpscrMask = 0;
991 fpscrMask.ioc = ones;
992 fpscrMask.dzc = ones;
993 fpscrMask.ofc = ones;
994 fpscrMask.ufc = ones;
995 fpscrMask.ixc = ones;
996 fpscrMask.idc = ones;
997 fpscrMask.qc = ones;
998 fpscrMask.v = ones;
999 fpscrMask.c = ones;
1000 fpscrMask.z = ones;
1001 fpscrMask.n = ones;
1002 newVal = (newVal & (uint32_t)fpscrMask) |
1003 (readMiscRegNoEffect(MISCREG_FPSCR) &
1004 ~(uint32_t)fpscrMask);
1005 misc_reg = MISCREG_FPSCR;
1006 }
1007 break;
1008 case MISCREG_FPCR:
1009 {
1010 const uint32_t ones = (uint32_t)(-1);
1011 FPSCR fpscrMask = 0;
1012 fpscrMask.len = ones;
1013 fpscrMask.fz16 = ones;
1014 fpscrMask.stride = ones;
1015 fpscrMask.rMode = ones;
1016 fpscrMask.fz = ones;
1017 fpscrMask.dn = ones;
1018 fpscrMask.ahp = ones;
1019 newVal = (newVal & (uint32_t)fpscrMask) |
1020 (readMiscRegNoEffect(MISCREG_FPSCR) &
1021 ~(uint32_t)fpscrMask);
1022 misc_reg = MISCREG_FPSCR;
1023 }
1024 break;
1025 case MISCREG_CPSR_Q:
1026 {
1027 assert(!(newVal & ~CpsrMaskQ));
1028 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
1029 misc_reg = MISCREG_CPSR;
1030 }
1031 break;
1032 case MISCREG_FPSCR_QC:
1033 {
1034 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1035 (newVal & FpscrQcMask);
1036 misc_reg = MISCREG_FPSCR;
1037 }
1038 break;
1039 case MISCREG_FPSCR_EXC:
1040 {
1041 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1042 (newVal & FpscrExcMask);
1043 misc_reg = MISCREG_FPSCR;
1044 }
1045 break;
1046 case MISCREG_FPEXC:
1047 {
1048 // vfpv3 architecture, section B.6.1 of DDI04068
1049 // bit 29 - valid only if fpexc[31] is 0
1050 const uint32_t fpexcMask = 0x60000000;
1051 newVal = (newVal & fpexcMask) |
1052 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
1053 }
1054 break;
1055 case MISCREG_HCR2:
1056 if (!haveVirtualization)
1057 return;
1058 break;
1059 case MISCREG_HCR:
1060 {
1061 const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1062 selfDebug->setenableTDETGE((HCR)val, mdcr);
1063 if (!haveVirtualization)
1064 return;
1065 }
1066 break;
1067
1068 case MISCREG_HDCR:
1069 {
1070 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1071 selfDebug->setenableTDETGE(hcr, (HDCR)val);
1072 }
1073 break;
1074 case MISCREG_DBGOSLAR:
1075 {
1076 OSL r = tc->readMiscReg(MISCREG_DBGOSLSR);
1077 const uint32_t temp = (val == 0xC5ACCE55)? 0x1 : 0x0;
1078 selfDebug->updateOSLock((RegVal) temp);
1079 r.oslk = bits(temp,0);
1080 tc->setMiscReg(MISCREG_DBGOSLSR, r);
1081 }
1082 break;
1083 case MISCREG_DBGBCR0:
1084 selfDebug->updateDBGBCR(0, val);
1085 break;
1086 case MISCREG_DBGBCR1:
1087 selfDebug->updateDBGBCR(1, val);
1088 break;
1089 case MISCREG_DBGBCR2:
1090 selfDebug->updateDBGBCR(2, val);
1091 break;
1092 case MISCREG_DBGBCR3:
1093 selfDebug->updateDBGBCR(3, val);
1094 break;
1095 case MISCREG_DBGBCR4:
1096 selfDebug->updateDBGBCR(4, val);
1097 break;
1098 case MISCREG_DBGBCR5:
1099 selfDebug->updateDBGBCR(5, val);
1100 break;
1101 case MISCREG_DBGBCR6:
1102 selfDebug->updateDBGBCR(6, val);
1103 break;
1104 case MISCREG_DBGBCR7:
1105 selfDebug->updateDBGBCR(7, val);
1106 break;
1107 case MISCREG_DBGBCR8:
1108 selfDebug->updateDBGBCR(8, val);
1109 break;
1110 case MISCREG_DBGBCR9:
1111 selfDebug->updateDBGBCR(9, val);
1112 break;
1113 case MISCREG_DBGBCR10:
1114 selfDebug->updateDBGBCR(10, val);
1115 break;
1116 case MISCREG_DBGBCR11:
1117 selfDebug->updateDBGBCR(11, val);
1118 break;
1119 case MISCREG_DBGBCR12:
1120 selfDebug->updateDBGBCR(12, val);
1121 break;
1122 case MISCREG_DBGBCR13:
1123 selfDebug->updateDBGBCR(13, val);
1124 break;
1125 case MISCREG_DBGBCR14:
1126 selfDebug->updateDBGBCR(14, val);
1127 break;
1128 case MISCREG_DBGBCR15:
1129 selfDebug->updateDBGBCR(15, val);
1130 break;
1131 case MISCREG_DBGWCR0:
1132 selfDebug->updateDBGWCR(0, val);
1133 break;
1134 case MISCREG_DBGWCR1:
1135 selfDebug->updateDBGWCR(1, val);
1136 break;
1137 case MISCREG_DBGWCR2:
1138 selfDebug->updateDBGWCR(2, val);
1139 break;
1140 case MISCREG_DBGWCR3:
1141 selfDebug->updateDBGWCR(3, val);
1142 break;
1143 case MISCREG_DBGWCR4:
1144 selfDebug->updateDBGWCR(4, val);
1145 break;
1146 case MISCREG_DBGWCR5:
1147 selfDebug->updateDBGWCR(5, val);
1148 break;
1149 case MISCREG_DBGWCR6:
1150 selfDebug->updateDBGWCR(6, val);
1151 break;
1152 case MISCREG_DBGWCR7:
1153 selfDebug->updateDBGWCR(7, val);
1154 break;
1155 case MISCREG_DBGWCR8:
1156 selfDebug->updateDBGWCR(8, val);
1157 break;
1158 case MISCREG_DBGWCR9:
1159 selfDebug->updateDBGWCR(9, val);
1160 break;
1161 case MISCREG_DBGWCR10:
1162 selfDebug->updateDBGWCR(10, val);
1163 break;
1164 case MISCREG_DBGWCR11:
1165 selfDebug->updateDBGWCR(11, val);
1166 break;
1167 case MISCREG_DBGWCR12:
1168 selfDebug->updateDBGWCR(12, val);
1169 break;
1170 case MISCREG_DBGWCR13:
1171 selfDebug->updateDBGWCR(13, val);
1172 break;
1173 case MISCREG_DBGWCR14:
1174 selfDebug->updateDBGWCR(14, val);
1175 break;
1176 case MISCREG_DBGWCR15:
1177 selfDebug->updateDBGWCR(15, val);
1178 break;
1179
1180 case MISCREG_MDCR_EL2:
1181 {
1182 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1183 selfDebug->setenableTDETGE(hcr, (HDCR)val);
1184 }
1185 break;
1186 case MISCREG_SDCR:
1187 case MISCREG_MDCR_EL3:
1188 {
1189 selfDebug->setbSDD(val);
1190 }
1191 break;
1192 case MISCREG_DBGDSCRext:
1193 {
1194 selfDebug->setMDBGen(val);
1195 DBGDS32 r = tc->readMiscReg(MISCREG_DBGDSCRint);
1196 DBGDS32 v = val;
1197 r.moe = v.moe;
1198 r.udccdis = v.udccdis;
1199 r.mdbgen = v.mdbgen;
1200 tc->setMiscReg(MISCREG_DBGDSCRint, r);
1201 r = tc->readMiscReg(MISCREG_DBGDSCRint);
1202 }
1203
1204 break;
1205 case MISCREG_MDSCR_EL1:
1206 {
1207 selfDebug->setMDSCRvals(val);
1208 }
1209 break;
1210
1211 case MISCREG_OSLAR_EL1:
1212 {
1213 selfDebug->updateOSLock(val);
1214 OSL r = tc->readMiscReg(MISCREG_OSLSR_EL1);
1215 r.oslk = bits(val, 0);
1216 r.oslm_3 = 1;
1217 tc->setMiscReg(MISCREG_OSLSR_EL1, r);
1218 }
1219 break;
1220
1221 case MISCREG_DBGBCR0_EL1:
1222 selfDebug->updateDBGBCR(0, val);
1223 break;
1224 case MISCREG_DBGBCR1_EL1:
1225 selfDebug->updateDBGBCR(1, val);
1226 break;
1227 case MISCREG_DBGBCR2_EL1:
1228 selfDebug->updateDBGBCR(2, val);
1229 break;
1230 case MISCREG_DBGBCR3_EL1:
1231 selfDebug->updateDBGBCR(3, val);
1232 break;
1233 case MISCREG_DBGBCR4_EL1:
1234 selfDebug->updateDBGBCR(4, val);
1235 break;
1236 case MISCREG_DBGBCR5_EL1:
1237 selfDebug->updateDBGBCR(5, val);
1238 break;
1239 case MISCREG_DBGBCR6_EL1:
1240 selfDebug->updateDBGBCR(6, val);
1241 break;
1242 case MISCREG_DBGBCR7_EL1:
1243 selfDebug->updateDBGBCR(7, val);
1244 break;
1245 case MISCREG_DBGBCR8_EL1:
1246 selfDebug->updateDBGBCR(8, val);
1247 break;
1248 case MISCREG_DBGBCR9_EL1:
1249 selfDebug->updateDBGBCR(9, val);
1250 break;
1251 case MISCREG_DBGBCR10_EL1:
1252 selfDebug->updateDBGBCR(10, val);
1253 break;
1254 case MISCREG_DBGBCR11_EL1:
1255 selfDebug->updateDBGBCR(11, val);
1256 break;
1257 case MISCREG_DBGBCR12_EL1:
1258 selfDebug->updateDBGBCR(12, val);
1259 break;
1260 case MISCREG_DBGBCR13_EL1:
1261 selfDebug->updateDBGBCR(13, val);
1262 break;
1263 case MISCREG_DBGBCR14_EL1:
1264 selfDebug->updateDBGBCR(14, val);
1265 break;
1266 case MISCREG_DBGBCR15_EL1:
1267 selfDebug->updateDBGBCR(15, val);
1268 break;
1269 case MISCREG_DBGWCR0_EL1:
1270 selfDebug->updateDBGWCR(0, val);
1271 break;
1272 case MISCREG_DBGWCR1_EL1:
1273 selfDebug->updateDBGWCR(1, val);
1274 break;
1275 case MISCREG_DBGWCR2_EL1:
1276 selfDebug->updateDBGWCR(2, val);
1277 break;
1278 case MISCREG_DBGWCR3_EL1:
1279 selfDebug->updateDBGWCR(3, val);
1280 break;
1281 case MISCREG_DBGWCR4_EL1:
1282 selfDebug->updateDBGWCR(4, val);
1283 break;
1284 case MISCREG_DBGWCR5_EL1:
1285 selfDebug->updateDBGWCR(5, val);
1286 break;
1287 case MISCREG_DBGWCR6_EL1:
1288 selfDebug->updateDBGWCR(6, val);
1289 break;
1290 case MISCREG_DBGWCR7_EL1:
1291 selfDebug->updateDBGWCR(7, val);
1292 break;
1293 case MISCREG_DBGWCR8_EL1:
1294 selfDebug->updateDBGWCR(8, val);
1295 break;
1296 case MISCREG_DBGWCR9_EL1:
1297 selfDebug->updateDBGWCR(9, val);
1298 break;
1299 case MISCREG_DBGWCR10_EL1:
1300 selfDebug->updateDBGWCR(10, val);
1301 break;
1302 case MISCREG_DBGWCR11_EL1:
1303 selfDebug->updateDBGWCR(11, val);
1304 break;
1305 case MISCREG_DBGWCR12_EL1:
1306 selfDebug->updateDBGWCR(12, val);
1307 break;
1308 case MISCREG_DBGWCR13_EL1:
1309 selfDebug->updateDBGWCR(13, val);
1310 break;
1311 case MISCREG_DBGWCR14_EL1:
1312 selfDebug->updateDBGWCR(14, val);
1313 break;
1314 case MISCREG_DBGWCR15_EL1:
1315 selfDebug->updateDBGWCR(15, val);
1316 break;
1317 case MISCREG_IFSR:
1318 {
1319 // ARM ARM (ARM DDI 0406C.b) B4.1.96
1320 const uint32_t ifsrMask =
1321 mask(31, 13) | mask(11, 11) | mask(8, 6);
1322 newVal = newVal & ~ifsrMask;
1323 }
1324 break;
1325 case MISCREG_DFSR:
1326 {
1327 // ARM ARM (ARM DDI 0406C.b) B4.1.52
1328 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
1329 newVal = newVal & ~dfsrMask;
1330 }
1331 break;
1332 case MISCREG_AMAIR0:
1333 case MISCREG_AMAIR1:
1334 {
1335 // ARM ARM (ARM DDI 0406C.b) B4.1.5
1336 // Valid only with LPAE
1337 if (!haveLPAE)
1338 return;
1339 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
1340 }
1341 break;
1342 case MISCREG_SCR:
1343 getITBPtr(tc)->invalidateMiscReg();
1344 getDTBPtr(tc)->invalidateMiscReg();
1345 break;
1346 case MISCREG_SCTLR:
1347 {
1348 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
1349 scr = readMiscRegNoEffect(MISCREG_SCR);
1350
1351 MiscRegIndex sctlr_idx;
1352 if (haveSecurity && !highestELIs64 && !scr.ns) {
1353 sctlr_idx = MISCREG_SCTLR_S;
1354 } else {
1355 sctlr_idx = MISCREG_SCTLR_NS;
1356 }
1357
1358 SCTLR sctlr = miscRegs[sctlr_idx];
1359 SCTLR new_sctlr = newVal;
1360 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;
1361 miscRegs[sctlr_idx] = (RegVal)new_sctlr;
1362 getITBPtr(tc)->invalidateMiscReg();
1363 getDTBPtr(tc)->invalidateMiscReg();
1364 }
1365 case MISCREG_MIDR:
1366 case MISCREG_ID_PFR0:
1367 case MISCREG_ID_PFR1:
1368 case MISCREG_ID_DFR0:
1369 case MISCREG_ID_MMFR0:
1370 case MISCREG_ID_MMFR1:
1371 case MISCREG_ID_MMFR2:
1372 case MISCREG_ID_MMFR3:
1373 case MISCREG_ID_ISAR0:
1374 case MISCREG_ID_ISAR1:
1375 case MISCREG_ID_ISAR2:
1376 case MISCREG_ID_ISAR3:
1377 case MISCREG_ID_ISAR4:
1378 case MISCREG_ID_ISAR5:
1379
1380 case MISCREG_MPIDR:
1381 case MISCREG_FPSID:
1382 case MISCREG_TLBTR:
1383 case MISCREG_MVFR0:
1384 case MISCREG_MVFR1:
1385
1386 case MISCREG_ID_AA64AFR0_EL1:
1387 case MISCREG_ID_AA64AFR1_EL1:
1388 case MISCREG_ID_AA64DFR0_EL1:
1389 case MISCREG_ID_AA64DFR1_EL1:
1390 case MISCREG_ID_AA64ISAR0_EL1:
1391 case MISCREG_ID_AA64ISAR1_EL1:
1392 case MISCREG_ID_AA64MMFR0_EL1:
1393 case MISCREG_ID_AA64MMFR1_EL1:
1394 case MISCREG_ID_AA64MMFR2_EL1:
1395 case MISCREG_ID_AA64PFR0_EL1:
1396 case MISCREG_ID_AA64PFR1_EL1:
1397 // ID registers are constants.
1398 return;
1399
1400 // TLB Invalidate All
1401 case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
1402 {
1403 assert32();
1404 scr = readMiscReg(MISCREG_SCR);
1405
1406 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1407 tlbiOp(tc);
1408 return;
1409 }
1410 // TLB Invalidate All, Inner Shareable
1411 case MISCREG_TLBIALLIS:
1412 {
1413 assert32();
1414 scr = readMiscReg(MISCREG_SCR);
1415
1416 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1417 tlbiOp.broadcast(tc);
1418 return;
1419 }
1420 // Instruction TLB Invalidate All
1421 case MISCREG_ITLBIALL:
1422 {
1423 assert32();
1424 scr = readMiscReg(MISCREG_SCR);
1425
1426 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1427 tlbiOp(tc);
1428 return;
1429 }
1430 // Data TLB Invalidate All
1431 case MISCREG_DTLBIALL:
1432 {
1433 assert32();
1434 scr = readMiscReg(MISCREG_SCR);
1435
1436 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1437 tlbiOp(tc);
1438 return;
1439 }
1440 // TLB Invalidate by VA
1441 // mcr tlbimval(is) is invalidating all matching entries
1442 // regardless of the level of lookup, since in gem5 we cache
1443 // in the tlb the last level of lookup only.
1444 case MISCREG_TLBIMVA:
1445 case MISCREG_TLBIMVAL:
1446 {
1447 assert32();
1448 scr = readMiscReg(MISCREG_SCR);
1449
1450 TLBIMVA tlbiOp(EL1,
1451 haveSecurity && !scr.ns,
1452 mbits(newVal, 31, 12),
1453 bits(newVal, 7,0));
1454
1455 tlbiOp(tc);
1456 return;
1457 }
1458 // TLB Invalidate by VA, Inner Shareable
1459 case MISCREG_TLBIMVAIS:
1460 case MISCREG_TLBIMVALIS:
1461 {
1462 assert32();
1463 scr = readMiscReg(MISCREG_SCR);
1464
1465 TLBIMVA tlbiOp(EL1,
1466 haveSecurity && !scr.ns,
1467 mbits(newVal, 31, 12),
1468 bits(newVal, 7,0));
1469
1470 tlbiOp.broadcast(tc);
1471 return;
1472 }
1473 // TLB Invalidate by ASID match
1474 case MISCREG_TLBIASID:
1475 {
1476 assert32();
1477 scr = readMiscReg(MISCREG_SCR);
1478
1479 TLBIASID tlbiOp(EL1,
1480 haveSecurity && !scr.ns,
1481 bits(newVal, 7,0));
1482
1483 tlbiOp(tc);
1484 return;
1485 }
1486 // TLB Invalidate by ASID match, Inner Shareable
1487 case MISCREG_TLBIASIDIS:
1488 {
1489 assert32();
1490 scr = readMiscReg(MISCREG_SCR);
1491
1492 TLBIASID tlbiOp(EL1,
1493 haveSecurity && !scr.ns,
1494 bits(newVal, 7,0));
1495
1496 tlbiOp.broadcast(tc);
1497 return;
1498 }
1499 // mcr tlbimvaal(is) is invalidating all matching entries
1500 // regardless of the level of lookup, since in gem5 we cache
1501 // in the tlb the last level of lookup only.
1502 // TLB Invalidate by VA, All ASID
1503 case MISCREG_TLBIMVAA:
1504 case MISCREG_TLBIMVAAL:
1505 {
1506 assert32();
1507 scr = readMiscReg(MISCREG_SCR);
1508
1509 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1510 mbits(newVal, 31,12));
1511
1512 tlbiOp(tc);
1513 return;
1514 }
1515 // TLB Invalidate by VA, All ASID, Inner Shareable
1516 case MISCREG_TLBIMVAAIS:
1517 case MISCREG_TLBIMVAALIS:
1518 {
1519 assert32();
1520 scr = readMiscReg(MISCREG_SCR);
1521
1522 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1523 mbits(newVal, 31,12));
1524
1525 tlbiOp.broadcast(tc);
1526 return;
1527 }
1528 // mcr tlbimvalh(is) is invalidating all matching entries
1529 // regardless of the level of lookup, since in gem5 we cache
1530 // in the tlb the last level of lookup only.
1531 // TLB Invalidate by VA, Hyp mode
1532 case MISCREG_TLBIMVAH:
1533 case MISCREG_TLBIMVALH:
1534 {
1535 assert32();
1536 scr = readMiscReg(MISCREG_SCR);
1537
1538 TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
1539 mbits(newVal, 31,12));
1540
1541 tlbiOp(tc);
1542 return;
1543 }
1544 // TLB Invalidate by VA, Hyp mode, Inner Shareable
1545 case MISCREG_TLBIMVAHIS:
1546 case MISCREG_TLBIMVALHIS:
1547 {
1548 assert32();
1549 scr = readMiscReg(MISCREG_SCR);
1550
1551 TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
1552 mbits(newVal, 31,12));
1553
1554 tlbiOp.broadcast(tc);
1555 return;
1556 }
1557 // mcr tlbiipas2l(is) is invalidating all matching entries
1558 // regardless of the level of lookup, since in gem5 we cache
1559 // in the tlb the last level of lookup only.
1560 // TLB Invalidate by Intermediate Physical Address, Stage 2
1561 case MISCREG_TLBIIPAS2:
1562 case MISCREG_TLBIIPAS2L:
1563 {
1564 assert32();
1565 scr = readMiscReg(MISCREG_SCR);
1566
1567 TLBIIPA tlbiOp(EL1,
1568 haveSecurity && !scr.ns,
1569 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1570
1571 tlbiOp(tc);
1572 return;
1573 }
1574 // TLB Invalidate by Intermediate Physical Address, Stage 2,
1575 // Inner Shareable
1576 case MISCREG_TLBIIPAS2IS:
1577 case MISCREG_TLBIIPAS2LIS:
1578 {
1579 assert32();
1580 scr = readMiscReg(MISCREG_SCR);
1581
1582 TLBIIPA tlbiOp(EL1,
1583 haveSecurity && !scr.ns,
1584 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1585
1586 tlbiOp.broadcast(tc);
1587 return;
1588 }
1589 // Instruction TLB Invalidate by VA
1590 case MISCREG_ITLBIMVA:
1591 {
1592 assert32();
1593 scr = readMiscReg(MISCREG_SCR);
1594
1595 ITLBIMVA tlbiOp(EL1,
1596 haveSecurity && !scr.ns,
1597 mbits(newVal, 31, 12),
1598 bits(newVal, 7,0));
1599
1600 tlbiOp(tc);
1601 return;
1602 }
1603 // Data TLB Invalidate by VA
1604 case MISCREG_DTLBIMVA:
1605 {
1606 assert32();
1607 scr = readMiscReg(MISCREG_SCR);
1608
1609 DTLBIMVA tlbiOp(EL1,
1610 haveSecurity && !scr.ns,
1611 mbits(newVal, 31, 12),
1612 bits(newVal, 7,0));
1613
1614 tlbiOp(tc);
1615 return;
1616 }
1617 // Instruction TLB Invalidate by ASID match
1618 case MISCREG_ITLBIASID:
1619 {
1620 assert32();
1621 scr = readMiscReg(MISCREG_SCR);
1622
1623 ITLBIASID tlbiOp(EL1,
1624 haveSecurity && !scr.ns,
1625 bits(newVal, 7,0));
1626
1627 tlbiOp(tc);
1628 return;
1629 }
1630 // Data TLB Invalidate by ASID match
1631 case MISCREG_DTLBIASID:
1632 {
1633 assert32();
1634 scr = readMiscReg(MISCREG_SCR);
1635
1636 DTLBIASID tlbiOp(EL1,
1637 haveSecurity && !scr.ns,
1638 bits(newVal, 7,0));
1639
1640 tlbiOp(tc);
1641 return;
1642 }
1643 // TLB Invalidate All, Non-Secure Non-Hyp
1644 case MISCREG_TLBIALLNSNH:
1645 {
1646 assert32();
1647
1648 TLBIALLN tlbiOp(EL1);
1649 tlbiOp(tc);
1650 return;
1651 }
1652 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
1653 case MISCREG_TLBIALLNSNHIS:
1654 {
1655 assert32();
1656
1657 TLBIALLN tlbiOp(EL1);
1658 tlbiOp.broadcast(tc);
1659 return;
1660 }
1661 // TLB Invalidate All, Hyp mode
1662 case MISCREG_TLBIALLH:
1663 {
1664 assert32();
1665
1666 TLBIALLN tlbiOp(EL2);
1667 tlbiOp(tc);
1668 return;
1669 }
1670 // TLB Invalidate All, Hyp mode, Inner Shareable
1671 case MISCREG_TLBIALLHIS:
1672 {
1673 assert32();
1674
1675 TLBIALLN tlbiOp(EL2);
1676 tlbiOp.broadcast(tc);
1677 return;
1678 }
1679 // AArch64 TLB Invalidate All, EL3
1680 case MISCREG_TLBI_ALLE3:
1681 {
1682 assert64();
1683
1684 TLBIALL tlbiOp(EL3, true);
1685 tlbiOp(tc);
1686 return;
1687 }
1688 // AArch64 TLB Invalidate All, EL3, Inner Shareable
1689 case MISCREG_TLBI_ALLE3IS:
1690 {
1691 assert64();
1692
1693 TLBIALL tlbiOp(EL3, true);
1694 tlbiOp.broadcast(tc);
1695 return;
1696 }
1697 // AArch64 TLB Invalidate All, EL2, Inner Shareable
1698 case MISCREG_TLBI_ALLE2:
1699 case MISCREG_TLBI_ALLE2IS:
1700 {
1701 assert64();
1702 scr = readMiscReg(MISCREG_SCR);
1703
1704 TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns);
1705 tlbiOp(tc);
1706 return;
1707 }
1708 // AArch64 TLB Invalidate All, EL1
1709 case MISCREG_TLBI_ALLE1:
1710 case MISCREG_TLBI_VMALLE1:
1711 case MISCREG_TLBI_VMALLS12E1:
1712 // @todo: handle VMID and stage 2 to enable Virtualization
1713 {
1714 assert64();
1715 scr = readMiscReg(MISCREG_SCR);
1716
1717 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1718 tlbiOp(tc);
1719 return;
1720 }
1721 // AArch64 TLB Invalidate All, EL1, Inner Shareable
1722 case MISCREG_TLBI_ALLE1IS:
1723 case MISCREG_TLBI_VMALLE1IS:
1724 case MISCREG_TLBI_VMALLS12E1IS:
1725 // @todo: handle VMID and stage 2 to enable Virtualization
1726 {
1727 assert64();
1728 scr = readMiscReg(MISCREG_SCR);
1729
1730 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1731 tlbiOp.broadcast(tc);
1732 return;
1733 }
1734 // VAEx(IS) and VALEx(IS) are the same because TLBs
1735 // only store entries
1736 // from the last level of translation table walks
1737 // @todo: handle VMID to enable Virtualization
1738 // AArch64 TLB Invalidate by VA, EL3
1739 case MISCREG_TLBI_VAE3_Xt:
1740 case MISCREG_TLBI_VALE3_Xt:
1741 {
1742 assert64();
1743
1744 TLBIMVA tlbiOp(EL3, true,
1745 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1746 0xbeef);
1747 tlbiOp(tc);
1748 return;
1749 }
1750 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable
1751 case MISCREG_TLBI_VAE3IS_Xt:
1752 case MISCREG_TLBI_VALE3IS_Xt:
1753 {
1754 assert64();
1755
1756 TLBIMVA tlbiOp(EL3, true,
1757 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1758 0xbeef);
1759
1760 tlbiOp.broadcast(tc);
1761 return;
1762 }
1763 // AArch64 TLB Invalidate by VA, EL2
1764 case MISCREG_TLBI_VAE2_Xt:
1765 case MISCREG_TLBI_VALE2_Xt:
1766 {
1767 assert64();
1768 scr = readMiscReg(MISCREG_SCR);
1769
1770 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1771 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1772 0xbeef);
1773 tlbiOp(tc);
1774 return;
1775 }
1776 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable
1777 case MISCREG_TLBI_VAE2IS_Xt:
1778 case MISCREG_TLBI_VALE2IS_Xt:
1779 {
1780 assert64();
1781 scr = readMiscReg(MISCREG_SCR);
1782
1783 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1784 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1785 0xbeef);
1786
1787 tlbiOp.broadcast(tc);
1788 return;
1789 }
1790 // AArch64 TLB Invalidate by VA, EL1
1791 case MISCREG_TLBI_VAE1_Xt:
1792 case MISCREG_TLBI_VALE1_Xt:
1793 {
1794 assert64();
1795 scr = readMiscReg(MISCREG_SCR);
1796 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1797 bits(newVal, 55, 48);
1798
1799 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns,
1800 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1801 asid);
1802
1803 tlbiOp(tc);
1804 return;
1805 }
1806 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable
1807 case MISCREG_TLBI_VAE1IS_Xt:
1808 case MISCREG_TLBI_VALE1IS_Xt:
1809 {
1810 assert64();
1811 scr = readMiscReg(MISCREG_SCR);
1812 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1813 bits(newVal, 55, 48);
1814
1815 TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns,
1816 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1817 asid);
1818
1819 tlbiOp.broadcast(tc);
1820 return;
1821 }
1822 // AArch64 TLB Invalidate by ASID, EL1
1823 // @todo: handle VMID to enable Virtualization
1824 case MISCREG_TLBI_ASIDE1_Xt:
1825 {
1826 assert64();
1827 scr = readMiscReg(MISCREG_SCR);
1828 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1829 bits(newVal, 55, 48);
1830
1831 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid);
1832 tlbiOp(tc);
1833 return;
1834 }
1835 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable
1836 case MISCREG_TLBI_ASIDE1IS_Xt:
1837 {
1838 assert64();
1839 scr = readMiscReg(MISCREG_SCR);
1840 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1841 bits(newVal, 55, 48);
1842
1843 TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid);
1844 tlbiOp.broadcast(tc);
1845 return;
1846 }
1847 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1848 // entries from the last level of translation table walks
1849 // AArch64 TLB Invalidate by VA, All ASID, EL1
1850 case MISCREG_TLBI_VAAE1_Xt:
1851 case MISCREG_TLBI_VAALE1_Xt:
1852 {
1853 assert64();
1854 scr = readMiscReg(MISCREG_SCR);
1855
1856 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1857 static_cast<Addr>(bits(newVal, 43, 0)) << 12);
1858
1859 tlbiOp(tc);
1860 return;
1861 }
1862 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable
1863 case MISCREG_TLBI_VAAE1IS_Xt:
1864 case MISCREG_TLBI_VAALE1IS_Xt:
1865 {
1866 assert64();
1867 scr = readMiscReg(MISCREG_SCR);
1868
1869 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1870 static_cast<Addr>(bits(newVal, 43, 0)) << 12);
1871
1872 tlbiOp.broadcast(tc);
1873 return;
1874 }
1875 // AArch64 TLB Invalidate by Intermediate Physical Address,
1876 // Stage 2, EL1
1877 case MISCREG_TLBI_IPAS2E1_Xt:
1878 case MISCREG_TLBI_IPAS2LE1_Xt:
1879 {
1880 assert64();
1881 scr = readMiscReg(MISCREG_SCR);
1882
1883 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
1884 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1885
1886 tlbiOp(tc);
1887 return;
1888 }
1889 // AArch64 TLB Invalidate by Intermediate Physical Address,
1890 // Stage 2, EL1, Inner Shareable
1891 case MISCREG_TLBI_IPAS2E1IS_Xt:
1892 case MISCREG_TLBI_IPAS2LE1IS_Xt:
1893 {
1894 assert64();
1895 scr = readMiscReg(MISCREG_SCR);
1896
1897 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
1898 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1899
1900 tlbiOp.broadcast(tc);
1901 return;
1902 }
1903 case MISCREG_ACTLR:
1904 warn("Not doing anything for write of miscreg ACTLR\n");
1905 break;
1906
1907 case MISCREG_PMXEVTYPER_PMCCFILTR:
1908 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
1909 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
1910 case MISCREG_PMCR ... MISCREG_PMOVSSET:
1911 pmu->setMiscReg(misc_reg, newVal);
1912 break;
1913
1914
1915 case MISCREG_HSTR: // TJDBX, now redifined to be RES0
1916 {
1917 HSTR hstrMask = 0;
1918 hstrMask.tjdbx = 1;
1919 newVal &= ~((uint32_t) hstrMask);
1920 break;
1921 }
1922 case MISCREG_HCPTR:
1923 {
1924 // If a CP bit in NSACR is 0 then the corresponding bit in
1925 // HCPTR is RAO/WI. Same applies to NSASEDIS
1926 secure_lookup = haveSecurity &&
1927 inSecureState(readMiscRegNoEffect(MISCREG_SCR),
1928 readMiscRegNoEffect(MISCREG_CPSR));
1929 if (!secure_lookup) {
1930 RegVal oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
1931 RegVal mask =
1932 (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
1933 newVal = (newVal & ~mask) | (oldValue & mask);
1934 }
1935 break;
1936 }
1937 case MISCREG_HDFAR: // alias for secure DFAR
1938 misc_reg = MISCREG_DFAR_S;
1939 break;
1940 case MISCREG_HIFAR: // alias for secure IFAR
1941 misc_reg = MISCREG_IFAR_S;
1942 break;
1943 case MISCREG_ATS1CPR:
1944 case MISCREG_ATS1CPW:
1945 case MISCREG_ATS1CUR:
1946 case MISCREG_ATS1CUW:
1947 case MISCREG_ATS12NSOPR:
1948 case MISCREG_ATS12NSOPW:
1949 case MISCREG_ATS12NSOUR:
1950 case MISCREG_ATS12NSOUW:
1951 case MISCREG_ATS1HR:
1952 case MISCREG_ATS1HW:
1953 {
1954 Request::Flags flags = 0;
1955 BaseTLB::Mode mode = BaseTLB::Read;
1956 TLB::ArmTranslationType tranType = TLB::NormalTran;
1957 Fault fault;
1958 switch(misc_reg) {
1959 case MISCREG_ATS1CPR:
1960 tranType = TLB::S1CTran;
1961 mode = BaseTLB::Read;
1962 break;
1963 case MISCREG_ATS1CPW:
1964 tranType = TLB::S1CTran;
1965 mode = BaseTLB::Write;
1966 break;
1967 case MISCREG_ATS1CUR:
1968 flags = TLB::UserMode;
1969 tranType = TLB::S1CTran;
1970 mode = BaseTLB::Read;
1971 break;
1972 case MISCREG_ATS1CUW:
1973 flags = TLB::UserMode;
1974 tranType = TLB::S1CTran;
1975 mode = BaseTLB::Write;
1976 break;
1977 case MISCREG_ATS12NSOPR:
1978 if (!haveSecurity)
1979 panic("Security Extensions required for ATS12NSOPR");
1980 tranType = TLB::S1S2NsTran;
1981 mode = BaseTLB::Read;
1982 break;
1983 case MISCREG_ATS12NSOPW:
1984 if (!haveSecurity)
1985 panic("Security Extensions required for ATS12NSOPW");
1986 tranType = TLB::S1S2NsTran;
1987 mode = BaseTLB::Write;
1988 break;
1989 case MISCREG_ATS12NSOUR:
1990 if (!haveSecurity)
1991 panic("Security Extensions required for ATS12NSOUR");
1992 flags = TLB::UserMode;
1993 tranType = TLB::S1S2NsTran;
1994 mode = BaseTLB::Read;
1995 break;
1996 case MISCREG_ATS12NSOUW:
1997 if (!haveSecurity)
1998 panic("Security Extensions required for ATS12NSOUW");
1999 flags = TLB::UserMode;
2000 tranType = TLB::S1S2NsTran;
2001 mode = BaseTLB::Write;
2002 break;
2003 case MISCREG_ATS1HR: // only really useful from secure mode.
2004 tranType = TLB::HypMode;
2005 mode = BaseTLB::Read;
2006 break;
2007 case MISCREG_ATS1HW:
2008 tranType = TLB::HypMode;
2009 mode = BaseTLB::Write;
2010 break;
2011 }
2012 // If we're in timing mode then doing the translation in
2013 // functional mode then we're slightly distorting performance
2014 // results obtained from simulations. The translation should be
2015 // done in the same mode the core is running in. NOTE: This
2016 // can't be an atomic translation because that causes problems
2017 // with unexpected atomic snoop requests.
2018 warn("Translating via %s in functional mode! Fix Me!\n",
2019 miscRegName[misc_reg]);
2020
2021 auto req = std::make_shared<Request>(
2022 val, 0, flags, Request::funcMasterId,
2023 tc->pcState().pc(), tc->contextId());
2024
2025 fault = getDTBPtr(tc)->translateFunctional(
2026 req, tc, mode, tranType);
2027
2028 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
2029 HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
2030
2031 RegVal newVal;
2032 if (fault == NoFault) {
2033 Addr paddr = req->getPaddr();
2034 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
2035 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
2036 newVal = (paddr & mask(39, 12)) |
2037 (getDTBPtr(tc)->getAttr());
2038 } else {
2039 newVal = (paddr & 0xfffff000) |
2040 (getDTBPtr(tc)->getAttr());
2041 }
2042 DPRINTF(MiscRegs,
2043 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
2044 val, newVal);
2045 } else {
2046 ArmFault *armFault = static_cast<ArmFault *>(fault.get());
2047 armFault->update(tc);
2048 // Set fault bit and FSR
2049 FSR fsr = armFault->getFsr(tc);
2050
2051 newVal = ((fsr >> 9) & 1) << 11;
2052 if (newVal) {
2053 // LPAE - rearange fault status
2054 newVal |= ((fsr >> 0) & 0x3f) << 1;
2055 } else {
2056 // VMSA - rearange fault status
2057 newVal |= ((fsr >> 0) & 0xf) << 1;
2058 newVal |= ((fsr >> 10) & 0x1) << 5;
2059 newVal |= ((fsr >> 12) & 0x1) << 6;
2060 }
2061 newVal |= 0x1; // F bit
2062 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
2063 newVal |= armFault->isStage2() ? 0x200 : 0;
2064 DPRINTF(MiscRegs,
2065 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
2066 val, fsr, newVal);
2067 }
2068 setMiscRegNoEffect(MISCREG_PAR, newVal);
2069 return;
2070 }
2071 case MISCREG_TTBCR:
2072 {
2073 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
2074 const uint32_t ones = (uint32_t)(-1);
2075 TTBCR ttbcrMask = 0;
2076 TTBCR ttbcrNew = newVal;
2077
2078 // ARM DDI 0406C.b, ARMv7-32
2079 ttbcrMask.n = ones; // T0SZ
2080 if (haveSecurity) {
2081 ttbcrMask.pd0 = ones;
2082 ttbcrMask.pd1 = ones;
2083 }
2084 ttbcrMask.epd0 = ones;
2085 ttbcrMask.irgn0 = ones;
2086 ttbcrMask.orgn0 = ones;
2087 ttbcrMask.sh0 = ones;
2088 ttbcrMask.ps = ones; // T1SZ
2089 ttbcrMask.a1 = ones;
2090 ttbcrMask.epd1 = ones;
2091 ttbcrMask.irgn1 = ones;
2092 ttbcrMask.orgn1 = ones;
2093 ttbcrMask.sh1 = ones;
2094 if (haveLPAE)
2095 ttbcrMask.eae = ones;
2096
2097 if (haveLPAE && ttbcrNew.eae) {
2098 newVal = newVal & ttbcrMask;
2099 } else {
2100 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
2101 }
2102 // Invalidate TLB MiscReg
2103 getITBPtr(tc)->invalidateMiscReg();
2104 getDTBPtr(tc)->invalidateMiscReg();
2105 break;
2106 }
2107 case MISCREG_TTBR0:
2108 case MISCREG_TTBR1:
2109 {
2110 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
2111 if (haveLPAE) {
2112 if (ttbcr.eae) {
2113 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
2114 // ARMv8 AArch32 bit 63-56 only
2115 uint64_t ttbrMask = mask(63,56) | mask(47,40);
2116 newVal = (newVal & (~ttbrMask));
2117 }
2118 }
2119 // Invalidate TLB MiscReg
2120 getITBPtr(tc)->invalidateMiscReg();
2121 getDTBPtr(tc)->invalidateMiscReg();
2122 break;
2123 }
2124 case MISCREG_SCTLR_EL1:
2125 case MISCREG_CONTEXTIDR:
2126 case MISCREG_PRRR:
2127 case MISCREG_NMRR:
2128 case MISCREG_MAIR0:
2129 case MISCREG_MAIR1:
2130 case MISCREG_DACR:
2131 case MISCREG_VTTBR:
2132 case MISCREG_SCR_EL3:
2133 case MISCREG_TCR_EL1:
2134 case MISCREG_TCR_EL2:
2135 case MISCREG_TCR_EL3:
2136 case MISCREG_SCTLR_EL2:
2137 case MISCREG_SCTLR_EL3:
2138 case MISCREG_HSCTLR:
2139 case MISCREG_TTBR0_EL1:
2140 case MISCREG_TTBR1_EL1:
2141 case MISCREG_TTBR0_EL2:
2142 case MISCREG_TTBR1_EL2:
2143 case MISCREG_TTBR0_EL3:
2144 getITBPtr(tc)->invalidateMiscReg();
2145 getDTBPtr(tc)->invalidateMiscReg();
2146 break;
2147 case MISCREG_HCR_EL2:
2148 {
2149 const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
2150 selfDebug->setenableTDETGE((HCR)val, mdcr);
2151 getITBPtr(tc)->invalidateMiscReg();
2152 getDTBPtr(tc)->invalidateMiscReg();
2153 }
2154 break;
2155 case MISCREG_NZCV:
2156 {
2157 CPSR cpsr = val;
2158
2159 tc->setCCReg(CCREG_NZ, cpsr.nz);
2160 tc->setCCReg(CCREG_C, cpsr.c);
2161 tc->setCCReg(CCREG_V, cpsr.v);
2162 }
2163 break;
2164 case MISCREG_DAIF:
2165 {
2166 CPSR cpsr = miscRegs[MISCREG_CPSR];
2167 cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
2168 newVal = cpsr;
2169 misc_reg = MISCREG_CPSR;
2170 }
2171 break;
2172 case MISCREG_SP_EL0:
2173 tc->setIntReg(INTREG_SP0, newVal);
2174 break;
2175 case MISCREG_SP_EL1:
2176 tc->setIntReg(INTREG_SP1, newVal);
2177 break;
2178 case MISCREG_SP_EL2:
2179 tc->setIntReg(INTREG_SP2, newVal);
2180 break;
2181 case MISCREG_SPSEL:
2182 {
2183 CPSR cpsr = miscRegs[MISCREG_CPSR];
2184 cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
2185 newVal = cpsr;
2186 misc_reg = MISCREG_CPSR;
2187 }
2188 break;
2189 case MISCREG_CURRENTEL:
2190 {
2191 CPSR cpsr = miscRegs[MISCREG_CPSR];
2192 cpsr.el = (uint8_t) ((CPSR) newVal).el;
2193 newVal = cpsr;
2194 misc_reg = MISCREG_CPSR;
2195 }
2196 break;
2197 case MISCREG_PAN:
2198 {
2199 // PAN is affecting data accesses
2200 getDTBPtr(tc)->invalidateMiscReg();
2201
2202 CPSR cpsr = miscRegs[MISCREG_CPSR];
2203 cpsr.pan = (uint8_t) ((CPSR) newVal).pan;
2204 newVal = cpsr;
2205 misc_reg = MISCREG_CPSR;
2206 }
2207 break;
2208 case MISCREG_AT_S1E1R_Xt:
2209 case MISCREG_AT_S1E1W_Xt:
2210 case MISCREG_AT_S1E0R_Xt:
2211 case MISCREG_AT_S1E0W_Xt:
2212 case MISCREG_AT_S1E2R_Xt:
2213 case MISCREG_AT_S1E2W_Xt:
2214 case MISCREG_AT_S12E1R_Xt:
2215 case MISCREG_AT_S12E1W_Xt:
2216 case MISCREG_AT_S12E0R_Xt:
2217 case MISCREG_AT_S12E0W_Xt:
2218 case MISCREG_AT_S1E3R_Xt:
2219 case MISCREG_AT_S1E3W_Xt:
2220 {
2221 RequestPtr req = std::make_shared<Request>();
2222 Request::Flags flags = 0;
2223 BaseTLB::Mode mode = BaseTLB::Read;
2224 TLB::ArmTranslationType tranType = TLB::NormalTran;
2225 Fault fault;
2226 switch(misc_reg) {
2227 case MISCREG_AT_S1E1R_Xt:
2228 tranType = TLB::S1E1Tran;
2229 mode = BaseTLB::Read;
2230 break;
2231 case MISCREG_AT_S1E1W_Xt:
2232 tranType = TLB::S1E1Tran;
2233 mode = BaseTLB::Write;
2234 break;
2235 case MISCREG_AT_S1E0R_Xt:
2236 flags = TLB::UserMode;
2237 tranType = TLB::S1E0Tran;
2238 mode = BaseTLB::Read;
2239 break;
2240 case MISCREG_AT_S1E0W_Xt:
2241 flags = TLB::UserMode;
2242 tranType = TLB::S1E0Tran;
2243 mode = BaseTLB::Write;
2244 break;
2245 case MISCREG_AT_S1E2R_Xt:
2246 tranType = TLB::S1E2Tran;
2247 mode = BaseTLB::Read;
2248 break;
2249 case MISCREG_AT_S1E2W_Xt:
2250 tranType = TLB::S1E2Tran;
2251 mode = BaseTLB::Write;
2252 break;
2253 case MISCREG_AT_S12E0R_Xt:
2254 flags = TLB::UserMode;
2255 tranType = TLB::S12E0Tran;
2256 mode = BaseTLB::Read;
2257 break;
2258 case MISCREG_AT_S12E0W_Xt:
2259 flags = TLB::UserMode;
2260 tranType = TLB::S12E0Tran;
2261 mode = BaseTLB::Write;
2262 break;
2263 case MISCREG_AT_S12E1R_Xt:
2264 tranType = TLB::S12E1Tran;
2265 mode = BaseTLB::Read;
2266 break;
2267 case MISCREG_AT_S12E1W_Xt:
2268 tranType = TLB::S12E1Tran;
2269 mode = BaseTLB::Write;
2270 break;
2271 case MISCREG_AT_S1E3R_Xt:
2272 tranType = TLB::S1E3Tran;
2273 mode = BaseTLB::Read;
2274 break;
2275 case MISCREG_AT_S1E3W_Xt:
2276 tranType = TLB::S1E3Tran;
2277 mode = BaseTLB::Write;
2278 break;
2279 }
2280 // If we're in timing mode then doing the translation in
2281 // functional mode then we're slightly distorting performance
2282 // results obtained from simulations. The translation should be
2283 // done in the same mode the core is running in. NOTE: This
2284 // can't be an atomic translation because that causes problems
2285 // with unexpected atomic snoop requests.
2286 warn("Translating via %s in functional mode! Fix Me!\n",
2287 miscRegName[misc_reg]);
2288
2289 req->setVirt(val, 0, flags, Request::funcMasterId,
2290 tc->pcState().pc());
2291 req->setContext(tc->contextId());
2292 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode,
2293 tranType);
2294
2295 RegVal newVal;
2296 if (fault == NoFault) {
2297 Addr paddr = req->getPaddr();
2298 uint64_t attr = getDTBPtr(tc)->getAttr();
2299 uint64_t attr1 = attr >> 56;
2300 if (!attr1 || attr1 ==0x44) {
2301 attr |= 0x100;
2302 attr &= ~ uint64_t(0x80);
2303 }
2304 newVal = (paddr & mask(47, 12)) | attr;
2305 DPRINTF(MiscRegs,
2306 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
2307 val, newVal);
2308 } else {
2309 ArmFault *armFault = static_cast<ArmFault *>(fault.get());
2310 armFault->update(tc);
2311 // Set fault bit and FSR
2312 FSR fsr = armFault->getFsr(tc);
2313
2314 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
2315 if (cpsr.width) { // AArch32
2316 newVal = ((fsr >> 9) & 1) << 11;
2317 // rearrange fault status
2318 newVal |= ((fsr >> 0) & 0x3f) << 1;
2319 newVal |= 0x1; // F bit
2320 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
2321 newVal |= armFault->isStage2() ? 0x200 : 0;
2322 } else { // AArch64
2323 newVal = 1; // F bit
2324 newVal |= fsr << 1; // FST
2325 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
2326 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
2327 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
2328 newVal |= 1 << 11; // RES1
2329 }
2330 DPRINTF(MiscRegs,
2331 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
2332 val, fsr, newVal);
2333 }
2334 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
2335 return;
2336 }
2337 case MISCREG_SPSR_EL3:
2338 case MISCREG_SPSR_EL2:
2339 case MISCREG_SPSR_EL1:
2340 {
2341 RegVal spsr_mask = havePAN ?
2342 ~(0x2 << 22) : ~(0x3 << 22);
2343
2344 newVal = val & spsr_mask;
2345 break;
2346 }
2347 case MISCREG_L2CTLR:
2348 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
2349 miscRegName[misc_reg], uint32_t(val));
2350 break;
2351
2352 // Generic Timer registers
2353 case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
2354 case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
2355 getGenericTimer().setMiscReg(misc_reg, newVal);
2356 break;
2357 case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15:
2358 case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
2359 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
2360 getGICv3CPUInterface().setMiscReg(misc_reg, newVal);
2361 return;
2362 case MISCREG_ZCR_EL3:
2363 case MISCREG_ZCR_EL2:
2364 case MISCREG_ZCR_EL1:
2365 tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits() >> 7) - 1);
2366 break;
2367 }
2368 }
2369 setMiscRegNoEffect(misc_reg, newVal);
2370 }
2371
2372 BaseISADevice &
2373 ISA::getGenericTimer()
2374 {
2375 // We only need to create an ISA interface the first time we try
2376 // to access the timer.
2377 if (timer)
2378 return *timer.get();
2379
2380 assert(system);
2381 GenericTimer *generic_timer(system->getGenericTimer());
2382 if (!generic_timer) {
2383 panic("Trying to get a generic timer from a system that hasn't "
2384 "been configured to use a generic timer.\n");
2385 }
2386
2387 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
2388 timer->setThreadContext(tc);
2389
2390 return *timer.get();
2391 }
2392
2393 BaseISADevice &
2394 ISA::getGICv3CPUInterface()
2395 {
2396 panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!");
2397 return *gicv3CpuInterface.get();
2398 }
2399
2400 unsigned
2401 ISA::getCurSveVecLenInBits() const
2402 {
2403 if (!FullSystem) {
2404 return sveVL * 128;
2405 }
2406
2407 panic_if(!tc,
2408 "A ThreadContext is needed to determine the SVE vector length "
2409 "in full-system mode");
2410
2411 CPSR cpsr = miscRegs[MISCREG_CPSR];
2412 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
2413
2414 unsigned len = 0;
2415
2416 if (el == EL1 || (el == EL0 && !ELIsInHost(tc, el))) {
2417 len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL1]).len;
2418 }
2419
2420 if (el == EL2 || (el == EL0 && ELIsInHost(tc, el))) {
2421 len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len;
2422 } else if (haveVirtualization && !inSecureState(tc) &&
2423 (el == EL0 || el == EL1)) {
2424 len = std::min(
2425 len,
2426 static_cast<unsigned>(
2427 static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len));
2428 }
2429
2430 if (el == EL3) {
2431 len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len;
2432 } else if (haveSecurity) {
2433 len = std::min(
2434 len,
2435 static_cast<unsigned>(
2436 static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len));
2437 }
2438
2439 len = std::min(len, sveVL - 1);
2440
2441 return (len + 1) * 128;
2442 }
2443
2444 void
2445 ISA::zeroSveVecRegUpperPart(VecRegContainer &vc, unsigned eCount)
2446 {
2447 auto vv = vc.as<uint64_t>();
2448 for (int i = 2; i < eCount; ++i) {
2449 vv[i] = 0;
2450 }
2451 }
2452
2453 ISA::MiscRegLUTEntryInitializer::chain
2454 ISA::MiscRegLUTEntryInitializer::highest(ArmSystem *const sys) const
2455 {
2456 switch (FullSystem ? sys->highestEL() : EL1) {
2457 case EL0:
2458 case EL1: priv(); break;
2459 case EL2: hyp(); break;
2460 case EL3: mon(); break;
2461 }
2462 return *this;
2463 }
2464
2465 } // namespace ArmISA
2466
2467 ArmISA::ISA *
2468 ArmISAParams::create()
2469 {
2470 return new ArmISA::ISA(this);
2471 }