2 * Copyright (c) 2010-2016 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
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17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
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23 * this software without specific prior written permission.
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 #include "arch/arm/isa.hh"
42 #include "arch/arm/pmu.hh"
43 #include "arch/arm/system.hh"
44 #include "arch/arm/tlb.hh"
45 #include "cpu/base.hh"
46 #include "cpu/checker/cpu.hh"
47 #include "debug/Arm.hh"
48 #include "debug/MiscRegs.hh"
49 #include "dev/arm/generic_timer.hh"
50 #include "params/ArmISA.hh"
51 #include "sim/faults.hh"
52 #include "sim/stat_control.hh"
53 #include "sim/system.hh"
61 _decoderFlavour(p
->decoderFlavour
),
62 _vecRegRenameMode(p
->vecRegRenameMode
),
65 miscRegs
[MISCREG_SCTLR_RST
] = 0;
67 // Hook up a dummy device if we haven't been configured with a
68 // real PMU. By using a dummy device, we don't need to check that
69 // the PMU exist every time we try to access a PMU register.
73 // Give all ISA devices a pointer to this ISA
76 system
= dynamic_cast<ArmSystem
*>(p
->system
);
78 // Cache system-level properties
79 if (FullSystem
&& system
) {
80 highestELIs64
= system
->highestELIs64();
81 haveSecurity
= system
->haveSecurity();
82 haveLPAE
= system
->haveLPAE();
83 haveVirtualization
= system
->haveVirtualization();
84 haveLargeAsid64
= system
->haveLargeAsid64();
85 physAddrRange64
= system
->physAddrRange64();
87 highestELIs64
= true; // ArmSystem::highestELIs64 does the same
88 haveSecurity
= haveLPAE
= haveVirtualization
= false;
89 haveLargeAsid64
= false;
90 physAddrRange64
= 32; // dummy value
93 initializeMiscRegMetadata();
94 preUnflattenMiscReg();
99 std::vector
<struct ISA::MiscRegLUTEntry
> ISA::lookUpMiscReg(NUM_MISCREGS
);
104 return dynamic_cast<const Params
*>(_params
);
110 const Params
*p(params());
112 SCTLR sctlr_rst
= miscRegs
[MISCREG_SCTLR_RST
];
113 memset(miscRegs
, 0, sizeof(miscRegs
));
115 // Initialize configurable default values
116 miscRegs
[MISCREG_MIDR
] = p
->midr
;
117 miscRegs
[MISCREG_MIDR_EL1
] = p
->midr
;
118 miscRegs
[MISCREG_VPIDR
] = p
->midr
;
120 if (FullSystem
&& system
->highestELIs64()) {
121 // Initialize AArch64 state
126 // Initialize AArch32 state...
129 cpsr
.mode
= MODE_USER
;
130 miscRegs
[MISCREG_CPSR
] = cpsr
;
134 sctlr
.te
= (bool) sctlr_rst
.te
;
135 sctlr
.nmfi
= (bool) sctlr_rst
.nmfi
;
136 sctlr
.v
= (bool) sctlr_rst
.v
;
141 sctlr
.rao4
= 0xf; // SCTLR[6:3]
144 miscRegs
[MISCREG_SCTLR_NS
] = sctlr
;
145 miscRegs
[MISCREG_SCTLR_RST
] = sctlr_rst
;
146 miscRegs
[MISCREG_HCPTR
] = 0;
148 // Start with an event in the mailbox
149 miscRegs
[MISCREG_SEV_MAILBOX
] = 1;
151 // Separate Instruction and Data TLBs
152 miscRegs
[MISCREG_TLBTR
] = 1;
155 mvfr0
.advSimdRegisters
= 2;
156 mvfr0
.singlePrecision
= 2;
157 mvfr0
.doublePrecision
= 2;
158 mvfr0
.vfpExceptionTrapping
= 0;
160 mvfr0
.squareRoot
= 1;
161 mvfr0
.shortVectors
= 1;
162 mvfr0
.roundingModes
= 1;
163 miscRegs
[MISCREG_MVFR0
] = mvfr0
;
166 mvfr1
.flushToZero
= 1;
167 mvfr1
.defaultNaN
= 1;
168 mvfr1
.advSimdLoadStore
= 1;
169 mvfr1
.advSimdInteger
= 1;
170 mvfr1
.advSimdSinglePrecision
= 1;
171 mvfr1
.advSimdHalfPrecision
= 1;
172 mvfr1
.vfpHalfPrecision
= 1;
173 miscRegs
[MISCREG_MVFR1
] = mvfr1
;
175 // Reset values of PRRR and NMRR are implementation dependent
177 // @todo: PRRR and NMRR in secure state?
178 miscRegs
[MISCREG_PRRR_NS
] =
191 miscRegs
[MISCREG_NMRR_NS
] =
208 miscRegs
[MISCREG_CPACR
] = 0;
210 miscRegs
[MISCREG_ID_MMFR0
] = p
->id_mmfr0
;
211 miscRegs
[MISCREG_ID_MMFR1
] = p
->id_mmfr1
;
212 miscRegs
[MISCREG_ID_MMFR2
] = p
->id_mmfr2
;
213 miscRegs
[MISCREG_ID_MMFR3
] = p
->id_mmfr3
;
215 miscRegs
[MISCREG_ID_ISAR0
] = p
->id_isar0
;
216 miscRegs
[MISCREG_ID_ISAR1
] = p
->id_isar1
;
217 miscRegs
[MISCREG_ID_ISAR2
] = p
->id_isar2
;
218 miscRegs
[MISCREG_ID_ISAR3
] = p
->id_isar3
;
219 miscRegs
[MISCREG_ID_ISAR4
] = p
->id_isar4
;
220 miscRegs
[MISCREG_ID_ISAR5
] = p
->id_isar5
;
222 miscRegs
[MISCREG_FPSID
] = p
->fpsid
;
225 TTBCR ttbcr
= miscRegs
[MISCREG_TTBCR_NS
];
227 miscRegs
[MISCREG_TTBCR_NS
] = ttbcr
;
228 // Enforce consistency with system-level settings
229 miscRegs
[MISCREG_ID_MMFR0
] = (miscRegs
[MISCREG_ID_MMFR0
] & ~0xf) | 0x5;
233 miscRegs
[MISCREG_SCTLR_S
] = sctlr
;
234 miscRegs
[MISCREG_SCR
] = 0;
235 miscRegs
[MISCREG_VBAR_S
] = 0;
237 // we're always non-secure
238 miscRegs
[MISCREG_SCR
] = 1;
241 //XXX We need to initialize the rest of the state.
245 ISA::clear64(const ArmISAParams
*p
)
248 Addr rvbar
= system
->resetAddr64();
249 switch (system
->highestEL()) {
250 // Set initial EL to highest implemented EL using associated stack
251 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
254 cpsr
.mode
= MODE_EL3H
;
255 miscRegs
[MISCREG_RVBAR_EL3
] = rvbar
;
258 cpsr
.mode
= MODE_EL2H
;
259 miscRegs
[MISCREG_RVBAR_EL2
] = rvbar
;
262 cpsr
.mode
= MODE_EL1H
;
263 miscRegs
[MISCREG_RVBAR_EL1
] = rvbar
;
266 panic("Invalid highest implemented exception level");
270 // Initialize rest of CPSR
271 cpsr
.daif
= 0xf; // Mask all interrupts
274 miscRegs
[MISCREG_CPSR
] = cpsr
;
277 // Initialize other control registers
278 miscRegs
[MISCREG_MPIDR_EL1
] = 0x80000000;
280 miscRegs
[MISCREG_SCTLR_EL3
] = 0x30c50830;
281 miscRegs
[MISCREG_SCR_EL3
] = 0x00000030; // RES1 fields
282 } else if (haveVirtualization
) {
283 // also MISCREG_SCTLR_EL2 (by mapping)
284 miscRegs
[MISCREG_HSCTLR
] = 0x30c50830;
286 // also MISCREG_SCTLR_EL1 (by mapping)
287 miscRegs
[MISCREG_SCTLR_NS
] = 0x30d00800 | 0x00050030; // RES1 | init
289 miscRegs
[MISCREG_SCR_EL3
] = 1;
292 // Initialize configurable id registers
293 miscRegs
[MISCREG_ID_AA64AFR0_EL1
] = p
->id_aa64afr0_el1
;
294 miscRegs
[MISCREG_ID_AA64AFR1_EL1
] = p
->id_aa64afr1_el1
;
295 miscRegs
[MISCREG_ID_AA64DFR0_EL1
] =
296 (p
->id_aa64dfr0_el1
& 0xfffffffffffff0ffULL
) |
297 (p
->pmu
? 0x0000000000000100ULL
: 0); // Enable PMUv3
299 miscRegs
[MISCREG_ID_AA64DFR1_EL1
] = p
->id_aa64dfr1_el1
;
300 miscRegs
[MISCREG_ID_AA64ISAR0_EL1
] = p
->id_aa64isar0_el1
;
301 miscRegs
[MISCREG_ID_AA64ISAR1_EL1
] = p
->id_aa64isar1_el1
;
302 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
] = p
->id_aa64mmfr0_el1
;
303 miscRegs
[MISCREG_ID_AA64MMFR1_EL1
] = p
->id_aa64mmfr1_el1
;
305 miscRegs
[MISCREG_ID_DFR0_EL1
] =
306 (p
->pmu
? 0x03000000ULL
: 0); // Enable PMUv3
308 miscRegs
[MISCREG_ID_DFR0
] = miscRegs
[MISCREG_ID_DFR0_EL1
];
310 // Enforce consistency with system-level settings...
313 miscRegs
[MISCREG_ID_AA64PFR0_EL1
] = insertBits(
314 miscRegs
[MISCREG_ID_AA64PFR0_EL1
], 15, 12,
315 haveSecurity
? 0x2 : 0x0);
317 miscRegs
[MISCREG_ID_AA64PFR0_EL1
] = insertBits(
318 miscRegs
[MISCREG_ID_AA64PFR0_EL1
], 11, 8,
319 haveVirtualization
? 0x2 : 0x0);
320 // Large ASID support
321 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
] = insertBits(
322 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
], 7, 4,
323 haveLargeAsid64
? 0x2 : 0x0);
324 // Physical address size
325 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
] = insertBits(
326 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
], 3, 0,
327 encodePhysAddrRange64(physAddrRange64
));
331 ISA::readMiscRegNoEffect(int misc_reg
) const
333 assert(misc_reg
< NumMiscRegs
);
335 const auto ®
= lookUpMiscReg
[misc_reg
]; // bit masks
336 const auto &map
= getMiscIndices(misc_reg
);
337 int lower
= map
.first
, upper
= map
.second
;
338 // NB!: apply architectural masks according to desired register,
339 // despite possibly getting value from different (mapped) register.
340 auto val
= !upper
? miscRegs
[lower
] : ((miscRegs
[lower
] & mask(32))
341 |(miscRegs
[upper
] << 32));
342 if (val
& reg
.res0()) {
343 DPRINTF(MiscRegs
, "Reading MiscReg %s with set res0 bits: %#x\n",
344 miscRegName
[misc_reg
], val
& reg
.res0());
346 if ((val
& reg
.res1()) != reg
.res1()) {
347 DPRINTF(MiscRegs
, "Reading MiscReg %s with clear res1 bits: %#x\n",
348 miscRegName
[misc_reg
], (val
& reg
.res1()) ^ reg
.res1());
350 return (val
& ~reg
.raz()) | reg
.rao(); // enforce raz/rao
355 ISA::readMiscReg(int misc_reg
, ThreadContext
*tc
)
361 if (misc_reg
== MISCREG_CPSR
) {
362 cpsr
= miscRegs
[misc_reg
];
364 cpsr
.j
= pc
.jazelle() ? 1 : 0;
365 cpsr
.t
= pc
.thumb() ? 1 : 0;
370 if (!miscRegInfo
[misc_reg
][MISCREG_IMPLEMENTED
]) {
371 if (miscRegInfo
[misc_reg
][MISCREG_WARN_NOT_FAIL
])
372 warn("Unimplemented system register %s read.\n",
373 miscRegName
[misc_reg
]);
375 panic("Unimplemented system register %s read.\n",
376 miscRegName
[misc_reg
]);
380 switch (unflattenMiscReg(misc_reg
)) {
383 if (!haveVirtualization
)
386 return readMiscRegNoEffect(MISCREG_HCR
);
390 const uint32_t ones
= (uint32_t)(-1);
392 // Only cp10, cp11, and ase are implemented, nothing else should
393 // be readable? (straight copy from the write code)
394 cpacrMask
.cp10
= ones
;
395 cpacrMask
.cp11
= ones
;
396 cpacrMask
.asedis
= ones
;
398 // Security Extensions may limit the readability of CPACR
400 scr
= readMiscRegNoEffect(MISCREG_SCR
);
401 cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
402 if (scr
.ns
&& (cpsr
.mode
!= MODE_MON
)) {
403 NSACR nsacr
= readMiscRegNoEffect(MISCREG_NSACR
);
404 // NB: Skipping the full loop, here
405 if (!nsacr
.cp10
) cpacrMask
.cp10
= 0;
406 if (!nsacr
.cp11
) cpacrMask
.cp11
= 0;
409 MiscReg val
= readMiscRegNoEffect(MISCREG_CPACR
);
411 DPRINTF(MiscRegs
, "Reading misc reg %s: %#x\n",
412 miscRegName
[misc_reg
], val
);
416 cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
417 scr
= readMiscRegNoEffect(MISCREG_SCR
);
418 if ((cpsr
.mode
== MODE_HYP
) || inSecureState(scr
, cpsr
)) {
419 return getMPIDR(system
, tc
);
421 return readMiscReg(MISCREG_VMPIDR
, tc
);
424 case MISCREG_MPIDR_EL1
:
425 // @todo in the absence of v8 virtualization support just return MPIDR_EL1
426 return getMPIDR(system
, tc
) & 0xffffffff;
428 // top bit defined as RES1
429 return readMiscRegNoEffect(misc_reg
) | 0x80000000;
430 case MISCREG_ID_AFR0
: // not implemented, so alias MIDR
431 case MISCREG_REVIDR
: // not implemented, so alias MIDR
433 cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
434 scr
= readMiscRegNoEffect(MISCREG_SCR
);
435 if ((cpsr
.mode
== MODE_HYP
) || inSecureState(scr
, cpsr
)) {
436 return readMiscRegNoEffect(misc_reg
);
438 return readMiscRegNoEffect(MISCREG_VPIDR
);
441 case MISCREG_JOSCR
: // Jazelle trivial implementation, RAZ/WI
442 case MISCREG_JMCR
: // Jazelle trivial implementation, RAZ/WI
443 case MISCREG_JIDR
: // Jazelle trivial implementation, RAZ/WI
444 case MISCREG_AIDR
: // AUX ID set to 0
445 case MISCREG_TCMTR
: // No TCM's
449 warn_once("The clidr register always reports 0 caches.\n");
450 warn_once("clidr LoUIS field of 0b001 to match current "
451 "ARM implementations.\n");
454 warn_once("The ccsidr register isn't implemented and "
455 "always reads as 0.\n");
457 case MISCREG_CTR
: // AArch32, ARMv7, top bit set
458 case MISCREG_CTR_EL0
: // AArch64
460 //all caches have the same line size in gem5
461 //4 byte words in ARM
462 unsigned lineSizeWords
=
463 tc
->getSystemPtr()->cacheLineSize() / 4;
464 unsigned log2LineSizeWords
= 0;
466 while (lineSizeWords
>>= 1) {
471 //log2 of minimun i-cache line size (words)
472 ctr
.iCacheLineSize
= log2LineSizeWords
;
473 //b11 - gem5 uses pipt
474 ctr
.l1IndexPolicy
= 0x3;
475 //log2 of minimum d-cache line size (words)
476 ctr
.dCacheLineSize
= log2LineSizeWords
;
477 //log2 of max reservation size (words)
478 ctr
.erg
= log2LineSizeWords
;
479 //log2 of max writeback size (words)
480 ctr
.cwg
= log2LineSizeWords
;
481 //b100 - gem5 format is ARMv7
487 warn("Not doing anything for miscreg ACTLR\n");
490 case MISCREG_PMXEVTYPER_PMCCFILTR
:
491 case MISCREG_PMINTENSET_EL1
... MISCREG_PMOVSSET_EL0
:
492 case MISCREG_PMEVCNTR0_EL0
... MISCREG_PMEVTYPER5_EL0
:
493 case MISCREG_PMCR
... MISCREG_PMOVSSET
:
494 return pmu
->readMiscReg(misc_reg
);
497 panic("shouldn't be reading this register seperately\n");
498 case MISCREG_FPSCR_QC
:
499 return readMiscRegNoEffect(MISCREG_FPSCR
) & ~FpscrQcMask
;
500 case MISCREG_FPSCR_EXC
:
501 return readMiscRegNoEffect(MISCREG_FPSCR
) & ~FpscrExcMask
;
504 const uint32_t ones
= (uint32_t)(-1);
506 fpscrMask
.ioc
= ones
;
507 fpscrMask
.dzc
= ones
;
508 fpscrMask
.ofc
= ones
;
509 fpscrMask
.ufc
= ones
;
510 fpscrMask
.ixc
= ones
;
511 fpscrMask
.idc
= ones
;
517 return readMiscRegNoEffect(MISCREG_FPSCR
) & (uint32_t)fpscrMask
;
521 const uint32_t ones
= (uint32_t)(-1);
523 fpscrMask
.ioe
= ones
;
524 fpscrMask
.dze
= ones
;
525 fpscrMask
.ofe
= ones
;
526 fpscrMask
.ufe
= ones
;
527 fpscrMask
.ixe
= ones
;
528 fpscrMask
.ide
= ones
;
529 fpscrMask
.len
= ones
;
530 fpscrMask
.stride
= ones
;
531 fpscrMask
.rMode
= ones
;
534 fpscrMask
.ahp
= ones
;
535 return readMiscRegNoEffect(MISCREG_FPSCR
) & (uint32_t)fpscrMask
;
540 cpsr
.nz
= tc
->readCCReg(CCREG_NZ
);
541 cpsr
.c
= tc
->readCCReg(CCREG_C
);
542 cpsr
.v
= tc
->readCCReg(CCREG_V
);
548 cpsr
.daif
= (uint8_t) ((CPSR
) miscRegs
[MISCREG_CPSR
]).daif
;
553 return tc
->readIntReg(INTREG_SP0
);
557 return tc
->readIntReg(INTREG_SP1
);
561 return tc
->readIntReg(INTREG_SP2
);
565 return miscRegs
[MISCREG_CPSR
] & 0x1;
567 case MISCREG_CURRENTEL
:
569 return miscRegs
[MISCREG_CPSR
] & 0xc;
573 // mostly unimplemented, just set NumCPUs field from sim and return
575 // b00:1CPU to b11:4CPUs
576 l2ctlr
.numCPUs
= tc
->getSystemPtr()->numContexts() - 1;
579 case MISCREG_DBGDIDR
:
580 /* For now just implement the version number.
581 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
584 case MISCREG_DBGDSCRint
:
587 return tc
->getCpuPtr()->getInterruptController(tc
->threadId())->getISR(
588 readMiscRegNoEffect(MISCREG_HCR
),
589 readMiscRegNoEffect(MISCREG_CPSR
),
590 readMiscRegNoEffect(MISCREG_SCR
));
591 case MISCREG_ISR_EL1
:
592 return tc
->getCpuPtr()->getInterruptController(tc
->threadId())->getISR(
593 readMiscRegNoEffect(MISCREG_HCR_EL2
),
594 readMiscRegNoEffect(MISCREG_CPSR
),
595 readMiscRegNoEffect(MISCREG_SCR_EL3
));
596 case MISCREG_DCZID_EL0
:
597 return 0x04; // DC ZVA clear 64-byte chunks
600 MiscReg val
= readMiscRegNoEffect(misc_reg
);
601 // The trap bit associated with CP14 is defined as RAZ
603 // If a CP bit in NSACR is 0 then the corresponding bit in
605 bool secure_lookup
= haveSecurity
&&
606 inSecureState(readMiscRegNoEffect(MISCREG_SCR
),
607 readMiscRegNoEffect(MISCREG_CPSR
));
608 if (!secure_lookup
) {
609 MiscReg mask
= readMiscRegNoEffect(MISCREG_NSACR
);
610 val
|= (mask
^ 0x7FFF) & 0xBFFF;
612 // Set the bits for unimplemented coprocessors to RAO/WI
616 case MISCREG_HDFAR
: // alias for secure DFAR
617 return readMiscRegNoEffect(MISCREG_DFAR_S
);
618 case MISCREG_HIFAR
: // alias for secure IFAR
619 return readMiscRegNoEffect(MISCREG_IFAR_S
);
620 case MISCREG_HVBAR
: // bottom bits reserved
621 return readMiscRegNoEffect(MISCREG_HVBAR
) & 0xFFFFFFE0;
623 return (readMiscRegNoEffect(misc_reg
) & 0x72DD39FF) | 0x00C00818;
624 case MISCREG_SCTLR_EL1
:
625 return (readMiscRegNoEffect(misc_reg
) & 0x37DDDBBF) | 0x30D00800;
626 case MISCREG_SCTLR_EL2
:
627 case MISCREG_SCTLR_EL3
:
629 return (readMiscRegNoEffect(misc_reg
) & 0x32CD183F) | 0x30C50830;
631 case MISCREG_ID_PFR0
:
632 // !ThumbEE | !Jazelle | Thumb | ARM
634 case MISCREG_ID_PFR1
:
635 { // Timer | Virti | !M Profile | TrustZone | ARMv4
636 bool haveTimer
= (system
->getGenericTimer() != NULL
);
638 | (haveSecurity
? 0x00000010 : 0x0)
639 | (haveVirtualization
? 0x00001000 : 0x0)
640 | (haveTimer
? 0x00010000 : 0x0);
642 case MISCREG_ID_AA64PFR0_EL1
:
643 return 0x0000000000000002 // AArch{64,32} supported at EL0
644 | 0x0000000000000020 // EL1
645 | (haveVirtualization
? 0x0000000000000200 : 0) // EL2
646 | (haveSecurity
? 0x0000000000002000 : 0); // EL3
647 case MISCREG_ID_AA64PFR1_EL1
:
648 return 0; // bits [63:0] RES0 (reserved for future use)
650 // Generic Timer registers
651 case MISCREG_CNTFRQ
... MISCREG_CNTHP_CTL
:
652 case MISCREG_CNTPCT
... MISCREG_CNTHP_CVAL
:
653 case MISCREG_CNTKCTL_EL1
... MISCREG_CNTV_CVAL_EL0
:
654 case MISCREG_CNTVOFF_EL2
... MISCREG_CNTPS_CVAL_EL1
:
655 return getGenericTimer(tc
).readMiscReg(misc_reg
);
661 return readMiscRegNoEffect(misc_reg
);
665 ISA::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
)
667 assert(misc_reg
< NumMiscRegs
);
669 const auto ®
= lookUpMiscReg
[misc_reg
]; // bit masks
670 const auto &map
= getMiscIndices(misc_reg
);
671 int lower
= map
.first
, upper
= map
.second
;
673 auto v
= (val
& ~reg
.wi()) | reg
.rao();
675 miscRegs
[lower
] = bits(v
, 31, 0);
676 miscRegs
[upper
] = bits(v
, 63, 32);
677 DPRINTF(MiscRegs
, "Writing to misc reg %d (%d:%d) : %#x\n",
678 misc_reg
, lower
, upper
, v
);
681 DPRINTF(MiscRegs
, "Writing to misc reg %d (%d) : %#x\n",
692 auto tlb
= dynamic_cast<TLB
*>(tc
->getITBPtr());
701 auto tlb
= dynamic_cast<TLB
*>(tc
->getDTBPtr());
706 } // anonymous namespace
709 ISA::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadContext
*tc
)
712 MiscReg newVal
= val
;
722 if (misc_reg
== MISCREG_CPSR
) {
726 CPSR old_cpsr
= miscRegs
[MISCREG_CPSR
];
727 int old_mode
= old_cpsr
.mode
;
729 if (old_mode
!= cpsr
.mode
|| cpsr
.il
!= old_cpsr
.il
) {
730 getITBPtr(tc
)->invalidateMiscReg();
731 getDTBPtr(tc
)->invalidateMiscReg();
734 DPRINTF(Arm
, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
735 miscRegs
[misc_reg
], cpsr
, cpsr
.f
, cpsr
.i
, cpsr
.a
, cpsr
.mode
);
736 PCState pc
= tc
->pcState();
737 pc
.nextThumb(cpsr
.t
);
738 pc
.nextJazelle(cpsr
.j
);
740 // Follow slightly different semantics if a CheckerCPU object
742 CheckerCPU
*checker
= tc
->getCheckerCpuPtr();
744 tc
->pcStateNoRecord(pc
);
750 if (!miscRegInfo
[misc_reg
][MISCREG_IMPLEMENTED
]) {
751 if (miscRegInfo
[misc_reg
][MISCREG_WARN_NOT_FAIL
])
752 warn("Unimplemented system register %s write with %#x.\n",
753 miscRegName
[misc_reg
], val
);
755 panic("Unimplemented system register %s write with %#x.\n",
756 miscRegName
[misc_reg
], val
);
759 switch (unflattenMiscReg(misc_reg
)) {
763 const uint32_t ones
= (uint32_t)(-1);
765 // Only cp10, cp11, and ase are implemented, nothing else should
767 cpacrMask
.cp10
= ones
;
768 cpacrMask
.cp11
= ones
;
769 cpacrMask
.asedis
= ones
;
771 // Security Extensions may limit the writability of CPACR
773 scr
= readMiscRegNoEffect(MISCREG_SCR
);
774 CPSR cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
775 if (scr
.ns
&& (cpsr
.mode
!= MODE_MON
)) {
776 NSACR nsacr
= readMiscRegNoEffect(MISCREG_NSACR
);
777 // NB: Skipping the full loop, here
778 if (!nsacr
.cp10
) cpacrMask
.cp10
= 0;
779 if (!nsacr
.cp11
) cpacrMask
.cp11
= 0;
783 MiscReg old_val
= readMiscRegNoEffect(MISCREG_CPACR
);
785 newVal
|= old_val
& ~cpacrMask
;
786 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
787 miscRegName
[misc_reg
], newVal
);
790 case MISCREG_CPACR_EL1
:
792 const uint32_t ones
= (uint32_t)(-1);
794 cpacrMask
.tta
= ones
;
795 cpacrMask
.fpen
= ones
;
797 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
798 miscRegName
[misc_reg
], newVal
);
801 case MISCREG_CPTR_EL2
:
803 const uint32_t ones
= (uint32_t)(-1);
805 cptrMask
.tcpac
= ones
;
810 cptrMask
.res1_13_12_el2
= ones
;
811 cptrMask
.res1_9_0_el2
= ones
;
813 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
814 miscRegName
[misc_reg
], newVal
);
817 case MISCREG_CPTR_EL3
:
819 const uint32_t ones
= (uint32_t)(-1);
821 cptrMask
.tcpac
= ones
;
825 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
826 miscRegName
[misc_reg
], newVal
);
830 warn_once("The csselr register isn't implemented.\n");
833 case MISCREG_DC_ZVA_Xt
:
834 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
839 const uint32_t ones
= (uint32_t)(-1);
841 fpscrMask
.ioc
= ones
;
842 fpscrMask
.dzc
= ones
;
843 fpscrMask
.ofc
= ones
;
844 fpscrMask
.ufc
= ones
;
845 fpscrMask
.ixc
= ones
;
846 fpscrMask
.idc
= ones
;
847 fpscrMask
.ioe
= ones
;
848 fpscrMask
.dze
= ones
;
849 fpscrMask
.ofe
= ones
;
850 fpscrMask
.ufe
= ones
;
851 fpscrMask
.ixe
= ones
;
852 fpscrMask
.ide
= ones
;
853 fpscrMask
.len
= ones
;
854 fpscrMask
.stride
= ones
;
855 fpscrMask
.rMode
= ones
;
858 fpscrMask
.ahp
= ones
;
864 newVal
= (newVal
& (uint32_t)fpscrMask
) |
865 (readMiscRegNoEffect(MISCREG_FPSCR
) &
866 ~(uint32_t)fpscrMask
);
867 tc
->getDecoderPtr()->setContext(newVal
);
872 const uint32_t ones
= (uint32_t)(-1);
874 fpscrMask
.ioc
= ones
;
875 fpscrMask
.dzc
= ones
;
876 fpscrMask
.ofc
= ones
;
877 fpscrMask
.ufc
= ones
;
878 fpscrMask
.ixc
= ones
;
879 fpscrMask
.idc
= ones
;
885 newVal
= (newVal
& (uint32_t)fpscrMask
) |
886 (readMiscRegNoEffect(MISCREG_FPSCR
) &
887 ~(uint32_t)fpscrMask
);
888 misc_reg
= MISCREG_FPSCR
;
893 const uint32_t ones
= (uint32_t)(-1);
895 fpscrMask
.ioe
= ones
;
896 fpscrMask
.dze
= ones
;
897 fpscrMask
.ofe
= ones
;
898 fpscrMask
.ufe
= ones
;
899 fpscrMask
.ixe
= ones
;
900 fpscrMask
.ide
= ones
;
901 fpscrMask
.len
= ones
;
902 fpscrMask
.stride
= ones
;
903 fpscrMask
.rMode
= ones
;
906 fpscrMask
.ahp
= ones
;
907 newVal
= (newVal
& (uint32_t)fpscrMask
) |
908 (readMiscRegNoEffect(MISCREG_FPSCR
) &
909 ~(uint32_t)fpscrMask
);
910 misc_reg
= MISCREG_FPSCR
;
915 assert(!(newVal
& ~CpsrMaskQ
));
916 newVal
= readMiscRegNoEffect(MISCREG_CPSR
) | newVal
;
917 misc_reg
= MISCREG_CPSR
;
920 case MISCREG_FPSCR_QC
:
922 newVal
= readMiscRegNoEffect(MISCREG_FPSCR
) |
923 (newVal
& FpscrQcMask
);
924 misc_reg
= MISCREG_FPSCR
;
927 case MISCREG_FPSCR_EXC
:
929 newVal
= readMiscRegNoEffect(MISCREG_FPSCR
) |
930 (newVal
& FpscrExcMask
);
931 misc_reg
= MISCREG_FPSCR
;
936 // vfpv3 architecture, section B.6.1 of DDI04068
937 // bit 29 - valid only if fpexc[31] is 0
938 const uint32_t fpexcMask
= 0x60000000;
939 newVal
= (newVal
& fpexcMask
) |
940 (readMiscRegNoEffect(MISCREG_FPEXC
) & ~fpexcMask
);
945 if (!haveVirtualization
)
951 // ARM ARM (ARM DDI 0406C.b) B4.1.96
952 const uint32_t ifsrMask
=
953 mask(31, 13) | mask(11, 11) | mask(8, 6);
954 newVal
= newVal
& ~ifsrMask
;
959 // ARM ARM (ARM DDI 0406C.b) B4.1.52
960 const uint32_t dfsrMask
= mask(31, 14) | mask(8, 8);
961 newVal
= newVal
& ~dfsrMask
;
967 // ARM ARM (ARM DDI 0406C.b) B4.1.5
968 // Valid only with LPAE
971 DPRINTF(MiscRegs
, "Writing AMAIR: %#x\n", newVal
);
975 getITBPtr(tc
)->invalidateMiscReg();
976 getDTBPtr(tc
)->invalidateMiscReg();
980 DPRINTF(MiscRegs
, "Writing SCTLR: %#x\n", newVal
);
981 scr
= readMiscRegNoEffect(MISCREG_SCR
);
982 MiscRegIndex sctlr_idx
= (haveSecurity
&& !scr
.ns
)
983 ? MISCREG_SCTLR_S
: MISCREG_SCTLR_NS
;
984 SCTLR sctlr
= miscRegs
[sctlr_idx
];
985 SCTLR new_sctlr
= newVal
;
986 new_sctlr
.nmfi
= ((bool)sctlr
.nmfi
) && !haveVirtualization
;
987 miscRegs
[sctlr_idx
] = (MiscReg
)new_sctlr
;
988 getITBPtr(tc
)->invalidateMiscReg();
989 getDTBPtr(tc
)->invalidateMiscReg();
992 case MISCREG_ID_PFR0
:
993 case MISCREG_ID_PFR1
:
994 case MISCREG_ID_DFR0
:
995 case MISCREG_ID_MMFR0
:
996 case MISCREG_ID_MMFR1
:
997 case MISCREG_ID_MMFR2
:
998 case MISCREG_ID_MMFR3
:
999 case MISCREG_ID_ISAR0
:
1000 case MISCREG_ID_ISAR1
:
1001 case MISCREG_ID_ISAR2
:
1002 case MISCREG_ID_ISAR3
:
1003 case MISCREG_ID_ISAR4
:
1004 case MISCREG_ID_ISAR5
:
1012 case MISCREG_ID_AA64AFR0_EL1
:
1013 case MISCREG_ID_AA64AFR1_EL1
:
1014 case MISCREG_ID_AA64DFR0_EL1
:
1015 case MISCREG_ID_AA64DFR1_EL1
:
1016 case MISCREG_ID_AA64ISAR0_EL1
:
1017 case MISCREG_ID_AA64ISAR1_EL1
:
1018 case MISCREG_ID_AA64MMFR0_EL1
:
1019 case MISCREG_ID_AA64MMFR1_EL1
:
1020 case MISCREG_ID_AA64PFR0_EL1
:
1021 case MISCREG_ID_AA64PFR1_EL1
:
1022 // ID registers are constants.
1025 // TLBI all entries, EL0&1 inner sharable (ignored)
1026 case MISCREG_TLBIALLIS
:
1027 case MISCREG_TLBIALL
: // TLBI all entries, EL0&1,
1029 target_el
= 1; // el 0 and 1 are handled together
1030 scr
= readMiscReg(MISCREG_SCR
, tc
);
1031 secure_lookup
= haveSecurity
&& !scr
.ns
;
1032 sys
= tc
->getSystemPtr();
1033 for (x
= 0; x
< sys
->numContexts(); x
++) {
1034 oc
= sys
->getThreadContext(x
);
1035 getITBPtr(oc
)->flushAllSecurity(secure_lookup
, target_el
);
1036 getDTBPtr(oc
)->flushAllSecurity(secure_lookup
, target_el
);
1038 // If CheckerCPU is connected, need to notify it of a flush
1039 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1041 getITBPtr(checker
)->flushAllSecurity(secure_lookup
,
1043 getDTBPtr(checker
)->flushAllSecurity(secure_lookup
,
1048 // TLBI all entries, EL0&1, instruction side
1049 case MISCREG_ITLBIALL
:
1051 target_el
= 1; // el 0 and 1 are handled together
1052 scr
= readMiscReg(MISCREG_SCR
, tc
);
1053 secure_lookup
= haveSecurity
&& !scr
.ns
;
1054 getITBPtr(tc
)->flushAllSecurity(secure_lookup
, target_el
);
1056 // TLBI all entries, EL0&1, data side
1057 case MISCREG_DTLBIALL
:
1059 target_el
= 1; // el 0 and 1 are handled together
1060 scr
= readMiscReg(MISCREG_SCR
, tc
);
1061 secure_lookup
= haveSecurity
&& !scr
.ns
;
1062 getDTBPtr(tc
)->flushAllSecurity(secure_lookup
, target_el
);
1064 // TLBI based on VA, EL0&1 inner sharable (ignored)
1065 case MISCREG_TLBIMVAIS
:
1066 case MISCREG_TLBIMVA
:
1068 target_el
= 1; // el 0 and 1 are handled together
1069 scr
= readMiscReg(MISCREG_SCR
, tc
);
1070 secure_lookup
= haveSecurity
&& !scr
.ns
;
1071 sys
= tc
->getSystemPtr();
1072 for (x
= 0; x
< sys
->numContexts(); x
++) {
1073 oc
= sys
->getThreadContext(x
);
1074 getITBPtr(oc
)->flushMvaAsid(mbits(newVal
, 31, 12),
1076 secure_lookup
, target_el
);
1077 getDTBPtr(oc
)->flushMvaAsid(mbits(newVal
, 31, 12),
1079 secure_lookup
, target_el
);
1081 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1083 getITBPtr(checker
)->flushMvaAsid(mbits(newVal
, 31, 12),
1084 bits(newVal
, 7,0), secure_lookup
, target_el
);
1085 getDTBPtr(checker
)->flushMvaAsid(mbits(newVal
, 31, 12),
1086 bits(newVal
, 7,0), secure_lookup
, target_el
);
1090 // TLBI by ASID, EL0&1, inner sharable
1091 case MISCREG_TLBIASIDIS
:
1092 case MISCREG_TLBIASID
:
1094 target_el
= 1; // el 0 and 1 are handled together
1095 scr
= readMiscReg(MISCREG_SCR
, tc
);
1096 secure_lookup
= haveSecurity
&& !scr
.ns
;
1097 sys
= tc
->getSystemPtr();
1098 for (x
= 0; x
< sys
->numContexts(); x
++) {
1099 oc
= sys
->getThreadContext(x
);
1100 getITBPtr(oc
)->flushAsid(bits(newVal
, 7,0),
1101 secure_lookup
, target_el
);
1102 getDTBPtr(oc
)->flushAsid(bits(newVal
, 7,0),
1103 secure_lookup
, target_el
);
1104 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1106 getITBPtr(checker
)->flushAsid(bits(newVal
, 7,0),
1107 secure_lookup
, target_el
);
1108 getDTBPtr(checker
)->flushAsid(bits(newVal
, 7,0),
1109 secure_lookup
, target_el
);
1113 // TLBI by address, EL0&1, inner sharable (ignored)
1114 case MISCREG_TLBIMVAAIS
:
1115 case MISCREG_TLBIMVAA
:
1117 target_el
= 1; // el 0 and 1 are handled together
1118 scr
= readMiscReg(MISCREG_SCR
, tc
);
1119 secure_lookup
= haveSecurity
&& !scr
.ns
;
1121 tlbiMVA(tc
, newVal
, secure_lookup
, hyp
, target_el
);
1123 // TLBI by address, EL2, hypervisor mode
1124 case MISCREG_TLBIMVAH
:
1125 case MISCREG_TLBIMVAHIS
:
1127 target_el
= 1; // aarch32, use hyp bit
1128 scr
= readMiscReg(MISCREG_SCR
, tc
);
1129 secure_lookup
= haveSecurity
&& !scr
.ns
;
1131 tlbiMVA(tc
, newVal
, secure_lookup
, hyp
, target_el
);
1133 // TLBI by address and asid, EL0&1, instruction side only
1134 case MISCREG_ITLBIMVA
:
1136 target_el
= 1; // el 0 and 1 are handled together
1137 scr
= readMiscReg(MISCREG_SCR
, tc
);
1138 secure_lookup
= haveSecurity
&& !scr
.ns
;
1139 getITBPtr(tc
)->flushMvaAsid(mbits(newVal
, 31, 12),
1140 bits(newVal
, 7,0), secure_lookup
, target_el
);
1142 // TLBI by address and asid, EL0&1, data side only
1143 case MISCREG_DTLBIMVA
:
1145 target_el
= 1; // el 0 and 1 are handled together
1146 scr
= readMiscReg(MISCREG_SCR
, tc
);
1147 secure_lookup
= haveSecurity
&& !scr
.ns
;
1148 getDTBPtr(tc
)->flushMvaAsid(mbits(newVal
, 31, 12),
1149 bits(newVal
, 7,0), secure_lookup
, target_el
);
1151 // TLBI by ASID, EL0&1, instrution side only
1152 case MISCREG_ITLBIASID
:
1154 target_el
= 1; // el 0 and 1 are handled together
1155 scr
= readMiscReg(MISCREG_SCR
, tc
);
1156 secure_lookup
= haveSecurity
&& !scr
.ns
;
1157 getITBPtr(tc
)->flushAsid(bits(newVal
, 7,0), secure_lookup
,
1160 // TLBI by ASID EL0&1 data size only
1161 case MISCREG_DTLBIASID
:
1163 target_el
= 1; // el 0 and 1 are handled together
1164 scr
= readMiscReg(MISCREG_SCR
, tc
);
1165 secure_lookup
= haveSecurity
&& !scr
.ns
;
1166 getDTBPtr(tc
)->flushAsid(bits(newVal
, 7,0), secure_lookup
,
1169 // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB
1170 case MISCREG_TLBIALLNSNH
:
1171 case MISCREG_TLBIALLNSNHIS
:
1173 target_el
= 1; // el 0 and 1 are handled together
1175 tlbiALLN(tc
, hyp
, target_el
);
1177 // TLBI all entries, EL2, hyp,
1178 case MISCREG_TLBIALLH
:
1179 case MISCREG_TLBIALLHIS
:
1181 target_el
= 1; // aarch32, use hyp bit
1183 tlbiALLN(tc
, hyp
, target_el
);
1185 // AArch64 TLBI: invalidate all entries EL3
1186 case MISCREG_TLBI_ALLE3IS
:
1187 case MISCREG_TLBI_ALLE3
:
1190 secure_lookup
= true;
1191 tlbiALL(tc
, secure_lookup
, target_el
);
1193 // @todo: uncomment this to enable Virtualization
1194 // case MISCREG_TLBI_ALLE2IS:
1195 // case MISCREG_TLBI_ALLE2:
1196 // TLBI all entries, EL0&1
1197 case MISCREG_TLBI_ALLE1IS
:
1198 case MISCREG_TLBI_ALLE1
:
1199 // AArch64 TLBI: invalidate all entries, stage 1, current VMID
1200 case MISCREG_TLBI_VMALLE1IS
:
1201 case MISCREG_TLBI_VMALLE1
:
1202 // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID
1203 case MISCREG_TLBI_VMALLS12E1IS
:
1204 case MISCREG_TLBI_VMALLS12E1
:
1205 // @todo: handle VMID and stage 2 to enable Virtualization
1207 target_el
= 1; // el 0 and 1 are handled together
1208 scr
= readMiscReg(MISCREG_SCR
, tc
);
1209 secure_lookup
= haveSecurity
&& !scr
.ns
;
1210 tlbiALL(tc
, secure_lookup
, target_el
);
1212 // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID
1213 // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries
1214 // from the last level of translation table walks
1215 // @todo: handle VMID to enable Virtualization
1216 // TLBI all entries, EL0&1
1217 case MISCREG_TLBI_VAE3IS_Xt
:
1218 case MISCREG_TLBI_VAE3_Xt
:
1219 // TLBI by VA, EL3 regime stage 1, last level walk
1220 case MISCREG_TLBI_VALE3IS_Xt
:
1221 case MISCREG_TLBI_VALE3_Xt
:
1224 asid
= 0xbeef; // does not matter, tlbi is global
1225 secure_lookup
= true;
1226 tlbiVA(tc
, newVal
, asid
, secure_lookup
, target_el
);
1229 case MISCREG_TLBI_VAE2IS_Xt
:
1230 case MISCREG_TLBI_VAE2_Xt
:
1231 // TLBI by VA, EL2, stage1 last level walk
1232 case MISCREG_TLBI_VALE2IS_Xt
:
1233 case MISCREG_TLBI_VALE2_Xt
:
1236 asid
= 0xbeef; // does not matter, tlbi is global
1237 scr
= readMiscReg(MISCREG_SCR
, tc
);
1238 secure_lookup
= haveSecurity
&& !scr
.ns
;
1239 tlbiVA(tc
, newVal
, asid
, secure_lookup
, target_el
);
1241 // TLBI by VA EL1 & 0, stage1, ASID, current VMID
1242 case MISCREG_TLBI_VAE1IS_Xt
:
1243 case MISCREG_TLBI_VAE1_Xt
:
1244 case MISCREG_TLBI_VALE1IS_Xt
:
1245 case MISCREG_TLBI_VALE1_Xt
:
1247 asid
= bits(newVal
, 63, 48);
1248 target_el
= 1; // el 0 and 1 are handled together
1249 scr
= readMiscReg(MISCREG_SCR
, tc
);
1250 secure_lookup
= haveSecurity
&& !scr
.ns
;
1251 tlbiVA(tc
, newVal
, asid
, secure_lookup
, target_el
);
1253 // AArch64 TLBI: invalidate by ASID, stage 1, current VMID
1254 // @todo: handle VMID to enable Virtualization
1255 case MISCREG_TLBI_ASIDE1IS_Xt
:
1256 case MISCREG_TLBI_ASIDE1_Xt
:
1258 target_el
= 1; // el 0 and 1 are handled together
1259 scr
= readMiscReg(MISCREG_SCR
, tc
);
1260 secure_lookup
= haveSecurity
&& !scr
.ns
;
1261 sys
= tc
->getSystemPtr();
1262 for (x
= 0; x
< sys
->numContexts(); x
++) {
1263 oc
= sys
->getThreadContext(x
);
1264 asid
= bits(newVal
, 63, 48);
1265 if (!haveLargeAsid64
)
1267 getITBPtr(oc
)->flushAsid(asid
, secure_lookup
, target_el
);
1268 getDTBPtr(oc
)->flushAsid(asid
, secure_lookup
, target_el
);
1269 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1271 getITBPtr(checker
)->flushAsid(asid
,
1272 secure_lookup
, target_el
);
1273 getDTBPtr(checker
)->flushAsid(asid
,
1274 secure_lookup
, target_el
);
1278 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID
1279 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1280 // entries from the last level of translation table walks
1281 // @todo: handle VMID to enable Virtualization
1282 case MISCREG_TLBI_VAAE1IS_Xt
:
1283 case MISCREG_TLBI_VAAE1_Xt
:
1284 case MISCREG_TLBI_VAALE1IS_Xt
:
1285 case MISCREG_TLBI_VAALE1_Xt
:
1287 target_el
= 1; // el 0 and 1 are handled together
1288 scr
= readMiscReg(MISCREG_SCR
, tc
);
1289 secure_lookup
= haveSecurity
&& !scr
.ns
;
1290 sys
= tc
->getSystemPtr();
1291 for (x
= 0; x
< sys
->numContexts(); x
++) {
1292 // @todo: extra controls on TLBI broadcast?
1293 oc
= sys
->getThreadContext(x
);
1294 Addr va
= ((Addr
) bits(newVal
, 43, 0)) << 12;
1295 getITBPtr(oc
)->flushMva(va
,
1296 secure_lookup
, false, target_el
);
1297 getDTBPtr(oc
)->flushMva(va
,
1298 secure_lookup
, false, target_el
);
1300 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1302 getITBPtr(checker
)->flushMva(va
,
1303 secure_lookup
, false, target_el
);
1304 getDTBPtr(checker
)->flushMva(va
,
1305 secure_lookup
, false, target_el
);
1309 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID
1310 case MISCREG_TLBI_IPAS2LE1IS_Xt
:
1311 case MISCREG_TLBI_IPAS2LE1_Xt
:
1312 case MISCREG_TLBI_IPAS2E1IS_Xt
:
1313 case MISCREG_TLBI_IPAS2E1_Xt
:
1315 target_el
= 1; // EL 0 and 1 are handled together
1316 scr
= readMiscReg(MISCREG_SCR
, tc
);
1317 secure_lookup
= haveSecurity
&& !scr
.ns
;
1318 sys
= tc
->getSystemPtr();
1319 for (x
= 0; x
< sys
->numContexts(); x
++) {
1320 oc
= sys
->getThreadContext(x
);
1321 Addr ipa
= ((Addr
) bits(newVal
, 35, 0)) << 12;
1322 getITBPtr(oc
)->flushIpaVmid(ipa
,
1323 secure_lookup
, false, target_el
);
1324 getDTBPtr(oc
)->flushIpaVmid(ipa
,
1325 secure_lookup
, false, target_el
);
1327 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1329 getITBPtr(checker
)->flushIpaVmid(ipa
,
1330 secure_lookup
, false, target_el
);
1331 getDTBPtr(checker
)->flushIpaVmid(ipa
,
1332 secure_lookup
, false, target_el
);
1337 warn("Not doing anything for write of miscreg ACTLR\n");
1340 case MISCREG_PMXEVTYPER_PMCCFILTR
:
1341 case MISCREG_PMINTENSET_EL1
... MISCREG_PMOVSSET_EL0
:
1342 case MISCREG_PMEVCNTR0_EL0
... MISCREG_PMEVTYPER5_EL0
:
1343 case MISCREG_PMCR
... MISCREG_PMOVSSET
:
1344 pmu
->setMiscReg(misc_reg
, newVal
);
1348 case MISCREG_HSTR
: // TJDBX, now redifined to be RES0
1352 newVal
&= ~((uint32_t) hstrMask
);
1357 // If a CP bit in NSACR is 0 then the corresponding bit in
1358 // HCPTR is RAO/WI. Same applies to NSASEDIS
1359 secure_lookup
= haveSecurity
&&
1360 inSecureState(readMiscRegNoEffect(MISCREG_SCR
),
1361 readMiscRegNoEffect(MISCREG_CPSR
));
1362 if (!secure_lookup
) {
1363 MiscReg oldValue
= readMiscRegNoEffect(MISCREG_HCPTR
);
1364 MiscReg mask
= (readMiscRegNoEffect(MISCREG_NSACR
) ^ 0x7FFF) & 0xBFFF;
1365 newVal
= (newVal
& ~mask
) | (oldValue
& mask
);
1369 case MISCREG_HDFAR
: // alias for secure DFAR
1370 misc_reg
= MISCREG_DFAR_S
;
1372 case MISCREG_HIFAR
: // alias for secure IFAR
1373 misc_reg
= MISCREG_IFAR_S
;
1375 case MISCREG_ATS1CPR
:
1376 case MISCREG_ATS1CPW
:
1377 case MISCREG_ATS1CUR
:
1378 case MISCREG_ATS1CUW
:
1379 case MISCREG_ATS12NSOPR
:
1380 case MISCREG_ATS12NSOPW
:
1381 case MISCREG_ATS12NSOUR
:
1382 case MISCREG_ATS12NSOUW
:
1383 case MISCREG_ATS1HR
:
1384 case MISCREG_ATS1HW
:
1386 Request::Flags flags
= 0;
1387 BaseTLB::Mode mode
= BaseTLB::Read
;
1388 TLB::ArmTranslationType tranType
= TLB::NormalTran
;
1391 case MISCREG_ATS1CPR
:
1392 flags
= TLB::MustBeOne
;
1393 tranType
= TLB::S1CTran
;
1394 mode
= BaseTLB::Read
;
1396 case MISCREG_ATS1CPW
:
1397 flags
= TLB::MustBeOne
;
1398 tranType
= TLB::S1CTran
;
1399 mode
= BaseTLB::Write
;
1401 case MISCREG_ATS1CUR
:
1402 flags
= TLB::MustBeOne
| TLB::UserMode
;
1403 tranType
= TLB::S1CTran
;
1404 mode
= BaseTLB::Read
;
1406 case MISCREG_ATS1CUW
:
1407 flags
= TLB::MustBeOne
| TLB::UserMode
;
1408 tranType
= TLB::S1CTran
;
1409 mode
= BaseTLB::Write
;
1411 case MISCREG_ATS12NSOPR
:
1413 panic("Security Extensions required for ATS12NSOPR");
1414 flags
= TLB::MustBeOne
;
1415 tranType
= TLB::S1S2NsTran
;
1416 mode
= BaseTLB::Read
;
1418 case MISCREG_ATS12NSOPW
:
1420 panic("Security Extensions required for ATS12NSOPW");
1421 flags
= TLB::MustBeOne
;
1422 tranType
= TLB::S1S2NsTran
;
1423 mode
= BaseTLB::Write
;
1425 case MISCREG_ATS12NSOUR
:
1427 panic("Security Extensions required for ATS12NSOUR");
1428 flags
= TLB::MustBeOne
| TLB::UserMode
;
1429 tranType
= TLB::S1S2NsTran
;
1430 mode
= BaseTLB::Read
;
1432 case MISCREG_ATS12NSOUW
:
1434 panic("Security Extensions required for ATS12NSOUW");
1435 flags
= TLB::MustBeOne
| TLB::UserMode
;
1436 tranType
= TLB::S1S2NsTran
;
1437 mode
= BaseTLB::Write
;
1439 case MISCREG_ATS1HR
: // only really useful from secure mode.
1440 flags
= TLB::MustBeOne
;
1441 tranType
= TLB::HypMode
;
1442 mode
= BaseTLB::Read
;
1444 case MISCREG_ATS1HW
:
1445 flags
= TLB::MustBeOne
;
1446 tranType
= TLB::HypMode
;
1447 mode
= BaseTLB::Write
;
1450 // If we're in timing mode then doing the translation in
1451 // functional mode then we're slightly distorting performance
1452 // results obtained from simulations. The translation should be
1453 // done in the same mode the core is running in. NOTE: This
1454 // can't be an atomic translation because that causes problems
1455 // with unexpected atomic snoop requests.
1456 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg
);
1457 Request
req(0, val
, 0, flags
, Request::funcMasterId
,
1458 tc
->pcState().pc(), tc
->contextId());
1459 fault
= getDTBPtr(tc
)->translateFunctional(
1460 &req
, tc
, mode
, tranType
);
1461 TTBCR ttbcr
= readMiscRegNoEffect(MISCREG_TTBCR
);
1462 HCR hcr
= readMiscRegNoEffect(MISCREG_HCR
);
1465 if (fault
== NoFault
) {
1466 Addr paddr
= req
.getPaddr();
1467 if (haveLPAE
&& (ttbcr
.eae
|| tranType
& TLB::HypMode
||
1468 ((tranType
& TLB::S1S2NsTran
) && hcr
.vm
) )) {
1469 newVal
= (paddr
& mask(39, 12)) |
1470 (getDTBPtr(tc
)->getAttr());
1472 newVal
= (paddr
& 0xfffff000) |
1473 (getDTBPtr(tc
)->getAttr());
1476 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
1479 ArmFault
*armFault
= reinterpret_cast<ArmFault
*>(fault
.get());
1480 // Set fault bit and FSR
1481 FSR fsr
= armFault
->getFsr(tc
);
1483 newVal
= ((fsr
>> 9) & 1) << 11;
1485 // LPAE - rearange fault status
1486 newVal
|= ((fsr
>> 0) & 0x3f) << 1;
1488 // VMSA - rearange fault status
1489 newVal
|= ((fsr
>> 0) & 0xf) << 1;
1490 newVal
|= ((fsr
>> 10) & 0x1) << 5;
1491 newVal
|= ((fsr
>> 12) & 0x1) << 6;
1493 newVal
|= 0x1; // F bit
1494 newVal
|= ((armFault
->iss() >> 7) & 0x1) << 8;
1495 newVal
|= armFault
->isStage2() ? 0x200 : 0;
1497 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
1500 setMiscRegNoEffect(MISCREG_PAR
, newVal
);
1505 TTBCR ttbcr
= readMiscRegNoEffect(MISCREG_TTBCR
);
1506 const uint32_t ones
= (uint32_t)(-1);
1507 TTBCR ttbcrMask
= 0;
1508 TTBCR ttbcrNew
= newVal
;
1510 // ARM DDI 0406C.b, ARMv7-32
1511 ttbcrMask
.n
= ones
; // T0SZ
1513 ttbcrMask
.pd0
= ones
;
1514 ttbcrMask
.pd1
= ones
;
1516 ttbcrMask
.epd0
= ones
;
1517 ttbcrMask
.irgn0
= ones
;
1518 ttbcrMask
.orgn0
= ones
;
1519 ttbcrMask
.sh0
= ones
;
1520 ttbcrMask
.ps
= ones
; // T1SZ
1521 ttbcrMask
.a1
= ones
;
1522 ttbcrMask
.epd1
= ones
;
1523 ttbcrMask
.irgn1
= ones
;
1524 ttbcrMask
.orgn1
= ones
;
1525 ttbcrMask
.sh1
= ones
;
1527 ttbcrMask
.eae
= ones
;
1529 if (haveLPAE
&& ttbcrNew
.eae
) {
1530 newVal
= newVal
& ttbcrMask
;
1532 newVal
= (newVal
& ttbcrMask
) | (ttbcr
& (~ttbcrMask
));
1539 TTBCR ttbcr
= readMiscRegNoEffect(MISCREG_TTBCR
);
1542 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1543 // ARMv8 AArch32 bit 63-56 only
1544 uint64_t ttbrMask
= mask(63,56) | mask(47,40);
1545 newVal
= (newVal
& (~ttbrMask
));
1550 case MISCREG_SCTLR_EL1
:
1552 getITBPtr(tc
)->invalidateMiscReg();
1553 getDTBPtr(tc
)->invalidateMiscReg();
1554 setMiscRegNoEffect(misc_reg
, newVal
);
1557 case MISCREG_CONTEXTIDR
:
1564 case MISCREG_SCR_EL3
:
1565 case MISCREG_HCR_EL2
:
1566 case MISCREG_TCR_EL1
:
1567 case MISCREG_TCR_EL2
:
1568 case MISCREG_TCR_EL3
:
1569 case MISCREG_SCTLR_EL2
:
1570 case MISCREG_SCTLR_EL3
:
1571 case MISCREG_HSCTLR
:
1572 case MISCREG_TTBR0_EL1
:
1573 case MISCREG_TTBR1_EL1
:
1574 case MISCREG_TTBR0_EL2
:
1575 case MISCREG_TTBR0_EL3
:
1576 getITBPtr(tc
)->invalidateMiscReg();
1577 getDTBPtr(tc
)->invalidateMiscReg();
1583 tc
->setCCReg(CCREG_NZ
, cpsr
.nz
);
1584 tc
->setCCReg(CCREG_C
, cpsr
.c
);
1585 tc
->setCCReg(CCREG_V
, cpsr
.v
);
1590 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1591 cpsr
.daif
= (uint8_t) ((CPSR
) newVal
).daif
;
1593 misc_reg
= MISCREG_CPSR
;
1596 case MISCREG_SP_EL0
:
1597 tc
->setIntReg(INTREG_SP0
, newVal
);
1599 case MISCREG_SP_EL1
:
1600 tc
->setIntReg(INTREG_SP1
, newVal
);
1602 case MISCREG_SP_EL2
:
1603 tc
->setIntReg(INTREG_SP2
, newVal
);
1607 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1608 cpsr
.sp
= (uint8_t) ((CPSR
) newVal
).sp
;
1610 misc_reg
= MISCREG_CPSR
;
1613 case MISCREG_CURRENTEL
:
1615 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1616 cpsr
.el
= (uint8_t) ((CPSR
) newVal
).el
;
1618 misc_reg
= MISCREG_CPSR
;
1621 case MISCREG_AT_S1E1R_Xt
:
1622 case MISCREG_AT_S1E1W_Xt
:
1623 case MISCREG_AT_S1E0R_Xt
:
1624 case MISCREG_AT_S1E0W_Xt
:
1625 case MISCREG_AT_S1E2R_Xt
:
1626 case MISCREG_AT_S1E2W_Xt
:
1627 case MISCREG_AT_S12E1R_Xt
:
1628 case MISCREG_AT_S12E1W_Xt
:
1629 case MISCREG_AT_S12E0R_Xt
:
1630 case MISCREG_AT_S12E0W_Xt
:
1631 case MISCREG_AT_S1E3R_Xt
:
1632 case MISCREG_AT_S1E3W_Xt
:
1634 RequestPtr req
= new Request
;
1635 Request::Flags flags
= 0;
1636 BaseTLB::Mode mode
= BaseTLB::Read
;
1637 TLB::ArmTranslationType tranType
= TLB::NormalTran
;
1640 case MISCREG_AT_S1E1R_Xt
:
1641 flags
= TLB::MustBeOne
;
1642 tranType
= TLB::S1E1Tran
;
1643 mode
= BaseTLB::Read
;
1645 case MISCREG_AT_S1E1W_Xt
:
1646 flags
= TLB::MustBeOne
;
1647 tranType
= TLB::S1E1Tran
;
1648 mode
= BaseTLB::Write
;
1650 case MISCREG_AT_S1E0R_Xt
:
1651 flags
= TLB::MustBeOne
| TLB::UserMode
;
1652 tranType
= TLB::S1E0Tran
;
1653 mode
= BaseTLB::Read
;
1655 case MISCREG_AT_S1E0W_Xt
:
1656 flags
= TLB::MustBeOne
| TLB::UserMode
;
1657 tranType
= TLB::S1E0Tran
;
1658 mode
= BaseTLB::Write
;
1660 case MISCREG_AT_S1E2R_Xt
:
1661 flags
= TLB::MustBeOne
;
1662 tranType
= TLB::S1E2Tran
;
1663 mode
= BaseTLB::Read
;
1665 case MISCREG_AT_S1E2W_Xt
:
1666 flags
= TLB::MustBeOne
;
1667 tranType
= TLB::S1E2Tran
;
1668 mode
= BaseTLB::Write
;
1670 case MISCREG_AT_S12E0R_Xt
:
1671 flags
= TLB::MustBeOne
| TLB::UserMode
;
1672 tranType
= TLB::S12E0Tran
;
1673 mode
= BaseTLB::Read
;
1675 case MISCREG_AT_S12E0W_Xt
:
1676 flags
= TLB::MustBeOne
| TLB::UserMode
;
1677 tranType
= TLB::S12E0Tran
;
1678 mode
= BaseTLB::Write
;
1680 case MISCREG_AT_S12E1R_Xt
:
1681 flags
= TLB::MustBeOne
;
1682 tranType
= TLB::S12E1Tran
;
1683 mode
= BaseTLB::Read
;
1685 case MISCREG_AT_S12E1W_Xt
:
1686 flags
= TLB::MustBeOne
;
1687 tranType
= TLB::S12E1Tran
;
1688 mode
= BaseTLB::Write
;
1690 case MISCREG_AT_S1E3R_Xt
:
1691 flags
= TLB::MustBeOne
;
1692 tranType
= TLB::S1E3Tran
;
1693 mode
= BaseTLB::Read
;
1695 case MISCREG_AT_S1E3W_Xt
:
1696 flags
= TLB::MustBeOne
;
1697 tranType
= TLB::S1E3Tran
;
1698 mode
= BaseTLB::Write
;
1701 // If we're in timing mode then doing the translation in
1702 // functional mode then we're slightly distorting performance
1703 // results obtained from simulations. The translation should be
1704 // done in the same mode the core is running in. NOTE: This
1705 // can't be an atomic translation because that causes problems
1706 // with unexpected atomic snoop requests.
1707 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg
);
1708 req
->setVirt(0, val
, 0, flags
, Request::funcMasterId
,
1709 tc
->pcState().pc());
1710 req
->setContext(tc
->contextId());
1711 fault
= getDTBPtr(tc
)->translateFunctional(req
, tc
, mode
,
1715 if (fault
== NoFault
) {
1716 Addr paddr
= req
->getPaddr();
1717 uint64_t attr
= getDTBPtr(tc
)->getAttr();
1718 uint64_t attr1
= attr
>> 56;
1719 if (!attr1
|| attr1
==0x44) {
1721 attr
&= ~ uint64_t(0x80);
1723 newVal
= (paddr
& mask(47, 12)) | attr
;
1725 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
1728 ArmFault
*armFault
= reinterpret_cast<ArmFault
*>(fault
.get());
1729 // Set fault bit and FSR
1730 FSR fsr
= armFault
->getFsr(tc
);
1732 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
1733 if (cpsr
.width
) { // AArch32
1734 newVal
= ((fsr
>> 9) & 1) << 11;
1735 // rearrange fault status
1736 newVal
|= ((fsr
>> 0) & 0x3f) << 1;
1737 newVal
|= 0x1; // F bit
1738 newVal
|= ((armFault
->iss() >> 7) & 0x1) << 8;
1739 newVal
|= armFault
->isStage2() ? 0x200 : 0;
1741 newVal
= 1; // F bit
1742 newVal
|= fsr
<< 1; // FST
1743 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
1744 newVal
|= armFault
->isStage2() ? 1 << 8 : 0; // PTW
1745 newVal
|= armFault
->isStage2() ? 1 << 9 : 0; // S
1746 newVal
|= 1 << 11; // RES1
1749 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
1753 setMiscRegNoEffect(MISCREG_PAR_EL1
, newVal
);
1756 case MISCREG_SPSR_EL3
:
1757 case MISCREG_SPSR_EL2
:
1758 case MISCREG_SPSR_EL1
:
1759 // Force bits 23:21 to 0
1760 newVal
= val
& ~(0x7 << 21);
1762 case MISCREG_L2CTLR
:
1763 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
1764 miscRegName
[misc_reg
], uint32_t(val
));
1767 // Generic Timer registers
1768 case MISCREG_CNTFRQ
... MISCREG_CNTHP_CTL
:
1769 case MISCREG_CNTPCT
... MISCREG_CNTHP_CVAL
:
1770 case MISCREG_CNTKCTL_EL1
... MISCREG_CNTV_CVAL_EL0
:
1771 case MISCREG_CNTVOFF_EL2
... MISCREG_CNTPS_CVAL_EL1
:
1772 getGenericTimer(tc
).setMiscReg(misc_reg
, newVal
);
1776 setMiscRegNoEffect(misc_reg
, newVal
);
1780 ISA::tlbiVA(ThreadContext
*tc
, MiscReg newVal
, uint16_t asid
,
1781 bool secure_lookup
, uint8_t target_el
)
1783 if (!haveLargeAsid64
)
1785 Addr va
= ((Addr
) bits(newVal
, 43, 0)) << 12;
1786 System
*sys
= tc
->getSystemPtr();
1787 for (int x
= 0; x
< sys
->numContexts(); x
++) {
1788 ThreadContext
*oc
= sys
->getThreadContext(x
);
1789 getITBPtr(oc
)->flushMvaAsid(va
, asid
,
1790 secure_lookup
, target_el
);
1791 getDTBPtr(oc
)->flushMvaAsid(va
, asid
,
1792 secure_lookup
, target_el
);
1794 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1796 getITBPtr(checker
)->flushMvaAsid(
1797 va
, asid
, secure_lookup
, target_el
);
1798 getDTBPtr(checker
)->flushMvaAsid(
1799 va
, asid
, secure_lookup
, target_el
);
1805 ISA::tlbiALL(ThreadContext
*tc
, bool secure_lookup
, uint8_t target_el
)
1807 System
*sys
= tc
->getSystemPtr();
1808 for (int x
= 0; x
< sys
->numContexts(); x
++) {
1809 ThreadContext
*oc
= sys
->getThreadContext(x
);
1810 getITBPtr(oc
)->flushAllSecurity(secure_lookup
, target_el
);
1811 getDTBPtr(oc
)->flushAllSecurity(secure_lookup
, target_el
);
1813 // If CheckerCPU is connected, need to notify it of a flush
1814 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1816 getITBPtr(checker
)->flushAllSecurity(secure_lookup
,
1818 getDTBPtr(checker
)->flushAllSecurity(secure_lookup
,
1825 ISA::tlbiALLN(ThreadContext
*tc
, bool hyp
, uint8_t target_el
)
1827 System
*sys
= tc
->getSystemPtr();
1828 for (int x
= 0; x
< sys
->numContexts(); x
++) {
1829 ThreadContext
*oc
= sys
->getThreadContext(x
);
1830 getITBPtr(oc
)->flushAllNs(hyp
, target_el
);
1831 getDTBPtr(oc
)->flushAllNs(hyp
, target_el
);
1833 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1835 getITBPtr(checker
)->flushAllNs(hyp
, target_el
);
1836 getDTBPtr(checker
)->flushAllNs(hyp
, target_el
);
1842 ISA::tlbiMVA(ThreadContext
*tc
, MiscReg newVal
, bool secure_lookup
, bool hyp
,
1845 System
*sys
= tc
->getSystemPtr();
1846 for (int x
= 0; x
< sys
->numContexts(); x
++) {
1847 ThreadContext
*oc
= sys
->getThreadContext(x
);
1848 getITBPtr(oc
)->flushMva(mbits(newVal
, 31,12),
1849 secure_lookup
, hyp
, target_el
);
1850 getDTBPtr(oc
)->flushMva(mbits(newVal
, 31,12),
1851 secure_lookup
, hyp
, target_el
);
1853 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
1855 getITBPtr(checker
)->flushMva(mbits(newVal
, 31,12),
1856 secure_lookup
, hyp
, target_el
);
1857 getDTBPtr(checker
)->flushMva(mbits(newVal
, 31,12),
1858 secure_lookup
, hyp
, target_el
);
1864 ISA::getGenericTimer(ThreadContext
*tc
)
1866 // We only need to create an ISA interface the first time we try
1867 // to access the timer.
1869 return *timer
.get();
1872 GenericTimer
*generic_timer(system
->getGenericTimer());
1873 if (!generic_timer
) {
1874 panic("Trying to get a generic timer from a system that hasn't "
1875 "been configured to use a generic timer.\n");
1878 timer
.reset(new GenericTimerISA(*generic_timer
, tc
->contextId()));
1879 return *timer
.get();
1885 ArmISAParams::create()
1887 return new ArmISA::ISA(this);