src/arch/arm/isa.cc

   1 /*
   2  * Copyright (c) 2010 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Gabe Black
  38  *          Ali Saidi
  39  */
  40
  41 #include "arch/arm/isa.hh"
  42
  43 namespace ArmISA
  44 {
  45
  46 void
  47 ISA::clear()
  48 {
  49     SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
  50
  51     memset(miscRegs, 0, sizeof(miscRegs));
  52     CPSR cpsr = 0;
  53     cpsr.mode = MODE_USER;
  54     miscRegs[MISCREG_CPSR] = cpsr;
  55     updateRegMap(cpsr);
  56
  57     SCTLR sctlr = 0;
  58     sctlr.te = (bool)sctlr_rst.te;
  59     sctlr.nmfi = (bool)sctlr_rst.nmfi;
  60     sctlr.v = (bool)sctlr_rst.v;
  61     sctlr.u    = 1;
  62     sctlr.xp = 1;
  63     sctlr.rao2 = 1;
  64     sctlr.rao3 = 1;
  65     sctlr.rao4 = 1;
  66     miscRegs[MISCREG_SCTLR] = sctlr;
  67     miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
  68
  69
  70     /*
  71      * Technically this should be 0, but we don't support those
  72      * settings.
  73      */
  74     CPACR cpacr = 0;
  75     // Enable CP 10, 11
  76     cpacr.cp10 = 0x3;
  77     cpacr.cp11 = 0x3;
  78     miscRegs[MISCREG_CPACR] = cpacr;
  79
  80     /* Start with an event in the mailbox */
  81     miscRegs[MISCREG_SEV_MAILBOX] = 1;
  82
  83     /*
  84      * Implemented = '5' from "M5",
  85      * Variant = 0,
  86      */
  87     miscRegs[MISCREG_MIDR] =
  88         (0x35 << 24) | //Implementor is '5' from "M5"
  89         (0 << 20)    | //Variant
  90         (0xf << 16)  | //Architecture from CPUID scheme
  91         (0 << 4)     | //Primary part number
  92         (0 << 0)     | //Revision
  93         0;
  94
  95     // Separate Instruction and Data TLBs.
  96     miscRegs[MISCREG_TLBTR] = 1;
  97
  98     MVFR0 mvfr0 = 0;
  99     mvfr0.advSimdRegisters = 2;
 100     mvfr0.singlePrecision = 2;
 101     mvfr0.doublePrecision = 2;
 102     mvfr0.vfpExceptionTrapping = 0;
 103     mvfr0.divide = 1;
 104     mvfr0.squareRoot = 1;
 105     mvfr0.shortVectors = 1;
 106     mvfr0.roundingModes = 1;
 107     miscRegs[MISCREG_MVFR0] = mvfr0;
 108
 109     MVFR1 mvfr1 = 0;
 110     mvfr1.flushToZero = 1;
 111     mvfr1.defaultNaN = 1;
 112     mvfr1.advSimdLoadStore = 1;
 113     mvfr1.advSimdInteger = 1;
 114     mvfr1.advSimdSinglePrecision = 1;
 115     mvfr1.advSimdHalfPrecision = 1;
 116     mvfr1.vfpHalfPrecision = 1;
 117     miscRegs[MISCREG_MVFR1] = mvfr1;
 118
 119     miscRegs[MISCREG_MPIDR] = 0;
 120
 121     // Reset values of PRRR and NMRR are implementation dependent
 122
 123     miscRegs[MISCREG_PRRR] =
 124         (1 << 19) | // 19
 125         (0 << 18) | // 18
 126         (0 << 17) | // 17
 127         (1 << 16) | // 16
 128         (2 << 14) | // 15:14
 129         (0 << 12) | // 13:12
 130         (2 << 10) | // 11:10
 131         (2 << 8)  | // 9:8
 132         (2 << 6)  | // 7:6
 133         (2 << 4)  | // 5:4
 134         (1 << 2)  | // 3:2
 135         0;          // 1:0
 136     miscRegs[MISCREG_NMRR] =
 137         (1 << 30) | // 31:30
 138         (0 << 26) | // 27:26
 139         (0 << 24) | // 25:24
 140         (3 << 22) | // 23:22
 141         (2 << 20) | // 21:20
 142         (0 << 18) | // 19:18
 143         (0 << 16) | // 17:16
 144         (1 << 14) | // 15:14
 145         (0 << 12) | // 13:12
 146         (2 << 10) | // 11:10
 147         (0 << 8)  | // 9:8
 148         (3 << 6)  | // 7:6
 149         (2 << 4)  | // 5:4
 150         (0 << 2)  | // 3:2
 151         0;          // 1:0
 152
 153     //XXX We need to initialize the rest of the state.
 154 }
 155
 156 MiscReg
 157 ISA::readMiscRegNoEffect(int misc_reg)
 158 {
 159     assert(misc_reg < NumMiscRegs);
 160
 161     int flat_idx;
 162     if (misc_reg == MISCREG_SPSR)
 163         flat_idx = flattenMiscIndex(misc_reg);
 164     else
 165         flat_idx = misc_reg;
 166     MiscReg val = miscRegs[flat_idx];
 167
 168     DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n",
 169             misc_reg, flat_idx, val);
 170     return val;
 171 }
 172
 173
 174 MiscReg
 175 ISA::readMiscReg(int misc_reg, ThreadContext *tc)
 176 {
 177     if (misc_reg == MISCREG_CPSR) {
 178         CPSR cpsr = miscRegs[misc_reg];
 179         Addr pc = tc->readPC();
 180         if (pc & (ULL(1) << PcJBitShift))
 181             cpsr.j = 1;
 182         else
 183             cpsr.j = 0;
 184         if (pc & (ULL(1) << PcTBitShift))
 185             cpsr.t = 1;
 186         else
 187             cpsr.t = 0;
 188         return cpsr;
 189     }
 190     if (misc_reg >= MISCREG_CP15_UNIMP_START &&
 191         misc_reg < MISCREG_CP15_END) {
 192         panic("Unimplemented CP15 register %s read.\n",
 193               miscRegName[misc_reg]);
 194     }
 195     switch (misc_reg) {
 196       case MISCREG_CLIDR:
 197         warn("The clidr register always reports 0 caches.\n");
 198         break;
 199       case MISCREG_CCSIDR:
 200         warn("The ccsidr register isn't implemented and "
 201                 "always reads as 0.\n");
 202         break;
 203       case MISCREG_ID_PFR0:
 204         warn("Returning thumbEE disabled for now since we don't support CP14"
 205              "config registers and jumping to ThumbEE vectors\n");
 206         return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
 207       case MISCREG_ID_MMFR0:
 208         return 0x03; //VMSAz7
 209       case MISCREG_CTR:
 210         return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
 211       case MISCREG_ACTLR:
 212         warn("Not doing anything for miscreg ACTLR\n");
 213         break;
 214       case MISCREG_PMCR:
 215       case MISCREG_PMCCNTR:
 216       case MISCREG_PMSELR:
 217         warn("Not doing anyhting for read to miscreg %s\n",
 218                 miscRegName[misc_reg]);
 219         break;
 220
 221     }
 222     return readMiscRegNoEffect(misc_reg);
 223 }
 224
 225 void
 226 ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
 227 {
 228     assert(misc_reg < NumMiscRegs);
 229
 230     int flat_idx;
 231     if (misc_reg == MISCREG_SPSR)
 232         flat_idx = flattenMiscIndex(misc_reg);
 233     else
 234         flat_idx = misc_reg;
 235     miscRegs[flat_idx] = val;
 236
 237     DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg,
 238             flat_idx, val);
 239 }
 240
 241 void
 242 ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
 243 {
 244     MiscReg newVal = val;
 245     if (misc_reg == MISCREG_CPSR) {
 246         updateRegMap(val);
 247         CPSR cpsr = val;
 248         DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
 249                 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
 250         Addr npc = tc->readNextPC() & ~PcModeMask;
 251         if (cpsr.j)
 252             npc = npc | (ULL(1) << PcJBitShift);
 253         if (cpsr.t)
 254             npc = npc | (ULL(1) << PcTBitShift);
 255
 256         tc->setNextPC(npc);
 257     } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
 258         misc_reg < MISCREG_CP15_END) {
 259         panic("Unimplemented CP15 register %s wrote with %#x.\n",
 260               miscRegName[misc_reg], val);
 261     } else {
 262         switch (misc_reg) {
 263           case MISCREG_ITSTATE:
 264             {
 265                 ITSTATE itstate = newVal;
 266                 CPSR cpsr = miscRegs[MISCREG_CPSR];
 267                 cpsr.it1 = itstate.bottom2;
 268                 cpsr.it2 = itstate.top6;
 269                 miscRegs[MISCREG_CPSR] = cpsr;
 270                 DPRINTF(MiscRegs,
 271                         "Updating ITSTATE -> %#x in CPSR -> %#x.\n",
 272                         (uint8_t)itstate, (uint32_t)cpsr);
 273             }
 274             break;
 275           case MISCREG_CPACR:
 276             {
 277                 CPACR newCpacr = 0;
 278                 CPACR valCpacr = val;
 279                 newCpacr.cp10 = valCpacr.cp10;
 280                 newCpacr.cp11 = valCpacr.cp11;
 281                 if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) {
 282                     panic("Disabling coprocessors isn't implemented.\n");
 283                 }
 284                 newVal = newCpacr;
 285             }
 286             break;
 287           case MISCREG_CSSELR:
 288             warn("The csselr register isn't implemented.\n");
 289             break;
 290           case MISCREG_FPSCR:
 291             {
 292                 const uint32_t ones = (uint32_t)(-1);
 293                 FPSCR fpscrMask = 0;
 294                 fpscrMask.ioc = ones;
 295                 fpscrMask.dzc = ones;
 296                 fpscrMask.ofc = ones;
 297                 fpscrMask.ufc = ones;
 298                 fpscrMask.ixc = ones;
 299                 fpscrMask.idc = ones;
 300                 fpscrMask.len = ones;
 301                 fpscrMask.stride = ones;
 302                 fpscrMask.rMode = ones;
 303                 fpscrMask.fz = ones;
 304                 fpscrMask.dn = ones;
 305                 fpscrMask.ahp = ones;
 306                 fpscrMask.qc = ones;
 307                 fpscrMask.v = ones;
 308                 fpscrMask.c = ones;
 309                 fpscrMask.z = ones;
 310                 fpscrMask.n = ones;
 311                 newVal = (newVal & (uint32_t)fpscrMask) |
 312                          (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
 313             }
 314             break;
 315           case MISCREG_FPEXC:
 316             {
 317                 const uint32_t fpexcMask = 0x60000000;
 318                 newVal = (newVal & fpexcMask) |
 319                          (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
 320             }
 321             break;
 322           case MISCREG_SCTLR:
 323             {
 324                 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
 325                 SCTLR sctlr = miscRegs[MISCREG_SCTLR];
 326                 SCTLR new_sctlr = newVal;
 327                 new_sctlr.nmfi =  (bool)sctlr.nmfi;
 328                 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
 329                 return;
 330             }
 331           case MISCREG_TLBTR:
 332           case MISCREG_MVFR0:
 333           case MISCREG_MVFR1:
 334           case MISCREG_MPIDR:
 335           case MISCREG_FPSID:
 336             return;
 337           case MISCREG_TLBIALLIS:
 338           case MISCREG_TLBIALL:
 339             warn("Need to flush all TLBs in MP\n");
 340             tc->getITBPtr()->flushAll();
 341             tc->getDTBPtr()->flushAll();
 342             return;
 343           case MISCREG_ITLBIALL:
 344             tc->getITBPtr()->flushAll();
 345             return;
 346           case MISCREG_DTLBIALL:
 347             tc->getDTBPtr()->flushAll();
 348             return;
 349           case MISCREG_TLBIMVAIS:
 350           case MISCREG_TLBIMVA:
 351             warn("Need to flush all TLBs in MP\n");
 352             tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
 353                     bits(newVal, 7,0));
 354             tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
 355                     bits(newVal, 7,0));
 356             return;
 357           case MISCREG_TLBIASIDIS:
 358           case MISCREG_TLBIASID:
 359             warn("Need to flush all TLBs in MP\n");
 360             tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
 361             tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
 362             return;
 363           case MISCREG_TLBIMVAAIS:
 364           case MISCREG_TLBIMVAA:
 365             warn("Need to flush all TLBs in MP\n");
 366             tc->getITBPtr()->flushMva(mbits(newVal, 31,12));
 367             tc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
 368             return;
 369           case MISCREG_ITLBIMVA:
 370             tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
 371                     bits(newVal, 7,0));
 372             return;
 373           case MISCREG_DTLBIMVA:
 374             tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
 375                     bits(newVal, 7,0));
 376             return;
 377           case MISCREG_ITLBIASID:
 378             tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
 379             return;
 380           case MISCREG_DTLBIASID:
 381             tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
 382             return;
 383           case MISCREG_ACTLR:
 384             warn("Not doing anything for write of miscreg ACTLR\n");
 385             break;
 386           case MISCREG_PMCR:
 387           case MISCREG_PMCCNTR:
 388           case MISCREG_PMSELR:
 389             warn("Not doing anything for write to miscreg %s\n",
 390                     miscRegName[misc_reg]);
 391             break;
 392           case MISCREG_V2PCWPR:
 393           case MISCREG_V2PCWPW:
 394           case MISCREG_V2PCWUR:
 395           case MISCREG_V2PCWUW:
 396           case MISCREG_V2POWPR:
 397           case MISCREG_V2POWPW:
 398           case MISCREG_V2POWUR:
 399           case MISCREG_V2POWUW:
 400             {
 401               RequestPtr req = new Request;
 402               unsigned flags;
 403               BaseTLB::Mode mode;
 404               Fault fault;
 405               switch(misc_reg) {
 406                   case MISCREG_V2PCWPR:
 407                       flags = TLB::MustBeOne;
 408                       mode = BaseTLB::Read;
 409                       break;
 410                   case MISCREG_V2PCWPW:
 411                       flags = TLB::MustBeOne;
 412                       mode = BaseTLB::Write;
 413                       break;
 414                   case MISCREG_V2PCWUR:
 415                       flags = TLB::MustBeOne | TLB::UserMode;
 416                       mode = BaseTLB::Read;
 417                       break;
 418                   case MISCREG_V2PCWUW:
 419                       flags = TLB::MustBeOne | TLB::UserMode;
 420                       mode = BaseTLB::Write;
 421                       break;
 422                   default:
 423                       panic("Security Extensions not implemented!");
 424               }
 425               req->setVirt(0, val, 1, flags, tc->readPC());
 426               fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
 427               if (fault == NoFault) {
 428                   miscRegs[MISCREG_PAR] =
 429                       (req->getPaddr() & 0xfffff000) |
 430                       (tc->getDTBPtr()->getAttr() );
 431                   DPRINTF(MiscRegs,
 432                           "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
 433                           val, miscRegs[MISCREG_PAR]);
 434               }
 435               else {
 436                   // Set fault bit and FSR
 437                   FSR fsr = miscRegs[MISCREG_DFSR];
 438                   miscRegs[MISCREG_PAR] =
 439                       (fsr.ext << 6) |
 440                       (fsr.fsHigh << 5) |
 441                       (fsr.fsLow << 1) |
 442                       0x1; // F bit
 443               }
 444               return;
 445             }
 446         }
 447     }
 448     setMiscRegNoEffect(misc_reg, newVal);
 449 }
 450
 451 }