2 * Copyright (c) 2010-2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
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15 * modification, are permitted provided that the following conditions are
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17 * notice, this list of conditions and the following disclaimer;
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23 * this software without specific prior written permission.
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 #include "arch/arm/isa.hh"
42 #include "arch/arm/system.hh"
43 #include "cpu/checker/cpu.hh"
44 #include "debug/Arm.hh"
45 #include "debug/MiscRegs.hh"
46 #include "sim/faults.hh"
47 #include "sim/stat_control.hh"
48 #include "sim/system.hh"
56 SCTLR sctlr_rst
= miscRegs
[MISCREG_SCTLR_RST
];
57 uint32_t midr
= miscRegs
[MISCREG_MIDR
];
58 memset(miscRegs
, 0, sizeof(miscRegs
));
60 cpsr
.mode
= MODE_USER
;
61 miscRegs
[MISCREG_CPSR
] = cpsr
;
65 sctlr
.te
= (bool)sctlr_rst
.te
;
66 sctlr
.nmfi
= (bool)sctlr_rst
.nmfi
;
67 sctlr
.v
= (bool)sctlr_rst
.v
;
73 miscRegs
[MISCREG_SCTLR
] = sctlr
;
74 miscRegs
[MISCREG_SCTLR_RST
] = sctlr_rst
;
76 // Preserve MIDR across reset
77 miscRegs
[MISCREG_MIDR
] = midr
;
79 /* Start with an event in the mailbox */
80 miscRegs
[MISCREG_SEV_MAILBOX
] = 1;
82 // Separate Instruction and Data TLBs.
83 miscRegs
[MISCREG_TLBTR
] = 1;
86 mvfr0
.advSimdRegisters
= 2;
87 mvfr0
.singlePrecision
= 2;
88 mvfr0
.doublePrecision
= 2;
89 mvfr0
.vfpExceptionTrapping
= 0;
92 mvfr0
.shortVectors
= 1;
93 mvfr0
.roundingModes
= 1;
94 miscRegs
[MISCREG_MVFR0
] = mvfr0
;
97 mvfr1
.flushToZero
= 1;
99 mvfr1
.advSimdLoadStore
= 1;
100 mvfr1
.advSimdInteger
= 1;
101 mvfr1
.advSimdSinglePrecision
= 1;
102 mvfr1
.advSimdHalfPrecision
= 1;
103 mvfr1
.vfpHalfPrecision
= 1;
104 miscRegs
[MISCREG_MVFR1
] = mvfr1
;
106 // Reset values of PRRR and NMRR are implementation dependent
108 miscRegs
[MISCREG_PRRR
] =
121 miscRegs
[MISCREG_NMRR
] =
138 miscRegs
[MISCREG_CPACR
] = 0;
139 miscRegs
[MISCREG_FPSID
] = 0x410430A0;
141 // See section B4.1.84 of ARM ARM
142 // All values are latest for ARMv7-A profile
143 miscRegs
[MISCREG_ID_ISAR0
] = 0x02101111;
144 miscRegs
[MISCREG_ID_ISAR1
] = 0x02112111;
145 miscRegs
[MISCREG_ID_ISAR2
] = 0x21232141;
146 miscRegs
[MISCREG_ID_ISAR3
] = 0x01112131;
147 miscRegs
[MISCREG_ID_ISAR4
] = 0x10010142;
148 miscRegs
[MISCREG_ID_ISAR5
] = 0x00000000;
150 //XXX We need to initialize the rest of the state.
154 ISA::readMiscRegNoEffect(int misc_reg
)
156 assert(misc_reg
< NumMiscRegs
);
159 if (misc_reg
== MISCREG_SPSR
)
160 flat_idx
= flattenMiscIndex(misc_reg
);
163 MiscReg val
= miscRegs
[flat_idx
];
165 DPRINTF(MiscRegs
, "Reading From misc reg %d (%d) : %#x\n",
166 misc_reg
, flat_idx
, val
);
172 ISA::readMiscReg(int misc_reg
, ThreadContext
*tc
)
176 if (misc_reg
== MISCREG_CPSR
) {
177 CPSR cpsr
= miscRegs
[misc_reg
];
178 PCState pc
= tc
->pcState();
179 cpsr
.j
= pc
.jazelle() ? 1 : 0;
180 cpsr
.t
= pc
.thumb() ? 1 : 0;
183 if (misc_reg
>= MISCREG_CP15_UNIMP_START
)
184 panic("Unimplemented CP15 register %s read.\n",
185 miscRegName
[misc_reg
]);
189 arm_sys
= dynamic_cast<ArmSystem
*>(tc
->getSystemPtr());
192 if (arm_sys
->multiProc
) {
193 return 0x80000000 | // multiprocessor extensions available
196 return 0x80000000 | // multiprocessor extensions available
197 0x40000000 | // in up system
201 case MISCREG_ID_MMFR0
:
202 return 0x03; // VMSAv7 support
203 case MISCREG_ID_MMFR2
:
204 return 0x01230000; // no HW access | WFI stalling | ISB and DSB
205 // | all TLB maintenance | no Harvard
206 case MISCREG_ID_MMFR3
:
207 return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint |
208 // BP Maint | Cache Maint Set/way | Cache Maint MVA
210 warn_once("The clidr register always reports 0 caches.\n");
211 warn_once("clidr LoUIS field of 0b001 to match current "
212 "ARM implementations.\n");
215 warn_once("The ccsidr register isn't implemented and "
216 "always reads as 0.\n");
218 case MISCREG_ID_PFR0
:
219 warn("Returning thumbEE disabled for now since we don't support CP14"
220 "config registers and jumping to ThumbEE vectors\n");
221 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
222 case MISCREG_ID_PFR1
:
223 return 0x00001; // !Timer | !Virti | !M Profile | !TrustZone | ARMv4
226 //all caches have the same line size in gem5
227 //4 byte words in ARM
228 unsigned lineSizeWords
=
229 tc
->getCpuPtr()->getInstPort().peerBlockSize() / 4;
230 unsigned log2LineSizeWords
= 0;
232 while (lineSizeWords
>>= 1) {
237 //log2 of minimun i-cache line size (words)
238 ctr
.iCacheLineSize
= log2LineSizeWords
;
239 //b11 - gem5 uses pipt
240 ctr
.l1IndexPolicy
= 0x3;
241 //log2 of minimum d-cache line size (words)
242 ctr
.dCacheLineSize
= log2LineSizeWords
;
243 //log2 of max reservation size (words)
244 ctr
.erg
= log2LineSizeWords
;
245 //log2 of max writeback size (words)
246 ctr
.cwg
= log2LineSizeWords
;
247 //b100 - gem5 format is ARMv7
253 warn("Not doing anything for miscreg ACTLR\n");
256 case MISCREG_PMCCNTR
:
258 warn("Not doing anything for read to miscreg %s\n",
259 miscRegName
[misc_reg
]);
262 panic("shouldn't be reading this register seperately\n");
263 case MISCREG_FPSCR_QC
:
264 return readMiscRegNoEffect(MISCREG_FPSCR
) & ~FpscrQcMask
;
265 case MISCREG_FPSCR_EXC
:
266 return readMiscRegNoEffect(MISCREG_FPSCR
) & ~FpscrExcMask
;
269 // mostly unimplemented, just set NumCPUs field from sim and return
271 // b00:1CPU to b11:4CPUs
272 l2ctlr
.numCPUs
= tc
->getSystemPtr()->numContexts() - 1;
275 case MISCREG_DBGDIDR
:
276 /* For now just implement the version number.
277 * Return 0 as we don't support debug architecture yet.
280 case MISCREG_DBGDSCR_INT
:
283 return readMiscRegNoEffect(misc_reg
);
287 ISA::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
)
289 assert(misc_reg
< NumMiscRegs
);
292 if (misc_reg
== MISCREG_SPSR
)
293 flat_idx
= flattenMiscIndex(misc_reg
);
296 miscRegs
[flat_idx
] = val
;
298 DPRINTF(MiscRegs
, "Writing to misc reg %d (%d) : %#x\n", misc_reg
,
303 ISA::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadContext
*tc
)
306 MiscReg newVal
= val
;
311 if (misc_reg
== MISCREG_CPSR
) {
315 CPSR old_cpsr
= miscRegs
[MISCREG_CPSR
];
316 int old_mode
= old_cpsr
.mode
;
318 if (old_mode
!= cpsr
.mode
) {
319 tc
->getITBPtr()->invalidateMiscReg();
320 tc
->getDTBPtr()->invalidateMiscReg();
323 DPRINTF(Arm
, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
324 miscRegs
[misc_reg
], cpsr
, cpsr
.f
, cpsr
.i
, cpsr
.a
, cpsr
.mode
);
325 PCState pc
= tc
->pcState();
326 pc
.nextThumb(cpsr
.t
);
327 pc
.nextJazelle(cpsr
.j
);
329 // Follow slightly different semantics if a CheckerCPU object
331 CheckerCPU
*checker
= tc
->getCheckerCpuPtr();
333 tc
->pcStateNoRecord(pc
);
337 } else if (misc_reg
>= MISCREG_CP15_UNIMP_START
&&
338 misc_reg
< MISCREG_CP15_END
) {
339 panic("Unimplemented CP15 register %s wrote with %#x.\n",
340 miscRegName
[misc_reg
], val
);
346 const uint32_t ones
= (uint32_t)(-1);
348 // Only cp10, cp11, and ase are implemented, nothing else should
350 cpacrMask
.cp10
= ones
;
351 cpacrMask
.cp11
= ones
;
352 cpacrMask
.asedis
= ones
;
354 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
355 miscRegName
[misc_reg
], newVal
);
359 warn_once("The csselr register isn't implemented.\n");
363 const uint32_t ones
= (uint32_t)(-1);
365 fpscrMask
.ioc
= ones
;
366 fpscrMask
.dzc
= ones
;
367 fpscrMask
.ofc
= ones
;
368 fpscrMask
.ufc
= ones
;
369 fpscrMask
.ixc
= ones
;
370 fpscrMask
.idc
= ones
;
371 fpscrMask
.len
= ones
;
372 fpscrMask
.stride
= ones
;
373 fpscrMask
.rMode
= ones
;
376 fpscrMask
.ahp
= ones
;
382 newVal
= (newVal
& (uint32_t)fpscrMask
) |
383 (miscRegs
[MISCREG_FPSCR
] & ~(uint32_t)fpscrMask
);
384 tc
->getDecoderPtr()->setContext(newVal
);
389 assert(!(newVal
& ~CpsrMaskQ
));
390 newVal
= miscRegs
[MISCREG_CPSR
] | newVal
;
391 misc_reg
= MISCREG_CPSR
;
394 case MISCREG_FPSCR_QC
:
396 newVal
= miscRegs
[MISCREG_FPSCR
] | (newVal
& FpscrQcMask
);
397 misc_reg
= MISCREG_FPSCR
;
400 case MISCREG_FPSCR_EXC
:
402 newVal
= miscRegs
[MISCREG_FPSCR
] | (newVal
& FpscrExcMask
);
403 misc_reg
= MISCREG_FPSCR
;
408 // vfpv3 architecture, section B.6.1 of DDI04068
409 // bit 29 - valid only if fpexc[31] is 0
410 const uint32_t fpexcMask
= 0x60000000;
411 newVal
= (newVal
& fpexcMask
) |
412 (miscRegs
[MISCREG_FPEXC
] & ~fpexcMask
);
417 DPRINTF(MiscRegs
, "Writing SCTLR: %#x\n", newVal
);
418 SCTLR sctlr
= miscRegs
[MISCREG_SCTLR
];
419 SCTLR new_sctlr
= newVal
;
420 new_sctlr
.nmfi
= (bool)sctlr
.nmfi
;
421 miscRegs
[MISCREG_SCTLR
] = (MiscReg
)new_sctlr
;
422 tc
->getITBPtr()->invalidateMiscReg();
423 tc
->getDTBPtr()->invalidateMiscReg();
425 // Check if all CPUs are booted with caches enabled
426 // so we can stop enforcing coherency of some kernel
427 // structures manually.
428 sys
= tc
->getSystemPtr();
429 for (x
= 0; x
< sys
->numContexts(); x
++) {
430 oc
= sys
->getThreadContext(x
);
431 SCTLR other_sctlr
= oc
->readMiscRegNoEffect(MISCREG_SCTLR
);
432 if (!other_sctlr
.c
&& oc
->status() != ThreadContext::Halted
)
436 for (x
= 0; x
< sys
->numContexts(); x
++) {
437 oc
= sys
->getThreadContext(x
);
438 oc
->getDTBPtr()->allCpusCaching();
439 oc
->getITBPtr()->allCpusCaching();
441 // If CheckerCPU is connected, need to notify it.
442 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
444 checker
->getDTBPtr()->allCpusCaching();
445 checker
->getITBPtr()->allCpusCaching();
456 case MISCREG_TLBIALLIS
:
457 case MISCREG_TLBIALL
:
458 sys
= tc
->getSystemPtr();
459 for (x
= 0; x
< sys
->numContexts(); x
++) {
460 oc
= sys
->getThreadContext(x
);
461 assert(oc
->getITBPtr() && oc
->getDTBPtr());
462 oc
->getITBPtr()->flushAll();
463 oc
->getDTBPtr()->flushAll();
465 // If CheckerCPU is connected, need to notify it of a flush
466 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
468 checker
->getITBPtr()->flushAll();
469 checker
->getDTBPtr()->flushAll();
473 case MISCREG_ITLBIALL
:
474 tc
->getITBPtr()->flushAll();
476 case MISCREG_DTLBIALL
:
477 tc
->getDTBPtr()->flushAll();
479 case MISCREG_TLBIMVAIS
:
480 case MISCREG_TLBIMVA
:
481 sys
= tc
->getSystemPtr();
482 for (x
= 0; x
< sys
->numContexts(); x
++) {
483 oc
= sys
->getThreadContext(x
);
484 assert(oc
->getITBPtr() && oc
->getDTBPtr());
485 oc
->getITBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
487 oc
->getDTBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
490 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
492 checker
->getITBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
494 checker
->getDTBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
499 case MISCREG_TLBIASIDIS
:
500 case MISCREG_TLBIASID
:
501 sys
= tc
->getSystemPtr();
502 for (x
= 0; x
< sys
->numContexts(); x
++) {
503 oc
= sys
->getThreadContext(x
);
504 assert(oc
->getITBPtr() && oc
->getDTBPtr());
505 oc
->getITBPtr()->flushAsid(bits(newVal
, 7,0));
506 oc
->getDTBPtr()->flushAsid(bits(newVal
, 7,0));
507 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
509 checker
->getITBPtr()->flushAsid(bits(newVal
, 7,0));
510 checker
->getDTBPtr()->flushAsid(bits(newVal
, 7,0));
514 case MISCREG_TLBIMVAAIS
:
515 case MISCREG_TLBIMVAA
:
516 sys
= tc
->getSystemPtr();
517 for (x
= 0; x
< sys
->numContexts(); x
++) {
518 oc
= sys
->getThreadContext(x
);
519 assert(oc
->getITBPtr() && oc
->getDTBPtr());
520 oc
->getITBPtr()->flushMva(mbits(newVal
, 31,12));
521 oc
->getDTBPtr()->flushMva(mbits(newVal
, 31,12));
523 CheckerCPU
*checker
= oc
->getCheckerCpuPtr();
525 checker
->getITBPtr()->flushMva(mbits(newVal
, 31,12));
526 checker
->getDTBPtr()->flushMva(mbits(newVal
, 31,12));
530 case MISCREG_ITLBIMVA
:
531 tc
->getITBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
534 case MISCREG_DTLBIMVA
:
535 tc
->getDTBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
538 case MISCREG_ITLBIASID
:
539 tc
->getITBPtr()->flushAsid(bits(newVal
, 7,0));
541 case MISCREG_DTLBIASID
:
542 tc
->getDTBPtr()->flushAsid(bits(newVal
, 7,0));
545 warn("Not doing anything for write of miscreg ACTLR\n");
549 // Performance counters not implemented. Instead, interpret
550 // a reset command to this register to reset the simulator
552 // PMCR_E | PMCR_P | PMCR_C
553 const int ResetAndEnableCounters
= 0x7;
554 if (newVal
== ResetAndEnableCounters
) {
555 inform("Resetting all simobject stats\n");
556 Stats::schedStatEvent(false, true);
560 case MISCREG_PMCCNTR
:
562 warn("Not doing anything for write to miscreg %s\n",
563 miscRegName
[misc_reg
]);
565 case MISCREG_V2PCWPR
:
566 case MISCREG_V2PCWPW
:
567 case MISCREG_V2PCWUR
:
568 case MISCREG_V2PCWUW
:
569 case MISCREG_V2POWPR
:
570 case MISCREG_V2POWPW
:
571 case MISCREG_V2POWUR
:
572 case MISCREG_V2POWUW
:
574 RequestPtr req
= new Request
;
579 case MISCREG_V2PCWPR
:
580 flags
= TLB::MustBeOne
;
581 mode
= BaseTLB::Read
;
583 case MISCREG_V2PCWPW
:
584 flags
= TLB::MustBeOne
;
585 mode
= BaseTLB::Write
;
587 case MISCREG_V2PCWUR
:
588 flags
= TLB::MustBeOne
| TLB::UserMode
;
589 mode
= BaseTLB::Read
;
591 case MISCREG_V2PCWUW
:
592 flags
= TLB::MustBeOne
| TLB::UserMode
;
593 mode
= BaseTLB::Write
;
596 panic("Security Extensions not implemented!");
598 warn("Translating via MISCREG in atomic mode! Fix Me!\n");
599 req
->setVirt(0, val
, 1, flags
, tc
->pcState().pc(),
600 Request::funcMasterId
);
601 fault
= tc
->getDTBPtr()->translateAtomic(req
, tc
, mode
);
602 if (fault
== NoFault
) {
603 miscRegs
[MISCREG_PAR
] =
604 (req
->getPaddr() & 0xfffff000) |
605 (tc
->getDTBPtr()->getAttr() );
607 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
608 val
, miscRegs
[MISCREG_PAR
]);
611 // Set fault bit and FSR
612 FSR fsr
= miscRegs
[MISCREG_DFSR
];
613 miscRegs
[MISCREG_PAR
] =
621 case MISCREG_CONTEXTIDR
:
625 tc
->getITBPtr()->invalidateMiscReg();
626 tc
->getDTBPtr()->invalidateMiscReg();
628 case MISCREG_CPSR_MODE
:
629 // This miscreg is used by copy*Regs to set the CPSR mode
630 // without updating other CPSR variables. It's used to
631 // make sure the register map is in such a state that we can
632 // see all of the registers for the copy.
636 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
637 miscRegName
[misc_reg
], uint32_t(val
));
640 setMiscRegNoEffect(misc_reg
, newVal
);