2 * Copyright (c) 2010-2018 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
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23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 #include "arch/arm/isa.hh"
42 #include "arch/arm/pmu.hh"
43 #include "arch/arm/system.hh"
44 #include "arch/arm/tlb.hh"
45 #include "arch/arm/tlbi_op.hh"
46 #include "cpu/base.hh"
47 #include "cpu/checker/cpu.hh"
48 #include "debug/Arm.hh"
49 #include "debug/MiscRegs.hh"
50 #include "dev/arm/generic_timer.hh"
51 #include "params/ArmISA.hh"
52 #include "sim/faults.hh"
53 #include "sim/stat_control.hh"
54 #include "sim/system.hh"
62 _decoderFlavour(p
->decoderFlavour
),
63 _vecRegRenameMode(p
->vecRegRenameMode
),
66 miscRegs
[MISCREG_SCTLR_RST
] = 0;
68 // Hook up a dummy device if we haven't been configured with a
69 // real PMU. By using a dummy device, we don't need to check that
70 // the PMU exist every time we try to access a PMU register.
74 // Give all ISA devices a pointer to this ISA
77 system
= dynamic_cast<ArmSystem
*>(p
->system
);
79 // Cache system-level properties
80 if (FullSystem
&& system
) {
81 highestELIs64
= system
->highestELIs64();
82 haveSecurity
= system
->haveSecurity();
83 haveLPAE
= system
->haveLPAE();
84 haveVirtualization
= system
->haveVirtualization();
85 haveLargeAsid64
= system
->haveLargeAsid64();
86 physAddrRange64
= system
->physAddrRange64();
88 highestELIs64
= true; // ArmSystem::highestELIs64 does the same
89 haveSecurity
= haveLPAE
= haveVirtualization
= false;
90 haveLargeAsid64
= false;
91 physAddrRange64
= 32; // dummy value
94 initializeMiscRegMetadata();
95 preUnflattenMiscReg();
100 std::vector
<struct ISA::MiscRegLUTEntry
> ISA::lookUpMiscReg(NUM_MISCREGS
);
105 return dynamic_cast<const Params
*>(_params
);
111 const Params
*p(params());
113 SCTLR sctlr_rst
= miscRegs
[MISCREG_SCTLR_RST
];
114 memset(miscRegs
, 0, sizeof(miscRegs
));
116 // Initialize configurable default values
117 miscRegs
[MISCREG_MIDR
] = p
->midr
;
118 miscRegs
[MISCREG_MIDR_EL1
] = p
->midr
;
119 miscRegs
[MISCREG_VPIDR
] = p
->midr
;
121 if (FullSystem
&& system
->highestELIs64()) {
122 // Initialize AArch64 state
127 // Initialize AArch32 state...
130 cpsr
.mode
= MODE_USER
;
131 miscRegs
[MISCREG_CPSR
] = cpsr
;
135 sctlr
.te
= (bool) sctlr_rst
.te
;
136 sctlr
.nmfi
= (bool) sctlr_rst
.nmfi
;
137 sctlr
.v
= (bool) sctlr_rst
.v
;
142 sctlr
.rao4
= 0xf; // SCTLR[6:3]
145 miscRegs
[MISCREG_SCTLR_NS
] = sctlr
;
146 miscRegs
[MISCREG_SCTLR_RST
] = sctlr_rst
;
147 miscRegs
[MISCREG_HCPTR
] = 0;
149 // Start with an event in the mailbox
150 miscRegs
[MISCREG_SEV_MAILBOX
] = 1;
152 // Separate Instruction and Data TLBs
153 miscRegs
[MISCREG_TLBTR
] = 1;
156 mvfr0
.advSimdRegisters
= 2;
157 mvfr0
.singlePrecision
= 2;
158 mvfr0
.doublePrecision
= 2;
159 mvfr0
.vfpExceptionTrapping
= 0;
161 mvfr0
.squareRoot
= 1;
162 mvfr0
.shortVectors
= 1;
163 mvfr0
.roundingModes
= 1;
164 miscRegs
[MISCREG_MVFR0
] = mvfr0
;
167 mvfr1
.flushToZero
= 1;
168 mvfr1
.defaultNaN
= 1;
169 mvfr1
.advSimdLoadStore
= 1;
170 mvfr1
.advSimdInteger
= 1;
171 mvfr1
.advSimdSinglePrecision
= 1;
172 mvfr1
.advSimdHalfPrecision
= 1;
173 mvfr1
.vfpHalfPrecision
= 1;
174 miscRegs
[MISCREG_MVFR1
] = mvfr1
;
176 // Reset values of PRRR and NMRR are implementation dependent
178 // @todo: PRRR and NMRR in secure state?
179 miscRegs
[MISCREG_PRRR_NS
] =
192 miscRegs
[MISCREG_NMRR_NS
] =
209 miscRegs
[MISCREG_CPACR
] = 0;
211 miscRegs
[MISCREG_ID_MMFR0
] = p
->id_mmfr0
;
212 miscRegs
[MISCREG_ID_MMFR1
] = p
->id_mmfr1
;
213 miscRegs
[MISCREG_ID_MMFR2
] = p
->id_mmfr2
;
214 miscRegs
[MISCREG_ID_MMFR3
] = p
->id_mmfr3
;
216 miscRegs
[MISCREG_ID_ISAR0
] = p
->id_isar0
;
217 miscRegs
[MISCREG_ID_ISAR1
] = p
->id_isar1
;
218 miscRegs
[MISCREG_ID_ISAR2
] = p
->id_isar2
;
219 miscRegs
[MISCREG_ID_ISAR3
] = p
->id_isar3
;
220 miscRegs
[MISCREG_ID_ISAR4
] = p
->id_isar4
;
221 miscRegs
[MISCREG_ID_ISAR5
] = p
->id_isar5
;
223 miscRegs
[MISCREG_FPSID
] = p
->fpsid
;
226 TTBCR ttbcr
= miscRegs
[MISCREG_TTBCR_NS
];
228 miscRegs
[MISCREG_TTBCR_NS
] = ttbcr
;
229 // Enforce consistency with system-level settings
230 miscRegs
[MISCREG_ID_MMFR0
] = (miscRegs
[MISCREG_ID_MMFR0
] & ~0xf) | 0x5;
234 miscRegs
[MISCREG_SCTLR_S
] = sctlr
;
235 miscRegs
[MISCREG_SCR
] = 0;
236 miscRegs
[MISCREG_VBAR_S
] = 0;
238 // we're always non-secure
239 miscRegs
[MISCREG_SCR
] = 1;
242 //XXX We need to initialize the rest of the state.
246 ISA::clear64(const ArmISAParams
*p
)
249 Addr rvbar
= system
->resetAddr64();
250 switch (system
->highestEL()) {
251 // Set initial EL to highest implemented EL using associated stack
252 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
255 cpsr
.mode
= MODE_EL3H
;
256 miscRegs
[MISCREG_RVBAR_EL3
] = rvbar
;
259 cpsr
.mode
= MODE_EL2H
;
260 miscRegs
[MISCREG_RVBAR_EL2
] = rvbar
;
263 cpsr
.mode
= MODE_EL1H
;
264 miscRegs
[MISCREG_RVBAR_EL1
] = rvbar
;
267 panic("Invalid highest implemented exception level");
271 // Initialize rest of CPSR
272 cpsr
.daif
= 0xf; // Mask all interrupts
275 miscRegs
[MISCREG_CPSR
] = cpsr
;
278 // Initialize other control registers
279 miscRegs
[MISCREG_MPIDR_EL1
] = 0x80000000;
281 miscRegs
[MISCREG_SCTLR_EL3
] = 0x30c50830;
282 miscRegs
[MISCREG_SCR_EL3
] = 0x00000030; // RES1 fields
283 } else if (haveVirtualization
) {
284 // also MISCREG_SCTLR_EL2 (by mapping)
285 miscRegs
[MISCREG_HSCTLR
] = 0x30c50830;
287 // also MISCREG_SCTLR_EL1 (by mapping)
288 miscRegs
[MISCREG_SCTLR_NS
] = 0x30d00800 | 0x00050030; // RES1 | init
290 miscRegs
[MISCREG_SCR_EL3
] = 1;
293 // Initialize configurable id registers
294 miscRegs
[MISCREG_ID_AA64AFR0_EL1
] = p
->id_aa64afr0_el1
;
295 miscRegs
[MISCREG_ID_AA64AFR1_EL1
] = p
->id_aa64afr1_el1
;
296 miscRegs
[MISCREG_ID_AA64DFR0_EL1
] =
297 (p
->id_aa64dfr0_el1
& 0xfffffffffffff0ffULL
) |
298 (p
->pmu
? 0x0000000000000100ULL
: 0); // Enable PMUv3
300 miscRegs
[MISCREG_ID_AA64DFR1_EL1
] = p
->id_aa64dfr1_el1
;
301 miscRegs
[MISCREG_ID_AA64ISAR0_EL1
] = p
->id_aa64isar0_el1
;
302 miscRegs
[MISCREG_ID_AA64ISAR1_EL1
] = p
->id_aa64isar1_el1
;
303 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
] = p
->id_aa64mmfr0_el1
;
304 miscRegs
[MISCREG_ID_AA64MMFR1_EL1
] = p
->id_aa64mmfr1_el1
;
306 miscRegs
[MISCREG_ID_DFR0_EL1
] =
307 (p
->pmu
? 0x03000000ULL
: 0); // Enable PMUv3
309 miscRegs
[MISCREG_ID_DFR0
] = miscRegs
[MISCREG_ID_DFR0_EL1
];
311 // Enforce consistency with system-level settings...
314 miscRegs
[MISCREG_ID_AA64PFR0_EL1
] = insertBits(
315 miscRegs
[MISCREG_ID_AA64PFR0_EL1
], 15, 12,
316 haveSecurity
? 0x2 : 0x0);
318 miscRegs
[MISCREG_ID_AA64PFR0_EL1
] = insertBits(
319 miscRegs
[MISCREG_ID_AA64PFR0_EL1
], 11, 8,
320 haveVirtualization
? 0x2 : 0x0);
321 // Large ASID support
322 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
] = insertBits(
323 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
], 7, 4,
324 haveLargeAsid64
? 0x2 : 0x0);
325 // Physical address size
326 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
] = insertBits(
327 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
], 3, 0,
328 encodePhysAddrRange64(physAddrRange64
));
332 ISA::readMiscRegNoEffect(int misc_reg
) const
334 assert(misc_reg
< NumMiscRegs
);
336 const auto ®
= lookUpMiscReg
[misc_reg
]; // bit masks
337 const auto &map
= getMiscIndices(misc_reg
);
338 int lower
= map
.first
, upper
= map
.second
;
339 // NB!: apply architectural masks according to desired register,
340 // despite possibly getting value from different (mapped) register.
341 auto val
= !upper
? miscRegs
[lower
] : ((miscRegs
[lower
] & mask(32))
342 |(miscRegs
[upper
] << 32));
343 if (val
& reg
.res0()) {
344 DPRINTF(MiscRegs
, "Reading MiscReg %s with set res0 bits: %#x\n",
345 miscRegName
[misc_reg
], val
& reg
.res0());
347 if ((val
& reg
.res1()) != reg
.res1()) {
348 DPRINTF(MiscRegs
, "Reading MiscReg %s with clear res1 bits: %#x\n",
349 miscRegName
[misc_reg
], (val
& reg
.res1()) ^ reg
.res1());
351 return (val
& ~reg
.raz()) | reg
.rao(); // enforce raz/rao
356 ISA::readMiscReg(int misc_reg
, ThreadContext
*tc
)
362 if (misc_reg
== MISCREG_CPSR
) {
363 cpsr
= miscRegs
[misc_reg
];
365 cpsr
.j
= pc
.jazelle() ? 1 : 0;
366 cpsr
.t
= pc
.thumb() ? 1 : 0;
371 if (!miscRegInfo
[misc_reg
][MISCREG_IMPLEMENTED
]) {
372 if (miscRegInfo
[misc_reg
][MISCREG_WARN_NOT_FAIL
])
373 warn("Unimplemented system register %s read.\n",
374 miscRegName
[misc_reg
]);
376 panic("Unimplemented system register %s read.\n",
377 miscRegName
[misc_reg
]);
381 switch (unflattenMiscReg(misc_reg
)) {
384 if (!haveVirtualization
)
387 return readMiscRegNoEffect(MISCREG_HCR
);
391 const uint32_t ones
= (uint32_t)(-1);
393 // Only cp10, cp11, and ase are implemented, nothing else should
394 // be readable? (straight copy from the write code)
395 cpacrMask
.cp10
= ones
;
396 cpacrMask
.cp11
= ones
;
397 cpacrMask
.asedis
= ones
;
399 // Security Extensions may limit the readability of CPACR
401 scr
= readMiscRegNoEffect(MISCREG_SCR
);
402 cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
403 if (scr
.ns
&& (cpsr
.mode
!= MODE_MON
) && ELIs32(tc
, EL3
)) {
404 NSACR nsacr
= readMiscRegNoEffect(MISCREG_NSACR
);
405 // NB: Skipping the full loop, here
406 if (!nsacr
.cp10
) cpacrMask
.cp10
= 0;
407 if (!nsacr
.cp11
) cpacrMask
.cp11
= 0;
410 MiscReg val
= readMiscRegNoEffect(MISCREG_CPACR
);
412 DPRINTF(MiscRegs
, "Reading misc reg %s: %#x\n",
413 miscRegName
[misc_reg
], val
);
417 cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
418 scr
= readMiscRegNoEffect(MISCREG_SCR
);
419 if ((cpsr
.mode
== MODE_HYP
) || inSecureState(scr
, cpsr
)) {
420 return getMPIDR(system
, tc
);
422 return readMiscReg(MISCREG_VMPIDR
, tc
);
425 case MISCREG_MPIDR_EL1
:
426 // @todo in the absence of v8 virtualization support just return MPIDR_EL1
427 return getMPIDR(system
, tc
) & 0xffffffff;
429 // top bit defined as RES1
430 return readMiscRegNoEffect(misc_reg
) | 0x80000000;
431 case MISCREG_ID_AFR0
: // not implemented, so alias MIDR
432 case MISCREG_REVIDR
: // not implemented, so alias MIDR
434 cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
435 scr
= readMiscRegNoEffect(MISCREG_SCR
);
436 if ((cpsr
.mode
== MODE_HYP
) || inSecureState(scr
, cpsr
)) {
437 return readMiscRegNoEffect(misc_reg
);
439 return readMiscRegNoEffect(MISCREG_VPIDR
);
442 case MISCREG_JOSCR
: // Jazelle trivial implementation, RAZ/WI
443 case MISCREG_JMCR
: // Jazelle trivial implementation, RAZ/WI
444 case MISCREG_JIDR
: // Jazelle trivial implementation, RAZ/WI
445 case MISCREG_AIDR
: // AUX ID set to 0
446 case MISCREG_TCMTR
: // No TCM's
450 warn_once("The clidr register always reports 0 caches.\n");
451 warn_once("clidr LoUIS field of 0b001 to match current "
452 "ARM implementations.\n");
455 warn_once("The ccsidr register isn't implemented and "
456 "always reads as 0.\n");
458 case MISCREG_CTR
: // AArch32, ARMv7, top bit set
459 case MISCREG_CTR_EL0
: // AArch64
461 //all caches have the same line size in gem5
462 //4 byte words in ARM
463 unsigned lineSizeWords
=
464 tc
->getSystemPtr()->cacheLineSize() / 4;
465 unsigned log2LineSizeWords
= 0;
467 while (lineSizeWords
>>= 1) {
472 //log2 of minimun i-cache line size (words)
473 ctr
.iCacheLineSize
= log2LineSizeWords
;
474 //b11 - gem5 uses pipt
475 ctr
.l1IndexPolicy
= 0x3;
476 //log2 of minimum d-cache line size (words)
477 ctr
.dCacheLineSize
= log2LineSizeWords
;
478 //log2 of max reservation size (words)
479 ctr
.erg
= log2LineSizeWords
;
480 //log2 of max writeback size (words)
481 ctr
.cwg
= log2LineSizeWords
;
482 //b100 - gem5 format is ARMv7
488 warn("Not doing anything for miscreg ACTLR\n");
491 case MISCREG_PMXEVTYPER_PMCCFILTR
:
492 case MISCREG_PMINTENSET_EL1
... MISCREG_PMOVSSET_EL0
:
493 case MISCREG_PMEVCNTR0_EL0
... MISCREG_PMEVTYPER5_EL0
:
494 case MISCREG_PMCR
... MISCREG_PMOVSSET
:
495 return pmu
->readMiscReg(misc_reg
);
498 panic("shouldn't be reading this register seperately\n");
499 case MISCREG_FPSCR_QC
:
500 return readMiscRegNoEffect(MISCREG_FPSCR
) & ~FpscrQcMask
;
501 case MISCREG_FPSCR_EXC
:
502 return readMiscRegNoEffect(MISCREG_FPSCR
) & ~FpscrExcMask
;
505 const uint32_t ones
= (uint32_t)(-1);
507 fpscrMask
.ioc
= ones
;
508 fpscrMask
.dzc
= ones
;
509 fpscrMask
.ofc
= ones
;
510 fpscrMask
.ufc
= ones
;
511 fpscrMask
.ixc
= ones
;
512 fpscrMask
.idc
= ones
;
518 return readMiscRegNoEffect(MISCREG_FPSCR
) & (uint32_t)fpscrMask
;
522 const uint32_t ones
= (uint32_t)(-1);
524 fpscrMask
.ioe
= ones
;
525 fpscrMask
.dze
= ones
;
526 fpscrMask
.ofe
= ones
;
527 fpscrMask
.ufe
= ones
;
528 fpscrMask
.ixe
= ones
;
529 fpscrMask
.ide
= ones
;
530 fpscrMask
.len
= ones
;
531 fpscrMask
.stride
= ones
;
532 fpscrMask
.rMode
= ones
;
535 fpscrMask
.ahp
= ones
;
536 return readMiscRegNoEffect(MISCREG_FPSCR
) & (uint32_t)fpscrMask
;
541 cpsr
.nz
= tc
->readCCReg(CCREG_NZ
);
542 cpsr
.c
= tc
->readCCReg(CCREG_C
);
543 cpsr
.v
= tc
->readCCReg(CCREG_V
);
549 cpsr
.daif
= (uint8_t) ((CPSR
) miscRegs
[MISCREG_CPSR
]).daif
;
554 return tc
->readIntReg(INTREG_SP0
);
558 return tc
->readIntReg(INTREG_SP1
);
562 return tc
->readIntReg(INTREG_SP2
);
566 return miscRegs
[MISCREG_CPSR
] & 0x1;
568 case MISCREG_CURRENTEL
:
570 return miscRegs
[MISCREG_CPSR
] & 0xc;
574 // mostly unimplemented, just set NumCPUs field from sim and return
576 // b00:1CPU to b11:4CPUs
577 l2ctlr
.numCPUs
= tc
->getSystemPtr()->numContexts() - 1;
580 case MISCREG_DBGDIDR
:
581 /* For now just implement the version number.
582 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
585 case MISCREG_DBGDSCRint
:
588 return tc
->getCpuPtr()->getInterruptController(tc
->threadId())->getISR(
589 readMiscRegNoEffect(MISCREG_HCR
),
590 readMiscRegNoEffect(MISCREG_CPSR
),
591 readMiscRegNoEffect(MISCREG_SCR
));
592 case MISCREG_ISR_EL1
:
593 return tc
->getCpuPtr()->getInterruptController(tc
->threadId())->getISR(
594 readMiscRegNoEffect(MISCREG_HCR_EL2
),
595 readMiscRegNoEffect(MISCREG_CPSR
),
596 readMiscRegNoEffect(MISCREG_SCR_EL3
));
597 case MISCREG_DCZID_EL0
:
598 return 0x04; // DC ZVA clear 64-byte chunks
601 MiscReg val
= readMiscRegNoEffect(misc_reg
);
602 // The trap bit associated with CP14 is defined as RAZ
604 // If a CP bit in NSACR is 0 then the corresponding bit in
606 bool secure_lookup
= haveSecurity
&&
607 inSecureState(readMiscRegNoEffect(MISCREG_SCR
),
608 readMiscRegNoEffect(MISCREG_CPSR
));
609 if (!secure_lookup
) {
610 MiscReg mask
= readMiscRegNoEffect(MISCREG_NSACR
);
611 val
|= (mask
^ 0x7FFF) & 0xBFFF;
613 // Set the bits for unimplemented coprocessors to RAO/WI
617 case MISCREG_HDFAR
: // alias for secure DFAR
618 return readMiscRegNoEffect(MISCREG_DFAR_S
);
619 case MISCREG_HIFAR
: // alias for secure IFAR
620 return readMiscRegNoEffect(MISCREG_IFAR_S
);
621 case MISCREG_HVBAR
: // bottom bits reserved
622 return readMiscRegNoEffect(MISCREG_HVBAR
) & 0xFFFFFFE0;
624 return (readMiscRegNoEffect(misc_reg
) & 0x72DD39FF) | 0x00C00818;
625 case MISCREG_SCTLR_EL1
:
626 return (readMiscRegNoEffect(misc_reg
) & 0x37DDDBBF) | 0x30D00800;
627 case MISCREG_SCTLR_EL2
:
628 case MISCREG_SCTLR_EL3
:
630 return (readMiscRegNoEffect(misc_reg
) & 0x32CD183F) | 0x30C50830;
632 case MISCREG_ID_PFR0
:
633 // !ThumbEE | !Jazelle | Thumb | ARM
635 case MISCREG_ID_PFR1
:
636 { // Timer | Virti | !M Profile | TrustZone | ARMv4
637 bool haveTimer
= (system
->getGenericTimer() != NULL
);
639 | (haveSecurity
? 0x00000010 : 0x0)
640 | (haveVirtualization
? 0x00001000 : 0x0)
641 | (haveTimer
? 0x00010000 : 0x0);
643 case MISCREG_ID_AA64PFR0_EL1
:
644 return 0x0000000000000002 // AArch{64,32} supported at EL0
645 | 0x0000000000000020 // EL1
646 | (haveVirtualization
? 0x0000000000000200 : 0) // EL2
647 | (haveSecurity
? 0x0000000000002000 : 0); // EL3
648 case MISCREG_ID_AA64PFR1_EL1
:
649 return 0; // bits [63:0] RES0 (reserved for future use)
651 // Generic Timer registers
652 case MISCREG_CNTFRQ
... MISCREG_CNTHP_CTL
:
653 case MISCREG_CNTPCT
... MISCREG_CNTHP_CVAL
:
654 case MISCREG_CNTKCTL_EL1
... MISCREG_CNTV_CVAL_EL0
:
655 case MISCREG_CNTVOFF_EL2
... MISCREG_CNTPS_CVAL_EL1
:
656 return getGenericTimer(tc
).readMiscReg(misc_reg
);
662 return readMiscRegNoEffect(misc_reg
);
666 ISA::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
)
668 assert(misc_reg
< NumMiscRegs
);
670 const auto ®
= lookUpMiscReg
[misc_reg
]; // bit masks
671 const auto &map
= getMiscIndices(misc_reg
);
672 int lower
= map
.first
, upper
= map
.second
;
674 auto v
= (val
& ~reg
.wi()) | reg
.rao();
676 miscRegs
[lower
] = bits(v
, 31, 0);
677 miscRegs
[upper
] = bits(v
, 63, 32);
678 DPRINTF(MiscRegs
, "Writing to misc reg %d (%d:%d) : %#x\n",
679 misc_reg
, lower
, upper
, v
);
682 DPRINTF(MiscRegs
, "Writing to misc reg %d (%d) : %#x\n",
688 ISA::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadContext
*tc
)
691 MiscReg newVal
= val
;
695 if (misc_reg
== MISCREG_CPSR
) {
699 CPSR old_cpsr
= miscRegs
[MISCREG_CPSR
];
700 int old_mode
= old_cpsr
.mode
;
702 if (old_mode
!= cpsr
.mode
|| cpsr
.il
!= old_cpsr
.il
) {
703 getITBPtr(tc
)->invalidateMiscReg();
704 getDTBPtr(tc
)->invalidateMiscReg();
707 DPRINTF(Arm
, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
708 miscRegs
[misc_reg
], cpsr
, cpsr
.f
, cpsr
.i
, cpsr
.a
, cpsr
.mode
);
709 PCState pc
= tc
->pcState();
710 pc
.nextThumb(cpsr
.t
);
711 pc
.nextJazelle(cpsr
.j
);
713 // Follow slightly different semantics if a CheckerCPU object
715 CheckerCPU
*checker
= tc
->getCheckerCpuPtr();
717 tc
->pcStateNoRecord(pc
);
723 if (!miscRegInfo
[misc_reg
][MISCREG_IMPLEMENTED
]) {
724 if (miscRegInfo
[misc_reg
][MISCREG_WARN_NOT_FAIL
])
725 warn("Unimplemented system register %s write with %#x.\n",
726 miscRegName
[misc_reg
], val
);
728 panic("Unimplemented system register %s write with %#x.\n",
729 miscRegName
[misc_reg
], val
);
732 switch (unflattenMiscReg(misc_reg
)) {
736 const uint32_t ones
= (uint32_t)(-1);
738 // Only cp10, cp11, and ase are implemented, nothing else should
740 cpacrMask
.cp10
= ones
;
741 cpacrMask
.cp11
= ones
;
742 cpacrMask
.asedis
= ones
;
744 // Security Extensions may limit the writability of CPACR
746 scr
= readMiscRegNoEffect(MISCREG_SCR
);
747 CPSR cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
748 if (scr
.ns
&& (cpsr
.mode
!= MODE_MON
) && ELIs32(tc
, EL3
)) {
749 NSACR nsacr
= readMiscRegNoEffect(MISCREG_NSACR
);
750 // NB: Skipping the full loop, here
751 if (!nsacr
.cp10
) cpacrMask
.cp10
= 0;
752 if (!nsacr
.cp11
) cpacrMask
.cp11
= 0;
756 MiscReg old_val
= readMiscRegNoEffect(MISCREG_CPACR
);
758 newVal
|= old_val
& ~cpacrMask
;
759 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
760 miscRegName
[misc_reg
], newVal
);
763 case MISCREG_CPACR_EL1
:
765 const uint32_t ones
= (uint32_t)(-1);
767 cpacrMask
.tta
= ones
;
768 cpacrMask
.fpen
= ones
;
770 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
771 miscRegName
[misc_reg
], newVal
);
774 case MISCREG_CPTR_EL2
:
776 const uint32_t ones
= (uint32_t)(-1);
778 cptrMask
.tcpac
= ones
;
783 cptrMask
.res1_13_12_el2
= ones
;
784 cptrMask
.res1_9_0_el2
= ones
;
786 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
787 miscRegName
[misc_reg
], newVal
);
790 case MISCREG_CPTR_EL3
:
792 const uint32_t ones
= (uint32_t)(-1);
794 cptrMask
.tcpac
= ones
;
798 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
799 miscRegName
[misc_reg
], newVal
);
803 warn_once("The csselr register isn't implemented.\n");
806 case MISCREG_DC_ZVA_Xt
:
807 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
812 const uint32_t ones
= (uint32_t)(-1);
814 fpscrMask
.ioc
= ones
;
815 fpscrMask
.dzc
= ones
;
816 fpscrMask
.ofc
= ones
;
817 fpscrMask
.ufc
= ones
;
818 fpscrMask
.ixc
= ones
;
819 fpscrMask
.idc
= ones
;
820 fpscrMask
.ioe
= ones
;
821 fpscrMask
.dze
= ones
;
822 fpscrMask
.ofe
= ones
;
823 fpscrMask
.ufe
= ones
;
824 fpscrMask
.ixe
= ones
;
825 fpscrMask
.ide
= ones
;
826 fpscrMask
.len
= ones
;
827 fpscrMask
.stride
= ones
;
828 fpscrMask
.rMode
= ones
;
831 fpscrMask
.ahp
= ones
;
837 newVal
= (newVal
& (uint32_t)fpscrMask
) |
838 (readMiscRegNoEffect(MISCREG_FPSCR
) &
839 ~(uint32_t)fpscrMask
);
840 tc
->getDecoderPtr()->setContext(newVal
);
845 const uint32_t ones
= (uint32_t)(-1);
847 fpscrMask
.ioc
= ones
;
848 fpscrMask
.dzc
= ones
;
849 fpscrMask
.ofc
= ones
;
850 fpscrMask
.ufc
= ones
;
851 fpscrMask
.ixc
= ones
;
852 fpscrMask
.idc
= ones
;
858 newVal
= (newVal
& (uint32_t)fpscrMask
) |
859 (readMiscRegNoEffect(MISCREG_FPSCR
) &
860 ~(uint32_t)fpscrMask
);
861 misc_reg
= MISCREG_FPSCR
;
866 const uint32_t ones
= (uint32_t)(-1);
868 fpscrMask
.ioe
= ones
;
869 fpscrMask
.dze
= ones
;
870 fpscrMask
.ofe
= ones
;
871 fpscrMask
.ufe
= ones
;
872 fpscrMask
.ixe
= ones
;
873 fpscrMask
.ide
= ones
;
874 fpscrMask
.len
= ones
;
875 fpscrMask
.stride
= ones
;
876 fpscrMask
.rMode
= ones
;
879 fpscrMask
.ahp
= ones
;
880 newVal
= (newVal
& (uint32_t)fpscrMask
) |
881 (readMiscRegNoEffect(MISCREG_FPSCR
) &
882 ~(uint32_t)fpscrMask
);
883 misc_reg
= MISCREG_FPSCR
;
888 assert(!(newVal
& ~CpsrMaskQ
));
889 newVal
= readMiscRegNoEffect(MISCREG_CPSR
) | newVal
;
890 misc_reg
= MISCREG_CPSR
;
893 case MISCREG_FPSCR_QC
:
895 newVal
= readMiscRegNoEffect(MISCREG_FPSCR
) |
896 (newVal
& FpscrQcMask
);
897 misc_reg
= MISCREG_FPSCR
;
900 case MISCREG_FPSCR_EXC
:
902 newVal
= readMiscRegNoEffect(MISCREG_FPSCR
) |
903 (newVal
& FpscrExcMask
);
904 misc_reg
= MISCREG_FPSCR
;
909 // vfpv3 architecture, section B.6.1 of DDI04068
910 // bit 29 - valid only if fpexc[31] is 0
911 const uint32_t fpexcMask
= 0x60000000;
912 newVal
= (newVal
& fpexcMask
) |
913 (readMiscRegNoEffect(MISCREG_FPEXC
) & ~fpexcMask
);
918 if (!haveVirtualization
)
924 // ARM ARM (ARM DDI 0406C.b) B4.1.96
925 const uint32_t ifsrMask
=
926 mask(31, 13) | mask(11, 11) | mask(8, 6);
927 newVal
= newVal
& ~ifsrMask
;
932 // ARM ARM (ARM DDI 0406C.b) B4.1.52
933 const uint32_t dfsrMask
= mask(31, 14) | mask(8, 8);
934 newVal
= newVal
& ~dfsrMask
;
940 // ARM ARM (ARM DDI 0406C.b) B4.1.5
941 // Valid only with LPAE
944 DPRINTF(MiscRegs
, "Writing AMAIR: %#x\n", newVal
);
948 getITBPtr(tc
)->invalidateMiscReg();
949 getDTBPtr(tc
)->invalidateMiscReg();
953 DPRINTF(MiscRegs
, "Writing SCTLR: %#x\n", newVal
);
954 scr
= readMiscRegNoEffect(MISCREG_SCR
);
956 MiscRegIndex sctlr_idx
;
957 if (haveSecurity
&& !highestELIs64
&& !scr
.ns
) {
958 sctlr_idx
= MISCREG_SCTLR_S
;
960 sctlr_idx
= MISCREG_SCTLR_NS
;
963 SCTLR sctlr
= miscRegs
[sctlr_idx
];
964 SCTLR new_sctlr
= newVal
;
965 new_sctlr
.nmfi
= ((bool)sctlr
.nmfi
) && !haveVirtualization
;
966 miscRegs
[sctlr_idx
] = (MiscReg
)new_sctlr
;
967 getITBPtr(tc
)->invalidateMiscReg();
968 getDTBPtr(tc
)->invalidateMiscReg();
971 case MISCREG_ID_PFR0
:
972 case MISCREG_ID_PFR1
:
973 case MISCREG_ID_DFR0
:
974 case MISCREG_ID_MMFR0
:
975 case MISCREG_ID_MMFR1
:
976 case MISCREG_ID_MMFR2
:
977 case MISCREG_ID_MMFR3
:
978 case MISCREG_ID_ISAR0
:
979 case MISCREG_ID_ISAR1
:
980 case MISCREG_ID_ISAR2
:
981 case MISCREG_ID_ISAR3
:
982 case MISCREG_ID_ISAR4
:
983 case MISCREG_ID_ISAR5
:
991 case MISCREG_ID_AA64AFR0_EL1
:
992 case MISCREG_ID_AA64AFR1_EL1
:
993 case MISCREG_ID_AA64DFR0_EL1
:
994 case MISCREG_ID_AA64DFR1_EL1
:
995 case MISCREG_ID_AA64ISAR0_EL1
:
996 case MISCREG_ID_AA64ISAR1_EL1
:
997 case MISCREG_ID_AA64MMFR0_EL1
:
998 case MISCREG_ID_AA64MMFR1_EL1
:
999 case MISCREG_ID_AA64PFR0_EL1
:
1000 case MISCREG_ID_AA64PFR1_EL1
:
1001 // ID registers are constants.
1004 // TLB Invalidate All
1005 case MISCREG_TLBIALL
: // TLBI all entries, EL0&1,
1008 scr
= readMiscReg(MISCREG_SCR
, tc
);
1010 TLBIALL
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
);
1014 // TLB Invalidate All, Inner Shareable
1015 case MISCREG_TLBIALLIS
:
1018 scr
= readMiscReg(MISCREG_SCR
, tc
);
1020 TLBIALL
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
);
1021 tlbiOp
.broadcast(tc
);
1024 // Instruction TLB Invalidate All
1025 case MISCREG_ITLBIALL
:
1028 scr
= readMiscReg(MISCREG_SCR
, tc
);
1030 ITLBIALL
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
);
1034 // Data TLB Invalidate All
1035 case MISCREG_DTLBIALL
:
1038 scr
= readMiscReg(MISCREG_SCR
, tc
);
1040 DTLBIALL
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
);
1044 // TLB Invalidate by VA
1045 // mcr tlbimval(is) is invalidating all matching entries
1046 // regardless of the level of lookup, since in gem5 we cache
1047 // in the tlb the last level of lookup only.
1048 case MISCREG_TLBIMVA
:
1049 case MISCREG_TLBIMVAL
:
1052 scr
= readMiscReg(MISCREG_SCR
, tc
);
1055 haveSecurity
&& !scr
.ns
,
1056 mbits(newVal
, 31, 12),
1062 // TLB Invalidate by VA, Inner Shareable
1063 case MISCREG_TLBIMVAIS
:
1064 case MISCREG_TLBIMVALIS
:
1067 scr
= readMiscReg(MISCREG_SCR
, tc
);
1070 haveSecurity
&& !scr
.ns
,
1071 mbits(newVal
, 31, 12),
1074 tlbiOp
.broadcast(tc
);
1077 // TLB Invalidate by ASID match
1078 case MISCREG_TLBIASID
:
1081 scr
= readMiscReg(MISCREG_SCR
, tc
);
1083 TLBIASID
tlbiOp(EL1
,
1084 haveSecurity
&& !scr
.ns
,
1090 // TLB Invalidate by ASID match, Inner Shareable
1091 case MISCREG_TLBIASIDIS
:
1094 scr
= readMiscReg(MISCREG_SCR
, tc
);
1096 TLBIASID
tlbiOp(EL1
,
1097 haveSecurity
&& !scr
.ns
,
1100 tlbiOp
.broadcast(tc
);
1103 // mcr tlbimvaal(is) is invalidating all matching entries
1104 // regardless of the level of lookup, since in gem5 we cache
1105 // in the tlb the last level of lookup only.
1106 // TLB Invalidate by VA, All ASID
1107 case MISCREG_TLBIMVAA
:
1108 case MISCREG_TLBIMVAAL
:
1111 scr
= readMiscReg(MISCREG_SCR
, tc
);
1113 TLBIMVAA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1114 mbits(newVal
, 31,12), false);
1119 // TLB Invalidate by VA, All ASID, Inner Shareable
1120 case MISCREG_TLBIMVAAIS
:
1121 case MISCREG_TLBIMVAALIS
:
1124 scr
= readMiscReg(MISCREG_SCR
, tc
);
1126 TLBIMVAA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1127 mbits(newVal
, 31,12), false);
1129 tlbiOp
.broadcast(tc
);
1132 // mcr tlbimvalh(is) is invalidating all matching entries
1133 // regardless of the level of lookup, since in gem5 we cache
1134 // in the tlb the last level of lookup only.
1135 // TLB Invalidate by VA, Hyp mode
1136 case MISCREG_TLBIMVAH
:
1137 case MISCREG_TLBIMVALH
:
1140 scr
= readMiscReg(MISCREG_SCR
, tc
);
1142 TLBIMVAA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1143 mbits(newVal
, 31,12), true);
1148 // TLB Invalidate by VA, Hyp mode, Inner Shareable
1149 case MISCREG_TLBIMVAHIS
:
1150 case MISCREG_TLBIMVALHIS
:
1153 scr
= readMiscReg(MISCREG_SCR
, tc
);
1155 TLBIMVAA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1156 mbits(newVal
, 31,12), true);
1158 tlbiOp
.broadcast(tc
);
1161 // mcr tlbiipas2l(is) is invalidating all matching entries
1162 // regardless of the level of lookup, since in gem5 we cache
1163 // in the tlb the last level of lookup only.
1164 // TLB Invalidate by Intermediate Physical Address, Stage 2
1165 case MISCREG_TLBIIPAS2
:
1166 case MISCREG_TLBIIPAS2L
:
1169 scr
= readMiscReg(MISCREG_SCR
, tc
);
1172 haveSecurity
&& !scr
.ns
,
1173 static_cast<Addr
>(bits(newVal
, 35, 0)) << 12);
1178 // TLB Invalidate by Intermediate Physical Address, Stage 2,
1180 case MISCREG_TLBIIPAS2IS
:
1181 case MISCREG_TLBIIPAS2LIS
:
1184 scr
= readMiscReg(MISCREG_SCR
, tc
);
1187 haveSecurity
&& !scr
.ns
,
1188 static_cast<Addr
>(bits(newVal
, 35, 0)) << 12);
1190 tlbiOp
.broadcast(tc
);
1193 // Instruction TLB Invalidate by VA
1194 case MISCREG_ITLBIMVA
:
1197 scr
= readMiscReg(MISCREG_SCR
, tc
);
1199 ITLBIMVA
tlbiOp(EL1
,
1200 haveSecurity
&& !scr
.ns
,
1201 mbits(newVal
, 31, 12),
1207 // Data TLB Invalidate by VA
1208 case MISCREG_DTLBIMVA
:
1211 scr
= readMiscReg(MISCREG_SCR
, tc
);
1213 DTLBIMVA
tlbiOp(EL1
,
1214 haveSecurity
&& !scr
.ns
,
1215 mbits(newVal
, 31, 12),
1221 // Instruction TLB Invalidate by ASID match
1222 case MISCREG_ITLBIASID
:
1225 scr
= readMiscReg(MISCREG_SCR
, tc
);
1227 ITLBIASID
tlbiOp(EL1
,
1228 haveSecurity
&& !scr
.ns
,
1234 // Data TLB Invalidate by ASID match
1235 case MISCREG_DTLBIASID
:
1238 scr
= readMiscReg(MISCREG_SCR
, tc
);
1240 DTLBIASID
tlbiOp(EL1
,
1241 haveSecurity
&& !scr
.ns
,
1247 // TLB Invalidate All, Non-Secure Non-Hyp
1248 case MISCREG_TLBIALLNSNH
:
1252 TLBIALLN
tlbiOp(EL1
, false);
1256 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
1257 case MISCREG_TLBIALLNSNHIS
:
1261 TLBIALLN
tlbiOp(EL1
, false);
1262 tlbiOp
.broadcast(tc
);
1265 // TLB Invalidate All, Hyp mode
1266 case MISCREG_TLBIALLH
:
1270 TLBIALLN
tlbiOp(EL1
, true);
1274 // TLB Invalidate All, Hyp mode, Inner Shareable
1275 case MISCREG_TLBIALLHIS
:
1279 TLBIALLN
tlbiOp(EL1
, true);
1280 tlbiOp
.broadcast(tc
);
1283 // AArch64 TLB Invalidate All, EL3
1284 case MISCREG_TLBI_ALLE3
:
1288 TLBIALL
tlbiOp(EL3
, true);
1292 // AArch64 TLB Invalidate All, EL3, Inner Shareable
1293 case MISCREG_TLBI_ALLE3IS
:
1297 TLBIALL
tlbiOp(EL3
, true);
1298 tlbiOp
.broadcast(tc
);
1301 // @todo: uncomment this to enable Virtualization
1302 // case MISCREG_TLBI_ALLE2IS:
1303 // case MISCREG_TLBI_ALLE2:
1304 // AArch64 TLB Invalidate All, EL1
1305 case MISCREG_TLBI_ALLE1
:
1306 case MISCREG_TLBI_VMALLE1
:
1307 case MISCREG_TLBI_VMALLS12E1
:
1308 // @todo: handle VMID and stage 2 to enable Virtualization
1311 scr
= readMiscReg(MISCREG_SCR
, tc
);
1313 TLBIALL
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
);
1317 // AArch64 TLB Invalidate All, EL1, Inner Shareable
1318 case MISCREG_TLBI_ALLE1IS
:
1319 case MISCREG_TLBI_VMALLE1IS
:
1320 case MISCREG_TLBI_VMALLS12E1IS
:
1321 // @todo: handle VMID and stage 2 to enable Virtualization
1324 scr
= readMiscReg(MISCREG_SCR
, tc
);
1326 TLBIALL
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
);
1327 tlbiOp
.broadcast(tc
);
1330 // VAEx(IS) and VALEx(IS) are the same because TLBs
1331 // only store entries
1332 // from the last level of translation table walks
1333 // @todo: handle VMID to enable Virtualization
1334 // AArch64 TLB Invalidate by VA, EL3
1335 case MISCREG_TLBI_VAE3_Xt
:
1336 case MISCREG_TLBI_VALE3_Xt
:
1340 TLBIMVA
tlbiOp(EL3
, true,
1341 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12,
1346 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable
1347 case MISCREG_TLBI_VAE3IS_Xt
:
1348 case MISCREG_TLBI_VALE3IS_Xt
:
1352 TLBIMVA
tlbiOp(EL3
, true,
1353 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12,
1356 tlbiOp
.broadcast(tc
);
1359 // AArch64 TLB Invalidate by VA, EL2
1360 case MISCREG_TLBI_VAE2_Xt
:
1361 case MISCREG_TLBI_VALE2_Xt
:
1364 scr
= readMiscReg(MISCREG_SCR
, tc
);
1366 TLBIMVA
tlbiOp(EL2
, haveSecurity
&& !scr
.ns
,
1367 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12,
1372 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable
1373 case MISCREG_TLBI_VAE2IS_Xt
:
1374 case MISCREG_TLBI_VALE2IS_Xt
:
1377 scr
= readMiscReg(MISCREG_SCR
, tc
);
1379 TLBIMVA
tlbiOp(EL2
, haveSecurity
&& !scr
.ns
,
1380 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12,
1383 tlbiOp
.broadcast(tc
);
1386 // AArch64 TLB Invalidate by VA, EL1
1387 case MISCREG_TLBI_VAE1_Xt
:
1388 case MISCREG_TLBI_VALE1_Xt
:
1391 scr
= readMiscReg(MISCREG_SCR
, tc
);
1392 auto asid
= haveLargeAsid64
? bits(newVal
, 63, 48) :
1393 bits(newVal
, 55, 48);
1395 TLBIMVA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1396 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12,
1402 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable
1403 case MISCREG_TLBI_VAE1IS_Xt
:
1404 case MISCREG_TLBI_VALE1IS_Xt
:
1407 scr
= readMiscReg(MISCREG_SCR
, tc
);
1408 auto asid
= haveLargeAsid64
? bits(newVal
, 63, 48) :
1409 bits(newVal
, 55, 48);
1411 TLBIMVA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1412 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12,
1415 tlbiOp
.broadcast(tc
);
1418 // AArch64 TLB Invalidate by ASID, EL1
1419 // @todo: handle VMID to enable Virtualization
1420 case MISCREG_TLBI_ASIDE1_Xt
:
1423 scr
= readMiscReg(MISCREG_SCR
, tc
);
1424 auto asid
= haveLargeAsid64
? bits(newVal
, 63, 48) :
1425 bits(newVal
, 55, 48);
1427 TLBIASID
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
, asid
);
1431 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable
1432 case MISCREG_TLBI_ASIDE1IS_Xt
:
1435 scr
= readMiscReg(MISCREG_SCR
, tc
);
1436 auto asid
= haveLargeAsid64
? bits(newVal
, 63, 48) :
1437 bits(newVal
, 55, 48);
1439 TLBIASID
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
, asid
);
1440 tlbiOp
.broadcast(tc
);
1443 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1444 // entries from the last level of translation table walks
1445 // AArch64 TLB Invalidate by VA, All ASID, EL1
1446 case MISCREG_TLBI_VAAE1_Xt
:
1447 case MISCREG_TLBI_VAALE1_Xt
:
1450 scr
= readMiscReg(MISCREG_SCR
, tc
);
1452 TLBIMVAA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1453 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12, false);
1458 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable
1459 case MISCREG_TLBI_VAAE1IS_Xt
:
1460 case MISCREG_TLBI_VAALE1IS_Xt
:
1463 scr
= readMiscReg(MISCREG_SCR
, tc
);
1465 TLBIMVAA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1466 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12, false);
1468 tlbiOp
.broadcast(tc
);
1471 // AArch64 TLB Invalidate by Intermediate Physical Address,
1473 case MISCREG_TLBI_IPAS2E1_Xt
:
1474 case MISCREG_TLBI_IPAS2LE1_Xt
:
1477 scr
= readMiscReg(MISCREG_SCR
, tc
);
1479 TLBIIPA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1480 static_cast<Addr
>(bits(newVal
, 35, 0)) << 12);
1485 // AArch64 TLB Invalidate by Intermediate Physical Address,
1486 // Stage 2, EL1, Inner Shareable
1487 case MISCREG_TLBI_IPAS2E1IS_Xt
:
1488 case MISCREG_TLBI_IPAS2LE1IS_Xt
:
1491 scr
= readMiscReg(MISCREG_SCR
, tc
);
1493 TLBIIPA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1494 static_cast<Addr
>(bits(newVal
, 35, 0)) << 12);
1496 tlbiOp
.broadcast(tc
);
1500 warn("Not doing anything for write of miscreg ACTLR\n");
1503 case MISCREG_PMXEVTYPER_PMCCFILTR
:
1504 case MISCREG_PMINTENSET_EL1
... MISCREG_PMOVSSET_EL0
:
1505 case MISCREG_PMEVCNTR0_EL0
... MISCREG_PMEVTYPER5_EL0
:
1506 case MISCREG_PMCR
... MISCREG_PMOVSSET
:
1507 pmu
->setMiscReg(misc_reg
, newVal
);
1511 case MISCREG_HSTR
: // TJDBX, now redifined to be RES0
1515 newVal
&= ~((uint32_t) hstrMask
);
1520 // If a CP bit in NSACR is 0 then the corresponding bit in
1521 // HCPTR is RAO/WI. Same applies to NSASEDIS
1522 secure_lookup
= haveSecurity
&&
1523 inSecureState(readMiscRegNoEffect(MISCREG_SCR
),
1524 readMiscRegNoEffect(MISCREG_CPSR
));
1525 if (!secure_lookup
) {
1526 MiscReg oldValue
= readMiscRegNoEffect(MISCREG_HCPTR
);
1527 MiscReg mask
= (readMiscRegNoEffect(MISCREG_NSACR
) ^ 0x7FFF) & 0xBFFF;
1528 newVal
= (newVal
& ~mask
) | (oldValue
& mask
);
1532 case MISCREG_HDFAR
: // alias for secure DFAR
1533 misc_reg
= MISCREG_DFAR_S
;
1535 case MISCREG_HIFAR
: // alias for secure IFAR
1536 misc_reg
= MISCREG_IFAR_S
;
1538 case MISCREG_ATS1CPR
:
1539 case MISCREG_ATS1CPW
:
1540 case MISCREG_ATS1CUR
:
1541 case MISCREG_ATS1CUW
:
1542 case MISCREG_ATS12NSOPR
:
1543 case MISCREG_ATS12NSOPW
:
1544 case MISCREG_ATS12NSOUR
:
1545 case MISCREG_ATS12NSOUW
:
1546 case MISCREG_ATS1HR
:
1547 case MISCREG_ATS1HW
:
1549 Request::Flags flags
= 0;
1550 BaseTLB::Mode mode
= BaseTLB::Read
;
1551 TLB::ArmTranslationType tranType
= TLB::NormalTran
;
1554 case MISCREG_ATS1CPR
:
1555 flags
= TLB::MustBeOne
;
1556 tranType
= TLB::S1CTran
;
1557 mode
= BaseTLB::Read
;
1559 case MISCREG_ATS1CPW
:
1560 flags
= TLB::MustBeOne
;
1561 tranType
= TLB::S1CTran
;
1562 mode
= BaseTLB::Write
;
1564 case MISCREG_ATS1CUR
:
1565 flags
= TLB::MustBeOne
| TLB::UserMode
;
1566 tranType
= TLB::S1CTran
;
1567 mode
= BaseTLB::Read
;
1569 case MISCREG_ATS1CUW
:
1570 flags
= TLB::MustBeOne
| TLB::UserMode
;
1571 tranType
= TLB::S1CTran
;
1572 mode
= BaseTLB::Write
;
1574 case MISCREG_ATS12NSOPR
:
1576 panic("Security Extensions required for ATS12NSOPR");
1577 flags
= TLB::MustBeOne
;
1578 tranType
= TLB::S1S2NsTran
;
1579 mode
= BaseTLB::Read
;
1581 case MISCREG_ATS12NSOPW
:
1583 panic("Security Extensions required for ATS12NSOPW");
1584 flags
= TLB::MustBeOne
;
1585 tranType
= TLB::S1S2NsTran
;
1586 mode
= BaseTLB::Write
;
1588 case MISCREG_ATS12NSOUR
:
1590 panic("Security Extensions required for ATS12NSOUR");
1591 flags
= TLB::MustBeOne
| TLB::UserMode
;
1592 tranType
= TLB::S1S2NsTran
;
1593 mode
= BaseTLB::Read
;
1595 case MISCREG_ATS12NSOUW
:
1597 panic("Security Extensions required for ATS12NSOUW");
1598 flags
= TLB::MustBeOne
| TLB::UserMode
;
1599 tranType
= TLB::S1S2NsTran
;
1600 mode
= BaseTLB::Write
;
1602 case MISCREG_ATS1HR
: // only really useful from secure mode.
1603 flags
= TLB::MustBeOne
;
1604 tranType
= TLB::HypMode
;
1605 mode
= BaseTLB::Read
;
1607 case MISCREG_ATS1HW
:
1608 flags
= TLB::MustBeOne
;
1609 tranType
= TLB::HypMode
;
1610 mode
= BaseTLB::Write
;
1613 // If we're in timing mode then doing the translation in
1614 // functional mode then we're slightly distorting performance
1615 // results obtained from simulations. The translation should be
1616 // done in the same mode the core is running in. NOTE: This
1617 // can't be an atomic translation because that causes problems
1618 // with unexpected atomic snoop requests.
1619 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg
);
1620 Request
req(0, val
, 0, flags
, Request::funcMasterId
,
1621 tc
->pcState().pc(), tc
->contextId());
1622 fault
= getDTBPtr(tc
)->translateFunctional(
1623 &req
, tc
, mode
, tranType
);
1624 TTBCR ttbcr
= readMiscRegNoEffect(MISCREG_TTBCR
);
1625 HCR hcr
= readMiscRegNoEffect(MISCREG_HCR
);
1628 if (fault
== NoFault
) {
1629 Addr paddr
= req
.getPaddr();
1630 if (haveLPAE
&& (ttbcr
.eae
|| tranType
& TLB::HypMode
||
1631 ((tranType
& TLB::S1S2NsTran
) && hcr
.vm
) )) {
1632 newVal
= (paddr
& mask(39, 12)) |
1633 (getDTBPtr(tc
)->getAttr());
1635 newVal
= (paddr
& 0xfffff000) |
1636 (getDTBPtr(tc
)->getAttr());
1639 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
1642 ArmFault
*armFault
= static_cast<ArmFault
*>(fault
.get());
1643 armFault
->update(tc
);
1644 // Set fault bit and FSR
1645 FSR fsr
= armFault
->getFsr(tc
);
1647 newVal
= ((fsr
>> 9) & 1) << 11;
1649 // LPAE - rearange fault status
1650 newVal
|= ((fsr
>> 0) & 0x3f) << 1;
1652 // VMSA - rearange fault status
1653 newVal
|= ((fsr
>> 0) & 0xf) << 1;
1654 newVal
|= ((fsr
>> 10) & 0x1) << 5;
1655 newVal
|= ((fsr
>> 12) & 0x1) << 6;
1657 newVal
|= 0x1; // F bit
1658 newVal
|= ((armFault
->iss() >> 7) & 0x1) << 8;
1659 newVal
|= armFault
->isStage2() ? 0x200 : 0;
1661 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
1664 setMiscRegNoEffect(MISCREG_PAR
, newVal
);
1669 TTBCR ttbcr
= readMiscRegNoEffect(MISCREG_TTBCR
);
1670 const uint32_t ones
= (uint32_t)(-1);
1671 TTBCR ttbcrMask
= 0;
1672 TTBCR ttbcrNew
= newVal
;
1674 // ARM DDI 0406C.b, ARMv7-32
1675 ttbcrMask
.n
= ones
; // T0SZ
1677 ttbcrMask
.pd0
= ones
;
1678 ttbcrMask
.pd1
= ones
;
1680 ttbcrMask
.epd0
= ones
;
1681 ttbcrMask
.irgn0
= ones
;
1682 ttbcrMask
.orgn0
= ones
;
1683 ttbcrMask
.sh0
= ones
;
1684 ttbcrMask
.ps
= ones
; // T1SZ
1685 ttbcrMask
.a1
= ones
;
1686 ttbcrMask
.epd1
= ones
;
1687 ttbcrMask
.irgn1
= ones
;
1688 ttbcrMask
.orgn1
= ones
;
1689 ttbcrMask
.sh1
= ones
;
1691 ttbcrMask
.eae
= ones
;
1693 if (haveLPAE
&& ttbcrNew
.eae
) {
1694 newVal
= newVal
& ttbcrMask
;
1696 newVal
= (newVal
& ttbcrMask
) | (ttbcr
& (~ttbcrMask
));
1698 // Invalidate TLB MiscReg
1699 getITBPtr(tc
)->invalidateMiscReg();
1700 getDTBPtr(tc
)->invalidateMiscReg();
1706 TTBCR ttbcr
= readMiscRegNoEffect(MISCREG_TTBCR
);
1709 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1710 // ARMv8 AArch32 bit 63-56 only
1711 uint64_t ttbrMask
= mask(63,56) | mask(47,40);
1712 newVal
= (newVal
& (~ttbrMask
));
1715 // Invalidate TLB MiscReg
1716 getITBPtr(tc
)->invalidateMiscReg();
1717 getDTBPtr(tc
)->invalidateMiscReg();
1720 case MISCREG_SCTLR_EL1
:
1721 case MISCREG_CONTEXTIDR
:
1728 case MISCREG_SCR_EL3
:
1729 case MISCREG_HCR_EL2
:
1730 case MISCREG_TCR_EL1
:
1731 case MISCREG_TCR_EL2
:
1732 case MISCREG_TCR_EL3
:
1733 case MISCREG_SCTLR_EL2
:
1734 case MISCREG_SCTLR_EL3
:
1735 case MISCREG_HSCTLR
:
1736 case MISCREG_TTBR0_EL1
:
1737 case MISCREG_TTBR1_EL1
:
1738 case MISCREG_TTBR0_EL2
:
1739 case MISCREG_TTBR0_EL3
:
1740 getITBPtr(tc
)->invalidateMiscReg();
1741 getDTBPtr(tc
)->invalidateMiscReg();
1747 tc
->setCCReg(CCREG_NZ
, cpsr
.nz
);
1748 tc
->setCCReg(CCREG_C
, cpsr
.c
);
1749 tc
->setCCReg(CCREG_V
, cpsr
.v
);
1754 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1755 cpsr
.daif
= (uint8_t) ((CPSR
) newVal
).daif
;
1757 misc_reg
= MISCREG_CPSR
;
1760 case MISCREG_SP_EL0
:
1761 tc
->setIntReg(INTREG_SP0
, newVal
);
1763 case MISCREG_SP_EL1
:
1764 tc
->setIntReg(INTREG_SP1
, newVal
);
1766 case MISCREG_SP_EL2
:
1767 tc
->setIntReg(INTREG_SP2
, newVal
);
1771 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1772 cpsr
.sp
= (uint8_t) ((CPSR
) newVal
).sp
;
1774 misc_reg
= MISCREG_CPSR
;
1777 case MISCREG_CURRENTEL
:
1779 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1780 cpsr
.el
= (uint8_t) ((CPSR
) newVal
).el
;
1782 misc_reg
= MISCREG_CPSR
;
1785 case MISCREG_AT_S1E1R_Xt
:
1786 case MISCREG_AT_S1E1W_Xt
:
1787 case MISCREG_AT_S1E0R_Xt
:
1788 case MISCREG_AT_S1E0W_Xt
:
1789 case MISCREG_AT_S1E2R_Xt
:
1790 case MISCREG_AT_S1E2W_Xt
:
1791 case MISCREG_AT_S12E1R_Xt
:
1792 case MISCREG_AT_S12E1W_Xt
:
1793 case MISCREG_AT_S12E0R_Xt
:
1794 case MISCREG_AT_S12E0W_Xt
:
1795 case MISCREG_AT_S1E3R_Xt
:
1796 case MISCREG_AT_S1E3W_Xt
:
1798 RequestPtr req
= new Request
;
1799 Request::Flags flags
= 0;
1800 BaseTLB::Mode mode
= BaseTLB::Read
;
1801 TLB::ArmTranslationType tranType
= TLB::NormalTran
;
1804 case MISCREG_AT_S1E1R_Xt
:
1805 flags
= TLB::MustBeOne
;
1806 tranType
= TLB::S1E1Tran
;
1807 mode
= BaseTLB::Read
;
1809 case MISCREG_AT_S1E1W_Xt
:
1810 flags
= TLB::MustBeOne
;
1811 tranType
= TLB::S1E1Tran
;
1812 mode
= BaseTLB::Write
;
1814 case MISCREG_AT_S1E0R_Xt
:
1815 flags
= TLB::MustBeOne
| TLB::UserMode
;
1816 tranType
= TLB::S1E0Tran
;
1817 mode
= BaseTLB::Read
;
1819 case MISCREG_AT_S1E0W_Xt
:
1820 flags
= TLB::MustBeOne
| TLB::UserMode
;
1821 tranType
= TLB::S1E0Tran
;
1822 mode
= BaseTLB::Write
;
1824 case MISCREG_AT_S1E2R_Xt
:
1825 flags
= TLB::MustBeOne
;
1826 tranType
= TLB::S1E2Tran
;
1827 mode
= BaseTLB::Read
;
1829 case MISCREG_AT_S1E2W_Xt
:
1830 flags
= TLB::MustBeOne
;
1831 tranType
= TLB::S1E2Tran
;
1832 mode
= BaseTLB::Write
;
1834 case MISCREG_AT_S12E0R_Xt
:
1835 flags
= TLB::MustBeOne
| TLB::UserMode
;
1836 tranType
= TLB::S12E0Tran
;
1837 mode
= BaseTLB::Read
;
1839 case MISCREG_AT_S12E0W_Xt
:
1840 flags
= TLB::MustBeOne
| TLB::UserMode
;
1841 tranType
= TLB::S12E0Tran
;
1842 mode
= BaseTLB::Write
;
1844 case MISCREG_AT_S12E1R_Xt
:
1845 flags
= TLB::MustBeOne
;
1846 tranType
= TLB::S12E1Tran
;
1847 mode
= BaseTLB::Read
;
1849 case MISCREG_AT_S12E1W_Xt
:
1850 flags
= TLB::MustBeOne
;
1851 tranType
= TLB::S12E1Tran
;
1852 mode
= BaseTLB::Write
;
1854 case MISCREG_AT_S1E3R_Xt
:
1855 flags
= TLB::MustBeOne
;
1856 tranType
= TLB::S1E3Tran
;
1857 mode
= BaseTLB::Read
;
1859 case MISCREG_AT_S1E3W_Xt
:
1860 flags
= TLB::MustBeOne
;
1861 tranType
= TLB::S1E3Tran
;
1862 mode
= BaseTLB::Write
;
1865 // If we're in timing mode then doing the translation in
1866 // functional mode then we're slightly distorting performance
1867 // results obtained from simulations. The translation should be
1868 // done in the same mode the core is running in. NOTE: This
1869 // can't be an atomic translation because that causes problems
1870 // with unexpected atomic snoop requests.
1871 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg
);
1872 req
->setVirt(0, val
, 0, flags
, Request::funcMasterId
,
1873 tc
->pcState().pc());
1874 req
->setContext(tc
->contextId());
1875 fault
= getDTBPtr(tc
)->translateFunctional(req
, tc
, mode
,
1879 if (fault
== NoFault
) {
1880 Addr paddr
= req
->getPaddr();
1881 uint64_t attr
= getDTBPtr(tc
)->getAttr();
1882 uint64_t attr1
= attr
>> 56;
1883 if (!attr1
|| attr1
==0x44) {
1885 attr
&= ~ uint64_t(0x80);
1887 newVal
= (paddr
& mask(47, 12)) | attr
;
1889 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
1892 ArmFault
*armFault
= static_cast<ArmFault
*>(fault
.get());
1893 armFault
->update(tc
);
1894 // Set fault bit and FSR
1895 FSR fsr
= armFault
->getFsr(tc
);
1897 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
1898 if (cpsr
.width
) { // AArch32
1899 newVal
= ((fsr
>> 9) & 1) << 11;
1900 // rearrange fault status
1901 newVal
|= ((fsr
>> 0) & 0x3f) << 1;
1902 newVal
|= 0x1; // F bit
1903 newVal
|= ((armFault
->iss() >> 7) & 0x1) << 8;
1904 newVal
|= armFault
->isStage2() ? 0x200 : 0;
1906 newVal
= 1; // F bit
1907 newVal
|= fsr
<< 1; // FST
1908 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
1909 newVal
|= armFault
->isStage2() ? 1 << 8 : 0; // PTW
1910 newVal
|= armFault
->isStage2() ? 1 << 9 : 0; // S
1911 newVal
|= 1 << 11; // RES1
1914 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
1918 setMiscRegNoEffect(MISCREG_PAR_EL1
, newVal
);
1921 case MISCREG_SPSR_EL3
:
1922 case MISCREG_SPSR_EL2
:
1923 case MISCREG_SPSR_EL1
:
1924 // Force bits 23:21 to 0
1925 newVal
= val
& ~(0x7 << 21);
1927 case MISCREG_L2CTLR
:
1928 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
1929 miscRegName
[misc_reg
], uint32_t(val
));
1932 // Generic Timer registers
1933 case MISCREG_CNTFRQ
... MISCREG_CNTHP_CTL
:
1934 case MISCREG_CNTPCT
... MISCREG_CNTHP_CVAL
:
1935 case MISCREG_CNTKCTL_EL1
... MISCREG_CNTV_CVAL_EL0
:
1936 case MISCREG_CNTVOFF_EL2
... MISCREG_CNTPS_CVAL_EL1
:
1937 getGenericTimer(tc
).setMiscReg(misc_reg
, newVal
);
1941 setMiscRegNoEffect(misc_reg
, newVal
);
1945 ISA::getGenericTimer(ThreadContext
*tc
)
1947 // We only need to create an ISA interface the first time we try
1948 // to access the timer.
1950 return *timer
.get();
1953 GenericTimer
*generic_timer(system
->getGenericTimer());
1954 if (!generic_timer
) {
1955 panic("Trying to get a generic timer from a system that hasn't "
1956 "been configured to use a generic timer.\n");
1959 timer
.reset(new GenericTimerISA(*generic_timer
, tc
->contextId()));
1960 return *timer
.get();
1966 ArmISAParams::create()
1968 return new ArmISA::ISA(this);