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43 #ifndef __ARCH_ARM_ISA_HH__
44 #define __ARCH_ARM_ISA_HH__
46 #include "arch/arm/isa_device.hh"
47 #include "arch/arm/registers.hh"
48 #include "arch/arm/system.hh"
49 #include "arch/arm/tlb.hh"
50 #include "arch/arm/types.hh"
51 #include "debug/Checkpoint.hh"
52 #include "sim/sim_object.hh"
53 #include "enums/DecoderFlavour.hh"
56 struct DummyArmISADeviceParams;
65 * At the moment there are 57 registers which need to be aliased/
66 * translated with other registers in the ISA. This enum helps with that
70 miscRegTranslateCSSELR_EL1,
71 miscRegTranslateSCTLR_EL1,
72 miscRegTranslateSCTLR_EL2,
73 miscRegTranslateACTLR_EL1,
74 miscRegTranslateACTLR_EL2,
75 miscRegTranslateCPACR_EL1,
76 miscRegTranslateCPTR_EL2,
77 miscRegTranslateHCR_EL2,
78 miscRegTranslateMDCR_EL2,
79 miscRegTranslateHSTR_EL2,
80 miscRegTranslateHACR_EL2,
81 miscRegTranslateTTBR0_EL1,
82 miscRegTranslateTTBR1_EL1,
83 miscRegTranslateTTBR0_EL2,
84 miscRegTranslateVTTBR_EL2,
85 miscRegTranslateTCR_EL1,
86 miscRegTranslateTCR_EL2,
87 miscRegTranslateVTCR_EL2,
88 miscRegTranslateAFSR0_EL1,
89 miscRegTranslateAFSR1_EL1,
90 miscRegTranslateAFSR0_EL2,
91 miscRegTranslateAFSR1_EL2,
92 miscRegTranslateESR_EL2,
93 miscRegTranslateFAR_EL1,
94 miscRegTranslateFAR_EL2,
95 miscRegTranslateHPFAR_EL2,
96 miscRegTranslatePAR_EL1,
97 miscRegTranslateMAIR_EL1,
98 miscRegTranslateMAIR_EL2,
99 miscRegTranslateAMAIR_EL1,
100 miscRegTranslateVBAR_EL1,
101 miscRegTranslateVBAR_EL2,
102 miscRegTranslateCONTEXTIDR_EL1,
103 miscRegTranslateTPIDR_EL0,
104 miscRegTranslateTPIDRRO_EL0,
105 miscRegTranslateTPIDR_EL1,
106 miscRegTranslateTPIDR_EL2,
107 miscRegTranslateTEECR32_EL1,
108 miscRegTranslateCNTFRQ_EL0,
109 miscRegTranslateCNTPCT_EL0,
110 miscRegTranslateCNTVCT_EL0,
111 miscRegTranslateCNTVOFF_EL2,
112 miscRegTranslateCNTKCTL_EL1,
113 miscRegTranslateCNTHCTL_EL2,
114 miscRegTranslateCNTP_TVAL_EL0,
115 miscRegTranslateCNTP_CTL_EL0,
116 miscRegTranslateCNTP_CVAL_EL0,
117 miscRegTranslateCNTV_TVAL_EL0,
118 miscRegTranslateCNTV_CTL_EL0,
119 miscRegTranslateCNTV_CVAL_EL0,
120 miscRegTranslateCNTHP_TVAL_EL2,
121 miscRegTranslateCNTHP_CTL_EL2,
122 miscRegTranslateCNTHP_CVAL_EL2,
123 miscRegTranslateDACR32_EL2,
124 miscRegTranslateIFSR32_EL2,
125 miscRegTranslateTEEHBR32_EL1,
126 miscRegTranslateSDER32_EL3,
130 class ISA : public SimObject
136 // Micro Architecture
137 const Enums::DecoderFlavour _decoderFlavour;
139 /** Dummy device for to handle non-existing ISA devices */
140 DummyISADevice dummyDevice;
142 // PMU belonging to this ISA
145 // Generic timer interface belonging to this ISA
146 std::unique_ptr<BaseISADevice> timer;
148 // Cached copies of system-level properties
151 bool haveVirtualization;
152 bool haveLargeAsid64;
153 uint8_t physAddrRange64;
155 /** Register translation entry used in lookUpMiscReg */
156 struct MiscRegLUTEntry {
161 struct MiscRegInitializerEntry {
163 struct MiscRegLUTEntry entry;
166 /** Register table noting all translations */
167 static const struct MiscRegInitializerEntry
168 MiscRegSwitch[miscRegTranslateMax];
170 /** Translation table accessible via the value of the register */
171 std::vector<struct MiscRegLUTEntry> lookUpMiscReg;
173 MiscReg miscRegs[NumMiscRegs];
174 const IntRegIndex *intRegMap;
177 updateRegMap(CPSR cpsr)
179 if (cpsr.width == 0) {
180 intRegMap = IntReg64Map;
185 intRegMap = IntRegUsrMap;
188 intRegMap = IntRegFiqMap;
191 intRegMap = IntRegIrqMap;
194 intRegMap = IntRegSvcMap;
197 intRegMap = IntRegMonMap;
200 intRegMap = IntRegAbtMap;
203 intRegMap = IntRegHypMap;
206 intRegMap = IntRegUndMap;
209 panic("Unrecognized mode setting in CPSR.\n");
214 BaseISADevice &getGenericTimer(ThreadContext *tc);
218 inline void assert32(ThreadContext *tc) {
219 CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc);
223 inline void assert64(ThreadContext *tc) {
224 CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc);
228 void tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid,
229 bool secure_lookup, uint8_t target_el);
231 void tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el);
233 void tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el);
235 void tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup,
236 bool hyp, uint8_t target_el);
240 void clear64(const ArmISAParams *p);
242 MiscReg readMiscRegNoEffect(int misc_reg) const;
243 MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
244 void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
245 void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
248 flattenIntIndex(int reg) const
251 if (reg < NUM_ARCH_INTREGS) {
252 return intRegMap[reg];
253 } else if (reg < NUM_INTREGS) {
255 } else if (reg == INTREG_SPX) {
256 CPSR cpsr = miscRegs[MISCREG_CPSR];
257 ExceptionLevel el = opModeToEL(
258 (OperatingMode) (uint8_t) cpsr.mode);
259 if (!cpsr.sp && el != EL0)
271 panic("Invalid exception level");
275 return flattenIntRegModeIndex(reg);
280 flattenFloatIndex(int reg) const
287 flattenCCIndex(int reg) const
294 flattenMiscIndex(int reg) const
299 if (reg == MISCREG_SPSR) {
300 CPSR cpsr = miscRegs[MISCREG_CPSR];
303 warn("User mode does not have SPSR\n");
304 flat_idx = MISCREG_SPSR;
308 flat_idx = MISCREG_SPSR_EL1;
312 flat_idx = MISCREG_SPSR_EL2;
316 flat_idx = MISCREG_SPSR_EL3;
319 warn("User mode does not have SPSR\n");
320 flat_idx = MISCREG_SPSR;
323 flat_idx = MISCREG_SPSR_FIQ;
326 flat_idx = MISCREG_SPSR_IRQ;
329 flat_idx = MISCREG_SPSR_SVC;
332 flat_idx = MISCREG_SPSR_MON;
335 flat_idx = MISCREG_SPSR_ABT;
338 flat_idx = MISCREG_SPSR_HYP;
341 flat_idx = MISCREG_SPSR_UND;
344 warn("Trying to access SPSR in an invalid mode: %d\n",
346 flat_idx = MISCREG_SPSR;
349 } else if (miscRegInfo[reg][MISCREG_MUTEX]) {
350 // Mutually exclusive CP15 register
352 case MISCREG_PRRR_MAIR0:
353 case MISCREG_PRRR_MAIR0_NS:
354 case MISCREG_PRRR_MAIR0_S:
356 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
357 // If the muxed reg has been flattened, work out the
358 // offset and apply it to the unmuxed reg
359 int idxOffset = reg - MISCREG_PRRR_MAIR0;
361 flat_idx = flattenMiscIndex(MISCREG_MAIR0 +
364 flat_idx = flattenMiscIndex(MISCREG_PRRR +
368 case MISCREG_NMRR_MAIR1:
369 case MISCREG_NMRR_MAIR1_NS:
370 case MISCREG_NMRR_MAIR1_S:
372 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
373 // If the muxed reg has been flattened, work out the
374 // offset and apply it to the unmuxed reg
375 int idxOffset = reg - MISCREG_NMRR_MAIR1;
377 flat_idx = flattenMiscIndex(MISCREG_MAIR1 +
380 flat_idx = flattenMiscIndex(MISCREG_NMRR +
384 case MISCREG_PMXEVTYPER_PMCCFILTR:
386 PMSELR pmselr = miscRegs[MISCREG_PMSELR];
387 if (pmselr.sel == 31)
388 flat_idx = flattenMiscIndex(MISCREG_PMCCFILTR);
390 flat_idx = flattenMiscIndex(MISCREG_PMXEVTYPER);
394 panic("Unrecognized misc. register.\n");
398 if (miscRegInfo[reg][MISCREG_BANKED]) {
399 bool secureReg = haveSecurity &&
400 inSecureState(miscRegs[MISCREG_SCR],
401 miscRegs[MISCREG_CPSR]);
402 flat_idx += secureReg ? 2 : 1;
408 void serialize(CheckpointOut &cp) const
410 DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
411 SERIALIZE_ARRAY(miscRegs, NumMiscRegs);
413 SERIALIZE_SCALAR(haveSecurity);
414 SERIALIZE_SCALAR(haveLPAE);
415 SERIALIZE_SCALAR(haveVirtualization);
416 SERIALIZE_SCALAR(haveLargeAsid64);
417 SERIALIZE_SCALAR(physAddrRange64);
419 void unserialize(CheckpointIn &cp)
421 DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
422 UNSERIALIZE_ARRAY(miscRegs, NumMiscRegs);
423 CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
424 updateRegMap(tmp_cpsr);
426 UNSERIALIZE_SCALAR(haveSecurity);
427 UNSERIALIZE_SCALAR(haveLPAE);
428 UNSERIALIZE_SCALAR(haveVirtualization);
429 UNSERIALIZE_SCALAR(haveLargeAsid64);
430 UNSERIALIZE_SCALAR(physAddrRange64);
433 void startup(ThreadContext *tc) {}
435 Enums::DecoderFlavour decoderFlavour() const { return _decoderFlavour; }
437 /// Explicitly import the otherwise hidden startup
438 using SimObject::startup;
440 typedef ArmISAParams Params;
442 const Params *params() const;