Registers: Add an ISA object which replaces the MiscRegFile.
[gem5.git] / src / arch / arm / isa.hh
1 /*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31 #ifndef __ARCH_ARM_ISA_HH__
32 #define __ARCH_MRM_ISA_HH__
33
34 #include "arch/arm/regfile/misc_regfile.hh"
35 #include "arch/arm/types.hh"
36
37 class Checkpoint;
38 class EventManager;
39
40 namespace ArmISA
41 {
42 class ISA
43 {
44 protected:
45 MiscRegFile miscRegFile;
46
47 public:
48 void clear();
49
50 MiscReg readMiscRegNoEffect(int miscReg);
51 MiscReg readMiscReg(int miscReg, ThreadContext *tc);
52
53 void setMiscRegNoEffect(int miscReg, const MiscReg val);
54 void setMiscReg(int miscReg, const MiscReg val,
55 ThreadContext *tc);
56
57 int
58 flattenIntIndex(int reg)
59 {
60 return reg;
61 }
62
63 int
64 flattenFloatIndex(int reg)
65 {
66 return reg;
67 }
68
69 void serialize(std::ostream &os);
70 void unserialize(Checkpoint *cp, const std::string &section);
71
72 ISA()
73 {
74 clear();
75 }
76 };
77 }
78
79 #endif