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43 #ifndef __ARCH_ARM_ISA_HH__
44 #define __ARCH_ARM_ISA_HH__
46 #include "arch/arm/registers.hh"
47 #include "arch/arm/system.hh"
48 #include "arch/arm/tlb.hh"
49 #include "arch/arm/types.hh"
50 #include "debug/Checkpoint.hh"
51 #include "dev/arm/generic_timer.hh"
52 #include "sim/sim_object.hh"
63 * At the moment there are 57 registers which need to be aliased/
64 * translated with other registers in the ISA. This enum helps with that
68 miscRegTranslateCSSELR_EL1,
69 miscRegTranslateSCTLR_EL1,
70 miscRegTranslateSCTLR_EL2,
71 miscRegTranslateACTLR_EL1,
72 miscRegTranslateACTLR_EL2,
73 miscRegTranslateCPACR_EL1,
74 miscRegTranslateCPTR_EL2,
75 miscRegTranslateHCR_EL2,
76 miscRegTranslateMDCR_EL2,
77 miscRegTranslateHSTR_EL2,
78 miscRegTranslateHACR_EL2,
79 miscRegTranslateTTBR0_EL1,
80 miscRegTranslateTTBR1_EL1,
81 miscRegTranslateTTBR0_EL2,
82 miscRegTranslateVTTBR_EL2,
83 miscRegTranslateTCR_EL1,
84 miscRegTranslateTCR_EL2,
85 miscRegTranslateVTCR_EL2,
86 miscRegTranslateAFSR0_EL1,
87 miscRegTranslateAFSR1_EL1,
88 miscRegTranslateAFSR0_EL2,
89 miscRegTranslateAFSR1_EL2,
90 miscRegTranslateESR_EL2,
91 miscRegTranslateFAR_EL1,
92 miscRegTranslateFAR_EL2,
93 miscRegTranslateHPFAR_EL2,
94 miscRegTranslatePAR_EL1,
95 miscRegTranslateMAIR_EL1,
96 miscRegTranslateMAIR_EL2,
97 miscRegTranslateAMAIR_EL1,
98 miscRegTranslateVBAR_EL1,
99 miscRegTranslateVBAR_EL2,
100 miscRegTranslateCONTEXTIDR_EL1,
101 miscRegTranslateTPIDR_EL0,
102 miscRegTranslateTPIDRRO_EL0,
103 miscRegTranslateTPIDR_EL1,
104 miscRegTranslateTPIDR_EL2,
105 miscRegTranslateTEECR32_EL1,
106 miscRegTranslateCNTFRQ_EL0,
107 miscRegTranslateCNTPCT_EL0,
108 miscRegTranslateCNTVCT_EL0,
109 miscRegTranslateCNTVOFF_EL2,
110 miscRegTranslateCNTKCTL_EL1,
111 miscRegTranslateCNTHCTL_EL2,
112 miscRegTranslateCNTP_TVAL_EL0,
113 miscRegTranslateCNTP_CTL_EL0,
114 miscRegTranslateCNTP_CVAL_EL0,
115 miscRegTranslateCNTV_TVAL_EL0,
116 miscRegTranslateCNTV_CTL_EL0,
117 miscRegTranslateCNTV_CVAL_EL0,
118 miscRegTranslateCNTHP_TVAL_EL2,
119 miscRegTranslateCNTHP_CTL_EL2,
120 miscRegTranslateCNTHP_CVAL_EL2,
121 miscRegTranslateDACR32_EL2,
122 miscRegTranslateIFSR32_EL2,
123 miscRegTranslateTEEHBR32_EL1,
124 miscRegTranslateSDER32_EL3,
128 class ISA : public SimObject
134 // Cached copies of system-level properties
137 bool haveVirtualization;
138 bool haveLargeAsid64;
139 uint8_t physAddrRange64;
141 /** Register translation entry used in lookUpMiscReg */
142 struct MiscRegLUTEntry {
147 struct MiscRegInitializerEntry {
149 struct MiscRegLUTEntry entry;
152 /** Register table noting all translations */
153 static const struct MiscRegInitializerEntry
154 MiscRegSwitch[miscRegTranslateMax];
156 /** Translation table accessible via the value of the register */
157 std::vector<struct MiscRegLUTEntry> lookUpMiscReg;
159 MiscReg miscRegs[NumMiscRegs];
160 const IntRegIndex *intRegMap;
163 updateRegMap(CPSR cpsr)
165 if (cpsr.width == 0) {
166 intRegMap = IntReg64Map;
171 intRegMap = IntRegUsrMap;
174 intRegMap = IntRegFiqMap;
177 intRegMap = IntRegIrqMap;
180 intRegMap = IntRegSvcMap;
183 intRegMap = IntRegMonMap;
186 intRegMap = IntRegAbtMap;
189 intRegMap = IntRegHypMap;
192 intRegMap = IntRegUndMap;
195 panic("Unrecognized mode setting in CPSR.\n");
200 ::GenericTimer::SystemCounter * getSystemCounter(ThreadContext *tc);
201 ::GenericTimer::ArchTimer * getArchTimer(ThreadContext *tc,
206 inline void assert32(ThreadContext *tc) {
207 CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc);
211 inline void assert64(ThreadContext *tc) {
212 CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc);
216 void tlbiVA(ThreadContext *tc, MiscReg newVal, uint8_t asid,
217 bool secure_lookup, uint8_t target_el);
219 void tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el);
221 void tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el);
223 void tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup,
224 bool hyp, uint8_t target_el);
228 void clear64(const ArmISAParams *p);
230 MiscReg readMiscRegNoEffect(int misc_reg) const;
231 MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
232 void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
233 void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
236 flattenIntIndex(int reg) const
239 if (reg < NUM_ARCH_INTREGS) {
240 return intRegMap[reg];
241 } else if (reg < NUM_INTREGS) {
243 } else if (reg == INTREG_SPX) {
244 CPSR cpsr = miscRegs[MISCREG_CPSR];
245 ExceptionLevel el = opModeToEL(
246 (OperatingMode) (uint8_t) cpsr.mode);
247 if (!cpsr.sp && el != EL0)
252 // @todo: uncomment this to enable Virtualization
254 // return INTREG_SP2;
260 panic("Invalid exception level");
264 return flattenIntRegModeIndex(reg);
269 flattenFloatIndex(int reg) const
276 flattenCCIndex(int reg) const
282 flattenMiscIndex(int reg) const
286 if (reg == MISCREG_SPSR) {
287 CPSR cpsr = miscRegs[MISCREG_CPSR];
290 warn("User mode does not have SPSR\n");
291 flat_idx = MISCREG_SPSR;
295 flat_idx = MISCREG_SPSR_EL1;
299 flat_idx = MISCREG_SPSR_EL2;
303 flat_idx = MISCREG_SPSR_EL3;
306 warn("User mode does not have SPSR\n");
307 flat_idx = MISCREG_SPSR;
310 flat_idx = MISCREG_SPSR_FIQ;
313 flat_idx = MISCREG_SPSR_IRQ;
316 flat_idx = MISCREG_SPSR_SVC;
319 flat_idx = MISCREG_SPSR_MON;
322 flat_idx = MISCREG_SPSR_ABT;
325 flat_idx = MISCREG_SPSR_HYP;
328 flat_idx = MISCREG_SPSR_UND;
331 warn("Trying to access SPSR in an invalid mode: %d\n",
333 flat_idx = MISCREG_SPSR;
336 } else if (miscRegInfo[reg][MISCREG_MUTEX]) {
337 // Mutually exclusive CP15 register
339 case MISCREG_PRRR_MAIR0:
340 case MISCREG_PRRR_MAIR0_NS:
341 case MISCREG_PRRR_MAIR0_S:
343 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
344 // If the muxed reg has been flattened, work out the
345 // offset and apply it to the unmuxed reg
346 int idxOffset = reg - MISCREG_PRRR_MAIR0;
348 flat_idx = flattenMiscIndex(MISCREG_MAIR0 +
351 flat_idx = flattenMiscIndex(MISCREG_PRRR +
355 case MISCREG_NMRR_MAIR1:
356 case MISCREG_NMRR_MAIR1_NS:
357 case MISCREG_NMRR_MAIR1_S:
359 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
360 // If the muxed reg has been flattened, work out the
361 // offset and apply it to the unmuxed reg
362 int idxOffset = reg - MISCREG_NMRR_MAIR1;
364 flat_idx = flattenMiscIndex(MISCREG_MAIR1 +
367 flat_idx = flattenMiscIndex(MISCREG_NMRR +
371 case MISCREG_PMXEVTYPER_PMCCFILTR:
373 PMSELR pmselr = miscRegs[MISCREG_PMSELR];
374 if (pmselr.sel == 31)
375 flat_idx = flattenMiscIndex(MISCREG_PMCCFILTR);
377 flat_idx = flattenMiscIndex(MISCREG_PMXEVTYPER);
381 panic("Unrecognized misc. register.\n");
385 if (miscRegInfo[reg][MISCREG_BANKED]) {
386 bool secureReg = haveSecurity &&
387 inSecureState(miscRegs[MISCREG_SCR],
388 miscRegs[MISCREG_CPSR]);
389 flat_idx += secureReg ? 2 : 1;
395 void serialize(std::ostream &os)
397 DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
398 SERIALIZE_ARRAY(miscRegs, NumMiscRegs);
400 SERIALIZE_SCALAR(haveSecurity);
401 SERIALIZE_SCALAR(haveLPAE);
402 SERIALIZE_SCALAR(haveVirtualization);
403 SERIALIZE_SCALAR(haveLargeAsid64);
404 SERIALIZE_SCALAR(physAddrRange64);
406 void unserialize(Checkpoint *cp, const std::string §ion)
408 DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
409 UNSERIALIZE_ARRAY(miscRegs, NumMiscRegs);
410 CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
411 updateRegMap(tmp_cpsr);
413 UNSERIALIZE_SCALAR(haveSecurity);
414 UNSERIALIZE_SCALAR(haveLPAE);
415 UNSERIALIZE_SCALAR(haveVirtualization);
416 UNSERIALIZE_SCALAR(haveLargeAsid64);
417 UNSERIALIZE_SCALAR(physAddrRange64);
420 void startup(ThreadContext *tc) {}
422 /// Explicitly import the otherwise hidden startup
423 using SimObject::startup;
425 typedef ArmISAParams Params;
427 const Params *params() const;