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43 #ifndef __ARCH_ARM_ISA_HH__
44 #define __ARCH_ARM_ISA_HH__
46 #include "arch/arm/registers.hh"
47 #include "arch/arm/tlb.hh"
48 #include "arch/arm/types.hh"
59 MiscReg miscRegs[NumMiscRegs];
60 const IntRegIndex *intRegMap;
63 updateRegMap(CPSR cpsr)
68 intRegMap = IntRegUsrMap;
71 intRegMap = IntRegFiqMap;
74 intRegMap = IntRegIrqMap;
77 intRegMap = IntRegSvcMap;
80 intRegMap = IntRegMonMap;
83 intRegMap = IntRegAbtMap;
86 intRegMap = IntRegUndMap;
89 panic("Unrecognized mode setting in CPSR.\n");
96 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
98 memset(miscRegs, 0, sizeof(miscRegs));
100 cpsr.mode = MODE_USER;
101 miscRegs[MISCREG_CPSR] = cpsr;
105 sctlr.nmfi = (bool)sctlr_rst.nmfi;
106 sctlr.v = (bool)sctlr_rst.v;
112 miscRegs[MISCREG_SCTLR] = sctlr;
113 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
117 * Technically this should be 0, but we don't support those
124 miscRegs[MISCREG_CPACR] = cpacr;
126 /* Start with an event in the mailbox */
127 miscRegs[MISCREG_SEV_MAILBOX] = 1;
130 * Implemented = '5' from "M5",
133 miscRegs[MISCREG_MIDR] =
134 (0x35 << 24) | //Implementor is '5' from "M5"
135 (0 << 20) | //Variant
136 (0xf << 16) | //Architecture from CPUID scheme
137 (0 << 4) | //Primary part number
138 (0 << 0) | //Revision
141 // Separate Instruction and Data TLBs.
142 miscRegs[MISCREG_TLBTR] = 1;
145 mvfr0.advSimdRegisters = 2;
146 mvfr0.singlePrecision = 2;
147 mvfr0.doublePrecision = 2;
148 mvfr0.vfpExceptionTrapping = 0;
150 mvfr0.squareRoot = 1;
151 mvfr0.shortVectors = 1;
152 mvfr0.roundingModes = 1;
153 miscRegs[MISCREG_MVFR0] = mvfr0;
156 mvfr1.flushToZero = 1;
157 mvfr1.defaultNaN = 1;
158 mvfr1.advSimdLoadStore = 1;
159 mvfr1.advSimdInteger = 1;
160 mvfr1.advSimdSinglePrecision = 1;
161 mvfr1.advSimdHalfPrecision = 1;
162 mvfr1.vfpHalfPrecision = 1;
163 miscRegs[MISCREG_MVFR1] = mvfr1;
165 miscRegs[MISCREG_MPIDR] = 0;
167 //XXX We need to initialize the rest of the state.
170 MiscReg readMiscRegNoEffect(int misc_reg);
172 MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
174 void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
176 void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
179 flattenIntIndex(int reg)
182 if (reg < NUM_ARCH_INTREGS) {
183 return intRegMap[reg];
184 } else if (reg < NUM_INTREGS) {
187 int mode = reg / intRegsPerMode;
188 reg = reg % intRegsPerMode;
192 return INTREG_USR(reg);
194 return INTREG_FIQ(reg);
196 return INTREG_IRQ(reg);
198 return INTREG_SVC(reg);
200 return INTREG_MON(reg);
202 return INTREG_ABT(reg);
204 return INTREG_UND(reg);
206 panic("Flattening into an unknown mode.\n");
212 flattenFloatIndex(int reg)
217 void serialize(EventManager *em, std::ostream &os)
219 void unserialize(EventManager *em, Checkpoint *cp,
220 const std::string §ion)
227 miscRegs[MISCREG_SCTLR_RST] = sctlr;