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43 #ifndef __ARCH_ARM_ISA_HH__
44 #define __ARCH_MRM_ISA_HH__
46 #include "arch/arm/registers.hh"
47 #include "arch/arm/types.hh"
58 MiscReg miscRegs[NumMiscRegs];
59 const IntRegIndex *intRegMap;
62 updateRegMap(CPSR cpsr)
67 intRegMap = IntRegUsrMap;
70 intRegMap = IntRegFiqMap;
73 intRegMap = IntRegIrqMap;
76 intRegMap = IntRegSvcMap;
79 intRegMap = IntRegMonMap;
82 intRegMap = IntRegAbtMap;
85 intRegMap = IntRegUndMap;
88 panic("Unrecognized mode setting in CPSR.\n");
95 memset(miscRegs, 0, sizeof(miscRegs));
97 cpsr.mode = MODE_USER;
98 miscRegs[MISCREG_CPSR] = cpsr;
107 miscRegs[MISCREG_SCTLR] = sctlr;
110 * Technically this should be 0, but we don't support those
117 miscRegs[MISCREG_CPACR] = cpacr;
119 /* Start with an event in the mailbox */
120 miscRegs[MISCREG_SEV_MAILBOX] = 1;
123 * Implemented = '5' from "M5",
126 miscRegs[MISCREG_MIDR] =
127 (0x35 << 24) | //Implementor is '5' from "M5"
128 (0 << 20) | //Variant
129 (0xf << 16) | //Architecture from CPUID scheme
130 (0 << 4) | //Primary part number
131 (0 << 0) | //Revision
134 // Separate Instruction and Data TLBs.
135 miscRegs[MISCREG_TLBTR] = 1;
138 mvfr0.advSimdRegisters = 2;
139 mvfr0.singlePrecision = 2;
140 mvfr0.doublePrecision = 2;
141 mvfr0.vfpExceptionTrapping = 0;
143 mvfr0.squareRoot = 1;
144 mvfr0.shortVectors = 1;
145 mvfr0.roundingModes = 1;
146 miscRegs[MISCREG_MVFR0] = mvfr0;
149 mvfr1.flushToZero = 1;
150 mvfr1.defaultNaN = 1;
151 mvfr1.advSimdLoadStore = 1;
152 mvfr1.advSimdInteger = 1;
153 mvfr1.advSimdSinglePrecision = 1;
154 mvfr1.advSimdHalfPrecision = 1;
155 mvfr1.vfpHalfPrecision = 1;
156 miscRegs[MISCREG_MVFR1] = mvfr1;
158 //XXX We need to initialize the rest of the state.
162 readMiscRegNoEffect(int misc_reg)
164 assert(misc_reg < NumMiscRegs);
165 if (misc_reg == MISCREG_SPSR) {
166 CPSR cpsr = miscRegs[MISCREG_CPSR];
169 return miscRegs[MISCREG_SPSR];
171 return miscRegs[MISCREG_SPSR_FIQ];
173 return miscRegs[MISCREG_SPSR_IRQ];
175 return miscRegs[MISCREG_SPSR_SVC];
177 return miscRegs[MISCREG_SPSR_MON];
179 return miscRegs[MISCREG_SPSR_ABT];
181 return miscRegs[MISCREG_SPSR_UND];
183 return miscRegs[MISCREG_SPSR];
186 return miscRegs[misc_reg];
190 readMiscReg(int misc_reg, ThreadContext *tc)
192 if (misc_reg == MISCREG_CPSR) {
193 CPSR cpsr = miscRegs[misc_reg];
194 Addr pc = tc->readPC();
195 if (pc & (ULL(1) << PcJBitShift))
199 if (pc & (ULL(1) << PcTBitShift))
205 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
206 misc_reg < MISCREG_CP15_END) {
207 panic("Unimplemented CP15 register %s read.\n",
208 miscRegName[misc_reg]);
212 warn("The clidr register always reports 0 caches.\n");
215 warn("The ccsidr register isn't implemented and "
216 "always reads as 0.\n");
219 return readMiscRegNoEffect(misc_reg);
223 setMiscRegNoEffect(int misc_reg, const MiscReg &val)
225 assert(misc_reg < NumMiscRegs);
226 if (misc_reg == MISCREG_SPSR) {
227 CPSR cpsr = miscRegs[MISCREG_CPSR];
230 miscRegs[MISCREG_SPSR] = val;
233 miscRegs[MISCREG_SPSR_FIQ] = val;
236 miscRegs[MISCREG_SPSR_IRQ] = val;
239 miscRegs[MISCREG_SPSR_SVC] = val;
242 miscRegs[MISCREG_SPSR_MON] = val;
245 miscRegs[MISCREG_SPSR_ABT] = val;
248 miscRegs[MISCREG_SPSR_UND] = val;
251 miscRegs[MISCREG_SPSR] = val;
255 miscRegs[misc_reg] = val;
259 setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
261 MiscReg newVal = val;
262 if (misc_reg == MISCREG_CPSR) {
265 DPRINTF(Arm, "Updating CPSR to %#x f:%d i:%d a:%d mode:%#x\n",
266 cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
267 Addr npc = tc->readNextPC() & ~PcModeMask;
269 npc = npc | (ULL(1) << PcJBitShift);
271 npc = npc | (ULL(1) << PcTBitShift);
275 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
276 misc_reg < MISCREG_CP15_END) {
277 panic("Unimplemented CP15 register %s wrote with %#x.\n",
278 miscRegName[misc_reg], val);
284 CPACR valCpacr = val;
285 newCpacr.cp10 = valCpacr.cp10;
286 newCpacr.cp11 = valCpacr.cp11;
287 if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) {
288 panic("Disabling coprocessors isn't implemented.\n");
294 warn("The csselr register isn't implemented.\n");
301 return setMiscRegNoEffect(misc_reg, newVal);
305 flattenIntIndex(int reg)
308 if (reg < NUM_ARCH_INTREGS) {
309 return intRegMap[reg];
310 } else if (reg < NUM_INTREGS) {
313 int mode = reg / intRegsPerMode;
314 reg = reg % intRegsPerMode;
318 return INTREG_USR(reg);
320 return INTREG_FIQ(reg);
322 return INTREG_IRQ(reg);
324 return INTREG_SVC(reg);
326 return INTREG_MON(reg);
328 return INTREG_ABT(reg);
330 return INTREG_UND(reg);
332 panic("Flattening into an unknown mode.\n");
338 flattenFloatIndex(int reg)
343 void serialize(EventManager *em, std::ostream &os)
345 void unserialize(EventManager *em, Checkpoint *cp,
346 const std::string §ion)