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43 #ifndef __ARCH_ARM_ISA_HH__
44 #define __ARCH_ARM_ISA_HH__
46 #include "arch/arm/isa_device.hh"
47 #include "arch/arm/registers.hh"
48 #include "arch/arm/system.hh"
49 #include "arch/arm/tlb.hh"
50 #include "arch/arm/types.hh"
51 #include "debug/Checkpoint.hh"
52 #include "sim/sim_object.hh"
55 struct DummyArmISADeviceParams;
64 * At the moment there are 57 registers which need to be aliased/
65 * translated with other registers in the ISA. This enum helps with that
69 miscRegTranslateCSSELR_EL1,
70 miscRegTranslateSCTLR_EL1,
71 miscRegTranslateSCTLR_EL2,
72 miscRegTranslateACTLR_EL1,
73 miscRegTranslateACTLR_EL2,
74 miscRegTranslateCPACR_EL1,
75 miscRegTranslateCPTR_EL2,
76 miscRegTranslateHCR_EL2,
77 miscRegTranslateMDCR_EL2,
78 miscRegTranslateHSTR_EL2,
79 miscRegTranslateHACR_EL2,
80 miscRegTranslateTTBR0_EL1,
81 miscRegTranslateTTBR1_EL1,
82 miscRegTranslateTTBR0_EL2,
83 miscRegTranslateVTTBR_EL2,
84 miscRegTranslateTCR_EL1,
85 miscRegTranslateTCR_EL2,
86 miscRegTranslateVTCR_EL2,
87 miscRegTranslateAFSR0_EL1,
88 miscRegTranslateAFSR1_EL1,
89 miscRegTranslateAFSR0_EL2,
90 miscRegTranslateAFSR1_EL2,
91 miscRegTranslateESR_EL2,
92 miscRegTranslateFAR_EL1,
93 miscRegTranslateFAR_EL2,
94 miscRegTranslateHPFAR_EL2,
95 miscRegTranslatePAR_EL1,
96 miscRegTranslateMAIR_EL1,
97 miscRegTranslateMAIR_EL2,
98 miscRegTranslateAMAIR_EL1,
99 miscRegTranslateVBAR_EL1,
100 miscRegTranslateVBAR_EL2,
101 miscRegTranslateCONTEXTIDR_EL1,
102 miscRegTranslateTPIDR_EL0,
103 miscRegTranslateTPIDRRO_EL0,
104 miscRegTranslateTPIDR_EL1,
105 miscRegTranslateTPIDR_EL2,
106 miscRegTranslateTEECR32_EL1,
107 miscRegTranslateCNTFRQ_EL0,
108 miscRegTranslateCNTPCT_EL0,
109 miscRegTranslateCNTVCT_EL0,
110 miscRegTranslateCNTVOFF_EL2,
111 miscRegTranslateCNTKCTL_EL1,
112 miscRegTranslateCNTHCTL_EL2,
113 miscRegTranslateCNTP_TVAL_EL0,
114 miscRegTranslateCNTP_CTL_EL0,
115 miscRegTranslateCNTP_CVAL_EL0,
116 miscRegTranslateCNTV_TVAL_EL0,
117 miscRegTranslateCNTV_CTL_EL0,
118 miscRegTranslateCNTV_CVAL_EL0,
119 miscRegTranslateCNTHP_TVAL_EL2,
120 miscRegTranslateCNTHP_CTL_EL2,
121 miscRegTranslateCNTHP_CVAL_EL2,
122 miscRegTranslateDACR32_EL2,
123 miscRegTranslateIFSR32_EL2,
124 miscRegTranslateTEEHBR32_EL1,
125 miscRegTranslateSDER32_EL3,
129 class ISA : public SimObject
135 /** Dummy device for to handle non-existing ISA devices */
136 DummyISADevice dummyDevice;
138 // PMU belonging to this ISA
141 // Generic timer interface belonging to this ISA
142 std::unique_ptr<BaseISADevice> timer;
144 // Cached copies of system-level properties
147 bool haveVirtualization;
148 bool haveLargeAsid64;
149 uint8_t physAddrRange64;
151 /** Register translation entry used in lookUpMiscReg */
152 struct MiscRegLUTEntry {
157 struct MiscRegInitializerEntry {
159 struct MiscRegLUTEntry entry;
162 /** Register table noting all translations */
163 static const struct MiscRegInitializerEntry
164 MiscRegSwitch[miscRegTranslateMax];
166 /** Translation table accessible via the value of the register */
167 std::vector<struct MiscRegLUTEntry> lookUpMiscReg;
169 MiscReg miscRegs[NumMiscRegs];
170 const IntRegIndex *intRegMap;
173 updateRegMap(CPSR cpsr)
175 if (cpsr.width == 0) {
176 intRegMap = IntReg64Map;
181 intRegMap = IntRegUsrMap;
184 intRegMap = IntRegFiqMap;
187 intRegMap = IntRegIrqMap;
190 intRegMap = IntRegSvcMap;
193 intRegMap = IntRegMonMap;
196 intRegMap = IntRegAbtMap;
199 intRegMap = IntRegHypMap;
202 intRegMap = IntRegUndMap;
205 panic("Unrecognized mode setting in CPSR.\n");
210 BaseISADevice &getGenericTimer(ThreadContext *tc);
214 inline void assert32(ThreadContext *tc) {
215 CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc);
219 inline void assert64(ThreadContext *tc) {
220 CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc);
224 void tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid,
225 bool secure_lookup, uint8_t target_el);
227 void tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el);
229 void tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el);
231 void tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup,
232 bool hyp, uint8_t target_el);
236 void clear64(const ArmISAParams *p);
238 MiscReg readMiscRegNoEffect(int misc_reg) const;
239 MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
240 void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
241 void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
244 flattenIntIndex(int reg) const
247 if (reg < NUM_ARCH_INTREGS) {
248 return intRegMap[reg];
249 } else if (reg < NUM_INTREGS) {
251 } else if (reg == INTREG_SPX) {
252 CPSR cpsr = miscRegs[MISCREG_CPSR];
253 ExceptionLevel el = opModeToEL(
254 (OperatingMode) (uint8_t) cpsr.mode);
255 if (!cpsr.sp && el != EL0)
260 // @todo: uncomment this to enable Virtualization
262 // return INTREG_SP2;
268 panic("Invalid exception level");
272 return flattenIntRegModeIndex(reg);
277 flattenFloatIndex(int reg) const
284 flattenCCIndex(int reg) const
291 flattenMiscIndex(int reg) const
296 if (reg == MISCREG_SPSR) {
297 CPSR cpsr = miscRegs[MISCREG_CPSR];
300 warn("User mode does not have SPSR\n");
301 flat_idx = MISCREG_SPSR;
305 flat_idx = MISCREG_SPSR_EL1;
309 flat_idx = MISCREG_SPSR_EL2;
313 flat_idx = MISCREG_SPSR_EL3;
316 warn("User mode does not have SPSR\n");
317 flat_idx = MISCREG_SPSR;
320 flat_idx = MISCREG_SPSR_FIQ;
323 flat_idx = MISCREG_SPSR_IRQ;
326 flat_idx = MISCREG_SPSR_SVC;
329 flat_idx = MISCREG_SPSR_MON;
332 flat_idx = MISCREG_SPSR_ABT;
335 flat_idx = MISCREG_SPSR_HYP;
338 flat_idx = MISCREG_SPSR_UND;
341 warn("Trying to access SPSR in an invalid mode: %d\n",
343 flat_idx = MISCREG_SPSR;
346 } else if (miscRegInfo[reg][MISCREG_MUTEX]) {
347 // Mutually exclusive CP15 register
349 case MISCREG_PRRR_MAIR0:
350 case MISCREG_PRRR_MAIR0_NS:
351 case MISCREG_PRRR_MAIR0_S:
353 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
354 // If the muxed reg has been flattened, work out the
355 // offset and apply it to the unmuxed reg
356 int idxOffset = reg - MISCREG_PRRR_MAIR0;
358 flat_idx = flattenMiscIndex(MISCREG_MAIR0 +
361 flat_idx = flattenMiscIndex(MISCREG_PRRR +
365 case MISCREG_NMRR_MAIR1:
366 case MISCREG_NMRR_MAIR1_NS:
367 case MISCREG_NMRR_MAIR1_S:
369 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
370 // If the muxed reg has been flattened, work out the
371 // offset and apply it to the unmuxed reg
372 int idxOffset = reg - MISCREG_NMRR_MAIR1;
374 flat_idx = flattenMiscIndex(MISCREG_MAIR1 +
377 flat_idx = flattenMiscIndex(MISCREG_NMRR +
381 case MISCREG_PMXEVTYPER_PMCCFILTR:
383 PMSELR pmselr = miscRegs[MISCREG_PMSELR];
384 if (pmselr.sel == 31)
385 flat_idx = flattenMiscIndex(MISCREG_PMCCFILTR);
387 flat_idx = flattenMiscIndex(MISCREG_PMXEVTYPER);
391 panic("Unrecognized misc. register.\n");
395 if (miscRegInfo[reg][MISCREG_BANKED]) {
396 bool secureReg = haveSecurity &&
397 inSecureState(miscRegs[MISCREG_SCR],
398 miscRegs[MISCREG_CPSR]);
399 flat_idx += secureReg ? 2 : 1;
405 void serialize(CheckpointOut &cp) const
407 DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
408 SERIALIZE_ARRAY(miscRegs, NumMiscRegs);
410 SERIALIZE_SCALAR(haveSecurity);
411 SERIALIZE_SCALAR(haveLPAE);
412 SERIALIZE_SCALAR(haveVirtualization);
413 SERIALIZE_SCALAR(haveLargeAsid64);
414 SERIALIZE_SCALAR(physAddrRange64);
416 void unserialize(CheckpointIn &cp)
418 DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
419 UNSERIALIZE_ARRAY(miscRegs, NumMiscRegs);
420 CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
421 updateRegMap(tmp_cpsr);
423 UNSERIALIZE_SCALAR(haveSecurity);
424 UNSERIALIZE_SCALAR(haveLPAE);
425 UNSERIALIZE_SCALAR(haveVirtualization);
426 UNSERIALIZE_SCALAR(haveLargeAsid64);
427 UNSERIALIZE_SCALAR(physAddrRange64);
430 void startup(ThreadContext *tc) {}
432 /// Explicitly import the otherwise hidden startup
433 using SimObject::startup;
435 typedef ArmISAParams Params;
437 const Params *params() const;