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43 #ifndef __ARCH_ARM_ISA_HH__
44 #define __ARCH_MRM_ISA_HH__
46 #include "arch/arm/registers.hh"
47 #include "arch/arm/types.hh"
58 MiscReg miscRegs[NumMiscRegs];
59 const IntRegIndex *intRegMap;
62 updateRegMap(CPSR cpsr)
67 intRegMap = IntRegUsrMap;
70 intRegMap = IntRegFiqMap;
73 intRegMap = IntRegIrqMap;
76 intRegMap = IntRegSvcMap;
79 intRegMap = IntRegMonMap;
82 intRegMap = IntRegAbtMap;
85 intRegMap = IntRegUndMap;
88 panic("Unrecognized mode setting in CPSR.\n");
95 memset(miscRegs, 0, sizeof(miscRegs));
97 cpsr.mode = MODE_USER;
98 miscRegs[MISCREG_CPSR] = cpsr;
107 miscRegs[MISCREG_SCTLR] = sctlr;
110 * Technically this should be 0, but we don't support those
117 miscRegs[MISCREG_CPACR] = cpacr;
119 /* Start with an event in the mailbox */
120 miscRegs[MISCREG_SEV_MAILBOX] = 1;
123 * Implemented = '5' from "M5",
126 miscRegs[MISCREG_MIDR] =
127 (0x35 << 24) | //Implementor is '5' from "M5"
128 (0 << 20) | //Variant
129 (0xf << 16) | //Architecture from CPUID scheme
130 (0 << 4) | //Primary part number
131 (0 << 0) | //Revision
134 //XXX We need to initialize the rest of the state.
138 readMiscRegNoEffect(int misc_reg)
140 assert(misc_reg < NumMiscRegs);
141 if (misc_reg == MISCREG_SPSR) {
142 CPSR cpsr = miscRegs[MISCREG_CPSR];
145 return miscRegs[MISCREG_SPSR];
147 return miscRegs[MISCREG_SPSR_FIQ];
149 return miscRegs[MISCREG_SPSR_IRQ];
151 return miscRegs[MISCREG_SPSR_SVC];
153 return miscRegs[MISCREG_SPSR_MON];
155 return miscRegs[MISCREG_SPSR_ABT];
157 return miscRegs[MISCREG_SPSR_UND];
159 return miscRegs[MISCREG_SPSR];
162 return miscRegs[misc_reg];
166 readMiscReg(int misc_reg, ThreadContext *tc)
168 if (misc_reg == MISCREG_CPSR) {
169 CPSR cpsr = miscRegs[misc_reg];
170 Addr pc = tc->readPC();
171 if (pc & (ULL(1) << PcJBitShift))
175 if (pc & (ULL(1) << PcTBitShift))
181 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
182 misc_reg < MISCREG_CP15_END) {
183 panic("Unimplemented CP15 register %s read.\n",
184 miscRegName[misc_reg]);
188 warn("The clidr register always reports 0 caches.\n");
191 warn("The ccsidr register isn't implemented and "
192 "always reads as 0.\n");
195 return readMiscRegNoEffect(misc_reg);
199 setMiscRegNoEffect(int misc_reg, const MiscReg &val)
201 assert(misc_reg < NumMiscRegs);
202 if (misc_reg == MISCREG_SPSR) {
203 CPSR cpsr = miscRegs[MISCREG_CPSR];
206 miscRegs[MISCREG_SPSR] = val;
209 miscRegs[MISCREG_SPSR_FIQ] = val;
212 miscRegs[MISCREG_SPSR_IRQ] = val;
215 miscRegs[MISCREG_SPSR_SVC] = val;
218 miscRegs[MISCREG_SPSR_MON] = val;
221 miscRegs[MISCREG_SPSR_ABT] = val;
224 miscRegs[MISCREG_SPSR_UND] = val;
227 miscRegs[MISCREG_SPSR] = val;
231 miscRegs[misc_reg] = val;
235 setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
237 MiscReg newVal = val;
238 if (misc_reg == MISCREG_CPSR) {
241 DPRINTF(Arm, "Updating CPSR to %#x f:%d i:%d a:%d mode:%#x\n",
242 cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
243 Addr npc = tc->readNextPC() & ~PcModeMask;
245 npc = npc | (ULL(1) << PcJBitShift);
247 npc = npc | (ULL(1) << PcTBitShift);
251 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
252 misc_reg < MISCREG_CP15_END) {
253 panic("Unimplemented CP15 register %s wrote with %#x.\n",
254 miscRegName[misc_reg], val);
260 CPACR valCpacr = val;
261 newCpacr.cp10 = valCpacr.cp10;
262 newCpacr.cp11 = valCpacr.cp11;
263 if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) {
264 panic("Disabling coprocessors isn't implemented.\n");
270 warn("The csselr register isn't implemented.\n");
273 return setMiscRegNoEffect(misc_reg, newVal);
277 flattenIntIndex(int reg)
280 if (reg < NUM_ARCH_INTREGS) {
281 return intRegMap[reg];
282 } else if (reg < NUM_INTREGS) {
285 int mode = reg / intRegsPerMode;
286 reg = reg % intRegsPerMode;
290 return INTREG_USR(reg);
292 return INTREG_FIQ(reg);
294 return INTREG_IRQ(reg);
296 return INTREG_SVC(reg);
298 return INTREG_MON(reg);
300 return INTREG_ABT(reg);
302 return INTREG_UND(reg);
304 panic("Flattening into an unknown mode.\n");
310 flattenFloatIndex(int reg)
315 void serialize(EventManager *em, std::ostream &os)
317 void unserialize(EventManager *em, Checkpoint *cp,
318 const std::string §ion)