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43 #ifndef __ARCH_ARM_ISA_HH__
44 #define __ARCH_MRM_ISA_HH__
46 #include "arch/arm/registers.hh"
47 #include "arch/arm/types.hh"
58 MiscReg miscRegs[NumMiscRegs];
59 const IntRegIndex *intRegMap;
62 updateRegMap(CPSR cpsr)
67 intRegMap = IntRegUsrMap;
70 intRegMap = IntRegFiqMap;
73 intRegMap = IntRegIrqMap;
76 intRegMap = IntRegSvcMap;
79 intRegMap = IntRegMonMap;
82 intRegMap = IntRegAbtMap;
85 intRegMap = IntRegUndMap;
88 panic("Unrecognized mode setting in CPSR.\n");
95 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
97 memset(miscRegs, 0, sizeof(miscRegs));
99 cpsr.mode = MODE_USER;
100 miscRegs[MISCREG_CPSR] = cpsr;
104 sctlr.nmfi = (bool)sctlr_rst.nmfi;
105 sctlr.v = (bool)sctlr_rst.v;
111 miscRegs[MISCREG_SCTLR] = sctlr;
112 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
116 * Technically this should be 0, but we don't support those
123 miscRegs[MISCREG_CPACR] = cpacr;
125 /* Start with an event in the mailbox */
126 miscRegs[MISCREG_SEV_MAILBOX] = 1;
129 * Implemented = '5' from "M5",
132 miscRegs[MISCREG_MIDR] =
133 (0x35 << 24) | //Implementor is '5' from "M5"
134 (0 << 20) | //Variant
135 (0xf << 16) | //Architecture from CPUID scheme
136 (0 << 4) | //Primary part number
137 (0 << 0) | //Revision
140 // Separate Instruction and Data TLBs.
141 miscRegs[MISCREG_TLBTR] = 1;
144 mvfr0.advSimdRegisters = 2;
145 mvfr0.singlePrecision = 2;
146 mvfr0.doublePrecision = 2;
147 mvfr0.vfpExceptionTrapping = 0;
149 mvfr0.squareRoot = 1;
150 mvfr0.shortVectors = 1;
151 mvfr0.roundingModes = 1;
152 miscRegs[MISCREG_MVFR0] = mvfr0;
155 mvfr1.flushToZero = 1;
156 mvfr1.defaultNaN = 1;
157 mvfr1.advSimdLoadStore = 1;
158 mvfr1.advSimdInteger = 1;
159 mvfr1.advSimdSinglePrecision = 1;
160 mvfr1.advSimdHalfPrecision = 1;
161 mvfr1.vfpHalfPrecision = 1;
162 miscRegs[MISCREG_MVFR1] = mvfr1;
164 miscRegs[MISCREG_MPIDR] = 0;
166 //XXX We need to initialize the rest of the state.
170 readMiscRegNoEffect(int misc_reg)
172 assert(misc_reg < NumMiscRegs);
173 if (misc_reg == MISCREG_SPSR) {
174 CPSR cpsr = miscRegs[MISCREG_CPSR];
177 return miscRegs[MISCREG_SPSR];
179 return miscRegs[MISCREG_SPSR_FIQ];
181 return miscRegs[MISCREG_SPSR_IRQ];
183 return miscRegs[MISCREG_SPSR_SVC];
185 return miscRegs[MISCREG_SPSR_MON];
187 return miscRegs[MISCREG_SPSR_ABT];
189 return miscRegs[MISCREG_SPSR_UND];
191 return miscRegs[MISCREG_SPSR];
194 return miscRegs[misc_reg];
198 readMiscReg(int misc_reg, ThreadContext *tc)
200 if (misc_reg == MISCREG_CPSR) {
201 CPSR cpsr = miscRegs[misc_reg];
202 Addr pc = tc->readPC();
203 if (pc & (ULL(1) << PcJBitShift))
207 if (pc & (ULL(1) << PcTBitShift))
213 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
214 misc_reg < MISCREG_CP15_END) {
215 panic("Unimplemented CP15 register %s read.\n",
216 miscRegName[misc_reg]);
220 warn("The clidr register always reports 0 caches.\n");
223 warn("The ccsidr register isn't implemented and "
224 "always reads as 0.\n");
227 return readMiscRegNoEffect(misc_reg);
231 setMiscRegNoEffect(int misc_reg, const MiscReg &val)
233 assert(misc_reg < NumMiscRegs);
234 if (misc_reg == MISCREG_SPSR) {
235 CPSR cpsr = miscRegs[MISCREG_CPSR];
238 miscRegs[MISCREG_SPSR] = val;
241 miscRegs[MISCREG_SPSR_FIQ] = val;
244 miscRegs[MISCREG_SPSR_IRQ] = val;
247 miscRegs[MISCREG_SPSR_SVC] = val;
250 miscRegs[MISCREG_SPSR_MON] = val;
253 miscRegs[MISCREG_SPSR_ABT] = val;
256 miscRegs[MISCREG_SPSR_UND] = val;
259 miscRegs[MISCREG_SPSR] = val;
263 miscRegs[misc_reg] = val;
267 setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
269 MiscReg newVal = val;
270 if (misc_reg == MISCREG_CPSR) {
273 DPRINTF(Arm, "Updating CPSR to %#x f:%d i:%d a:%d mode:%#x\n",
274 cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
275 Addr npc = tc->readNextPC() & ~PcModeMask;
277 npc = npc | (ULL(1) << PcJBitShift);
279 npc = npc | (ULL(1) << PcTBitShift);
283 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
284 misc_reg < MISCREG_CP15_END) {
285 panic("Unimplemented CP15 register %s wrote with %#x.\n",
286 miscRegName[misc_reg], val);
292 CPACR valCpacr = val;
293 newCpacr.cp10 = valCpacr.cp10;
294 newCpacr.cp11 = valCpacr.cp11;
295 if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) {
296 panic("Disabling coprocessors isn't implemented.\n");
302 warn("The csselr register isn't implemented.\n");
306 const uint32_t ones = (uint32_t)(-1);
308 fpscrMask.ioc = ones;
309 fpscrMask.dzc = ones;
310 fpscrMask.ofc = ones;
311 fpscrMask.ufc = ones;
312 fpscrMask.ixc = ones;
313 fpscrMask.idc = ones;
314 fpscrMask.len = ones;
315 fpscrMask.stride = ones;
316 fpscrMask.rMode = ones;
319 fpscrMask.ahp = ones;
325 newVal = (newVal & (uint32_t)fpscrMask) |
326 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
331 const uint32_t fpexcMask = 0x60000000;
332 newVal = (newVal & fpexcMask) |
333 (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
338 SCTLR sctlr = miscRegs[MISCREG_SCTLR];
339 SCTLR new_sctlr = newVal;
340 new_sctlr.nmfi = (bool)sctlr.nmfi;
341 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
351 setMiscRegNoEffect(misc_reg, newVal);
355 flattenIntIndex(int reg)
358 if (reg < NUM_ARCH_INTREGS) {
359 return intRegMap[reg];
360 } else if (reg < NUM_INTREGS) {
363 int mode = reg / intRegsPerMode;
364 reg = reg % intRegsPerMode;
368 return INTREG_USR(reg);
370 return INTREG_FIQ(reg);
372 return INTREG_IRQ(reg);
374 return INTREG_SVC(reg);
376 return INTREG_MON(reg);
378 return INTREG_ABT(reg);
380 return INTREG_UND(reg);
382 panic("Flattening into an unknown mode.\n");
388 flattenFloatIndex(int reg)
393 void serialize(EventManager *em, std::ostream &os)
395 void unserialize(EventManager *em, Checkpoint *cp,
396 const std::string §ion)
403 miscRegs[MISCREG_SCTLR_RST] = sctlr;