src/arch/arm/isa.hh

   1 /*
   2  * Copyright (c) 2009 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  */
  30
  31 #ifndef __ARCH_ARM_ISA_HH__
  32 #define __ARCH_MRM_ISA_HH__
  33
  34 #include "arch/arm/registers.hh"
  35 #include "arch/arm/types.hh"
  36
  37 class ThreadContext;
  38 class Checkpoint;
  39 class EventManager;
  40
  41 namespace ArmISA
  42 {
  43     class ISA
  44     {
  45       protected:
  46         MiscReg miscRegs[NumMiscRegs];
  47
  48       public:
  49         void clear()
  50         {
  51             // Unknown startup state currently
  52         }
  53
  54         MiscReg
  55         readMiscRegNoEffect(int misc_reg)
  56         {
  57             assert(misc_reg < NumMiscRegs);
  58             return miscRegs[misc_reg];
  59         }
  60
  61         MiscReg
  62         readMiscReg(int misc_reg, ThreadContext *tc)
  63         {
  64             assert(misc_reg < NumMiscRegs);
  65             return miscRegs[misc_reg];
  66         }
  67
  68         void
  69         setMiscRegNoEffect(int misc_reg, const MiscReg &val)
  70         {
  71             assert(misc_reg < NumMiscRegs);
  72             miscRegs[misc_reg] = val;
  73         }
  74
  75         void
  76         setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
  77         {
  78             assert(misc_reg < NumMiscRegs);
  79             miscRegs[misc_reg] = val;
  80         }
  81
  82         int
  83         flattenIntIndex(int reg)
  84         {
  85             return reg;
  86         }
  87
  88         int
  89         flattenFloatIndex(int reg)
  90         {
  91             return reg;
  92         }
  93
  94         void serialize(std::ostream &os)
  95         {}
  96         void unserialize(Checkpoint *cp, const std::string &section)
  97         {}
  98
  99         ISA()
 100         {
 101             clear();
 102         }
 103     };
 104 }
 105
 106 #endif