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43 #ifndef __ARCH_ARM_ISA_HH__
44 #define __ARCH_MRM_ISA_HH__
46 #include "arch/arm/registers.hh"
47 #include "arch/arm/types.hh"
58 MiscReg miscRegs[NumMiscRegs];
59 const IntRegIndex *intRegMap;
62 updateRegMap(CPSR cpsr)
67 intRegMap = IntRegUsrMap;
70 intRegMap = IntRegFiqMap;
73 intRegMap = IntRegIrqMap;
76 intRegMap = IntRegSvcMap;
79 intRegMap = IntRegMonMap;
82 intRegMap = IntRegAbtMap;
85 intRegMap = IntRegUndMap;
88 panic("Unrecognized mode setting in CPSR.\n");
95 memset(miscRegs, 0, sizeof(miscRegs));
97 cpsr.mode = MODE_USER;
98 miscRegs[MISCREG_CPSR] = cpsr;
107 miscRegs[MISCREG_SCTLR] = sctlr;
110 * Technically this should be 0, but we don't support those
117 miscRegs[MISCREG_CPACR] = cpacr;
119 /* Start with an event in the mailbox */
120 miscRegs[MISCREG_SEV_MAILBOX] = 1;
123 * Implemented = '5' from "M5",
126 miscRegs[MISCREG_MIDR] =
127 (0x35 << 24) | //Implementor is '5' from "M5"
128 (0 << 20) | //Variant
129 (0xf << 16) | //Architecture from CPUID scheme
130 (0 << 4) | //Primary part number
131 (0 << 0) | //Revision
134 // Separate Instruction and Data TLBs.
135 miscRegs[MISCREG_TLBTR] = 1;
137 //XXX We need to initialize the rest of the state.
141 readMiscRegNoEffect(int misc_reg)
143 assert(misc_reg < NumMiscRegs);
144 if (misc_reg == MISCREG_SPSR) {
145 CPSR cpsr = miscRegs[MISCREG_CPSR];
148 return miscRegs[MISCREG_SPSR];
150 return miscRegs[MISCREG_SPSR_FIQ];
152 return miscRegs[MISCREG_SPSR_IRQ];
154 return miscRegs[MISCREG_SPSR_SVC];
156 return miscRegs[MISCREG_SPSR_MON];
158 return miscRegs[MISCREG_SPSR_ABT];
160 return miscRegs[MISCREG_SPSR_UND];
162 return miscRegs[MISCREG_SPSR];
165 return miscRegs[misc_reg];
169 readMiscReg(int misc_reg, ThreadContext *tc)
171 if (misc_reg == MISCREG_CPSR) {
172 CPSR cpsr = miscRegs[misc_reg];
173 Addr pc = tc->readPC();
174 if (pc & (ULL(1) << PcJBitShift))
178 if (pc & (ULL(1) << PcTBitShift))
184 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
185 misc_reg < MISCREG_CP15_END) {
186 panic("Unimplemented CP15 register %s read.\n",
187 miscRegName[misc_reg]);
191 warn("The clidr register always reports 0 caches.\n");
194 warn("The ccsidr register isn't implemented and "
195 "always reads as 0.\n");
198 return readMiscRegNoEffect(misc_reg);
202 setMiscRegNoEffect(int misc_reg, const MiscReg &val)
204 assert(misc_reg < NumMiscRegs);
205 if (misc_reg == MISCREG_SPSR) {
206 CPSR cpsr = miscRegs[MISCREG_CPSR];
209 miscRegs[MISCREG_SPSR] = val;
212 miscRegs[MISCREG_SPSR_FIQ] = val;
215 miscRegs[MISCREG_SPSR_IRQ] = val;
218 miscRegs[MISCREG_SPSR_SVC] = val;
221 miscRegs[MISCREG_SPSR_MON] = val;
224 miscRegs[MISCREG_SPSR_ABT] = val;
227 miscRegs[MISCREG_SPSR_UND] = val;
230 miscRegs[MISCREG_SPSR] = val;
234 miscRegs[misc_reg] = val;
238 setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
240 MiscReg newVal = val;
241 if (misc_reg == MISCREG_CPSR) {
244 DPRINTF(Arm, "Updating CPSR to %#x f:%d i:%d a:%d mode:%#x\n",
245 cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
246 Addr npc = tc->readNextPC() & ~PcModeMask;
248 npc = npc | (ULL(1) << PcJBitShift);
250 npc = npc | (ULL(1) << PcTBitShift);
254 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
255 misc_reg < MISCREG_CP15_END) {
256 panic("Unimplemented CP15 register %s wrote with %#x.\n",
257 miscRegName[misc_reg], val);
263 CPACR valCpacr = val;
264 newCpacr.cp10 = valCpacr.cp10;
265 newCpacr.cp11 = valCpacr.cp11;
266 if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) {
267 panic("Disabling coprocessors isn't implemented.\n");
273 warn("The csselr register isn't implemented.\n");
278 return setMiscRegNoEffect(misc_reg, newVal);
282 flattenIntIndex(int reg)
285 if (reg < NUM_ARCH_INTREGS) {
286 return intRegMap[reg];
287 } else if (reg < NUM_INTREGS) {
290 int mode = reg / intRegsPerMode;
291 reg = reg % intRegsPerMode;
295 return INTREG_USR(reg);
297 return INTREG_FIQ(reg);
299 return INTREG_IRQ(reg);
301 return INTREG_SVC(reg);
303 return INTREG_MON(reg);
305 return INTREG_ABT(reg);
307 return INTREG_UND(reg);
309 panic("Flattening into an unknown mode.\n");
315 flattenFloatIndex(int reg)
320 void serialize(EventManager *em, std::ostream &os)
322 void unserialize(EventManager *em, Checkpoint *cp,
323 const std::string §ion)