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45 #ifndef __ARCH_ARM_ISA_TRAITS_HH__
46 #define __ARCH_ARM_ISA_TRAITS_HH__
48 #include "arch/arm/types.hh"
49 #include "base/types.hh"
50 #include "cpu/static_inst_fwd.hh"
54 const ByteOrder GuestByteOrder = LittleEndianByteOrder;
56 StaticInstPtr decodeInst(ExtMachInst);
58 const Addr PageShift = 12;
59 const Addr PageBytes = ULL(1) << PageShift;
60 const Addr Page_Mask = ~(PageBytes - 1);
61 const Addr PageOffset = PageBytes - 1;
64 ////////////////////////////////////////////////////////////////////////
69 const Addr PteShift = 3;
70 const Addr NPtePageShift = PageShift - PteShift;
71 const Addr NPtePage = ULL(1) << NPtePageShift;
72 const Addr PteMask = NPtePage - 1;
74 //// All 'Mapped' segments go through the TLB
75 //// All other segments are translated by dropping the MSB, to give
76 //// the corresponding physical address
77 // User Segment - Mapped
78 const Addr USegBase = ULL(0x0);
79 const Addr USegEnd = ULL(0x7FFFFFFF);
81 const unsigned VABits = 32;
82 const unsigned PABits = 32; // Is this correct?
83 const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
84 const Addr VAddrUnImplMask = ~VAddrImplMask;
85 inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
86 inline Addr VAddrVPN(Addr a) { return a >> ArmISA::PageShift; }
87 inline Addr VAddrOffset(Addr a) { return a & ArmISA::PageOffset; }
89 const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
91 // Max. physical address range in bits supported by the architecture
92 const unsigned MaxPhysAddrRange = 48;
94 const int MachineBytes = 4;
96 const uint32_t HighVecs = 0xFFFF0000;
98 // Memory accesses cannot be unaligned
99 const bool HasUnalignedMemAcc = true;
101 const bool CurThreadInfoImplemented = false;
102 const int CurThreadInfoReg = -1;
110 INT_SEV, // Special interrupt for recieving SEV's
115 } // namespace ArmISA
117 using namespace ArmISA;
119 #endif // __ARCH_ARM_ISA_TRAITS_HH__