src/arch/arm/isa_traits.hh

   1 /*
   2  * Copyright (c) 2010 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2007-2008 The Florida State University
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Gabe Black
  42  *          Stephen Hines
  43  */
  44
  45 #ifndef __ARCH_ARM_ISA_TRAITS_HH__
  46 #define __ARCH_ARM_ISA_TRAITS_HH__
  47
  48 #include "arch/arm/types.hh"
  49 #include "base/types.hh"
  50
  51 namespace LittleEndianGuest {}
  52
  53 #define TARGET_ARM
  54
  55 class StaticInstPtr;
  56
  57 namespace ArmISA
  58 {
  59     using namespace LittleEndianGuest;
  60
  61     StaticInstPtr decodeInst(ExtMachInst);
  62
  63     // ARM DOES NOT have a delay slot
  64     #define ISA_HAS_DELAY_SLOT 0
  65
  66     const Addr PageShift = 12;
  67     const Addr PageBytes = ULL(1) << PageShift;
  68     const Addr Page_Mask = ~(PageBytes - 1);
  69     const Addr PageOffset = PageBytes - 1;
  70
  71
  72     ////////////////////////////////////////////////////////////////////////
  73     //
  74     //  Translation stuff
  75     //
  76
  77     const Addr PteShift = 3;
  78     const Addr NPtePageShift = PageShift - PteShift;
  79     const Addr NPtePage = ULL(1) << NPtePageShift;
  80     const Addr PteMask = NPtePage - 1;
  81
  82     //// All 'Mapped' segments go through the TLB
  83     //// All other segments are translated by dropping the MSB, to give
  84     //// the corresponding physical address
  85     // User Segment - Mapped
  86     const Addr USegBase = ULL(0x0);
  87     const Addr USegEnd = ULL(0x7FFFFFFF);
  88
  89     const unsigned VABits = 32;
  90     const unsigned PABits = 32; // Is this correct?
  91     const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
  92     const Addr VAddrUnImplMask = ~VAddrImplMask;
  93     inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
  94     inline Addr VAddrVPN(Addr a) { return a >> ArmISA::PageShift; }
  95     inline Addr VAddrOffset(Addr a) { return a & ArmISA::PageOffset; }
  96
  97     const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
  98
  99     // return a no-op instruction... used for instruction fetch faults
 100     const ExtMachInst NoopMachInst = 0x00000000;
 101
 102     const int LogVMPageSize = 12;       // 4K bytes
 103     const int VMPageSize = (1 << LogVMPageSize);
 104
 105     // Shouldn't this be 1 because of Thumb?! Dynamic? --Ali
 106     const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
 107
 108     const int MachineBytes = 4;
 109     const int WordBytes = 4;
 110     const int HalfwordBytes = 2;
 111     const int ByteBytes = 1;
 112
 113     const uint32_t HighVecs = 0xFFFF0000;
 114
 115     // Memory accesses cannot be unaligned
 116     const bool HasUnalignedMemAcc = true;
 117
 118     enum InterruptTypes
 119     {
 120         INT_RST,
 121         INT_ABT,
 122         INT_IRQ,
 123         INT_FIQ,
 124         NumInterruptTypes
 125     };
 126 } // namespace ArmISA
 127
 128 using namespace ArmISA;
 129
 130 #endif // __ARCH_ARM_ISA_TRAITS_HH__