src/arch/arm/kvm/base_cpu.cc

   1 /*
   2  * Copyright (c) 2012, 2015, 2017 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #include "arch/arm/kvm/base_cpu.hh"
  39
  40 #include <linux/kvm.h>
  41
  42 #include "arch/arm/interrupts.hh"
  43 #include "debug/KvmInt.hh"
  44 #include "dev/arm/generic_timer.hh"
  45 #include "params/BaseArmKvmCPU.hh"
  46 #include "params/GenericTimer.hh"
  47
  48 using namespace ArmISA;
  49
  50 #define INTERRUPT_ID(type, vcpu, irq) (                    \
  51         ((type) << KVM_ARM_IRQ_TYPE_SHIFT) |               \
  52         ((vcpu) << KVM_ARM_IRQ_VCPU_SHIFT) |               \
  53         ((irq) << KVM_ARM_IRQ_NUM_SHIFT))
  54
  55 #define INTERRUPT_VCPU_IRQ(vcpu)                                \
  56     INTERRUPT_ID(KVM_ARM_IRQ_TYPE_CPU, vcpu, KVM_ARM_IRQ_CPU_IRQ)
  57
  58 #define INTERRUPT_VCPU_FIQ(vcpu)                                \
  59     INTERRUPT_ID(KVM_ARM_IRQ_TYPE_CPU, vcpu, KVM_ARM_IRQ_CPU_FIQ)
  60
  61
  62 BaseArmKvmCPU::BaseArmKvmCPU(BaseArmKvmCPUParams *params)
  63     : BaseKvmCPU(params),
  64       irqAsserted(false), fiqAsserted(false),
  65       virtTimerPin(nullptr), prevDeviceIRQLevel(0)
  66 {
  67 }
  68
  69 BaseArmKvmCPU::~BaseArmKvmCPU()
  70 {
  71 }
  72
  73 void
  74 BaseArmKvmCPU::startup()
  75 {
  76     BaseKvmCPU::startup();
  77
  78     /* TODO: This needs to be moved when we start to support VMs with
  79      * multiple threads since kvmArmVCpuInit requires that all CPUs in
  80      * the VM have been created.
  81      */
  82     struct kvm_vcpu_init target_config;
  83     memset(&target_config, 0, sizeof(target_config));
  84
  85     vm.kvmArmPreferredTarget(target_config);
  86     if (!((ArmSystem *)system)->highestELIs64()) {
  87         target_config.features[0] |= (1 << KVM_ARM_VCPU_EL1_32BIT);
  88     }
  89     kvmArmVCpuInit(target_config);
  90
  91     if (!vm.hasKernelIRQChip())
  92         virtTimerPin = static_cast<ArmSystem *>(system)\
  93             ->getGenericTimer()->params()->int_virt->get(tc);
  94 }
  95
  96 Tick
  97 BaseArmKvmCPU::kvmRun(Tick ticks)
  98 {
  99     auto interrupt = static_cast<ArmISA::Interrupts *>(interrupts[0]);
 100     const bool simFIQ(interrupt->checkRaw(INT_FIQ));
 101     const bool simIRQ(interrupt->checkRaw(INT_IRQ));
 102
 103     if (!vm.hasKernelIRQChip()) {
 104         if (fiqAsserted != simFIQ) {
 105             DPRINTF(KvmInt, "KVM: Update FIQ state: %i\n", simFIQ);
 106             vm.setIRQLine(INTERRUPT_VCPU_FIQ(vcpuID), simFIQ);
 107         }
 108         if (irqAsserted != simIRQ) {
 109             DPRINTF(KvmInt, "KVM: Update IRQ state: %i\n", simIRQ);
 110             vm.setIRQLine(INTERRUPT_VCPU_IRQ(vcpuID), simIRQ);
 111         }
 112     } else {
 113         warn_if(simFIQ && !fiqAsserted,
 114                 "FIQ raised by the simulated interrupt controller " \
 115                 "despite in-kernel GIC emulation. This is probably a bug.");
 116
 117         warn_if(simIRQ && !irqAsserted,
 118                 "IRQ raised by the simulated interrupt controller " \
 119                 "despite in-kernel GIC emulation. This is probably a bug.");
 120     }
 121
 122     irqAsserted = simIRQ;
 123     fiqAsserted = simFIQ;
 124
 125     Tick kvmRunTicks = BaseKvmCPU::kvmRun(ticks);
 126
 127     if (!vm.hasKernelIRQChip()) {
 128         uint64_t device_irq_level =
 129             getKvmRunState()->s.regs.device_irq_level;
 130
 131         if (!(prevDeviceIRQLevel & KVM_ARM_DEV_EL1_VTIMER) &&
 132             (device_irq_level & KVM_ARM_DEV_EL1_VTIMER)) {
 133
 134             DPRINTF(KvmInt, "In-kernel vtimer IRQ asserted\n");
 135             prevDeviceIRQLevel |= KVM_ARM_DEV_EL1_VTIMER;
 136             virtTimerPin->raise();
 137
 138         } else if ((prevDeviceIRQLevel & KVM_ARM_DEV_EL1_VTIMER) &&
 139                    !(device_irq_level & KVM_ARM_DEV_EL1_VTIMER)) {
 140
 141             DPRINTF(KvmInt, "In-kernel vtimer IRQ disasserted\n");
 142             prevDeviceIRQLevel &= ~KVM_ARM_DEV_EL1_VTIMER;
 143             virtTimerPin->clear();
 144         }
 145     }
 146
 147     return kvmRunTicks;
 148 }
 149
 150 const BaseArmKvmCPU::RegIndexVector &
 151 BaseArmKvmCPU::getRegList() const
 152 {
 153     // Do we need to request a list of registers from the kernel?
 154     if (_regIndexList.size() == 0) {
 155         // Start by probing for the size of the list. We do this
 156         // calling the ioctl with a struct size of 0. The kernel will
 157         // return the number of elements required to hold the list.
 158         kvm_reg_list regs_probe;
 159         regs_probe.n = 0;
 160         getRegList(regs_probe);
 161
 162         // Request the actual register list now that we know how many
 163         // register we need to allocate space for.
 164         std::unique_ptr<struct kvm_reg_list> regs;
 165         const size_t size(sizeof(struct kvm_reg_list) +
 166                           regs_probe.n * sizeof(uint64_t));
 167         regs.reset((struct kvm_reg_list *)operator new(size));
 168         regs->n = regs_probe.n;
 169         if (!getRegList(*regs))
 170             panic("Failed to determine register list size.\n");
 171
 172         _regIndexList.assign(regs->reg, regs->reg + regs->n);
 173     }
 174
 175     return _regIndexList;
 176 }
 177
 178 void
 179 BaseArmKvmCPU::kvmArmVCpuInit(const struct kvm_vcpu_init &init)
 180 {
 181     if (ioctl(KVM_ARM_VCPU_INIT, (void *)&init) == -1)
 182         panic("KVM: Failed to initialize vCPU\n");
 183 }
 184
 185 bool
 186 BaseArmKvmCPU::getRegList(struct kvm_reg_list &regs) const
 187 {
 188     if (ioctl(KVM_GET_REG_LIST, (void *)&regs) == -1) {
 189         if (errno == E2BIG) {
 190             return false;
 191         } else {
 192             panic("KVM: Failed to get vCPU register list (errno: %i)\n",
 193                   errno);
 194         }
 195     } else {
 196         return true;
 197     }
 198 }