2 * Copyright (c) 2012, 2015, 2017 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 * Authors: Andreas Sandberg
40 #include "arch/arm/kvm/base_cpu.hh"
42 #include <linux/kvm.h>
44 #include "debug/KvmInt.hh"
45 #include "params/BaseArmKvmCPU.hh"
47 #define INTERRUPT_ID(type, vcpu, irq) ( \
48 ((type) << KVM_ARM_IRQ_TYPE_SHIFT) | \
49 ((vcpu) << KVM_ARM_IRQ_VCPU_SHIFT) | \
50 ((irq) << KVM_ARM_IRQ_NUM_SHIFT))
52 #define INTERRUPT_VCPU_IRQ(vcpu) \
53 INTERRUPT_ID(KVM_ARM_IRQ_TYPE_CPU, vcpu, KVM_ARM_IRQ_CPU_IRQ)
55 #define INTERRUPT_VCPU_FIQ(vcpu) \
56 INTERRUPT_ID(KVM_ARM_IRQ_TYPE_CPU, vcpu, KVM_ARM_IRQ_CPU_FIQ)
59 BaseArmKvmCPU::BaseArmKvmCPU(BaseArmKvmCPUParams
*params
)
61 irqAsserted(false), fiqAsserted(false)
65 BaseArmKvmCPU::~BaseArmKvmCPU()
70 BaseArmKvmCPU::startup()
72 BaseKvmCPU::startup();
74 /* TODO: This needs to be moved when we start to support VMs with
75 * multiple threads since kvmArmVCpuInit requires that all CPUs in
76 * the VM have been created.
78 struct kvm_vcpu_init target_config
;
79 memset(&target_config
, 0, sizeof(target_config
));
81 vm
.kvmArmPreferredTarget(target_config
);
82 if (!((ArmSystem
*)system
)->highestELIs64()) {
83 target_config
.features
[0] |= (1 << KVM_ARM_VCPU_EL1_32BIT
);
85 kvmArmVCpuInit(target_config
);
89 BaseArmKvmCPU::kvmRun(Tick ticks
)
91 const bool simFIQ(interrupts
[0]->checkRaw(INT_FIQ
));
92 const bool simIRQ(interrupts
[0]->checkRaw(INT_IRQ
));
94 if (!vm
.hasKernelIRQChip()) {
95 if (fiqAsserted
!= simFIQ
) {
96 DPRINTF(KvmInt
, "KVM: Update FIQ state: %i\n", simFIQ
);
97 vm
.setIRQLine(INTERRUPT_VCPU_FIQ(vcpuID
), simFIQ
);
99 if (irqAsserted
!= simIRQ
) {
100 DPRINTF(KvmInt
, "KVM: Update IRQ state: %i\n", simIRQ
);
101 vm
.setIRQLine(INTERRUPT_VCPU_IRQ(vcpuID
), simIRQ
);
104 warn_if(simFIQ
&& !fiqAsserted
,
105 "FIQ raised by the simulated interrupt controller " \
106 "despite in-kernel GIC emulation. This is probably a bug.");
108 warn_if(simIRQ
&& !irqAsserted
,
109 "IRQ raised by the simulated interrupt controller " \
110 "despite in-kernel GIC emulation. This is probably a bug.");
113 irqAsserted
= simIRQ
;
114 fiqAsserted
= simFIQ
;
116 return BaseKvmCPU::kvmRun(ticks
);
119 const BaseArmKvmCPU::RegIndexVector
&
120 BaseArmKvmCPU::getRegList() const
122 // Do we need to request a list of registers from the kernel?
123 if (_regIndexList
.size() == 0) {
124 // Start by probing for the size of the list. We do this
125 // calling the ioctl with a struct size of 0. The kernel will
126 // return the number of elements required to hold the list.
127 kvm_reg_list regs_probe
;
129 getRegList(regs_probe
);
131 // Request the actual register list now that we know how many
132 // register we need to allocate space for.
133 std::unique_ptr
<struct kvm_reg_list
> regs
;
134 const size_t size(sizeof(struct kvm_reg_list
) +
135 regs_probe
.n
* sizeof(uint64_t));
136 regs
.reset((struct kvm_reg_list
*)operator new(size
));
137 regs
->n
= regs_probe
.n
;
138 if (!getRegList(*regs
))
139 panic("Failed to determine register list size.\n");
141 _regIndexList
.assign(regs
->reg
, regs
->reg
+ regs
->n
);
144 return _regIndexList
;
148 BaseArmKvmCPU::kvmArmVCpuInit(const struct kvm_vcpu_init
&init
)
150 if (ioctl(KVM_ARM_VCPU_INIT
, (void *)&init
) == -1)
151 panic("KVM: Failed to initialize vCPU\n");
155 BaseArmKvmCPU::getRegList(struct kvm_reg_list
®s
) const
157 if (ioctl(KVM_GET_REG_LIST
, (void *)®s
) == -1) {
158 if (errno
== E2BIG
) {
161 panic("KVM: Failed to get vCPU register list (errno: %i)\n",