2 * Copyright (c) 2010-2013 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 #ifndef __ARCH_ARM_LINUX_SYSTEM_HH__
44 #define __ARCH_ARM_LINUX_SYSTEM_HH__
51 #include "arch/arm/system.hh"
52 #include "base/output.hh"
53 #include "kern/linux/events.hh"
54 #include "params/LinuxArmSystem.hh"
55 #include "sim/core.hh"
57 class DumpStatsPCEvent;
59 class LinuxArmSystem : public GenericArmSystem
62 DumpStatsPCEvent *dumpStatsPCEvent;
65 /** Boilerplate params code */
66 typedef LinuxArmSystemParams Params;
70 return dynamic_cast<const Params *>(_params);
73 /** When enabled, dump stats/task info on context switches for
74 * Streamline and per-thread cache occupancy studies, etc. */
75 bool enableContextSwitchStatsDump;
77 /** This map stores a mapping of OS process IDs to internal Task IDs. The
78 * mapping is done because the stats system doesn't tend to like vectors
79 * that are much greater than 1000 items and the entire process space is
81 std::map<uint32_t, uint32_t> taskMap;
83 /** This is a file that is placed in the run directory that prints out
84 * mappings between taskIds and OS process IDs */
85 std::ostream* taskFile;
87 LinuxArmSystem(Params *p);
92 bool adderBootUncacheable(Addr a);
96 /** This function creates a new task Id for the given pid.
97 * @param tc thread context that is currentyl executing */
98 void mapPid(ThreadContext* tc, uint32_t pid);
101 /** Event to halt the simulator if the kernel calls panic() */
102 PCEvent *kernelPanicEvent;
104 /** Event to halt the simulator if the kernel calls oopses */
105 PCEvent *kernelOopsEvent;
108 * PC based event to skip udelay(<time>) calls and quiesce the
109 * processor for the appropriate amount of time. This is not functionally
110 * required but does speed up simulation.
112 Linux::UDelayEvent *uDelaySkipEvent;
114 /** Another PC based skip event for const_udelay(). Similar to the udelay
115 * skip, but this function precomputes the first multiply that is done
116 * in the generic case since the parameter is known at compile time.
117 * Thus we need to do some division to get back to us.
119 Linux::UDelayEvent *constUDelaySkipEvent;
121 /** These variables store addresses of important data structures
122 * that are normaly kept coherent at boot with cache mainetence operations.
123 * Since these operations aren't supported in gem5, we keep them coherent
124 * by making them uncacheable until all processors in the system boot.
129 Addr pen64ReleaseAddr;
130 Addr bootReleaseAddr;
133 class DumpStatsPCEvent : public PCEvent
136 DumpStatsPCEvent(PCEventQueue *q, const std::string &desc, Addr addr)
137 : PCEvent(q, desc, addr)
140 virtual void process(ThreadContext* tc);
144 #endif // __ARCH_ARM_LINUX_SYSTEM_HH__