src/arch/arm/locked_mem.hh

   1 /*
   2  * Copyright (c) 2012-2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2006 The Regents of The University of Michigan
  15  * Copyright (c) 2007-2008 The Florida State University
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Ali Saidi
  42  *          Steve Reinhardt
  43  *          Stephen Hines
  44  */
  45
  46 #ifndef __ARCH_ARM_LOCKED_MEM_HH__
  47 #define __ARCH_ARM_LOCKED_MEM_HH__
  48
  49 /**
  50  * @file
  51  *
  52  * ISA-specific helper functions for locked memory accesses.
  53  */
  54
  55 #include "arch/arm/miscregs.hh"
  56 #include "arch/arm/isa_traits.hh"
  57 #include "debug/LLSC.hh"
  58 #include "mem/packet.hh"
  59 #include "mem/request.hh"
  60
  61 namespace ArmISA
  62 {
  63 template <class XC>
  64 inline void
  65 handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
  66 {
  67     DPRINTF(LLSC,"%s:  handleing snoop for address: %#x locked: %d\n",
  68             xc->getCpuPtr()->name(),pkt->getAddr(),
  69             xc->readMiscReg(MISCREG_LOCKFLAG));
  70     if (!xc->readMiscReg(MISCREG_LOCKFLAG))
  71         return;
  72
  73     Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
  74     // If no caches are attached, the snoop address always needs to be masked
  75     Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
  76
  77     DPRINTF(LLSC,"%s:  handleing snoop for address: %#x locked addr: %#x\n",
  78             xc->getCpuPtr()->name(),snoop_addr, locked_addr);
  79     if (locked_addr == snoop_addr) {
  80         DPRINTF(LLSC,"%s: address match, clearing lock and signaling sev\n",
  81                 xc->getCpuPtr()->name());
  82         xc->setMiscReg(MISCREG_LOCKFLAG, false);
  83         // Implement ARMv8 WFE/SEV semantics
  84         xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
  85         xc->getCpuPtr()->wakeup();
  86     }
  87 }
  88
  89 template <class XC>
  90 inline void
  91 handleLockedRead(XC *xc, Request *req)
  92 {
  93     xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr());
  94     xc->setMiscReg(MISCREG_LOCKFLAG, true);
  95     DPRINTF(LLSC,"%s: Placing address %#x in monitor\n", xc->getCpuPtr()->name(),
  96                  req->getPaddr());
  97 }
  98
  99 template <class XC>
 100 inline void
 101 handleLockedSnoopHit(XC *xc)
 102 {
 103     DPRINTF(LLSC,"%s:  handling snoop lock hit address: %#x\n",
 104             xc->getCpuPtr()->name(), xc->readMiscReg(MISCREG_LOCKADDR));
 105         xc->setMiscReg(MISCREG_LOCKFLAG, false);
 106         xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
 107 }
 108
 109 template <class XC>
 110 inline bool
 111 handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
 112 {
 113     if (req->isSwap())
 114         return true;
 115
 116     DPRINTF(LLSC,"%s: handling locked write for  address %#x in monitor\n",
 117             xc->getCpuPtr()->name(), req->getPaddr());
 118     // Verify that the lock flag is still set and the address
 119     // is correct
 120     bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
 121     Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
 122     if (!lock_flag || (req->getPaddr() & cacheBlockMask) != lock_addr) {
 123         // Lock flag not set or addr mismatch in CPU;
 124         // don't even bother sending to memory system
 125         req->setExtraData(0);
 126         xc->setMiscReg(MISCREG_LOCKFLAG, false);
 127         DPRINTF(LLSC,"%s: clearing lock flag in handle locked write\n",
 128                 xc->getCpuPtr()->name());
 129         // the rest of this code is not architectural;
 130         // it's just a debugging aid to help detect
 131         // livelock by warning on long sequences of failed
 132         // store conditionals
 133         int stCondFailures = xc->readStCondFailures();
 134         stCondFailures++;
 135         xc->setStCondFailures(stCondFailures);
 136         if (stCondFailures % 100000 == 0) {
 137             warn("context %d: %d consecutive "
 138                  "store conditional failures\n",
 139                  xc->contextId(), stCondFailures);
 140         }
 141
 142         // store conditional failed already, so don't issue it to mem
 143         return false;
 144     }
 145     return true;
 146 }
 147
 148
 149 } // namespace ArmISA
 150
 151 #endif