src/arch/arm/locked_mem.hh

   1 /*
   2  * Copyright (c) 2012-2013,2017 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2006 The Regents of The University of Michigan
  15  * Copyright (c) 2007-2008 The Florida State University
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  */
  41
  42 #ifndef __ARCH_ARM_LOCKED_MEM_HH__
  43 #define __ARCH_ARM_LOCKED_MEM_HH__
  44
  45 /**
  46  * @file
  47  *
  48  * ISA-specific helper functions for locked memory accesses.
  49  */
  50
  51 #include "arch/arm/miscregs.hh"
  52 #include "arch/arm/isa_traits.hh"
  53 #include "debug/LLSC.hh"
  54 #include "mem/packet.hh"
  55 #include "mem/request.hh"
  56
  57 namespace ArmISA
  58 {
  59 template <class XC>
  60 inline void
  61 handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
  62 {
  63     // Should only every see invalidations / direct writes
  64     assert(pkt->isInvalidate() || pkt->isWrite());
  65
  66     DPRINTF(LLSC,"%s:  handling snoop for address: %#x locked: %d\n",
  67             xc->getCpuPtr()->name(),pkt->getAddr(),
  68             xc->readMiscReg(MISCREG_LOCKFLAG));
  69     if (!xc->readMiscReg(MISCREG_LOCKFLAG))
  70         return;
  71
  72     Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
  73     // If no caches are attached, the snoop address always needs to be masked
  74     Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
  75
  76     DPRINTF(LLSC,"%s:  handling snoop for address: %#x locked addr: %#x\n",
  77             xc->getCpuPtr()->name(),snoop_addr, locked_addr);
  78     if (locked_addr == snoop_addr) {
  79         DPRINTF(LLSC,"%s: address match, clearing lock and signaling sev\n",
  80                 xc->getCpuPtr()->name());
  81         xc->setMiscReg(MISCREG_LOCKFLAG, false);
  82         // Implement ARMv8 WFE/SEV semantics
  83         xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
  84         xc->getCpuPtr()->wakeup(xc->threadId());
  85     }
  86 }
  87
  88 template <class XC>
  89 inline void
  90 handleLockedRead(XC *xc, const RequestPtr &req)
  91 {
  92     xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr());
  93     xc->setMiscReg(MISCREG_LOCKFLAG, true);
  94     DPRINTF(LLSC,"%s: Placing address %#x in monitor\n", xc->getCpuPtr()->name(),
  95                  req->getPaddr());
  96 }
  97
  98 template <class XC>
  99 inline void
 100 handleLockedSnoopHit(XC *xc)
 101 {
 102     DPRINTF(LLSC,"%s:  handling snoop lock hit address: %#x\n",
 103             xc->getCpuPtr()->name(), xc->readMiscReg(MISCREG_LOCKADDR));
 104         xc->setMiscReg(MISCREG_LOCKFLAG, false);
 105         xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
 106 }
 107
 108 template <class XC>
 109 inline bool
 110 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
 111 {
 112     if (req->isSwap())
 113         return true;
 114
 115     DPRINTF(LLSC,"%s: handling locked write for  address %#x in monitor\n",
 116             xc->getCpuPtr()->name(), req->getPaddr());
 117     // Verify that the lock flag is still set and the address
 118     // is correct
 119     bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
 120     Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
 121     if (!lock_flag || (req->getPaddr() & cacheBlockMask) != lock_addr) {
 122         // Lock flag not set or addr mismatch in CPU;
 123         // don't even bother sending to memory system
 124         req->setExtraData(0);
 125         xc->setMiscReg(MISCREG_LOCKFLAG, false);
 126         DPRINTF(LLSC,"%s: clearing lock flag in handle locked write\n",
 127                 xc->getCpuPtr()->name());
 128         // the rest of this code is not architectural;
 129         // it's just a debugging aid to help detect
 130         // livelock by warning on long sequences of failed
 131         // store conditionals
 132         int stCondFailures = xc->readStCondFailures();
 133         stCondFailures++;
 134         xc->setStCondFailures(stCondFailures);
 135         if (stCondFailures % 100000 == 0) {
 136             warn("context %d: %d consecutive "
 137                  "store conditional failures\n",
 138                  xc->contextId(), stCondFailures);
 139         }
 140
 141         // store conditional failed already, so don't issue it to mem
 142         return false;
 143     }
 144     return true;
 145 }
 146
 147 template <class XC>
 148 inline void
 149 globalClearExclusive(XC *xc)
 150 {
 151     // A spinlock would typically include a Wait For Event (WFE) to
 152     // conserve energy. The ARMv8 architecture specifies that an event
 153     // is automatically generated when clearing the exclusive monitor
 154     // to wake up the processor in WFE.
 155     DPRINTF(LLSC,"Clearing lock and signaling sev\n");
 156     xc->setMiscReg(MISCREG_LOCKFLAG, false);
 157     // Implement ARMv8 WFE/SEV semantics
 158     xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
 159     xc->getCpuPtr()->wakeup(xc->threadId());
 160 }
 161
 162 } // namespace ArmISA
 163
 164 #endif