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arm: Remove unnecessary boot uncachability
[gem5.git] / src / arch / arm / miscregs.cc
1 /*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 * Giacomo Gabrielli
40 */
41
42 #include "arch/arm/isa.hh"
43 #include "arch/arm/miscregs.hh"
44 #include "base/misc.hh"
45 #include "cpu/thread_context.hh"
46
47 namespace ArmISA
48 {
49
50 MiscRegIndex
51 decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
52 {
53 switch(crn) {
54 case 0:
55 switch (opc1) {
56 case 0:
57 switch (opc2) {
58 case 0:
59 switch (crm) {
60 case 0:
61 return MISCREG_DBGDIDR;
62 case 1:
63 return MISCREG_DBGDSCRint;
64 }
65 break;
66 }
67 break;
68 case 7:
69 switch (opc2) {
70 case 0:
71 switch (crm) {
72 case 0:
73 return MISCREG_JIDR;
74 }
75 break;
76 }
77 break;
78 }
79 break;
80 case 1:
81 switch (opc1) {
82 case 6:
83 switch (crm) {
84 case 0:
85 switch (opc2) {
86 case 0:
87 return MISCREG_TEEHBR;
88 }
89 break;
90 }
91 break;
92 case 7:
93 switch (crm) {
94 case 0:
95 switch (opc2) {
96 case 0:
97 return MISCREG_JOSCR;
98 }
99 break;
100 }
101 break;
102 }
103 break;
104 case 2:
105 switch (opc1) {
106 case 7:
107 switch (crm) {
108 case 0:
109 switch (opc2) {
110 case 0:
111 return MISCREG_JMCR;
112 }
113 break;
114 }
115 break;
116 }
117 break;
118 }
119 // If we get here then it must be a register that we haven't implemented
120 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
121 crn, opc1, crm, opc2);
122 return MISCREG_CP14_UNIMPL;
123 }
124
125 using namespace std;
126
127 bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS] = {
128 // MISCREG_CPSR
129 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
130 // MISCREG_SPSR
131 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
132 // MISCREG_SPSR_FIQ
133 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
134 // MISCREG_SPSR_IRQ
135 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
136 // MISCREG_SPSR_SVC
137 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
138 // MISCREG_SPSR_MON
139 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
140 // MISCREG_SPSR_ABT
141 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
142 // MISCREG_SPSR_HYP
143 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
144 // MISCREG_SPSR_UND
145 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
146 // MISCREG_ELR_HYP
147 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
148 // MISCREG_FPSID
149 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
150 // MISCREG_FPSCR
151 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
152 // MISCREG_MVFR1
153 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
154 // MISCREG_MVFR0
155 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
156 // MISCREG_FPEXC
157 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
158
159 // Helper registers
160 // MISCREG_CPSR_MODE
161 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
162 // MISCREG_CPSR_Q
163 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
164 // MISCREG_FPSCR_Q
165 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
166 // MISCREG_FPSCR_EXC
167 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
168 // MISCREG_LOCKADDR
169 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
170 // MISCREG_LOCKFLAG
171 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
172 // MISCREG_PRRR_MAIR0
173 bitset<NUM_MISCREG_INFOS>(string("00000000000000011001")),
174 // MISCREG_PRRR_MAIR0_NS
175 bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")),
176 // MISCREG_PRRR_MAIR0_S
177 bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")),
178 // MISCREG_NMRR_MAIR1
179 bitset<NUM_MISCREG_INFOS>(string("00000000000000011001")),
180 // MISCREG_NMRR_MAIR1_NS
181 bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")),
182 // MISCREG_NMRR_MAIR1_S
183 bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")),
184 // MISCREG_PMXEVTYPER_PMCCFILTR
185 bitset<NUM_MISCREG_INFOS>(string("00000000000000001001")),
186 // MISCREG_SCTLR_RST
187 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
188 // MISCREG_SEV_MAILBOX
189 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
190
191 // AArch32 CP14 registers
192 // MISCREG_DBGDIDR
193 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")),
194 // MISCREG_DBGDSCRint
195 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")),
196 // MISCREG_DBGDCCINT
197 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
198 // MISCREG_DBGDTRTXint
199 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
200 // MISCREG_DBGDTRRXint
201 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
202 // MISCREG_DBGWFAR
203 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
204 // MISCREG_DBGVCR
205 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
206 // MISCREG_DBGDTRRXext
207 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
208 // MISCREG_DBGDSCRext
209 bitset<NUM_MISCREG_INFOS>(string("11111111111111000100")),
210 // MISCREG_DBGDTRTXext
211 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
212 // MISCREG_DBGOSECCR
213 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
214 // MISCREG_DBGBVR0
215 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
216 // MISCREG_DBGBVR1
217 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
218 // MISCREG_DBGBVR2
219 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
220 // MISCREG_DBGBVR3
221 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
222 // MISCREG_DBGBVR4
223 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
224 // MISCREG_DBGBVR5
225 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
226 // MISCREG_DBGBCR0
227 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
228 // MISCREG_DBGBCR1
229 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
230 // MISCREG_DBGBCR2
231 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
232 // MISCREG_DBGBCR3
233 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
234 // MISCREG_DBGBCR4
235 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
236 // MISCREG_DBGBCR5
237 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
238 // MISCREG_DBGWVR0
239 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
240 // MISCREG_DBGWVR1
241 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
242 // MISCREG_DBGWVR2
243 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
244 // MISCREG_DBGWVR3
245 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
246 // MISCREG_DBGWCR0
247 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
248 // MISCREG_DBGWCR1
249 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
250 // MISCREG_DBGWCR2
251 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
252 // MISCREG_DBGWCR3
253 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
254 // MISCREG_DBGDRAR
255 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
256 // MISCREG_DBGBXVR4
257 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
258 // MISCREG_DBGBXVR5
259 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
260 // MISCREG_DBGOSLAR
261 bitset<NUM_MISCREG_INFOS>(string("10101111111111000000")),
262 // MISCREG_DBGOSLSR
263 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
264 // MISCREG_DBGOSDLR
265 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
266 // MISCREG_DBGPRCR
267 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
268 // MISCREG_DBGDSAR
269 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
270 // MISCREG_DBGCLAIMSET
271 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
272 // MISCREG_DBGCLAIMCLR
273 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
274 // MISCREG_DBGAUTHSTATUS
275 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
276 // MISCREG_DBGDEVID2
277 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
278 // MISCREG_DBGDEVID1
279 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
280 // MISCREG_DBGDEVID0
281 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")),
282 // MISCREG_TEECR
283 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
284 // MISCREG_JIDR
285 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
286 // MISCREG_TEEHBR
287 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
288 // MISCREG_JOSCR
289 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
290 // MISCREG_JMCR
291 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
292
293 // AArch32 CP15 registers
294 // MISCREG_MIDR
295 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
296 // MISCREG_CTR
297 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
298 // MISCREG_TCMTR
299 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
300 // MISCREG_TLBTR
301 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
302 // MISCREG_MPIDR
303 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
304 // MISCREG_REVIDR
305 bitset<NUM_MISCREG_INFOS>(string("01010101010000000100")),
306 // MISCREG_ID_PFR0
307 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
308 // MISCREG_ID_PFR1
309 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
310 // MISCREG_ID_DFR0
311 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
312 // MISCREG_ID_AFR0
313 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
314 // MISCREG_ID_MMFR0
315 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
316 // MISCREG_ID_MMFR1
317 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
318 // MISCREG_ID_MMFR2
319 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
320 // MISCREG_ID_MMFR3
321 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
322 // MISCREG_ID_ISAR0
323 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
324 // MISCREG_ID_ISAR1
325 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
326 // MISCREG_ID_ISAR2
327 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
328 // MISCREG_ID_ISAR3
329 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
330 // MISCREG_ID_ISAR4
331 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
332 // MISCREG_ID_ISAR5
333 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
334 // MISCREG_CCSIDR
335 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
336 // MISCREG_CLIDR
337 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
338 // MISCREG_AIDR
339 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
340 // MISCREG_CSSELR
341 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
342 // MISCREG_CSSELR_NS
343 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
344 // MISCREG_CSSELR_S
345 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
346 // MISCREG_VPIDR
347 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
348 // MISCREG_VMPIDR
349 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
350 // MISCREG_SCTLR
351 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
352 // MISCREG_SCTLR_NS
353 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
354 // MISCREG_SCTLR_S
355 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
356 // MISCREG_ACTLR
357 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
358 // MISCREG_ACTLR_NS
359 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
360 // MISCREG_ACTLR_S
361 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
362 // MISCREG_CPACR
363 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
364 // MISCREG_SCR
365 bitset<NUM_MISCREG_INFOS>(string("11110011000000000001")),
366 // MISCREG_SDER
367 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
368 // MISCREG_NSACR
369 bitset<NUM_MISCREG_INFOS>(string("11110111010000000001")),
370 // MISCREG_HSCTLR
371 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
372 // MISCREG_HACTLR
373 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
374 // MISCREG_HCR
375 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
376 // MISCREG_HDCR
377 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
378 // MISCREG_HCPTR
379 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
380 // MISCREG_HSTR
381 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
382 // MISCREG_HACR
383 bitset<NUM_MISCREG_INFOS>(string("11001100000000000100")),
384 // MISCREG_TTBR0
385 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
386 // MISCREG_TTBR0_NS
387 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
388 // MISCREG_TTBR0_S
389 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
390 // MISCREG_TTBR1
391 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
392 // MISCREG_TTBR1_NS
393 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
394 // MISCREG_TTBR1_S
395 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
396 // MISCREG_TTBCR
397 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
398 // MISCREG_TTBCR_NS
399 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
400 // MISCREG_TTBCR_S
401 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
402 // MISCREG_HTCR
403 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
404 // MISCREG_VTCR
405 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
406 // MISCREG_DACR
407 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
408 // MISCREG_DACR_NS
409 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
410 // MISCREG_DACR_S
411 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
412 // MISCREG_DFSR
413 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
414 // MISCREG_DFSR_NS
415 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
416 // MISCREG_DFSR_S
417 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
418 // MISCREG_IFSR
419 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
420 // MISCREG_IFSR_NS
421 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
422 // MISCREG_IFSR_S
423 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
424 // MISCREG_ADFSR
425 bitset<NUM_MISCREG_INFOS>(string("00000000000000010100")),
426 // MISCREG_ADFSR_NS
427 bitset<NUM_MISCREG_INFOS>(string("11001100110000100100")),
428 // MISCREG_ADFSR_S
429 bitset<NUM_MISCREG_INFOS>(string("00110011000000100100")),
430 // MISCREG_AIFSR
431 bitset<NUM_MISCREG_INFOS>(string("00000000000000010100")),
432 // MISCREG_AIFSR_NS
433 bitset<NUM_MISCREG_INFOS>(string("11001100110000100100")),
434 // MISCREG_AIFSR_S
435 bitset<NUM_MISCREG_INFOS>(string("00110011000000100100")),
436 // MISCREG_HADFSR
437 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
438 // MISCREG_HAIFSR
439 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
440 // MISCREG_HSR
441 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
442 // MISCREG_DFAR
443 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
444 // MISCREG_DFAR_NS
445 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
446 // MISCREG_DFAR_S
447 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
448 // MISCREG_IFAR
449 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
450 // MISCREG_IFAR_NS
451 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
452 // MISCREG_IFAR_S
453 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
454 // MISCREG_HDFAR
455 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
456 // MISCREG_HIFAR
457 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
458 // MISCREG_HPFAR
459 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
460 // MISCREG_ICIALLUIS
461 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
462 // MISCREG_BPIALLIS
463 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
464 // MISCREG_PAR
465 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
466 // MISCREG_PAR_NS
467 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
468 // MISCREG_PAR_S
469 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
470 // MISCREG_ICIALLU
471 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
472 // MISCREG_ICIMVAU
473 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
474 // MISCREG_CP15ISB
475 bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")),
476 // MISCREG_BPIALL
477 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
478 // MISCREG_BPIMVA
479 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
480 // MISCREG_DCIMVAC
481 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
482 // MISCREG_DCISW
483 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
484 // MISCREG_ATS1CPR
485 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
486 // MISCREG_ATS1CPW
487 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
488 // MISCREG_ATS1CUR
489 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
490 // MISCREG_ATS1CUW
491 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
492 // MISCREG_ATS12NSOPR
493 bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")),
494 // MISCREG_ATS12NSOPW
495 bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")),
496 // MISCREG_ATS12NSOUR
497 bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")),
498 // MISCREG_ATS12NSOUW
499 bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")),
500 // MISCREG_DCCMVAC
501 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
502 // MISCREG_DCCSW
503 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
504 // MISCREG_CP15DSB
505 bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")),
506 // MISCREG_CP15DMB
507 bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")),
508 // MISCREG_DCCMVAU
509 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
510 // MISCREG_DCCIMVAC
511 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
512 // MISCREG_DCCISW
513 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")),
514 // MISCREG_ATS1HR
515 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
516 // MISCREG_ATS1HW
517 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
518 // MISCREG_TLBIALLIS
519 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
520 // MISCREG_TLBIMVAIS
521 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
522 // MISCREG_TLBIASIDIS
523 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
524 // MISCREG_TLBIMVAAIS
525 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
526 // MISCREG_TLBIMVALIS
527 bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")),
528 // MISCREG_TLBIMVAALIS
529 bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")),
530 // MISCREG_ITLBIALL
531 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
532 // MISCREG_ITLBIMVA
533 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
534 // MISCREG_ITLBIASID
535 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
536 // MISCREG_DTLBIALL
537 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
538 // MISCREG_DTLBIMVA
539 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
540 // MISCREG_DTLBIASID
541 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
542 // MISCREG_TLBIALL
543 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
544 // MISCREG_TLBIMVA
545 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
546 // MISCREG_TLBIASID
547 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
548 // MISCREG_TLBIMVAA
549 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
550 // MISCREG_TLBIMVAL
551 bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")),
552 // MISCREG_TLBIMVAAL
553 bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")),
554 // MISCREG_TLBIIPAS2IS
555 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")),
556 // MISCREG_TLBIIPAS2LIS
557 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")),
558 // MISCREG_TLBIALLHIS
559 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
560 // MISCREG_TLBIMVAHIS
561 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
562 // MISCREG_TLBIALLNSNHIS
563 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
564 // MISCREG_TLBIMVALHIS
565 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")),
566 // MISCREG_TLBIIPAS2
567 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")),
568 // MISCREG_TLBIIPAS2L
569 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")),
570 // MISCREG_TLBIALLH
571 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
572 // MISCREG_TLBIMVAH
573 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
574 // MISCREG_TLBIALLNSNH
575 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
576 // MISCREG_TLBIMVALH
577 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")),
578 // MISCREG_PMCR
579 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
580 // MISCREG_PMCNTENSET
581 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
582 // MISCREG_PMCNTENCLR
583 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
584 // MISCREG_PMOVSR
585 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
586 // MISCREG_PMSWINC
587 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
588 // MISCREG_PMSELR
589 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
590 // MISCREG_PMCEID0
591 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
592 // MISCREG_PMCEID1
593 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
594 // MISCREG_PMCCNTR
595 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
596 // MISCREG_PMXEVTYPER
597 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
598 // MISCREG_PMCCFILTR
599 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
600 // MISCREG_PMXEVCNTR
601 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
602 // MISCREG_PMUSERENR
603 bitset<NUM_MISCREG_INFOS>(string("11111111110101000001")),
604 // MISCREG_PMINTENSET
605 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
606 // MISCREG_PMINTENCLR
607 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
608 // MISCREG_PMOVSSET
609 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")),
610 // MISCREG_L2CTLR
611 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
612 // MISCREG_L2ECTLR
613 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
614 // MISCREG_PRRR
615 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
616 // MISCREG_PRRR_NS
617 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
618 // MISCREG_PRRR_S
619 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
620 // MISCREG_MAIR0
621 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
622 // MISCREG_MAIR0_NS
623 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
624 // MISCREG_MAIR0_S
625 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
626 // MISCREG_NMRR
627 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
628 // MISCREG_NMRR_NS
629 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
630 // MISCREG_NMRR_S
631 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
632 // MISCREG_MAIR1
633 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
634 // MISCREG_MAIR1_NS
635 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
636 // MISCREG_MAIR1_S
637 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
638 // MISCREG_AMAIR0
639 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
640 // MISCREG_AMAIR0_NS
641 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
642 // MISCREG_AMAIR0_S
643 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
644 // MISCREG_AMAIR1
645 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
646 // MISCREG_AMAIR1_NS
647 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
648 // MISCREG_AMAIR1_S
649 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
650 // MISCREG_HMAIR0
651 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
652 // MISCREG_HMAIR1
653 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
654 // MISCREG_HAMAIR0
655 bitset<NUM_MISCREG_INFOS>(string("11001100000000000100")),
656 // MISCREG_HAMAIR1
657 bitset<NUM_MISCREG_INFOS>(string("11001100000000000100")),
658 // MISCREG_VBAR
659 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
660 // MISCREG_VBAR_NS
661 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
662 // MISCREG_VBAR_S
663 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
664 // MISCREG_MVBAR
665 bitset<NUM_MISCREG_INFOS>(string("11110011000000000001")),
666 // MISCREG_RMR
667 bitset<NUM_MISCREG_INFOS>(string("11110011000000000000")),
668 // MISCREG_ISR
669 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
670 // MISCREG_HVBAR
671 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
672 // MISCREG_FCSEIDR
673 bitset<NUM_MISCREG_INFOS>(string("11111111110000000100")),
674 // MISCREG_CONTEXTIDR
675 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
676 // MISCREG_CONTEXTIDR_NS
677 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
678 // MISCREG_CONTEXTIDR_S
679 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
680 // MISCREG_TPIDRURW
681 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
682 // MISCREG_TPIDRURW_NS
683 bitset<NUM_MISCREG_INFOS>(string("11001100111111100001")),
684 // MISCREG_TPIDRURW_S
685 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
686 // MISCREG_TPIDRURO
687 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
688 // MISCREG_TPIDRURO_NS
689 bitset<NUM_MISCREG_INFOS>(string("11001100110101100001")),
690 // MISCREG_TPIDRURO_S
691 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
692 // MISCREG_TPIDRPRW
693 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
694 // MISCREG_TPIDRPRW_NS
695 bitset<NUM_MISCREG_INFOS>(string("11001100110000100001")),
696 // MISCREG_TPIDRPRW_S
697 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")),
698 // MISCREG_HTPIDR
699 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
700 // MISCREG_CNTFRQ
701 bitset<NUM_MISCREG_INFOS>(string("11110101010101000011")),
702 // MISCREG_CNTKCTL
703 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
704 // MISCREG_CNTP_TVAL
705 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
706 // MISCREG_CNTP_TVAL_NS
707 bitset<NUM_MISCREG_INFOS>(string("11001100111111100001")),
708 // MISCREG_CNTP_TVAL_S
709 bitset<NUM_MISCREG_INFOS>(string("00110011001111100000")),
710 // MISCREG_CNTP_CTL
711 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
712 // MISCREG_CNTP_CTL_NS
713 bitset<NUM_MISCREG_INFOS>(string("11001100111111100001")),
714 // MISCREG_CNTP_CTL_S
715 bitset<NUM_MISCREG_INFOS>(string("00110011001111100000")),
716 // MISCREG_CNTV_TVAL
717 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
718 // MISCREG_CNTV_CTL
719 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
720 // MISCREG_CNTHCTL
721 bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")),
722 // MISCREG_CNTHP_TVAL
723 bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")),
724 // MISCREG_CNTHP_CTL
725 bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")),
726 // MISCREG_IL1DATA0
727 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
728 // MISCREG_IL1DATA1
729 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
730 // MISCREG_IL1DATA2
731 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
732 // MISCREG_IL1DATA3
733 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
734 // MISCREG_DL1DATA0
735 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
736 // MISCREG_DL1DATA1
737 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
738 // MISCREG_DL1DATA2
739 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
740 // MISCREG_DL1DATA3
741 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
742 // MISCREG_DL1DATA4
743 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
744 // MISCREG_RAMINDEX
745 bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")),
746 // MISCREG_L2ACTLR
747 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
748 // MISCREG_CBAR
749 bitset<NUM_MISCREG_INFOS>(string("01010101010000000000")),
750 // MISCREG_HTTBR
751 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
752 // MISCREG_VTTBR
753 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
754 // MISCREG_CNTPCT
755 bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")),
756 // MISCREG_CNTVCT
757 bitset<NUM_MISCREG_INFOS>(string("01010101010101000011")),
758 // MISCREG_CNTP_CVAL
759 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")),
760 // MISCREG_CNTP_CVAL_NS
761 bitset<NUM_MISCREG_INFOS>(string("11001100111111100001")),
762 // MISCREG_CNTP_CVAL_S
763 bitset<NUM_MISCREG_INFOS>(string("00110011001111100000")),
764 // MISCREG_CNTV_CVAL
765 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
766 // MISCREG_CNTVOFF
767 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")),
768 // MISCREG_CNTHP_CVAL
769 bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")),
770 // MISCREG_CPUMERRSR
771 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")),
772 // MISCREG_L2MERRSR
773 bitset<NUM_MISCREG_INFOS>(string("11111111110000000100")),
774
775 // AArch64 registers (Op0=2)
776 // MISCREG_MDCCINT_EL1
777 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
778 // MISCREG_OSDTRRX_EL1
779 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
780 // MISCREG_MDSCR_EL1
781 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
782 // MISCREG_OSDTRTX_EL1
783 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
784 // MISCREG_OSECCR_EL1
785 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
786 // MISCREG_DBGBVR0_EL1
787 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
788 // MISCREG_DBGBVR1_EL1
789 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
790 // MISCREG_DBGBVR2_EL1
791 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
792 // MISCREG_DBGBVR3_EL1
793 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
794 // MISCREG_DBGBVR4_EL1
795 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
796 // MISCREG_DBGBVR5_EL1
797 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
798 // MISCREG_DBGBCR0_EL1
799 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
800 // MISCREG_DBGBCR1_EL1
801 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
802 // MISCREG_DBGBCR2_EL1
803 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
804 // MISCREG_DBGBCR3_EL1
805 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
806 // MISCREG_DBGBCR4_EL1
807 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
808 // MISCREG_DBGBCR5_EL1
809 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
810 // MISCREG_DBGWVR0_EL1
811 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
812 // MISCREG_DBGWVR1_EL1
813 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
814 // MISCREG_DBGWVR2_EL1
815 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
816 // MISCREG_DBGWVR3_EL1
817 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
818 // MISCREG_DBGWCR0_EL1
819 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
820 // MISCREG_DBGWCR1_EL1
821 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
822 // MISCREG_DBGWCR2_EL1
823 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
824 // MISCREG_DBGWCR3_EL1
825 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
826 // MISCREG_MDCCSR_EL0
827 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")),
828 // MISCREG_MDDTR_EL0
829 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
830 // MISCREG_MDDTRTX_EL0
831 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
832 // MISCREG_MDDTRRX_EL0
833 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
834 // MISCREG_DBGVCR32_EL2
835 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
836 // MISCREG_MDRAR_EL1
837 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")),
838 // MISCREG_OSLAR_EL1
839 bitset<NUM_MISCREG_INFOS>(string("10101111111111000001")),
840 // MISCREG_OSLSR_EL1
841 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")),
842 // MISCREG_OSDLR_EL1
843 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
844 // MISCREG_DBGPRCR_EL1
845 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
846 // MISCREG_DBGCLAIMSET_EL1
847 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
848 // MISCREG_DBGCLAIMCLR_EL1
849 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
850 // MISCREG_DBGAUTHSTATUS_EL1
851 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")),
852 // MISCREG_TEECR32_EL1
853 bitset<NUM_MISCREG_INFOS>(string("00000000000000000001")),
854 // MISCREG_TEEHBR32_EL1
855 bitset<NUM_MISCREG_INFOS>(string("00000000000000000001")),
856
857 // AArch64 registers (Op0=1,3)
858 // MISCREG_MIDR_EL1
859 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
860 // MISCREG_MPIDR_EL1
861 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
862 // MISCREG_REVIDR_EL1
863 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
864 // MISCREG_ID_PFR0_EL1
865 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
866 // MISCREG_ID_PFR1_EL1
867 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
868 // MISCREG_ID_DFR0_EL1
869 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
870 // MISCREG_ID_AFR0_EL1
871 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
872 // MISCREG_ID_MMFR0_EL1
873 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
874 // MISCREG_ID_MMFR1_EL1
875 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
876 // MISCREG_ID_MMFR2_EL1
877 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
878 // MISCREG_ID_MMFR3_EL1
879 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
880 // MISCREG_ID_ISAR0_EL1
881 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
882 // MISCREG_ID_ISAR1_EL1
883 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
884 // MISCREG_ID_ISAR2_EL1
885 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
886 // MISCREG_ID_ISAR3_EL1
887 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
888 // MISCREG_ID_ISAR4_EL1
889 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
890 // MISCREG_ID_ISAR5_EL1
891 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
892 // MISCREG_MVFR0_EL1
893 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
894 // MISCREG_MVFR1_EL1
895 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
896 // MISCREG_MVFR2_EL1
897 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
898 // MISCREG_ID_AA64PFR0_EL1
899 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
900 // MISCREG_ID_AA64PFR1_EL1
901 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
902 // MISCREG_ID_AA64DFR0_EL1
903 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
904 // MISCREG_ID_AA64DFR1_EL1
905 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
906 // MISCREG_ID_AA64AFR0_EL1
907 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
908 // MISCREG_ID_AA64AFR1_EL1
909 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
910 // MISCREG_ID_AA64ISAR0_EL1
911 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
912 // MISCREG_ID_AA64ISAR1_EL1
913 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
914 // MISCREG_ID_AA64MMFR0_EL1
915 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
916 // MISCREG_ID_AA64MMFR1_EL1
917 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
918 // MISCREG_CCSIDR_EL1
919 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
920 // MISCREG_CLIDR_EL1
921 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
922 // MISCREG_AIDR_EL1
923 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
924 // MISCREG_CSSELR_EL1
925 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
926 // MISCREG_CTR_EL0
927 bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")),
928 // MISCREG_DCZID_EL0
929 bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")),
930 // MISCREG_VPIDR_EL2
931 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
932 // MISCREG_VMPIDR_EL2
933 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
934 // MISCREG_SCTLR_EL1
935 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
936 // MISCREG_ACTLR_EL1
937 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
938 // MISCREG_CPACR_EL1
939 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
940 // MISCREG_SCTLR_EL2
941 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
942 // MISCREG_ACTLR_EL2
943 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
944 // MISCREG_HCR_EL2
945 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
946 // MISCREG_MDCR_EL2
947 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
948 // MISCREG_CPTR_EL2
949 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
950 // MISCREG_HSTR_EL2
951 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
952 // MISCREG_HACR_EL2
953 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
954 // MISCREG_SCTLR_EL3
955 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
956 // MISCREG_ACTLR_EL3
957 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
958 // MISCREG_SCR_EL3
959 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
960 // MISCREG_SDER32_EL3
961 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
962 // MISCREG_CPTR_EL3
963 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
964 // MISCREG_MDCR_EL3
965 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
966 // MISCREG_TTBR0_EL1
967 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
968 // MISCREG_TTBR1_EL1
969 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
970 // MISCREG_TCR_EL1
971 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
972 // MISCREG_TTBR0_EL2
973 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
974 // MISCREG_TCR_EL2
975 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
976 // MISCREG_VTTBR_EL2
977 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
978 // MISCREG_VTCR_EL2
979 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
980 // MISCREG_TTBR0_EL3
981 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
982 // MISCREG_TCR_EL3
983 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
984 // MISCREG_DACR32_EL2
985 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
986 // MISCREG_SPSR_EL1
987 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
988 // MISCREG_ELR_EL1
989 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
990 // MISCREG_SP_EL0
991 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
992 // MISCREG_SPSEL
993 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
994 // MISCREG_CURRENTEL
995 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
996 // MISCREG_NZCV
997 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
998 // MISCREG_DAIF
999 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1000 // MISCREG_FPCR
1001 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1002 // MISCREG_FPSR
1003 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1004 // MISCREG_DSPSR_EL0
1005 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1006 // MISCREG_DLR_EL0
1007 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1008 // MISCREG_SPSR_EL2
1009 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1010 // MISCREG_ELR_EL2
1011 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1012 // MISCREG_SP_EL1
1013 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1014 // MISCREG_SPSR_IRQ_AA64
1015 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1016 // MISCREG_SPSR_ABT_AA64
1017 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1018 // MISCREG_SPSR_UND_AA64
1019 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1020 // MISCREG_SPSR_FIQ_AA64
1021 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1022 // MISCREG_SPSR_EL3
1023 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1024 // MISCREG_ELR_EL3
1025 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1026 // MISCREG_SP_EL2
1027 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1028 // MISCREG_AFSR0_EL1
1029 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1030 // MISCREG_AFSR1_EL1
1031 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1032 // MISCREG_ESR_EL1
1033 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1034 // MISCREG_IFSR32_EL2
1035 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1036 // MISCREG_AFSR0_EL2
1037 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1038 // MISCREG_AFSR1_EL2
1039 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1040 // MISCREG_ESR_EL2
1041 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1042 // MISCREG_FPEXC32_EL2
1043 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1044 // MISCREG_AFSR0_EL3
1045 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1046 // MISCREG_AFSR1_EL3
1047 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1048 // MISCREG_ESR_EL3
1049 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1050 // MISCREG_FAR_EL1
1051 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1052 // MISCREG_FAR_EL2
1053 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1054 // MISCREG_HPFAR_EL2
1055 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1056 // MISCREG_FAR_EL3
1057 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1058 // MISCREG_IC_IALLUIS
1059 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
1060 // MISCREG_PAR_EL1
1061 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1062 // MISCREG_IC_IALLU
1063 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
1064 // MISCREG_DC_IVAC_Xt
1065 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
1066 // MISCREG_DC_ISW_Xt
1067 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
1068 // MISCREG_AT_S1E1R_Xt
1069 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1070 // MISCREG_AT_S1E1W_Xt
1071 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1072 // MISCREG_AT_S1E0R_Xt
1073 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1074 // MISCREG_AT_S1E0W_Xt
1075 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1076 // MISCREG_DC_CSW_Xt
1077 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
1078 // MISCREG_DC_CISW_Xt
1079 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
1080 // MISCREG_DC_ZVA_Xt
1081 bitset<NUM_MISCREG_INFOS>(string("10101010100010000101")),
1082 // MISCREG_IC_IVAU_Xt
1083 bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")),
1084 // MISCREG_DC_CVAC_Xt
1085 bitset<NUM_MISCREG_INFOS>(string("10101010101010000101")),
1086 // MISCREG_DC_CVAU_Xt
1087 bitset<NUM_MISCREG_INFOS>(string("10101010101010000101")),
1088 // MISCREG_DC_CIVAC_Xt
1089 bitset<NUM_MISCREG_INFOS>(string("10101010101010000101")),
1090 // MISCREG_AT_S1E2R_Xt
1091 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
1092 // MISCREG_AT_S1E2W_Xt
1093 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
1094 // MISCREG_AT_S12E1R_Xt
1095 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1096 // MISCREG_AT_S12E1W_Xt
1097 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1098 // MISCREG_AT_S12E0R_Xt
1099 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1100 // MISCREG_AT_S12E0W_Xt
1101 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1102 // MISCREG_AT_S1E3R_Xt
1103 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
1104 // MISCREG_AT_S1E3W_Xt
1105 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
1106 // MISCREG_TLBI_VMALLE1IS
1107 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1108 // MISCREG_TLBI_VAE1IS_Xt
1109 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1110 // MISCREG_TLBI_ASIDE1IS_Xt
1111 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1112 // MISCREG_TLBI_VAAE1IS_Xt
1113 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1114 // MISCREG_TLBI_VALE1IS_Xt
1115 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1116 // MISCREG_TLBI_VAALE1IS_Xt
1117 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1118 // MISCREG_TLBI_VMALLE1
1119 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1120 // MISCREG_TLBI_VAE1_Xt
1121 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1122 // MISCREG_TLBI_ASIDE1_Xt
1123 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1124 // MISCREG_TLBI_VAAE1_Xt
1125 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1126 // MISCREG_TLBI_VALE1_Xt
1127 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1128 // MISCREG_TLBI_VAALE1_Xt
1129 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1130 // MISCREG_TLBI_IPAS2E1IS_Xt
1131 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1132 // MISCREG_TLBI_IPAS2LE1IS_Xt
1133 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1134 // MISCREG_TLBI_ALLE2IS
1135 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
1136 // MISCREG_TLBI_VAE2IS_Xt
1137 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
1138 // MISCREG_TLBI_ALLE1IS
1139 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1140 // MISCREG_TLBI_VALE2IS_Xt
1141 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
1142 // MISCREG_TLBI_VMALLS12E1IS
1143 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1144 // MISCREG_TLBI_IPAS2E1_Xt
1145 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1146 // MISCREG_TLBI_IPAS2LE1_Xt
1147 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1148 // MISCREG_TLBI_ALLE2
1149 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
1150 // MISCREG_TLBI_VAE2_Xt
1151 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
1152 // MISCREG_TLBI_ALLE1
1153 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1154 // MISCREG_TLBI_VALE2_Xt
1155 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")),
1156 // MISCREG_TLBI_VMALLS12E1
1157 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")),
1158 // MISCREG_TLBI_ALLE3IS
1159 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
1160 // MISCREG_TLBI_VAE3IS_Xt
1161 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
1162 // MISCREG_TLBI_VALE3IS_Xt
1163 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
1164 // MISCREG_TLBI_ALLE3
1165 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
1166 // MISCREG_TLBI_VAE3_Xt
1167 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
1168 // MISCREG_TLBI_VALE3_Xt
1169 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")),
1170 // MISCREG_PMINTENSET_EL1
1171 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1172 // MISCREG_PMINTENCLR_EL1
1173 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1174 // MISCREG_PMCR_EL0
1175 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1176 // MISCREG_PMCNTENSET_EL0
1177 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1178 // MISCREG_PMCNTENCLR_EL0
1179 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1180 // MISCREG_PMOVSCLR_EL0
1181 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1182 // MISCREG_PMSWINC_EL0
1183 bitset<NUM_MISCREG_INFOS>(string("10101010101111000001")),
1184 // MISCREG_PMSELR_EL0
1185 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1186 // MISCREG_PMCEID0_EL0
1187 bitset<NUM_MISCREG_INFOS>(string("01010101011111000001")),
1188 // MISCREG_PMCEID1_EL0
1189 bitset<NUM_MISCREG_INFOS>(string("01010101011111000001")),
1190 // MISCREG_PMCCNTR_EL0
1191 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1192 // MISCREG_PMXEVTYPER_EL0
1193 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1194 // MISCREG_PMCCFILTR_EL0
1195 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1196 // MISCREG_PMXEVCNTR_EL0
1197 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1198 // MISCREG_PMUSERENR_EL0
1199 bitset<NUM_MISCREG_INFOS>(string("11111111110101000001")),
1200 // MISCREG_PMOVSSET_EL0
1201 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1202 // MISCREG_MAIR_EL1
1203 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1204 // MISCREG_AMAIR_EL1
1205 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1206 // MISCREG_MAIR_EL2
1207 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1208 // MISCREG_AMAIR_EL2
1209 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1210 // MISCREG_MAIR_EL3
1211 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1212 // MISCREG_AMAIR_EL3
1213 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1214 // MISCREG_L2CTLR_EL1
1215 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1216 // MISCREG_L2ECTLR_EL1
1217 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1218 // MISCREG_VBAR_EL1
1219 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1220 // MISCREG_RVBAR_EL1
1221 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
1222 // MISCREG_ISR_EL1
1223 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
1224 // MISCREG_VBAR_EL2
1225 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1226 // MISCREG_RVBAR_EL2
1227 bitset<NUM_MISCREG_INFOS>(string("01010100000000000001")),
1228 // MISCREG_VBAR_EL3
1229 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1230 // MISCREG_RVBAR_EL3
1231 bitset<NUM_MISCREG_INFOS>(string("01010000000000000001")),
1232 // MISCREG_RMR_EL3
1233 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1234 // MISCREG_CONTEXTIDR_EL1
1235 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1236 // MISCREG_TPIDR_EL1
1237 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1238 // MISCREG_TPIDR_EL0
1239 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1240 // MISCREG_TPIDRRO_EL0
1241 bitset<NUM_MISCREG_INFOS>(string("11111111110101000001")),
1242 // MISCREG_TPIDR_EL2
1243 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1244 // MISCREG_TPIDR_EL3
1245 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1246 // MISCREG_CNTKCTL_EL1
1247 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1248 // MISCREG_CNTFRQ_EL0
1249 bitset<NUM_MISCREG_INFOS>(string("11110101010101000001")),
1250 // MISCREG_CNTPCT_EL0
1251 bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")),
1252 // MISCREG_CNTVCT_EL0
1253 bitset<NUM_MISCREG_INFOS>(string("01010101010101000011")),
1254 // MISCREG_CNTP_TVAL_EL0
1255 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1256 // MISCREG_CNTP_CTL_EL0
1257 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1258 // MISCREG_CNTP_CVAL_EL0
1259 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1260 // MISCREG_CNTV_TVAL_EL0
1261 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
1262 // MISCREG_CNTV_CTL_EL0
1263 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
1264 // MISCREG_CNTV_CVAL_EL0
1265 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
1266 // MISCREG_PMEVCNTR0_EL0
1267 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1268 // MISCREG_PMEVCNTR1_EL0
1269 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1270 // MISCREG_PMEVCNTR2_EL0
1271 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1272 // MISCREG_PMEVCNTR3_EL0
1273 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1274 // MISCREG_PMEVCNTR4_EL0
1275 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1276 // MISCREG_PMEVCNTR5_EL0
1277 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1278 // MISCREG_PMEVTYPER0_EL0
1279 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1280 // MISCREG_PMEVTYPER1_EL0
1281 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1282 // MISCREG_PMEVTYPER2_EL0
1283 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1284 // MISCREG_PMEVTYPER3_EL0
1285 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1286 // MISCREG_PMEVTYPER4_EL0
1287 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1288 // MISCREG_PMEVTYPER5_EL0
1289 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1290 // MISCREG_CNTVOFF_EL2
1291 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1292 // MISCREG_CNTHCTL_EL2
1293 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
1294 // MISCREG_CNTHP_TVAL_EL2
1295 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
1296 // MISCREG_CNTHP_CTL_EL2
1297 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
1298 // MISCREG_CNTHP_CVAL_EL2
1299 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
1300 // MISCREG_CNTPS_TVAL_EL1
1301 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
1302 // MISCREG_CNTPS_CTL_EL1
1303 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
1304 // MISCREG_CNTPS_CVAL_EL1
1305 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")),
1306 // MISCREG_IL1DATA0_EL1
1307 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1308 // MISCREG_IL1DATA1_EL1
1309 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1310 // MISCREG_IL1DATA2_EL1
1311 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1312 // MISCREG_IL1DATA3_EL1
1313 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1314 // MISCREG_DL1DATA0_EL1
1315 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1316 // MISCREG_DL1DATA1_EL1
1317 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1318 // MISCREG_DL1DATA2_EL1
1319 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1320 // MISCREG_DL1DATA3_EL1
1321 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1322 // MISCREG_DL1DATA4_EL1
1323 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1324 // MISCREG_L2ACTLR_EL1
1325 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1326 // MISCREG_CPUACTLR_EL1
1327 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1328 // MISCREG_CPUECTLR_EL1
1329 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1330 // MISCREG_CPUMERRSR_EL1
1331 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1332 // MISCREG_L2MERRSR_EL1
1333 bitset<NUM_MISCREG_INFOS>(string("11111111110000000100")),
1334 // MISCREG_CBAR_EL1
1335 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
1336
1337 // Dummy registers
1338 // MISCREG_NOP
1339 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1340 // MISCREG_RAZ
1341 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
1342 // MISCREG_CP14_UNIMPL
1343 bitset<NUM_MISCREG_INFOS>(string("00000000000000000100")),
1344 // MISCREG_CP15_UNIMPL
1345 bitset<NUM_MISCREG_INFOS>(string("00000000000000000100")),
1346 // MISCREG_A64_UNIMPL
1347 bitset<NUM_MISCREG_INFOS>(string("00000000000000000100")),
1348 // MISCREG_UNKNOWN
1349 bitset<NUM_MISCREG_INFOS>(string("00000000000000000001"))
1350 };
1351
1352 MiscRegIndex
1353 decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
1354 {
1355 switch (crn) {
1356 case 0:
1357 switch (opc1) {
1358 case 0:
1359 switch (crm) {
1360 case 0:
1361 switch (opc2) {
1362 case 1:
1363 return MISCREG_CTR;
1364 case 2:
1365 return MISCREG_TCMTR;
1366 case 3:
1367 return MISCREG_TLBTR;
1368 case 5:
1369 return MISCREG_MPIDR;
1370 case 6:
1371 return MISCREG_REVIDR;
1372 default:
1373 return MISCREG_MIDR;
1374 }
1375 break;
1376 case 1:
1377 switch (opc2) {
1378 case 0:
1379 return MISCREG_ID_PFR0;
1380 case 1:
1381 return MISCREG_ID_PFR1;
1382 case 2:
1383 return MISCREG_ID_DFR0;
1384 case 3:
1385 return MISCREG_ID_AFR0;
1386 case 4:
1387 return MISCREG_ID_MMFR0;
1388 case 5:
1389 return MISCREG_ID_MMFR1;
1390 case 6:
1391 return MISCREG_ID_MMFR2;
1392 case 7:
1393 return MISCREG_ID_MMFR3;
1394 }
1395 break;
1396 case 2:
1397 switch (opc2) {
1398 case 0:
1399 return MISCREG_ID_ISAR0;
1400 case 1:
1401 return MISCREG_ID_ISAR1;
1402 case 2:
1403 return MISCREG_ID_ISAR2;
1404 case 3:
1405 return MISCREG_ID_ISAR3;
1406 case 4:
1407 return MISCREG_ID_ISAR4;
1408 case 5:
1409 return MISCREG_ID_ISAR5;
1410 case 6:
1411 case 7:
1412 return MISCREG_RAZ; // read as zero
1413 }
1414 break;
1415 default:
1416 return MISCREG_RAZ; // read as zero
1417 }
1418 break;
1419 case 1:
1420 if (crm == 0) {
1421 switch (opc2) {
1422 case 0:
1423 return MISCREG_CCSIDR;
1424 case 1:
1425 return MISCREG_CLIDR;
1426 case 7:
1427 return MISCREG_AIDR;
1428 }
1429 }
1430 break;
1431 case 2:
1432 if (crm == 0 && opc2 == 0) {
1433 return MISCREG_CSSELR;
1434 }
1435 break;
1436 case 4:
1437 if (crm == 0) {
1438 if (opc2 == 0)
1439 return MISCREG_VPIDR;
1440 else if (opc2 == 5)
1441 return MISCREG_VMPIDR;
1442 }
1443 break;
1444 }
1445 break;
1446 case 1:
1447 if (opc1 == 0) {
1448 if (crm == 0) {
1449 switch (opc2) {
1450 case 0:
1451 return MISCREG_SCTLR;
1452 case 1:
1453 return MISCREG_ACTLR;
1454 case 0x2:
1455 return MISCREG_CPACR;
1456 }
1457 } else if (crm == 1) {
1458 switch (opc2) {
1459 case 0:
1460 return MISCREG_SCR;
1461 case 1:
1462 return MISCREG_SDER;
1463 case 2:
1464 return MISCREG_NSACR;
1465 }
1466 }
1467 } else if (opc1 == 4) {
1468 if (crm == 0) {
1469 if (opc2 == 0)
1470 return MISCREG_HSCTLR;
1471 else if (opc2 == 1)
1472 return MISCREG_HACTLR;
1473 } else if (crm == 1) {
1474 switch (opc2) {
1475 case 0:
1476 return MISCREG_HCR;
1477 case 1:
1478 return MISCREG_HDCR;
1479 case 2:
1480 return MISCREG_HCPTR;
1481 case 3:
1482 return MISCREG_HSTR;
1483 case 7:
1484 return MISCREG_HACR;
1485 }
1486 }
1487 }
1488 break;
1489 case 2:
1490 if (opc1 == 0 && crm == 0) {
1491 switch (opc2) {
1492 case 0:
1493 return MISCREG_TTBR0;
1494 case 1:
1495 return MISCREG_TTBR1;
1496 case 2:
1497 return MISCREG_TTBCR;
1498 }
1499 } else if (opc1 == 4) {
1500 if (crm == 0 && opc2 == 2)
1501 return MISCREG_HTCR;
1502 else if (crm == 1 && opc2 == 2)
1503 return MISCREG_VTCR;
1504 }
1505 break;
1506 case 3:
1507 if (opc1 == 0 && crm == 0 && opc2 == 0) {
1508 return MISCREG_DACR;
1509 }
1510 break;
1511 case 5:
1512 if (opc1 == 0) {
1513 if (crm == 0) {
1514 if (opc2 == 0) {
1515 return MISCREG_DFSR;
1516 } else if (opc2 == 1) {
1517 return MISCREG_IFSR;
1518 }
1519 } else if (crm == 1) {
1520 if (opc2 == 0) {
1521 return MISCREG_ADFSR;
1522 } else if (opc2 == 1) {
1523 return MISCREG_AIFSR;
1524 }
1525 }
1526 } else if (opc1 == 4) {
1527 if (crm == 1) {
1528 if (opc2 == 0)
1529 return MISCREG_HADFSR;
1530 else if (opc2 == 1)
1531 return MISCREG_HAIFSR;
1532 } else if (crm == 2 && opc2 == 0) {
1533 return MISCREG_HSR;
1534 }
1535 }
1536 break;
1537 case 6:
1538 if (opc1 == 0 && crm == 0) {
1539 switch (opc2) {
1540 case 0:
1541 return MISCREG_DFAR;
1542 case 2:
1543 return MISCREG_IFAR;
1544 }
1545 } else if (opc1 == 4 && crm == 0) {
1546 switch (opc2) {
1547 case 0:
1548 return MISCREG_HDFAR;
1549 case 2:
1550 return MISCREG_HIFAR;
1551 case 4:
1552 return MISCREG_HPFAR;
1553 }
1554 }
1555 break;
1556 case 7:
1557 if (opc1 == 0) {
1558 switch (crm) {
1559 case 0:
1560 if (opc2 == 4) {
1561 return MISCREG_NOP;
1562 }
1563 break;
1564 case 1:
1565 switch (opc2) {
1566 case 0:
1567 return MISCREG_ICIALLUIS;
1568 case 6:
1569 return MISCREG_BPIALLIS;
1570 }
1571 break;
1572 case 4:
1573 if (opc2 == 0) {
1574 return MISCREG_PAR;
1575 }
1576 break;
1577 case 5:
1578 switch (opc2) {
1579 case 0:
1580 return MISCREG_ICIALLU;
1581 case 1:
1582 return MISCREG_ICIMVAU;
1583 case 4:
1584 return MISCREG_CP15ISB;
1585 case 6:
1586 return MISCREG_BPIALL;
1587 case 7:
1588 return MISCREG_BPIMVA;
1589 }
1590 break;
1591 case 6:
1592 if (opc2 == 1) {
1593 return MISCREG_DCIMVAC;
1594 } else if (opc2 == 2) {
1595 return MISCREG_DCISW;
1596 }
1597 break;
1598 case 8:
1599 switch (opc2) {
1600 case 0:
1601 return MISCREG_ATS1CPR;
1602 case 1:
1603 return MISCREG_ATS1CPW;
1604 case 2:
1605 return MISCREG_ATS1CUR;
1606 case 3:
1607 return MISCREG_ATS1CUW;
1608 case 4:
1609 return MISCREG_ATS12NSOPR;
1610 case 5:
1611 return MISCREG_ATS12NSOPW;
1612 case 6:
1613 return MISCREG_ATS12NSOUR;
1614 case 7:
1615 return MISCREG_ATS12NSOUW;
1616 }
1617 break;
1618 case 10:
1619 switch (opc2) {
1620 case 1:
1621 return MISCREG_DCCMVAC;
1622 case 2:
1623 return MISCREG_DCCSW;
1624 case 4:
1625 return MISCREG_CP15DSB;
1626 case 5:
1627 return MISCREG_CP15DMB;
1628 }
1629 break;
1630 case 11:
1631 if (opc2 == 1) {
1632 return MISCREG_DCCMVAU;
1633 }
1634 break;
1635 case 13:
1636 if (opc2 == 1) {
1637 return MISCREG_NOP;
1638 }
1639 break;
1640 case 14:
1641 if (opc2 == 1) {
1642 return MISCREG_DCCIMVAC;
1643 } else if (opc2 == 2) {
1644 return MISCREG_DCCISW;
1645 }
1646 break;
1647 }
1648 } else if (opc1 == 4 && crm == 8) {
1649 if (opc2 == 0)
1650 return MISCREG_ATS1HR;
1651 else if (opc2 == 1)
1652 return MISCREG_ATS1HW;
1653 }
1654 break;
1655 case 8:
1656 if (opc1 == 0) {
1657 switch (crm) {
1658 case 3:
1659 switch (opc2) {
1660 case 0:
1661 return MISCREG_TLBIALLIS;
1662 case 1:
1663 return MISCREG_TLBIMVAIS;
1664 case 2:
1665 return MISCREG_TLBIASIDIS;
1666 case 3:
1667 return MISCREG_TLBIMVAAIS;
1668 }
1669 break;
1670 case 5:
1671 switch (opc2) {
1672 case 0:
1673 return MISCREG_ITLBIALL;
1674 case 1:
1675 return MISCREG_ITLBIMVA;
1676 case 2:
1677 return MISCREG_ITLBIASID;
1678 }
1679 break;
1680 case 6:
1681 switch (opc2) {
1682 case 0:
1683 return MISCREG_DTLBIALL;
1684 case 1:
1685 return MISCREG_DTLBIMVA;
1686 case 2:
1687 return MISCREG_DTLBIASID;
1688 }
1689 break;
1690 case 7:
1691 switch (opc2) {
1692 case 0:
1693 return MISCREG_TLBIALL;
1694 case 1:
1695 return MISCREG_TLBIMVA;
1696 case 2:
1697 return MISCREG_TLBIASID;
1698 case 3:
1699 return MISCREG_TLBIMVAA;
1700 }
1701 break;
1702 }
1703 } else if (opc1 == 4) {
1704 if (crm == 3) {
1705 switch (opc2) {
1706 case 0:
1707 return MISCREG_TLBIALLHIS;
1708 case 1:
1709 return MISCREG_TLBIMVAHIS;
1710 case 4:
1711 return MISCREG_TLBIALLNSNHIS;
1712 }
1713 } else if (crm == 7) {
1714 switch (opc2) {
1715 case 0:
1716 return MISCREG_TLBIALLH;
1717 case 1:
1718 return MISCREG_TLBIMVAH;
1719 case 4:
1720 return MISCREG_TLBIALLNSNH;
1721 }
1722 }
1723 }
1724 break;
1725 case 9:
1726 if (opc1 == 0) {
1727 switch (crm) {
1728 case 12:
1729 switch (opc2) {
1730 case 0:
1731 return MISCREG_PMCR;
1732 case 1:
1733 return MISCREG_PMCNTENSET;
1734 case 2:
1735 return MISCREG_PMCNTENCLR;
1736 case 3:
1737 return MISCREG_PMOVSR;
1738 case 4:
1739 return MISCREG_PMSWINC;
1740 case 5:
1741 return MISCREG_PMSELR;
1742 case 6:
1743 return MISCREG_PMCEID0;
1744 case 7:
1745 return MISCREG_PMCEID1;
1746 }
1747 break;
1748 case 13:
1749 switch (opc2) {
1750 case 0:
1751 return MISCREG_PMCCNTR;
1752 case 1:
1753 // Selector is PMSELR.SEL
1754 return MISCREG_PMXEVTYPER_PMCCFILTR;
1755 case 2:
1756 return MISCREG_PMXEVCNTR;
1757 }
1758 break;
1759 case 14:
1760 switch (opc2) {
1761 case 0:
1762 return MISCREG_PMUSERENR;
1763 case 1:
1764 return MISCREG_PMINTENSET;
1765 case 2:
1766 return MISCREG_PMINTENCLR;
1767 case 3:
1768 return MISCREG_PMOVSSET;
1769 }
1770 break;
1771 }
1772 } else if (opc1 == 1) {
1773 switch (crm) {
1774 case 0:
1775 switch (opc2) {
1776 case 2: // L2CTLR, L2 Control Register
1777 return MISCREG_L2CTLR;
1778 case 3:
1779 return MISCREG_L2ECTLR;
1780 }
1781 break;
1782 break;
1783 }
1784 }
1785 break;
1786 case 10:
1787 if (opc1 == 0) {
1788 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
1789 if (crm == 2) { // TEX Remap Registers
1790 if (opc2 == 0) {
1791 // Selector is TTBCR.EAE
1792 return MISCREG_PRRR_MAIR0;
1793 } else if (opc2 == 1) {
1794 // Selector is TTBCR.EAE
1795 return MISCREG_NMRR_MAIR1;
1796 }
1797 } else if (crm == 3) {
1798 if (opc2 == 0) {
1799 return MISCREG_AMAIR0;
1800 } else if (opc2 == 1) {
1801 return MISCREG_AMAIR1;
1802 }
1803 }
1804 } else if (opc1 == 4) {
1805 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
1806 if (crm == 2) {
1807 if (opc2 == 0)
1808 return MISCREG_HMAIR0;
1809 else if (opc2 == 1)
1810 return MISCREG_HMAIR1;
1811 } else if (crm == 3) {
1812 if (opc2 == 0)
1813 return MISCREG_HAMAIR0;
1814 else if (opc2 == 1)
1815 return MISCREG_HAMAIR1;
1816 }
1817 }
1818 break;
1819 case 11:
1820 if (opc1 <=7) {
1821 switch (crm) {
1822 case 0:
1823 case 1:
1824 case 2:
1825 case 3:
1826 case 4:
1827 case 5:
1828 case 6:
1829 case 7:
1830 case 8:
1831 case 15:
1832 // Reserved for DMA operations for TCM access
1833 break;
1834 }
1835 }
1836 break;
1837 case 12:
1838 if (opc1 == 0) {
1839 if (crm == 0) {
1840 if (opc2 == 0) {
1841 return MISCREG_VBAR;
1842 } else if (opc2 == 1) {
1843 return MISCREG_MVBAR;
1844 }
1845 } else if (crm == 1) {
1846 if (opc2 == 0) {
1847 return MISCREG_ISR;
1848 }
1849 }
1850 } else if (opc1 == 4) {
1851 if (crm == 0 && opc2 == 0)
1852 return MISCREG_HVBAR;
1853 }
1854 break;
1855 case 13:
1856 if (opc1 == 0) {
1857 if (crm == 0) {
1858 switch (opc2) {
1859 case 0:
1860 return MISCREG_FCSEIDR;
1861 case 1:
1862 return MISCREG_CONTEXTIDR;
1863 case 2:
1864 return MISCREG_TPIDRURW;
1865 case 3:
1866 return MISCREG_TPIDRURO;
1867 case 4:
1868 return MISCREG_TPIDRPRW;
1869 }
1870 }
1871 } else if (opc1 == 4) {
1872 if (crm == 0 && opc2 == 2)
1873 return MISCREG_HTPIDR;
1874 }
1875 break;
1876 case 14:
1877 if (opc1 == 0) {
1878 switch (crm) {
1879 case 0:
1880 if (opc2 == 0)
1881 return MISCREG_CNTFRQ;
1882 break;
1883 case 1:
1884 if (opc2 == 0)
1885 return MISCREG_CNTKCTL;
1886 break;
1887 case 2:
1888 if (opc2 == 0)
1889 return MISCREG_CNTP_TVAL;
1890 else if (opc2 == 1)
1891 return MISCREG_CNTP_CTL;
1892 break;
1893 case 3:
1894 if (opc2 == 0)
1895 return MISCREG_CNTV_TVAL;
1896 else if (opc2 == 1)
1897 return MISCREG_CNTV_CTL;
1898 break;
1899 }
1900 } else if (opc1 == 4) {
1901 if (crm == 1 && opc2 == 0) {
1902 return MISCREG_CNTHCTL;
1903 } else if (crm == 2) {
1904 if (opc2 == 0)
1905 return MISCREG_CNTHP_TVAL;
1906 else if (opc2 == 1)
1907 return MISCREG_CNTHP_CTL;
1908 }
1909 }
1910 break;
1911 case 15:
1912 // Implementation defined
1913 return MISCREG_CP15_UNIMPL;
1914 }
1915 // Unrecognized register
1916 return MISCREG_CP15_UNIMPL;
1917 }
1918
1919 MiscRegIndex
1920 decodeCP15Reg64(unsigned crm, unsigned opc1)
1921 {
1922 switch (crm) {
1923 case 2:
1924 switch (opc1) {
1925 case 0:
1926 return MISCREG_TTBR0;
1927 case 1:
1928 return MISCREG_TTBR1;
1929 case 4:
1930 return MISCREG_HTTBR;
1931 case 6:
1932 return MISCREG_VTTBR;
1933 }
1934 break;
1935 case 7:
1936 if (opc1 == 0)
1937 return MISCREG_PAR;
1938 break;
1939 case 14:
1940 switch (opc1) {
1941 case 0:
1942 return MISCREG_CNTPCT;
1943 case 1:
1944 return MISCREG_CNTVCT;
1945 case 2:
1946 return MISCREG_CNTP_CVAL;
1947 case 3:
1948 return MISCREG_CNTV_CVAL;
1949 case 4:
1950 return MISCREG_CNTVOFF;
1951 case 6:
1952 return MISCREG_CNTHP_CVAL;
1953 }
1954 break;
1955 case 15:
1956 if (opc1 == 0)
1957 return MISCREG_CPUMERRSR;
1958 else if (opc1 == 1)
1959 return MISCREG_L2MERRSR;
1960 break;
1961 }
1962 // Unrecognized register
1963 return MISCREG_CP15_UNIMPL;
1964 }
1965
1966 bool
1967 canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1968 {
1969 bool secure = !scr.ns;
1970 bool canRead;
1971
1972 switch (cpsr.mode) {
1973 case MODE_USER:
1974 canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
1975 miscRegInfo[reg][MISCREG_USR_NS_RD];
1976 break;
1977 case MODE_FIQ:
1978 case MODE_IRQ:
1979 case MODE_SVC:
1980 case MODE_ABORT:
1981 case MODE_UNDEFINED:
1982 case MODE_SYSTEM:
1983 canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1984 miscRegInfo[reg][MISCREG_PRI_NS_RD];
1985 break;
1986 case MODE_MON:
1987 canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1988 miscRegInfo[reg][MISCREG_MON_NS1_RD];
1989 break;
1990 case MODE_HYP:
1991 canRead = miscRegInfo[reg][MISCREG_HYP_RD];
1992 break;
1993 default:
1994 panic("Unrecognized mode setting in CPSR.\n");
1995 }
1996 // can't do permissions checkes on the root of a banked pair of regs
1997 assert(!miscRegInfo[reg][MISCREG_BANKED]);
1998 return canRead;
1999 }
2000
2001 bool
2002 canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
2003 {
2004 bool secure = !scr.ns;
2005 bool canWrite;
2006
2007 switch (cpsr.mode) {
2008 case MODE_USER:
2009 canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
2010 miscRegInfo[reg][MISCREG_USR_NS_WR];
2011 break;
2012 case MODE_FIQ:
2013 case MODE_IRQ:
2014 case MODE_SVC:
2015 case MODE_ABORT:
2016 case MODE_UNDEFINED:
2017 case MODE_SYSTEM:
2018 canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
2019 miscRegInfo[reg][MISCREG_PRI_NS_WR];
2020 break;
2021 case MODE_MON:
2022 canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
2023 miscRegInfo[reg][MISCREG_MON_NS1_WR];
2024 break;
2025 case MODE_HYP:
2026 canWrite = miscRegInfo[reg][MISCREG_HYP_WR];
2027 break;
2028 default:
2029 panic("Unrecognized mode setting in CPSR.\n");
2030 }
2031 // can't do permissions checkes on the root of a banked pair of regs
2032 assert(!miscRegInfo[reg][MISCREG_BANKED]);
2033 return canWrite;
2034 }
2035
2036 int
2037 flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc)
2038 {
2039 int reg_as_int = static_cast<int>(reg);
2040 if (miscRegInfo[reg][MISCREG_BANKED]) {
2041 SCR scr = tc->readMiscReg(MISCREG_SCR);
2042 reg_as_int += (ArmSystem::haveSecurity(tc) && !scr.ns) ? 2 : 1;
2043 }
2044 return reg_as_int;
2045 }
2046
2047 int
2048 flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns)
2049 {
2050 int reg_as_int = static_cast<int>(reg);
2051 if (miscRegInfo[reg][MISCREG_BANKED]) {
2052 reg_as_int += (ArmSystem::haveSecurity(tc) && !ns) ? 2 : 1;
2053 }
2054 return reg_as_int;
2055 }
2056
2057
2058 /**
2059 * If the reg is a child reg of a banked set, then the parent is the last
2060 * banked one in the list. This is messy, and the wish is to eventually have
2061 * the bitmap replaced with a better data structure. the preUnflatten function
2062 * initializes a lookup table to speed up the search for these banked
2063 * registers.
2064 */
2065
2066 int unflattenResultMiscReg[NUM_MISCREGS];
2067
2068 void
2069 preUnflattenMiscReg()
2070 {
2071 int reg = -1;
2072 for (int i = 0 ; i < NUM_MISCREGS; i++){
2073 if (miscRegInfo[i][MISCREG_BANKED])
2074 reg = i;
2075 if (miscRegInfo[i][MISCREG_BANKED_CHILD])
2076 unflattenResultMiscReg[i] = reg;
2077 else
2078 unflattenResultMiscReg[i] = i;
2079 // if this assert fails, no parent was found, and something is broken
2080 assert(unflattenResultMiscReg[i] > -1);
2081 }
2082 }
2083
2084 int
2085 unflattenMiscReg(int reg)
2086 {
2087 return unflattenResultMiscReg[reg];
2088 }
2089
2090 bool
2091 canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
2092 {
2093 // Check for SP_EL0 access while SPSEL == 0
2094 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
2095 return false;
2096
2097 // Check for RVBAR access
2098 if (reg == MISCREG_RVBAR_EL1) {
2099 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
2100 if (highest_el == EL2 || highest_el == EL3)
2101 return false;
2102 }
2103 if (reg == MISCREG_RVBAR_EL2) {
2104 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
2105 if (highest_el == EL3)
2106 return false;
2107 }
2108
2109 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
2110
2111 switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) {
2112 case EL0:
2113 return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
2114 miscRegInfo[reg][MISCREG_USR_NS_RD];
2115 case EL1:
2116 return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
2117 miscRegInfo[reg][MISCREG_PRI_NS_RD];
2118 // @todo: uncomment this to enable Virtualization
2119 // case EL2:
2120 // return miscRegInfo[reg][MISCREG_HYP_RD];
2121 case EL3:
2122 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
2123 miscRegInfo[reg][MISCREG_MON_NS1_RD];
2124 default:
2125 panic("Invalid exception level");
2126 }
2127 }
2128
2129 bool
2130 canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
2131 {
2132 // Check for SP_EL0 access while SPSEL == 0
2133 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
2134 return false;
2135 ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
2136 if (reg == MISCREG_DAIF) {
2137 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
2138 if (el == EL0 && !sctlr.uma)
2139 return false;
2140 }
2141 if (reg == MISCREG_DC_ZVA_Xt) {
2142 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
2143 if (el == EL0 && !sctlr.dze)
2144 return false;
2145 }
2146 if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
2147 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
2148 if (el == EL0 && !sctlr.uci)
2149 return false;
2150 }
2151
2152 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
2153
2154 switch (el) {
2155 case EL0:
2156 return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
2157 miscRegInfo[reg][MISCREG_USR_NS_WR];
2158 case EL1:
2159 return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
2160 miscRegInfo[reg][MISCREG_PRI_NS_WR];
2161 // @todo: uncomment this to enable Virtualization
2162 // case EL2:
2163 // return miscRegInfo[reg][MISCREG_HYP_WR];
2164 case EL3:
2165 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
2166 miscRegInfo[reg][MISCREG_MON_NS1_WR];
2167 default:
2168 panic("Invalid exception level");
2169 }
2170 }
2171
2172 MiscRegIndex
2173 decodeAArch64SysReg(unsigned op0, unsigned op1,
2174 unsigned crn, unsigned crm,
2175 unsigned op2)
2176 {
2177 switch (op0) {
2178 case 1:
2179 switch (crn) {
2180 case 7:
2181 switch (op1) {
2182 case 0:
2183 switch (crm) {
2184 case 1:
2185 switch (op2) {
2186 case 0:
2187 return MISCREG_IC_IALLUIS;
2188 }
2189 break;
2190 case 5:
2191 switch (op2) {
2192 case 0:
2193 return MISCREG_IC_IALLU;
2194 }
2195 break;
2196 case 6:
2197 switch (op2) {
2198 case 1:
2199 return MISCREG_DC_IVAC_Xt;
2200 case 2:
2201 return MISCREG_DC_ISW_Xt;
2202 }
2203 break;
2204 case 8:
2205 switch (op2) {
2206 case 0:
2207 return MISCREG_AT_S1E1R_Xt;
2208 case 1:
2209 return MISCREG_AT_S1E1W_Xt;
2210 case 2:
2211 return MISCREG_AT_S1E0R_Xt;
2212 case 3:
2213 return MISCREG_AT_S1E0W_Xt;
2214 }
2215 break;
2216 case 10:
2217 switch (op2) {
2218 case 2:
2219 return MISCREG_DC_CSW_Xt;
2220 }
2221 break;
2222 case 14:
2223 switch (op2) {
2224 case 2:
2225 return MISCREG_DC_CISW_Xt;
2226 }
2227 break;
2228 }
2229 break;
2230 case 3:
2231 switch (crm) {
2232 case 4:
2233 switch (op2) {
2234 case 1:
2235 return MISCREG_DC_ZVA_Xt;
2236 }
2237 break;
2238 case 5:
2239 switch (op2) {
2240 case 1:
2241 return MISCREG_IC_IVAU_Xt;
2242 }
2243 break;
2244 case 10:
2245 switch (op2) {
2246 case 1:
2247 return MISCREG_DC_CVAC_Xt;
2248 }
2249 break;
2250 case 11:
2251 switch (op2) {
2252 case 1:
2253 return MISCREG_DC_CVAU_Xt;
2254 }
2255 break;
2256 case 14:
2257 switch (op2) {
2258 case 1:
2259 return MISCREG_DC_CIVAC_Xt;
2260 }
2261 break;
2262 }
2263 break;
2264 case 4:
2265 switch (crm) {
2266 case 8:
2267 switch (op2) {
2268 case 0:
2269 return MISCREG_AT_S1E2R_Xt;
2270 case 1:
2271 return MISCREG_AT_S1E2W_Xt;
2272 case 4:
2273 return MISCREG_AT_S12E1R_Xt;
2274 case 5:
2275 return MISCREG_AT_S12E1W_Xt;
2276 case 6:
2277 return MISCREG_AT_S12E0R_Xt;
2278 case 7:
2279 return MISCREG_AT_S12E0W_Xt;
2280 }
2281 break;
2282 }
2283 break;
2284 case 6:
2285 switch (crm) {
2286 case 8:
2287 switch (op2) {
2288 case 0:
2289 return MISCREG_AT_S1E3R_Xt;
2290 case 1:
2291 return MISCREG_AT_S1E3W_Xt;
2292 }
2293 break;
2294 }
2295 break;
2296 }
2297 break;
2298 case 8:
2299 switch (op1) {
2300 case 0:
2301 switch (crm) {
2302 case 3:
2303 switch (op2) {
2304 case 0:
2305 return MISCREG_TLBI_VMALLE1IS;
2306 case 1:
2307 return MISCREG_TLBI_VAE1IS_Xt;
2308 case 2:
2309 return MISCREG_TLBI_ASIDE1IS_Xt;
2310 case 3:
2311 return MISCREG_TLBI_VAAE1IS_Xt;
2312 case 5:
2313 return MISCREG_TLBI_VALE1IS_Xt;
2314 case 7:
2315 return MISCREG_TLBI_VAALE1IS_Xt;
2316 }
2317 break;
2318 case 7:
2319 switch (op2) {
2320 case 0:
2321 return MISCREG_TLBI_VMALLE1;
2322 case 1:
2323 return MISCREG_TLBI_VAE1_Xt;
2324 case 2:
2325 return MISCREG_TLBI_ASIDE1_Xt;
2326 case 3:
2327 return MISCREG_TLBI_VAAE1_Xt;
2328 case 5:
2329 return MISCREG_TLBI_VALE1_Xt;
2330 case 7:
2331 return MISCREG_TLBI_VAALE1_Xt;
2332 }
2333 break;
2334 }
2335 break;
2336 case 4:
2337 switch (crm) {
2338 case 0:
2339 switch (op2) {
2340 case 1:
2341 return MISCREG_TLBI_IPAS2E1IS_Xt;
2342 case 5:
2343 return MISCREG_TLBI_IPAS2LE1IS_Xt;
2344 }
2345 break;
2346 case 3:
2347 switch (op2) {
2348 case 0:
2349 return MISCREG_TLBI_ALLE2IS;
2350 case 1:
2351 return MISCREG_TLBI_VAE2IS_Xt;
2352 case 4:
2353 return MISCREG_TLBI_ALLE1IS;
2354 case 5:
2355 return MISCREG_TLBI_VALE2IS_Xt;
2356 case 6:
2357 return MISCREG_TLBI_VMALLS12E1IS;
2358 }
2359 break;
2360 case 4:
2361 switch (op2) {
2362 case 1:
2363 return MISCREG_TLBI_IPAS2E1_Xt;
2364 case 5:
2365 return MISCREG_TLBI_IPAS2LE1_Xt;
2366 }
2367 break;
2368 case 7:
2369 switch (op2) {
2370 case 0:
2371 return MISCREG_TLBI_ALLE2;
2372 case 1:
2373 return MISCREG_TLBI_VAE2_Xt;
2374 case 4:
2375 return MISCREG_TLBI_ALLE1;
2376 case 5:
2377 return MISCREG_TLBI_VALE2_Xt;
2378 case 6:
2379 return MISCREG_TLBI_VMALLS12E1;
2380 }
2381 break;
2382 }
2383 break;
2384 case 6:
2385 switch (crm) {
2386 case 3:
2387 switch (op2) {
2388 case 0:
2389 return MISCREG_TLBI_ALLE3IS;
2390 case 1:
2391 return MISCREG_TLBI_VAE3IS_Xt;
2392 case 5:
2393 return MISCREG_TLBI_VALE3IS_Xt;
2394 }
2395 break;
2396 case 7:
2397 switch (op2) {
2398 case 0:
2399 return MISCREG_TLBI_ALLE3;
2400 case 1:
2401 return MISCREG_TLBI_VAE3_Xt;
2402 case 5:
2403 return MISCREG_TLBI_VALE3_Xt;
2404 }
2405 break;
2406 }
2407 break;
2408 }
2409 break;
2410 }
2411 break;
2412 case 2:
2413 switch (crn) {
2414 case 0:
2415 switch (op1) {
2416 case 0:
2417 switch (crm) {
2418 case 0:
2419 switch (op2) {
2420 case 2:
2421 return MISCREG_OSDTRRX_EL1;
2422 case 4:
2423 return MISCREG_DBGBVR0_EL1;
2424 case 5:
2425 return MISCREG_DBGBCR0_EL1;
2426 case 6:
2427 return MISCREG_DBGWVR0_EL1;
2428 case 7:
2429 return MISCREG_DBGWCR0_EL1;
2430 }
2431 break;
2432 case 1:
2433 switch (op2) {
2434 case 4:
2435 return MISCREG_DBGBVR1_EL1;
2436 case 5:
2437 return MISCREG_DBGBCR1_EL1;
2438 case 6:
2439 return MISCREG_DBGWVR1_EL1;
2440 case 7:
2441 return MISCREG_DBGWCR1_EL1;
2442 }
2443 break;
2444 case 2:
2445 switch (op2) {
2446 case 0:
2447 return MISCREG_MDCCINT_EL1;
2448 case 2:
2449 return MISCREG_MDSCR_EL1;
2450 case 4:
2451 return MISCREG_DBGBVR2_EL1;
2452 case 5:
2453 return MISCREG_DBGBCR2_EL1;
2454 case 6:
2455 return MISCREG_DBGWVR2_EL1;
2456 case 7:
2457 return MISCREG_DBGWCR2_EL1;
2458 }
2459 break;
2460 case 3:
2461 switch (op2) {
2462 case 2:
2463 return MISCREG_OSDTRTX_EL1;
2464 case 4:
2465 return MISCREG_DBGBVR3_EL1;
2466 case 5:
2467 return MISCREG_DBGBCR3_EL1;
2468 case 6:
2469 return MISCREG_DBGWVR3_EL1;
2470 case 7:
2471 return MISCREG_DBGWCR3_EL1;
2472 }
2473 break;
2474 case 4:
2475 switch (op2) {
2476 case 4:
2477 return MISCREG_DBGBVR4_EL1;
2478 case 5:
2479 return MISCREG_DBGBCR4_EL1;
2480 }
2481 break;
2482 case 5:
2483 switch (op2) {
2484 case 4:
2485 return MISCREG_DBGBVR5_EL1;
2486 case 5:
2487 return MISCREG_DBGBCR5_EL1;
2488 }
2489 break;
2490 case 6:
2491 switch (op2) {
2492 case 2:
2493 return MISCREG_OSECCR_EL1;
2494 }
2495 break;
2496 }
2497 break;
2498 case 2:
2499 switch (crm) {
2500 case 0:
2501 switch (op2) {
2502 case 0:
2503 return MISCREG_TEECR32_EL1;
2504 }
2505 break;
2506 }
2507 break;
2508 case 3:
2509 switch (crm) {
2510 case 1:
2511 switch (op2) {
2512 case 0:
2513 return MISCREG_MDCCSR_EL0;
2514 }
2515 break;
2516 case 4:
2517 switch (op2) {
2518 case 0:
2519 return MISCREG_MDDTR_EL0;
2520 }
2521 break;
2522 case 5:
2523 switch (op2) {
2524 case 0:
2525 return MISCREG_MDDTRRX_EL0;
2526 }
2527 break;
2528 }
2529 break;
2530 case 4:
2531 switch (crm) {
2532 case 7:
2533 switch (op2) {
2534 case 0:
2535 return MISCREG_DBGVCR32_EL2;
2536 }
2537 break;
2538 }
2539 break;
2540 }
2541 break;
2542 case 1:
2543 switch (op1) {
2544 case 0:
2545 switch (crm) {
2546 case 0:
2547 switch (op2) {
2548 case 0:
2549 return MISCREG_MDRAR_EL1;
2550 case 4:
2551 return MISCREG_OSLAR_EL1;
2552 }
2553 break;
2554 case 1:
2555 switch (op2) {
2556 case 4:
2557 return MISCREG_OSLSR_EL1;
2558 }
2559 break;
2560 case 3:
2561 switch (op2) {
2562 case 4:
2563 return MISCREG_OSDLR_EL1;
2564 }
2565 break;
2566 case 4:
2567 switch (op2) {
2568 case 4:
2569 return MISCREG_DBGPRCR_EL1;
2570 }
2571 break;
2572 }
2573 break;
2574 case 2:
2575 switch (crm) {
2576 case 0:
2577 switch (op2) {
2578 case 0:
2579 return MISCREG_TEEHBR32_EL1;
2580 }
2581 break;
2582 }
2583 break;
2584 }
2585 break;
2586 case 7:
2587 switch (op1) {
2588 case 0:
2589 switch (crm) {
2590 case 8:
2591 switch (op2) {
2592 case 6:
2593 return MISCREG_DBGCLAIMSET_EL1;
2594 }
2595 break;
2596 case 9:
2597 switch (op2) {
2598 case 6:
2599 return MISCREG_DBGCLAIMCLR_EL1;
2600 }
2601 break;
2602 case 14:
2603 switch (op2) {
2604 case 6:
2605 return MISCREG_DBGAUTHSTATUS_EL1;
2606 }
2607 break;
2608 }
2609 break;
2610 }
2611 break;
2612 }
2613 break;
2614 case 3:
2615 switch (crn) {
2616 case 0:
2617 switch (op1) {
2618 case 0:
2619 switch (crm) {
2620 case 0:
2621 switch (op2) {
2622 case 0:
2623 return MISCREG_MIDR_EL1;
2624 case 5:
2625 return MISCREG_MPIDR_EL1;
2626 case 6:
2627 return MISCREG_REVIDR_EL1;
2628 }
2629 break;
2630 case 1:
2631 switch (op2) {
2632 case 0:
2633 return MISCREG_ID_PFR0_EL1;
2634 case 1:
2635 return MISCREG_ID_PFR1_EL1;
2636 case 2:
2637 return MISCREG_ID_DFR0_EL1;
2638 case 3:
2639 return MISCREG_ID_AFR0_EL1;
2640 case 4:
2641 return MISCREG_ID_MMFR0_EL1;
2642 case 5:
2643 return MISCREG_ID_MMFR1_EL1;
2644 case 6:
2645 return MISCREG_ID_MMFR2_EL1;
2646 case 7:
2647 return MISCREG_ID_MMFR3_EL1;
2648 }
2649 break;
2650 case 2:
2651 switch (op2) {
2652 case 0:
2653 return MISCREG_ID_ISAR0_EL1;
2654 case 1:
2655 return MISCREG_ID_ISAR1_EL1;
2656 case 2:
2657 return MISCREG_ID_ISAR2_EL1;
2658 case 3:
2659 return MISCREG_ID_ISAR3_EL1;
2660 case 4:
2661 return MISCREG_ID_ISAR4_EL1;
2662 case 5:
2663 return MISCREG_ID_ISAR5_EL1;
2664 }
2665 break;
2666 case 3:
2667 switch (op2) {
2668 case 0:
2669 return MISCREG_MVFR0_EL1;
2670 case 1:
2671 return MISCREG_MVFR1_EL1;
2672 case 2:
2673 return MISCREG_MVFR2_EL1;
2674 case 3 ... 7:
2675 return MISCREG_RAZ;
2676 }
2677 break;
2678 case 4:
2679 switch (op2) {
2680 case 0:
2681 return MISCREG_ID_AA64PFR0_EL1;
2682 case 1:
2683 return MISCREG_ID_AA64PFR1_EL1;
2684 case 2 ... 7:
2685 return MISCREG_RAZ;
2686 }
2687 break;
2688 case 5:
2689 switch (op2) {
2690 case 0:
2691 return MISCREG_ID_AA64DFR0_EL1;
2692 case 1:
2693 return MISCREG_ID_AA64DFR1_EL1;
2694 case 4:
2695 return MISCREG_ID_AA64AFR0_EL1;
2696 case 5:
2697 return MISCREG_ID_AA64AFR1_EL1;
2698 case 2:
2699 case 3:
2700 case 6:
2701 case 7:
2702 return MISCREG_RAZ;
2703 }
2704 break;
2705 case 6:
2706 switch (op2) {
2707 case 0:
2708 return MISCREG_ID_AA64ISAR0_EL1;
2709 case 1:
2710 return MISCREG_ID_AA64ISAR1_EL1;
2711 case 2 ... 7:
2712 return MISCREG_RAZ;
2713 }
2714 break;
2715 case 7:
2716 switch (op2) {
2717 case 0:
2718 return MISCREG_ID_AA64MMFR0_EL1;
2719 case 1:
2720 return MISCREG_ID_AA64MMFR1_EL1;
2721 case 2 ... 7:
2722 return MISCREG_RAZ;
2723 }
2724 break;
2725 }
2726 break;
2727 case 1:
2728 switch (crm) {
2729 case 0:
2730 switch (op2) {
2731 case 0:
2732 return MISCREG_CCSIDR_EL1;
2733 case 1:
2734 return MISCREG_CLIDR_EL1;
2735 case 7:
2736 return MISCREG_AIDR_EL1;
2737 }
2738 break;
2739 }
2740 break;
2741 case 2:
2742 switch (crm) {
2743 case 0:
2744 switch (op2) {
2745 case 0:
2746 return MISCREG_CSSELR_EL1;
2747 }
2748 break;
2749 }
2750 break;
2751 case 3:
2752 switch (crm) {
2753 case 0:
2754 switch (op2) {
2755 case 1:
2756 return MISCREG_CTR_EL0;
2757 case 7:
2758 return MISCREG_DCZID_EL0;
2759 }
2760 break;
2761 }
2762 break;
2763 case 4:
2764 switch (crm) {
2765 case 0:
2766 switch (op2) {
2767 case 0:
2768 return MISCREG_VPIDR_EL2;
2769 case 5:
2770 return MISCREG_VMPIDR_EL2;
2771 }
2772 break;
2773 }
2774 break;
2775 }
2776 break;
2777 case 1:
2778 switch (op1) {
2779 case 0:
2780 switch (crm) {
2781 case 0:
2782 switch (op2) {
2783 case 0:
2784 return MISCREG_SCTLR_EL1;
2785 case 1:
2786 return MISCREG_ACTLR_EL1;
2787 case 2:
2788 return MISCREG_CPACR_EL1;
2789 }
2790 break;
2791 }
2792 break;
2793 case 4:
2794 switch (crm) {
2795 case 0:
2796 switch (op2) {
2797 case 0:
2798 return MISCREG_SCTLR_EL2;
2799 case 1:
2800 return MISCREG_ACTLR_EL2;
2801 }
2802 break;
2803 case 1:
2804 switch (op2) {
2805 case 0:
2806 return MISCREG_HCR_EL2;
2807 case 1:
2808 return MISCREG_MDCR_EL2;
2809 case 2:
2810 return MISCREG_CPTR_EL2;
2811 case 3:
2812 return MISCREG_HSTR_EL2;
2813 case 7:
2814 return MISCREG_HACR_EL2;
2815 }
2816 break;
2817 }
2818 break;
2819 case 6:
2820 switch (crm) {
2821 case 0:
2822 switch (op2) {
2823 case 0:
2824 return MISCREG_SCTLR_EL3;
2825 case 1:
2826 return MISCREG_ACTLR_EL3;
2827 }
2828 break;
2829 case 1:
2830 switch (op2) {
2831 case 0:
2832 return MISCREG_SCR_EL3;
2833 case 1:
2834 return MISCREG_SDER32_EL3;
2835 case 2:
2836 return MISCREG_CPTR_EL3;
2837 }
2838 break;
2839 case 3:
2840 switch (op2) {
2841 case 1:
2842 return MISCREG_MDCR_EL3;
2843 }
2844 break;
2845 }
2846 break;
2847 }
2848 break;
2849 case 2:
2850 switch (op1) {
2851 case 0:
2852 switch (crm) {
2853 case 0:
2854 switch (op2) {
2855 case 0:
2856 return MISCREG_TTBR0_EL1;
2857 case 1:
2858 return MISCREG_TTBR1_EL1;
2859 case 2:
2860 return MISCREG_TCR_EL1;
2861 }
2862 break;
2863 }
2864 break;
2865 case 4:
2866 switch (crm) {
2867 case 0:
2868 switch (op2) {
2869 case 0:
2870 return MISCREG_TTBR0_EL2;
2871 case 2:
2872 return MISCREG_TCR_EL2;
2873 }
2874 break;
2875 case 1:
2876 switch (op2) {
2877 case 0:
2878 return MISCREG_VTTBR_EL2;
2879 case 2:
2880 return MISCREG_VTCR_EL2;
2881 }
2882 break;
2883 }
2884 break;
2885 case 6:
2886 switch (crm) {
2887 case 0:
2888 switch (op2) {
2889 case 0:
2890 return MISCREG_TTBR0_EL3;
2891 case 2:
2892 return MISCREG_TCR_EL3;
2893 }
2894 break;
2895 }
2896 break;
2897 }
2898 break;
2899 case 3:
2900 switch (op1) {
2901 case 4:
2902 switch (crm) {
2903 case 0:
2904 switch (op2) {
2905 case 0:
2906 return MISCREG_DACR32_EL2;
2907 }
2908 break;
2909 }
2910 break;
2911 }
2912 break;
2913 case 4:
2914 switch (op1) {
2915 case 0:
2916 switch (crm) {
2917 case 0:
2918 switch (op2) {
2919 case 0:
2920 return MISCREG_SPSR_EL1;
2921 case 1:
2922 return MISCREG_ELR_EL1;
2923 }
2924 break;
2925 case 1:
2926 switch (op2) {
2927 case 0:
2928 return MISCREG_SP_EL0;
2929 }
2930 break;
2931 case 2:
2932 switch (op2) {
2933 case 0:
2934 return MISCREG_SPSEL;
2935 case 2:
2936 return MISCREG_CURRENTEL;
2937 }
2938 break;
2939 }
2940 break;
2941 case 3:
2942 switch (crm) {
2943 case 2:
2944 switch (op2) {
2945 case 0:
2946 return MISCREG_NZCV;
2947 case 1:
2948 return MISCREG_DAIF;
2949 }
2950 break;
2951 case 4:
2952 switch (op2) {
2953 case 0:
2954 return MISCREG_FPCR;
2955 case 1:
2956 return MISCREG_FPSR;
2957 }
2958 break;
2959 case 5:
2960 switch (op2) {
2961 case 0:
2962 return MISCREG_DSPSR_EL0;
2963 case 1:
2964 return MISCREG_DLR_EL0;
2965 }
2966 break;
2967 }
2968 break;
2969 case 4:
2970 switch (crm) {
2971 case 0:
2972 switch (op2) {
2973 case 0:
2974 return MISCREG_SPSR_EL2;
2975 case 1:
2976 return MISCREG_ELR_EL2;
2977 }
2978 break;
2979 case 1:
2980 switch (op2) {
2981 case 0:
2982 return MISCREG_SP_EL1;
2983 }
2984 break;
2985 case 3:
2986 switch (op2) {
2987 case 0:
2988 return MISCREG_SPSR_IRQ_AA64;
2989 case 1:
2990 return MISCREG_SPSR_ABT_AA64;
2991 case 2:
2992 return MISCREG_SPSR_UND_AA64;
2993 case 3:
2994 return MISCREG_SPSR_FIQ_AA64;
2995 }
2996 break;
2997 }
2998 break;
2999 case 6:
3000 switch (crm) {
3001 case 0:
3002 switch (op2) {
3003 case 0:
3004 return MISCREG_SPSR_EL3;
3005 case 1:
3006 return MISCREG_ELR_EL3;
3007 }
3008 break;
3009 case 1:
3010 switch (op2) {
3011 case 0:
3012 return MISCREG_SP_EL2;
3013 }
3014 break;
3015 }
3016 break;
3017 }
3018 break;
3019 case 5:
3020 switch (op1) {
3021 case 0:
3022 switch (crm) {
3023 case 1:
3024 switch (op2) {
3025 case 0:
3026 return MISCREG_AFSR0_EL1;
3027 case 1:
3028 return MISCREG_AFSR1_EL1;
3029 }
3030 break;
3031 case 2:
3032 switch (op2) {
3033 case 0:
3034 return MISCREG_ESR_EL1;
3035 }
3036 break;
3037 }
3038 break;
3039 case 4:
3040 switch (crm) {
3041 case 0:
3042 switch (op2) {
3043 case 1:
3044 return MISCREG_IFSR32_EL2;
3045 }
3046 break;
3047 case 1:
3048 switch (op2) {
3049 case 0:
3050 return MISCREG_AFSR0_EL2;
3051 case 1:
3052 return MISCREG_AFSR1_EL2;
3053 }
3054 break;
3055 case 2:
3056 switch (op2) {
3057 case 0:
3058 return MISCREG_ESR_EL2;
3059 }
3060 break;
3061 case 3:
3062 switch (op2) {
3063 case 0:
3064 return MISCREG_FPEXC32_EL2;
3065 }
3066 break;
3067 }
3068 break;
3069 case 6:
3070 switch (crm) {
3071 case 1:
3072 switch (op2) {
3073 case 0:
3074 return MISCREG_AFSR0_EL3;
3075 case 1:
3076 return MISCREG_AFSR1_EL3;
3077 }
3078 break;
3079 case 2:
3080 switch (op2) {
3081 case 0:
3082 return MISCREG_ESR_EL3;
3083 }
3084 break;
3085 }
3086 break;
3087 }
3088 break;
3089 case 6:
3090 switch (op1) {
3091 case 0:
3092 switch (crm) {
3093 case 0:
3094 switch (op2) {
3095 case 0:
3096 return MISCREG_FAR_EL1;
3097 }
3098 break;
3099 }
3100 break;
3101 case 4:
3102 switch (crm) {
3103 case 0:
3104 switch (op2) {
3105 case 0:
3106 return MISCREG_FAR_EL2;
3107 case 4:
3108 return MISCREG_HPFAR_EL2;
3109 }
3110 break;
3111 }
3112 break;
3113 case 6:
3114 switch (crm) {
3115 case 0:
3116 switch (op2) {
3117 case 0:
3118 return MISCREG_FAR_EL3;
3119 }
3120 break;
3121 }
3122 break;
3123 }
3124 break;
3125 case 7:
3126 switch (op1) {
3127 case 0:
3128 switch (crm) {
3129 case 4:
3130 switch (op2) {
3131 case 0:
3132 return MISCREG_PAR_EL1;
3133 }
3134 break;
3135 }
3136 break;
3137 }
3138 break;
3139 case 9:
3140 switch (op1) {
3141 case 0:
3142 switch (crm) {
3143 case 14:
3144 switch (op2) {
3145 case 1:
3146 return MISCREG_PMINTENSET_EL1;
3147 case 2:
3148 return MISCREG_PMINTENCLR_EL1;
3149 }
3150 break;
3151 }
3152 break;
3153 case 3:
3154 switch (crm) {
3155 case 12:
3156 switch (op2) {
3157 case 0:
3158 return MISCREG_PMCR_EL0;
3159 case 1:
3160 return MISCREG_PMCNTENSET_EL0;
3161 case 2:
3162 return MISCREG_PMCNTENCLR_EL0;
3163 case 3:
3164 return MISCREG_PMOVSCLR_EL0;
3165 case 4:
3166 return MISCREG_PMSWINC_EL0;
3167 case 5:
3168 return MISCREG_PMSELR_EL0;
3169 case 6:
3170 return MISCREG_PMCEID0_EL0;
3171 case 7:
3172 return MISCREG_PMCEID1_EL0;
3173 }
3174 break;
3175 case 13:
3176 switch (op2) {
3177 case 0:
3178 return MISCREG_PMCCNTR_EL0;
3179 case 1:
3180 return MISCREG_PMXEVTYPER_EL0;
3181 case 2:
3182 return MISCREG_PMXEVCNTR_EL0;
3183 }
3184 break;
3185 case 14:
3186 switch (op2) {
3187 case 0:
3188 return MISCREG_PMUSERENR_EL0;
3189 case 3:
3190 return MISCREG_PMOVSSET_EL0;
3191 }
3192 break;
3193 }
3194 break;
3195 }
3196 break;
3197 case 10:
3198 switch (op1) {
3199 case 0:
3200 switch (crm) {
3201 case 2:
3202 switch (op2) {
3203 case 0:
3204 return MISCREG_MAIR_EL1;
3205 }
3206 break;
3207 case 3:
3208 switch (op2) {
3209 case 0:
3210 return MISCREG_AMAIR_EL1;
3211 }
3212 break;
3213 }
3214 break;
3215 case 4:
3216 switch (crm) {
3217 case 2:
3218 switch (op2) {
3219 case 0:
3220 return MISCREG_MAIR_EL2;
3221 }
3222 break;
3223 case 3:
3224 switch (op2) {
3225 case 0:
3226 return MISCREG_AMAIR_EL2;
3227 }
3228 break;
3229 }
3230 break;
3231 case 6:
3232 switch (crm) {
3233 case 2:
3234 switch (op2) {
3235 case 0:
3236 return MISCREG_MAIR_EL3;
3237 }
3238 break;
3239 case 3:
3240 switch (op2) {
3241 case 0:
3242 return MISCREG_AMAIR_EL3;
3243 }
3244 break;
3245 }
3246 break;
3247 }
3248 break;
3249 case 11:
3250 switch (op1) {
3251 case 1:
3252 switch (crm) {
3253 case 0:
3254 switch (op2) {
3255 case 2:
3256 return MISCREG_L2CTLR_EL1;
3257 case 3:
3258 return MISCREG_L2ECTLR_EL1;
3259 }
3260 break;
3261 }
3262 break;
3263 }
3264 break;
3265 case 12:
3266 switch (op1) {
3267 case 0:
3268 switch (crm) {
3269 case 0:
3270 switch (op2) {
3271 case 0:
3272 return MISCREG_VBAR_EL1;
3273 case 1:
3274 return MISCREG_RVBAR_EL1;
3275 }
3276 break;
3277 case 1:
3278 switch (op2) {
3279 case 0:
3280 return MISCREG_ISR_EL1;
3281 }
3282 break;
3283 }
3284 break;
3285 case 4:
3286 switch (crm) {
3287 case 0:
3288 switch (op2) {
3289 case 0:
3290 return MISCREG_VBAR_EL2;
3291 case 1:
3292 return MISCREG_RVBAR_EL2;
3293 }
3294 break;
3295 }
3296 break;
3297 case 6:
3298 switch (crm) {
3299 case 0:
3300 switch (op2) {
3301 case 0:
3302 return MISCREG_VBAR_EL3;
3303 case 1:
3304 return MISCREG_RVBAR_EL3;
3305 case 2:
3306 return MISCREG_RMR_EL3;
3307 }
3308 break;
3309 }
3310 break;
3311 }
3312 break;
3313 case 13:
3314 switch (op1) {
3315 case 0:
3316 switch (crm) {
3317 case 0:
3318 switch (op2) {
3319 case 1:
3320 return MISCREG_CONTEXTIDR_EL1;
3321 case 4:
3322 return MISCREG_TPIDR_EL1;
3323 }
3324 break;
3325 }
3326 break;
3327 case 3:
3328 switch (crm) {
3329 case 0:
3330 switch (op2) {
3331 case 2:
3332 return MISCREG_TPIDR_EL0;
3333 case 3:
3334 return MISCREG_TPIDRRO_EL0;
3335 }
3336 break;
3337 }
3338 break;
3339 case 4:
3340 switch (crm) {
3341 case 0:
3342 switch (op2) {
3343 case 2:
3344 return MISCREG_TPIDR_EL2;
3345 }
3346 break;
3347 }
3348 break;
3349 case 6:
3350 switch (crm) {
3351 case 0:
3352 switch (op2) {
3353 case 2:
3354 return MISCREG_TPIDR_EL3;
3355 }
3356 break;
3357 }
3358 break;
3359 }
3360 break;
3361 case 14:
3362 switch (op1) {
3363 case 0:
3364 switch (crm) {
3365 case 1:
3366 switch (op2) {
3367 case 0:
3368 return MISCREG_CNTKCTL_EL1;
3369 }
3370 break;
3371 }
3372 break;
3373 case 3:
3374 switch (crm) {
3375 case 0:
3376 switch (op2) {
3377 case 0:
3378 return MISCREG_CNTFRQ_EL0;
3379 case 1:
3380 return MISCREG_CNTPCT_EL0;
3381 case 2:
3382 return MISCREG_CNTVCT_EL0;
3383 }
3384 break;
3385 case 2:
3386 switch (op2) {
3387 case 0:
3388 return MISCREG_CNTP_TVAL_EL0;
3389 case 1:
3390 return MISCREG_CNTP_CTL_EL0;
3391 case 2:
3392 return MISCREG_CNTP_CVAL_EL0;
3393 }
3394 break;
3395 case 3:
3396 switch (op2) {
3397 case 0:
3398 return MISCREG_CNTV_TVAL_EL0;
3399 case 1:
3400 return MISCREG_CNTV_CTL_EL0;
3401 case 2:
3402 return MISCREG_CNTV_CVAL_EL0;
3403 }
3404 break;
3405 case 8:
3406 switch (op2) {
3407 case 0:
3408 return MISCREG_PMEVCNTR0_EL0;
3409 case 1:
3410 return MISCREG_PMEVCNTR1_EL0;
3411 case 2:
3412 return MISCREG_PMEVCNTR2_EL0;
3413 case 3:
3414 return MISCREG_PMEVCNTR3_EL0;
3415 case 4:
3416 return MISCREG_PMEVCNTR4_EL0;
3417 case 5:
3418 return MISCREG_PMEVCNTR5_EL0;
3419 }
3420 break;
3421 case 12:
3422 switch (op2) {
3423 case 0:
3424 return MISCREG_PMEVTYPER0_EL0;
3425 case 1:
3426 return MISCREG_PMEVTYPER1_EL0;
3427 case 2:
3428 return MISCREG_PMEVTYPER2_EL0;
3429 case 3:
3430 return MISCREG_PMEVTYPER3_EL0;
3431 case 4:
3432 return MISCREG_PMEVTYPER4_EL0;
3433 case 5:
3434 return MISCREG_PMEVTYPER5_EL0;
3435 }
3436 break;
3437 case 15:
3438 switch (op2) {
3439 case 7:
3440 return MISCREG_PMCCFILTR_EL0;
3441 }
3442 }
3443 break;
3444 case 4:
3445 switch (crm) {
3446 case 0:
3447 switch (op2) {
3448 case 3:
3449 return MISCREG_CNTVOFF_EL2;
3450 }
3451 break;
3452 case 1:
3453 switch (op2) {
3454 case 0:
3455 return MISCREG_CNTHCTL_EL2;
3456 }
3457 break;
3458 case 2:
3459 switch (op2) {
3460 case 0:
3461 return MISCREG_CNTHP_TVAL_EL2;
3462 case 1:
3463 return MISCREG_CNTHP_CTL_EL2;
3464 case 2:
3465 return MISCREG_CNTHP_CVAL_EL2;
3466 }
3467 break;
3468 }
3469 break;
3470 case 7:
3471 switch (crm) {
3472 case 2:
3473 switch (op2) {
3474 case 0:
3475 return MISCREG_CNTPS_TVAL_EL1;
3476 case 1:
3477 return MISCREG_CNTPS_CTL_EL1;
3478 case 2:
3479 return MISCREG_CNTPS_CVAL_EL1;
3480 }
3481 break;
3482 }
3483 break;
3484 }
3485 break;
3486 case 15:
3487 switch (op1) {
3488 case 0:
3489 switch (crm) {
3490 case 0:
3491 switch (op2) {
3492 case 0:
3493 return MISCREG_IL1DATA0_EL1;
3494 case 1:
3495 return MISCREG_IL1DATA1_EL1;
3496 case 2:
3497 return MISCREG_IL1DATA2_EL1;
3498 case 3:
3499 return MISCREG_IL1DATA3_EL1;
3500 }
3501 break;
3502 case 1:
3503 switch (op2) {
3504 case 0:
3505 return MISCREG_DL1DATA0_EL1;
3506 case 1:
3507 return MISCREG_DL1DATA1_EL1;
3508 case 2:
3509 return MISCREG_DL1DATA2_EL1;
3510 case 3:
3511 return MISCREG_DL1DATA3_EL1;
3512 case 4:
3513 return MISCREG_DL1DATA4_EL1;
3514 }
3515 break;
3516 }
3517 break;
3518 case 1:
3519 switch (crm) {
3520 case 0:
3521 switch (op2) {
3522 case 0:
3523 return MISCREG_L2ACTLR_EL1;
3524 }
3525 break;
3526 case 2:
3527 switch (op2) {
3528 case 0:
3529 return MISCREG_CPUACTLR_EL1;
3530 case 1:
3531 return MISCREG_CPUECTLR_EL1;
3532 case 2:
3533 return MISCREG_CPUMERRSR_EL1;
3534 case 3:
3535 return MISCREG_L2MERRSR_EL1;
3536 }
3537 break;
3538 case 3:
3539 switch (op2) {
3540 case 0:
3541 return MISCREG_CBAR_EL1;
3542
3543 }
3544 break;
3545 }
3546 break;
3547 }
3548 break;
3549 }
3550 break;
3551 }
3552
3553 return MISCREG_UNKNOWN;
3554 }
3555
3556 } // namespace ArmISA