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arch-power: Add doubleword modulo instructions
[gem5.git] / src / arch / arm / miscregs.cc
1 /*
2 * Copyright (c) 2010-2013, 2015-2020 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 #include "arch/arm/miscregs.hh"
39
40 #include <tuple>
41
42 #include "arch/arm/isa.hh"
43 #include "base/logging.hh"
44 #include "cpu/thread_context.hh"
45 #include "sim/full_system.hh"
46
47 namespace ArmISA
48 {
49
50 MiscRegIndex
51 decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
52 {
53 switch(crn) {
54 case 0:
55 switch (opc1) {
56 case 0:
57 switch (opc2) {
58 case 0:
59 switch (crm) {
60 case 0:
61 return MISCREG_DBGDIDR;
62 case 1:
63 return MISCREG_DBGDSCRint;
64 case 7:
65 return MISCREG_DBGVCR;
66 }
67 break;
68 case 2:
69 switch (crm) {
70 case 0:
71 return MISCREG_DBGDTRRXext;
72 case 2:
73 return MISCREG_DBGDSCRext;
74 case 3:
75 return MISCREG_DBGDTRTXext;
76 case 6:
77 return MISCREG_DBGOSECCR;
78 }
79 break;
80 case 4:
81 switch (crm) {
82 case 0:
83 return MISCREG_DBGBVR0;
84 case 1:
85 return MISCREG_DBGBVR1;
86 case 2:
87 return MISCREG_DBGBVR2;
88 case 3:
89 return MISCREG_DBGBVR3;
90 case 4:
91 return MISCREG_DBGBVR4;
92 case 5:
93 return MISCREG_DBGBVR5;
94 case 6:
95 return MISCREG_DBGBVR6;
96 case 7:
97 return MISCREG_DBGBVR7;
98 case 8:
99 return MISCREG_DBGBVR8;
100 case 9:
101 return MISCREG_DBGBVR9;
102 case 10:
103 return MISCREG_DBGBVR10;
104 case 11:
105 return MISCREG_DBGBVR11;
106 case 12:
107 return MISCREG_DBGBVR12;
108 case 13:
109 return MISCREG_DBGBVR13;
110 case 14:
111 return MISCREG_DBGBVR14;
112 case 15:
113 return MISCREG_DBGBVR15;
114 }
115 break;
116 case 5:
117 switch (crm) {
118 case 0:
119 return MISCREG_DBGBCR0;
120 case 1:
121 return MISCREG_DBGBCR1;
122 case 2:
123 return MISCREG_DBGBCR2;
124 case 3:
125 return MISCREG_DBGBCR3;
126 case 4:
127 return MISCREG_DBGBCR4;
128 case 5:
129 return MISCREG_DBGBCR5;
130 case 6:
131 return MISCREG_DBGBCR6;
132 case 7:
133 return MISCREG_DBGBCR7;
134 case 8:
135 return MISCREG_DBGBCR8;
136 case 9:
137 return MISCREG_DBGBCR9;
138 case 10:
139 return MISCREG_DBGBCR10;
140 case 11:
141 return MISCREG_DBGBCR11;
142 case 12:
143 return MISCREG_DBGBCR12;
144 case 13:
145 return MISCREG_DBGBCR13;
146 case 14:
147 return MISCREG_DBGBCR14;
148 case 15:
149 return MISCREG_DBGBCR15;
150 }
151 break;
152 case 6:
153 switch (crm) {
154 case 0:
155 return MISCREG_DBGWVR0;
156 case 1:
157 return MISCREG_DBGWVR1;
158 case 2:
159 return MISCREG_DBGWVR2;
160 case 3:
161 return MISCREG_DBGWVR3;
162 case 4:
163 return MISCREG_DBGWVR4;
164 case 5:
165 return MISCREG_DBGWVR5;
166 case 6:
167 return MISCREG_DBGWVR6;
168 case 7:
169 return MISCREG_DBGWVR7;
170 case 8:
171 return MISCREG_DBGWVR8;
172 case 9:
173 return MISCREG_DBGWVR9;
174 case 10:
175 return MISCREG_DBGWVR10;
176 case 11:
177 return MISCREG_DBGWVR11;
178 case 12:
179 return MISCREG_DBGWVR12;
180 case 13:
181 return MISCREG_DBGWVR13;
182 case 14:
183 return MISCREG_DBGWVR14;
184 case 15:
185 return MISCREG_DBGWVR15;
186 break;
187 }
188 break;
189 case 7:
190 switch (crm) {
191 case 0:
192 return MISCREG_DBGWCR0;
193 case 1:
194 return MISCREG_DBGWCR1;
195 case 2:
196 return MISCREG_DBGWCR2;
197 case 3:
198 return MISCREG_DBGWCR3;
199 case 4:
200 return MISCREG_DBGWCR4;
201 case 5:
202 return MISCREG_DBGWCR5;
203 case 6:
204 return MISCREG_DBGWCR6;
205 case 7:
206 return MISCREG_DBGWCR7;
207 case 8:
208 return MISCREG_DBGWCR8;
209 case 9:
210 return MISCREG_DBGWCR9;
211 case 10:
212 return MISCREG_DBGWCR10;
213 case 11:
214 return MISCREG_DBGWCR11;
215 case 12:
216 return MISCREG_DBGWCR12;
217 case 13:
218 return MISCREG_DBGWCR13;
219 case 14:
220 return MISCREG_DBGWCR14;
221 case 15:
222 return MISCREG_DBGWCR15;
223 }
224 break;
225 }
226 break;
227 case 7:
228 switch (opc2) {
229 case 0:
230 switch (crm) {
231 case 0:
232 return MISCREG_JIDR;
233 }
234 break;
235 }
236 break;
237 }
238 break;
239 case 1:
240 switch (opc1) {
241 case 0:
242 switch(opc2) {
243 case 1:
244 switch(crm) {
245 case 0:
246 return MISCREG_DBGBXVR0;
247 case 1:
248 return MISCREG_DBGBXVR1;
249 case 2:
250 return MISCREG_DBGBXVR2;
251 case 3:
252 return MISCREG_DBGBXVR3;
253 case 4:
254 return MISCREG_DBGBXVR4;
255 case 5:
256 return MISCREG_DBGBXVR5;
257 case 6:
258 return MISCREG_DBGBXVR6;
259 case 7:
260 return MISCREG_DBGBXVR7;
261 case 8:
262 return MISCREG_DBGBXVR8;
263 case 9:
264 return MISCREG_DBGBXVR9;
265 case 10:
266 return MISCREG_DBGBXVR10;
267 case 11:
268 return MISCREG_DBGBXVR11;
269 case 12:
270 return MISCREG_DBGBXVR12;
271 case 13:
272 return MISCREG_DBGBXVR13;
273 case 14:
274 return MISCREG_DBGBXVR14;
275 case 15:
276 return MISCREG_DBGBXVR15;
277 }
278 break;
279 case 4:
280 switch (crm) {
281 case 0:
282 return MISCREG_DBGOSLAR;
283 case 1:
284 return MISCREG_DBGOSLSR;
285 case 3:
286 return MISCREG_DBGOSDLR;
287 case 4:
288 return MISCREG_DBGPRCR;
289 }
290 break;
291 }
292 break;
293 case 6:
294 switch (crm) {
295 case 0:
296 switch (opc2) {
297 case 0:
298 return MISCREG_TEEHBR;
299 }
300 break;
301 }
302 break;
303 case 7:
304 switch (crm) {
305 case 0:
306 switch (opc2) {
307 case 0:
308 return MISCREG_JOSCR;
309 }
310 break;
311 }
312 break;
313 }
314 break;
315 case 2:
316 switch (opc1) {
317 case 7:
318 switch (crm) {
319 case 0:
320 switch (opc2) {
321 case 0:
322 return MISCREG_JMCR;
323 }
324 break;
325 }
326 break;
327 }
328 break;
329 }
330 // If we get here then it must be a register that we haven't implemented
331 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
332 crn, opc1, crm, opc2);
333 return MISCREG_CP14_UNIMPL;
334 }
335
336 MiscRegIndex
337 decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
338 {
339 switch (crn) {
340 case 0:
341 switch (opc1) {
342 case 0:
343 switch (crm) {
344 case 0:
345 switch (opc2) {
346 case 1:
347 return MISCREG_CTR;
348 case 2:
349 return MISCREG_TCMTR;
350 case 3:
351 return MISCREG_TLBTR;
352 case 5:
353 return MISCREG_MPIDR;
354 case 6:
355 return MISCREG_REVIDR;
356 default:
357 return MISCREG_MIDR;
358 }
359 break;
360 case 1:
361 switch (opc2) {
362 case 0:
363 return MISCREG_ID_PFR0;
364 case 1:
365 return MISCREG_ID_PFR1;
366 case 2:
367 return MISCREG_ID_DFR0;
368 case 3:
369 return MISCREG_ID_AFR0;
370 case 4:
371 return MISCREG_ID_MMFR0;
372 case 5:
373 return MISCREG_ID_MMFR1;
374 case 6:
375 return MISCREG_ID_MMFR2;
376 case 7:
377 return MISCREG_ID_MMFR3;
378 }
379 break;
380 case 2:
381 switch (opc2) {
382 case 0:
383 return MISCREG_ID_ISAR0;
384 case 1:
385 return MISCREG_ID_ISAR1;
386 case 2:
387 return MISCREG_ID_ISAR2;
388 case 3:
389 return MISCREG_ID_ISAR3;
390 case 4:
391 return MISCREG_ID_ISAR4;
392 case 5:
393 return MISCREG_ID_ISAR5;
394 case 6:
395 return MISCREG_ID_MMFR4;
396 case 7:
397 return MISCREG_ID_ISAR6;
398 }
399 break;
400 default:
401 return MISCREG_RAZ; // read as zero
402 }
403 break;
404 case 1:
405 if (crm == 0) {
406 switch (opc2) {
407 case 0:
408 return MISCREG_CCSIDR;
409 case 1:
410 return MISCREG_CLIDR;
411 case 7:
412 return MISCREG_AIDR;
413 }
414 }
415 break;
416 case 2:
417 if (crm == 0 && opc2 == 0) {
418 return MISCREG_CSSELR;
419 }
420 break;
421 case 4:
422 if (crm == 0) {
423 if (opc2 == 0)
424 return MISCREG_VPIDR;
425 else if (opc2 == 5)
426 return MISCREG_VMPIDR;
427 }
428 break;
429 }
430 break;
431 case 1:
432 if (opc1 == 0) {
433 if (crm == 0) {
434 switch (opc2) {
435 case 0:
436 return MISCREG_SCTLR;
437 case 1:
438 return MISCREG_ACTLR;
439 case 0x2:
440 return MISCREG_CPACR;
441 }
442 } else if (crm == 1) {
443 switch (opc2) {
444 case 0:
445 return MISCREG_SCR;
446 case 1:
447 return MISCREG_SDER;
448 case 2:
449 return MISCREG_NSACR;
450 }
451 } else if (crm == 3) {
452 if ( opc2 == 1)
453 return MISCREG_SDCR;
454 }
455 } else if (opc1 == 4) {
456 if (crm == 0) {
457 if (opc2 == 0)
458 return MISCREG_HSCTLR;
459 else if (opc2 == 1)
460 return MISCREG_HACTLR;
461 } else if (crm == 1) {
462 switch (opc2) {
463 case 0:
464 return MISCREG_HCR;
465 case 1:
466 return MISCREG_HDCR;
467 case 2:
468 return MISCREG_HCPTR;
469 case 4:
470 return MISCREG_HCR2;
471 case 3:
472 return MISCREG_HSTR;
473 case 7:
474 return MISCREG_HACR;
475 }
476 }
477 }
478 break;
479 case 2:
480 if (opc1 == 0 && crm == 0) {
481 switch (opc2) {
482 case 0:
483 return MISCREG_TTBR0;
484 case 1:
485 return MISCREG_TTBR1;
486 case 2:
487 return MISCREG_TTBCR;
488 }
489 } else if (opc1 == 4) {
490 if (crm == 0 && opc2 == 2)
491 return MISCREG_HTCR;
492 else if (crm == 1 && opc2 == 2)
493 return MISCREG_VTCR;
494 }
495 break;
496 case 3:
497 if (opc1 == 0 && crm == 0 && opc2 == 0) {
498 return MISCREG_DACR;
499 }
500 break;
501 case 4:
502 if (opc1 == 0 && crm == 6 && opc2 == 0) {
503 return MISCREG_ICC_PMR;
504 }
505 break;
506 case 5:
507 if (opc1 == 0) {
508 if (crm == 0) {
509 if (opc2 == 0) {
510 return MISCREG_DFSR;
511 } else if (opc2 == 1) {
512 return MISCREG_IFSR;
513 }
514 } else if (crm == 1) {
515 if (opc2 == 0) {
516 return MISCREG_ADFSR;
517 } else if (opc2 == 1) {
518 return MISCREG_AIFSR;
519 }
520 }
521 } else if (opc1 == 4) {
522 if (crm == 1) {
523 if (opc2 == 0)
524 return MISCREG_HADFSR;
525 else if (opc2 == 1)
526 return MISCREG_HAIFSR;
527 } else if (crm == 2 && opc2 == 0) {
528 return MISCREG_HSR;
529 }
530 }
531 break;
532 case 6:
533 if (opc1 == 0 && crm == 0) {
534 switch (opc2) {
535 case 0:
536 return MISCREG_DFAR;
537 case 2:
538 return MISCREG_IFAR;
539 }
540 } else if (opc1 == 4 && crm == 0) {
541 switch (opc2) {
542 case 0:
543 return MISCREG_HDFAR;
544 case 2:
545 return MISCREG_HIFAR;
546 case 4:
547 return MISCREG_HPFAR;
548 }
549 }
550 break;
551 case 7:
552 if (opc1 == 0) {
553 switch (crm) {
554 case 0:
555 if (opc2 == 4) {
556 return MISCREG_NOP;
557 }
558 break;
559 case 1:
560 switch (opc2) {
561 case 0:
562 return MISCREG_ICIALLUIS;
563 case 6:
564 return MISCREG_BPIALLIS;
565 }
566 break;
567 case 2:
568 switch (opc2) {
569 case 7:
570 return MISCREG_DBGDEVID0;
571 }
572 break;
573 case 4:
574 if (opc2 == 0) {
575 return MISCREG_PAR;
576 }
577 break;
578 case 5:
579 switch (opc2) {
580 case 0:
581 return MISCREG_ICIALLU;
582 case 1:
583 return MISCREG_ICIMVAU;
584 case 4:
585 return MISCREG_CP15ISB;
586 case 6:
587 return MISCREG_BPIALL;
588 case 7:
589 return MISCREG_BPIMVA;
590 }
591 break;
592 case 6:
593 if (opc2 == 1) {
594 return MISCREG_DCIMVAC;
595 } else if (opc2 == 2) {
596 return MISCREG_DCISW;
597 }
598 break;
599 case 8:
600 switch (opc2) {
601 case 0:
602 return MISCREG_ATS1CPR;
603 case 1:
604 return MISCREG_ATS1CPW;
605 case 2:
606 return MISCREG_ATS1CUR;
607 case 3:
608 return MISCREG_ATS1CUW;
609 case 4:
610 return MISCREG_ATS12NSOPR;
611 case 5:
612 return MISCREG_ATS12NSOPW;
613 case 6:
614 return MISCREG_ATS12NSOUR;
615 case 7:
616 return MISCREG_ATS12NSOUW;
617 }
618 break;
619 case 10:
620 switch (opc2) {
621 case 1:
622 return MISCREG_DCCMVAC;
623 case 2:
624 return MISCREG_DCCSW;
625 case 4:
626 return MISCREG_CP15DSB;
627 case 5:
628 return MISCREG_CP15DMB;
629 }
630 break;
631 case 11:
632 if (opc2 == 1) {
633 return MISCREG_DCCMVAU;
634 }
635 break;
636 case 13:
637 if (opc2 == 1) {
638 return MISCREG_NOP;
639 }
640 break;
641 case 14:
642 if (opc2 == 1) {
643 return MISCREG_DCCIMVAC;
644 } else if (opc2 == 2) {
645 return MISCREG_DCCISW;
646 }
647 break;
648 }
649 } else if (opc1 == 4 && crm == 8) {
650 if (opc2 == 0)
651 return MISCREG_ATS1HR;
652 else if (opc2 == 1)
653 return MISCREG_ATS1HW;
654 }
655 break;
656 case 8:
657 if (opc1 == 0) {
658 switch (crm) {
659 case 3:
660 switch (opc2) {
661 case 0:
662 return MISCREG_TLBIALLIS;
663 case 1:
664 return MISCREG_TLBIMVAIS;
665 case 2:
666 return MISCREG_TLBIASIDIS;
667 case 3:
668 return MISCREG_TLBIMVAAIS;
669 case 5:
670 return MISCREG_TLBIMVALIS;
671 case 7:
672 return MISCREG_TLBIMVAALIS;
673 }
674 break;
675 case 5:
676 switch (opc2) {
677 case 0:
678 return MISCREG_ITLBIALL;
679 case 1:
680 return MISCREG_ITLBIMVA;
681 case 2:
682 return MISCREG_ITLBIASID;
683 }
684 break;
685 case 6:
686 switch (opc2) {
687 case 0:
688 return MISCREG_DTLBIALL;
689 case 1:
690 return MISCREG_DTLBIMVA;
691 case 2:
692 return MISCREG_DTLBIASID;
693 }
694 break;
695 case 7:
696 switch (opc2) {
697 case 0:
698 return MISCREG_TLBIALL;
699 case 1:
700 return MISCREG_TLBIMVA;
701 case 2:
702 return MISCREG_TLBIASID;
703 case 3:
704 return MISCREG_TLBIMVAA;
705 case 5:
706 return MISCREG_TLBIMVAL;
707 case 7:
708 return MISCREG_TLBIMVAAL;
709 }
710 break;
711 }
712 } else if (opc1 == 4) {
713 if (crm == 0) {
714 switch (opc2) {
715 case 1:
716 return MISCREG_TLBIIPAS2IS;
717 case 5:
718 return MISCREG_TLBIIPAS2LIS;
719 }
720 } else if (crm == 3) {
721 switch (opc2) {
722 case 0:
723 return MISCREG_TLBIALLHIS;
724 case 1:
725 return MISCREG_TLBIMVAHIS;
726 case 4:
727 return MISCREG_TLBIALLNSNHIS;
728 case 5:
729 return MISCREG_TLBIMVALHIS;
730 }
731 } else if (crm == 4) {
732 switch (opc2) {
733 case 1:
734 return MISCREG_TLBIIPAS2;
735 case 5:
736 return MISCREG_TLBIIPAS2L;
737 }
738 } else if (crm == 7) {
739 switch (opc2) {
740 case 0:
741 return MISCREG_TLBIALLH;
742 case 1:
743 return MISCREG_TLBIMVAH;
744 case 4:
745 return MISCREG_TLBIALLNSNH;
746 case 5:
747 return MISCREG_TLBIMVALH;
748 }
749 }
750 }
751 break;
752 case 9:
753 // Every cop register with CRn = 9 and CRm in
754 // {0-2}, {5-8} is implementation defined regardless
755 // of opc1 and opc2.
756 switch (crm) {
757 case 0:
758 case 1:
759 case 2:
760 case 5:
761 case 6:
762 case 7:
763 case 8:
764 return MISCREG_IMPDEF_UNIMPL;
765 }
766 if (opc1 == 0) {
767 switch (crm) {
768 case 12:
769 switch (opc2) {
770 case 0:
771 return MISCREG_PMCR;
772 case 1:
773 return MISCREG_PMCNTENSET;
774 case 2:
775 return MISCREG_PMCNTENCLR;
776 case 3:
777 return MISCREG_PMOVSR;
778 case 4:
779 return MISCREG_PMSWINC;
780 case 5:
781 return MISCREG_PMSELR;
782 case 6:
783 return MISCREG_PMCEID0;
784 case 7:
785 return MISCREG_PMCEID1;
786 }
787 break;
788 case 13:
789 switch (opc2) {
790 case 0:
791 return MISCREG_PMCCNTR;
792 case 1:
793 // Selector is PMSELR.SEL
794 return MISCREG_PMXEVTYPER_PMCCFILTR;
795 case 2:
796 return MISCREG_PMXEVCNTR;
797 }
798 break;
799 case 14:
800 switch (opc2) {
801 case 0:
802 return MISCREG_PMUSERENR;
803 case 1:
804 return MISCREG_PMINTENSET;
805 case 2:
806 return MISCREG_PMINTENCLR;
807 case 3:
808 return MISCREG_PMOVSSET;
809 }
810 break;
811 }
812 } else if (opc1 == 1) {
813 switch (crm) {
814 case 0:
815 switch (opc2) {
816 case 2: // L2CTLR, L2 Control Register
817 return MISCREG_L2CTLR;
818 case 3:
819 return MISCREG_L2ECTLR;
820 }
821 break;
822 break;
823 }
824 }
825 break;
826 case 10:
827 if (opc1 == 0) {
828 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
829 if (crm < 2) {
830 return MISCREG_IMPDEF_UNIMPL;
831 } else if (crm == 2) { // TEX Remap Registers
832 if (opc2 == 0) {
833 // Selector is TTBCR.EAE
834 return MISCREG_PRRR_MAIR0;
835 } else if (opc2 == 1) {
836 // Selector is TTBCR.EAE
837 return MISCREG_NMRR_MAIR1;
838 }
839 } else if (crm == 3) {
840 if (opc2 == 0) {
841 return MISCREG_AMAIR0;
842 } else if (opc2 == 1) {
843 return MISCREG_AMAIR1;
844 }
845 }
846 } else if (opc1 == 4) {
847 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
848 if (crm == 2) {
849 if (opc2 == 0)
850 return MISCREG_HMAIR0;
851 else if (opc2 == 1)
852 return MISCREG_HMAIR1;
853 } else if (crm == 3) {
854 if (opc2 == 0)
855 return MISCREG_HAMAIR0;
856 else if (opc2 == 1)
857 return MISCREG_HAMAIR1;
858 }
859 }
860 break;
861 case 11:
862 if (opc1 <=7) {
863 switch (crm) {
864 case 0:
865 case 1:
866 case 2:
867 case 3:
868 case 4:
869 case 5:
870 case 6:
871 case 7:
872 case 8:
873 case 15:
874 // Reserved for DMA operations for TCM access
875 return MISCREG_IMPDEF_UNIMPL;
876 default:
877 break;
878 }
879 }
880 break;
881 case 12:
882 if (opc1 == 0) {
883 if (crm == 0) {
884 if (opc2 == 0) {
885 return MISCREG_VBAR;
886 } else if (opc2 == 1) {
887 return MISCREG_MVBAR;
888 }
889 } else if (crm == 1) {
890 if (opc2 == 0) {
891 return MISCREG_ISR;
892 }
893 } else if (crm == 8) {
894 switch (opc2) {
895 case 0:
896 return MISCREG_ICC_IAR0;
897 case 1:
898 return MISCREG_ICC_EOIR0;
899 case 2:
900 return MISCREG_ICC_HPPIR0;
901 case 3:
902 return MISCREG_ICC_BPR0;
903 case 4:
904 return MISCREG_ICC_AP0R0;
905 case 5:
906 return MISCREG_ICC_AP0R1;
907 case 6:
908 return MISCREG_ICC_AP0R2;
909 case 7:
910 return MISCREG_ICC_AP0R3;
911 }
912 } else if (crm == 9) {
913 switch (opc2) {
914 case 0:
915 return MISCREG_ICC_AP1R0;
916 case 1:
917 return MISCREG_ICC_AP1R1;
918 case 2:
919 return MISCREG_ICC_AP1R2;
920 case 3:
921 return MISCREG_ICC_AP1R3;
922 }
923 } else if (crm == 11) {
924 switch (opc2) {
925 case 1:
926 return MISCREG_ICC_DIR;
927 case 3:
928 return MISCREG_ICC_RPR;
929 }
930 } else if (crm == 12) {
931 switch (opc2) {
932 case 0:
933 return MISCREG_ICC_IAR1;
934 case 1:
935 return MISCREG_ICC_EOIR1;
936 case 2:
937 return MISCREG_ICC_HPPIR1;
938 case 3:
939 return MISCREG_ICC_BPR1;
940 case 4:
941 return MISCREG_ICC_CTLR;
942 case 5:
943 return MISCREG_ICC_SRE;
944 case 6:
945 return MISCREG_ICC_IGRPEN0;
946 case 7:
947 return MISCREG_ICC_IGRPEN1;
948 }
949 }
950 } else if (opc1 == 4) {
951 if (crm == 0 && opc2 == 0) {
952 return MISCREG_HVBAR;
953 } else if (crm == 8) {
954 switch (opc2) {
955 case 0:
956 return MISCREG_ICH_AP0R0;
957 case 1:
958 return MISCREG_ICH_AP0R1;
959 case 2:
960 return MISCREG_ICH_AP0R2;
961 case 3:
962 return MISCREG_ICH_AP0R3;
963 }
964 } else if (crm == 9) {
965 switch (opc2) {
966 case 0:
967 return MISCREG_ICH_AP1R0;
968 case 1:
969 return MISCREG_ICH_AP1R1;
970 case 2:
971 return MISCREG_ICH_AP1R2;
972 case 3:
973 return MISCREG_ICH_AP1R3;
974 case 5:
975 return MISCREG_ICC_HSRE;
976 }
977 } else if (crm == 11) {
978 switch (opc2) {
979 case 0:
980 return MISCREG_ICH_HCR;
981 case 1:
982 return MISCREG_ICH_VTR;
983 case 2:
984 return MISCREG_ICH_MISR;
985 case 3:
986 return MISCREG_ICH_EISR;
987 case 5:
988 return MISCREG_ICH_ELRSR;
989 case 7:
990 return MISCREG_ICH_VMCR;
991 }
992 } else if (crm == 12) {
993 switch (opc2) {
994 case 0:
995 return MISCREG_ICH_LR0;
996 case 1:
997 return MISCREG_ICH_LR1;
998 case 2:
999 return MISCREG_ICH_LR2;
1000 case 3:
1001 return MISCREG_ICH_LR3;
1002 case 4:
1003 return MISCREG_ICH_LR4;
1004 case 5:
1005 return MISCREG_ICH_LR5;
1006 case 6:
1007 return MISCREG_ICH_LR6;
1008 case 7:
1009 return MISCREG_ICH_LR7;
1010 }
1011 } else if (crm == 13) {
1012 switch (opc2) {
1013 case 0:
1014 return MISCREG_ICH_LR8;
1015 case 1:
1016 return MISCREG_ICH_LR9;
1017 case 2:
1018 return MISCREG_ICH_LR10;
1019 case 3:
1020 return MISCREG_ICH_LR11;
1021 case 4:
1022 return MISCREG_ICH_LR12;
1023 case 5:
1024 return MISCREG_ICH_LR13;
1025 case 6:
1026 return MISCREG_ICH_LR14;
1027 case 7:
1028 return MISCREG_ICH_LR15;
1029 }
1030 } else if (crm == 14) {
1031 switch (opc2) {
1032 case 0:
1033 return MISCREG_ICH_LRC0;
1034 case 1:
1035 return MISCREG_ICH_LRC1;
1036 case 2:
1037 return MISCREG_ICH_LRC2;
1038 case 3:
1039 return MISCREG_ICH_LRC3;
1040 case 4:
1041 return MISCREG_ICH_LRC4;
1042 case 5:
1043 return MISCREG_ICH_LRC5;
1044 case 6:
1045 return MISCREG_ICH_LRC6;
1046 case 7:
1047 return MISCREG_ICH_LRC7;
1048 }
1049 } else if (crm == 15) {
1050 switch (opc2) {
1051 case 0:
1052 return MISCREG_ICH_LRC8;
1053 case 1:
1054 return MISCREG_ICH_LRC9;
1055 case 2:
1056 return MISCREG_ICH_LRC10;
1057 case 3:
1058 return MISCREG_ICH_LRC11;
1059 case 4:
1060 return MISCREG_ICH_LRC12;
1061 case 5:
1062 return MISCREG_ICH_LRC13;
1063 case 6:
1064 return MISCREG_ICH_LRC14;
1065 case 7:
1066 return MISCREG_ICH_LRC15;
1067 }
1068 }
1069 } else if (opc1 == 6) {
1070 if (crm == 12) {
1071 switch (opc2) {
1072 case 4:
1073 return MISCREG_ICC_MCTLR;
1074 case 5:
1075 return MISCREG_ICC_MSRE;
1076 case 7:
1077 return MISCREG_ICC_MGRPEN1;
1078 }
1079 }
1080 }
1081 break;
1082 case 13:
1083 if (opc1 == 0) {
1084 if (crm == 0) {
1085 switch (opc2) {
1086 case 0:
1087 return MISCREG_FCSEIDR;
1088 case 1:
1089 return MISCREG_CONTEXTIDR;
1090 case 2:
1091 return MISCREG_TPIDRURW;
1092 case 3:
1093 return MISCREG_TPIDRURO;
1094 case 4:
1095 return MISCREG_TPIDRPRW;
1096 }
1097 }
1098 } else if (opc1 == 4) {
1099 if (crm == 0 && opc2 == 2)
1100 return MISCREG_HTPIDR;
1101 }
1102 break;
1103 case 14:
1104 if (opc1 == 0) {
1105 switch (crm) {
1106 case 0:
1107 if (opc2 == 0)
1108 return MISCREG_CNTFRQ;
1109 break;
1110 case 1:
1111 if (opc2 == 0)
1112 return MISCREG_CNTKCTL;
1113 break;
1114 case 2:
1115 if (opc2 == 0)
1116 return MISCREG_CNTP_TVAL;
1117 else if (opc2 == 1)
1118 return MISCREG_CNTP_CTL;
1119 break;
1120 case 3:
1121 if (opc2 == 0)
1122 return MISCREG_CNTV_TVAL;
1123 else if (opc2 == 1)
1124 return MISCREG_CNTV_CTL;
1125 break;
1126 }
1127 } else if (opc1 == 4) {
1128 if (crm == 1 && opc2 == 0) {
1129 return MISCREG_CNTHCTL;
1130 } else if (crm == 2) {
1131 if (opc2 == 0)
1132 return MISCREG_CNTHP_TVAL;
1133 else if (opc2 == 1)
1134 return MISCREG_CNTHP_CTL;
1135 }
1136 }
1137 break;
1138 case 15:
1139 // Implementation defined
1140 return MISCREG_IMPDEF_UNIMPL;
1141 }
1142 // Unrecognized register
1143 return MISCREG_CP15_UNIMPL;
1144 }
1145
1146 MiscRegIndex
1147 decodeCP15Reg64(unsigned crm, unsigned opc1)
1148 {
1149 switch (crm) {
1150 case 2:
1151 switch (opc1) {
1152 case 0:
1153 return MISCREG_TTBR0;
1154 case 1:
1155 return MISCREG_TTBR1;
1156 case 4:
1157 return MISCREG_HTTBR;
1158 case 6:
1159 return MISCREG_VTTBR;
1160 }
1161 break;
1162 case 7:
1163 if (opc1 == 0)
1164 return MISCREG_PAR;
1165 break;
1166 case 14:
1167 switch (opc1) {
1168 case 0:
1169 return MISCREG_CNTPCT;
1170 case 1:
1171 return MISCREG_CNTVCT;
1172 case 2:
1173 return MISCREG_CNTP_CVAL;
1174 case 3:
1175 return MISCREG_CNTV_CVAL;
1176 case 4:
1177 return MISCREG_CNTVOFF;
1178 case 6:
1179 return MISCREG_CNTHP_CVAL;
1180 }
1181 break;
1182 case 12:
1183 switch (opc1) {
1184 case 0:
1185 return MISCREG_ICC_SGI1R;
1186 case 1:
1187 return MISCREG_ICC_ASGI1R;
1188 case 2:
1189 return MISCREG_ICC_SGI0R;
1190 default:
1191 break;
1192 }
1193 break;
1194 case 15:
1195 if (opc1 == 0)
1196 return MISCREG_CPUMERRSR;
1197 else if (opc1 == 1)
1198 return MISCREG_L2MERRSR;
1199 break;
1200 }
1201 // Unrecognized register
1202 return MISCREG_CP15_UNIMPL;
1203 }
1204
1205 std::tuple<bool, bool>
1206 canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1207 {
1208 bool secure = !scr.ns;
1209 bool canRead = false;
1210 bool undefined = false;
1211
1212 switch (cpsr.mode) {
1213 case MODE_USER:
1214 canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
1215 miscRegInfo[reg][MISCREG_USR_NS_RD];
1216 break;
1217 case MODE_FIQ:
1218 case MODE_IRQ:
1219 case MODE_SVC:
1220 case MODE_ABORT:
1221 case MODE_UNDEFINED:
1222 case MODE_SYSTEM:
1223 canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1224 miscRegInfo[reg][MISCREG_PRI_NS_RD];
1225 break;
1226 case MODE_MON:
1227 canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1228 miscRegInfo[reg][MISCREG_MON_NS1_RD];
1229 break;
1230 case MODE_HYP:
1231 canRead = miscRegInfo[reg][MISCREG_HYP_NS_RD];
1232 break;
1233 default:
1234 undefined = true;
1235 }
1236
1237 switch (reg) {
1238 case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
1239 if (!undefined)
1240 undefined = AArch32isUndefinedGenericTimer(reg, tc);
1241 break;
1242 default:
1243 break;
1244 }
1245
1246 // can't do permissions checkes on the root of a banked pair of regs
1247 assert(!miscRegInfo[reg][MISCREG_BANKED]);
1248 return std::make_tuple(canRead, undefined);
1249 }
1250
1251 std::tuple<bool, bool>
1252 canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1253 {
1254 bool secure = !scr.ns;
1255 bool canWrite = false;
1256 bool undefined = false;
1257
1258 switch (cpsr.mode) {
1259 case MODE_USER:
1260 canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1261 miscRegInfo[reg][MISCREG_USR_NS_WR];
1262 break;
1263 case MODE_FIQ:
1264 case MODE_IRQ:
1265 case MODE_SVC:
1266 case MODE_ABORT:
1267 case MODE_UNDEFINED:
1268 case MODE_SYSTEM:
1269 canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1270 miscRegInfo[reg][MISCREG_PRI_NS_WR];
1271 break;
1272 case MODE_MON:
1273 canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1274 miscRegInfo[reg][MISCREG_MON_NS1_WR];
1275 break;
1276 case MODE_HYP:
1277 canWrite = miscRegInfo[reg][MISCREG_HYP_NS_WR];
1278 break;
1279 default:
1280 undefined = true;
1281 }
1282
1283 switch (reg) {
1284 case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
1285 if (!undefined)
1286 undefined = AArch32isUndefinedGenericTimer(reg, tc);
1287 break;
1288 default:
1289 break;
1290 }
1291
1292 // can't do permissions checkes on the root of a banked pair of regs
1293 assert(!miscRegInfo[reg][MISCREG_BANKED]);
1294 return std::make_tuple(canWrite, undefined);
1295 }
1296
1297 bool
1298 AArch32isUndefinedGenericTimer(MiscRegIndex reg, ThreadContext *tc)
1299 {
1300 if (currEL(tc) == EL0 && ELIs32(tc, EL1)) {
1301 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1302 bool trap_cond = condGenericTimerSystemAccessTrapEL1(reg, tc);
1303 if (trap_cond && (!EL2Enabled(tc) || !hcr.tge))
1304 return true;
1305 }
1306 return false;
1307 }
1308
1309 int
1310 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
1311 {
1312 SCR scr = tc->readMiscReg(MISCREG_SCR);
1313 return snsBankedIndex(reg, tc, scr.ns);
1314 }
1315
1316 int
1317 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
1318 {
1319 int reg_as_int = static_cast<int>(reg);
1320 if (miscRegInfo[reg][MISCREG_BANKED]) {
1321 reg_as_int += (ArmSystem::haveSecurity(tc) &&
1322 !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
1323 }
1324 return reg_as_int;
1325 }
1326
1327 int
1328 snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc)
1329 {
1330 auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
1331 SCR scr = tc->readMiscReg(MISCREG_SCR);
1332 return isa->snsBankedIndex64(reg, scr.ns);
1333 }
1334
1335 /**
1336 * If the reg is a child reg of a banked set, then the parent is the last
1337 * banked one in the list. This is messy, and the wish is to eventually have
1338 * the bitmap replaced with a better data structure. the preUnflatten function
1339 * initializes a lookup table to speed up the search for these banked
1340 * registers.
1341 */
1342
1343 int unflattenResultMiscReg[NUM_MISCREGS];
1344
1345 void
1346 preUnflattenMiscReg()
1347 {
1348 int reg = -1;
1349 for (int i = 0 ; i < NUM_MISCREGS; i++){
1350 if (miscRegInfo[i][MISCREG_BANKED])
1351 reg = i;
1352 if (miscRegInfo[i][MISCREG_BANKED_CHILD])
1353 unflattenResultMiscReg[i] = reg;
1354 else
1355 unflattenResultMiscReg[i] = i;
1356 // if this assert fails, no parent was found, and something is broken
1357 assert(unflattenResultMiscReg[i] > -1);
1358 }
1359 }
1360
1361 int
1362 unflattenMiscReg(int reg)
1363 {
1364 return unflattenResultMiscReg[reg];
1365 }
1366
1367 bool
1368 canReadAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
1369 ThreadContext *tc)
1370 {
1371 // Check for SP_EL0 access while SPSEL == 0
1372 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1373 return false;
1374
1375 // Check for RVBAR access
1376 if (reg == MISCREG_RVBAR_EL1) {
1377 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1378 if (highest_el == EL2 || highest_el == EL3)
1379 return false;
1380 }
1381 if (reg == MISCREG_RVBAR_EL2) {
1382 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1383 if (highest_el == EL3)
1384 return false;
1385 }
1386
1387 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
1388 bool el2_host = EL2Enabled(tc) && hcr.e2h;
1389
1390 switch (currEL(cpsr)) {
1391 case EL0:
1392 return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
1393 miscRegInfo[reg][MISCREG_USR_NS_RD];
1394 case EL1:
1395 return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1396 miscRegInfo[reg][MISCREG_PRI_NS_RD];
1397 case EL2:
1398 if (el2_host) {
1399 return secure ? miscRegInfo[reg][MISCREG_HYP_E2H_S_RD] :
1400 miscRegInfo[reg][MISCREG_HYP_E2H_NS_RD];
1401 } else {
1402 return secure ? miscRegInfo[reg][MISCREG_HYP_S_RD] :
1403 miscRegInfo[reg][MISCREG_HYP_NS_RD];
1404 }
1405 case EL3:
1406 return el2_host ? miscRegInfo[reg][MISCREG_MON_E2H_RD] :
1407 secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1408 miscRegInfo[reg][MISCREG_MON_NS1_RD];
1409 default:
1410 panic("Invalid exception level");
1411 }
1412 }
1413
1414 bool
1415 canWriteAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
1416 ThreadContext *tc)
1417 {
1418 // Check for SP_EL0 access while SPSEL == 0
1419 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1420 return false;
1421 ExceptionLevel el = currEL(cpsr);
1422
1423 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
1424 bool el2_host = EL2Enabled(tc) && hcr.e2h;
1425
1426 switch (el) {
1427 case EL0:
1428 return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1429 miscRegInfo[reg][MISCREG_USR_NS_WR];
1430 case EL1:
1431 return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1432 miscRegInfo[reg][MISCREG_PRI_NS_WR];
1433 case EL2:
1434 if (el2_host) {
1435 return secure ? miscRegInfo[reg][MISCREG_HYP_E2H_S_WR] :
1436 miscRegInfo[reg][MISCREG_HYP_E2H_NS_WR];
1437 } else {
1438 return secure ? miscRegInfo[reg][MISCREG_HYP_S_WR] :
1439 miscRegInfo[reg][MISCREG_HYP_NS_WR];
1440 }
1441 case EL3:
1442 return el2_host ? miscRegInfo[reg][MISCREG_MON_E2H_WR] :
1443 secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1444 miscRegInfo[reg][MISCREG_MON_NS1_WR];
1445 default:
1446 panic("Invalid exception level");
1447 }
1448 }
1449
1450 MiscRegIndex
1451 decodeAArch64SysReg(unsigned op0, unsigned op1,
1452 unsigned crn, unsigned crm,
1453 unsigned op2)
1454 {
1455 switch (op0) {
1456 case 1:
1457 switch (crn) {
1458 case 7:
1459 switch (op1) {
1460 case 0:
1461 switch (crm) {
1462 case 1:
1463 switch (op2) {
1464 case 0:
1465 return MISCREG_IC_IALLUIS;
1466 }
1467 break;
1468 case 5:
1469 switch (op2) {
1470 case 0:
1471 return MISCREG_IC_IALLU;
1472 }
1473 break;
1474 case 6:
1475 switch (op2) {
1476 case 1:
1477 return MISCREG_DC_IVAC_Xt;
1478 case 2:
1479 return MISCREG_DC_ISW_Xt;
1480 }
1481 break;
1482 case 8:
1483 switch (op2) {
1484 case 0:
1485 return MISCREG_AT_S1E1R_Xt;
1486 case 1:
1487 return MISCREG_AT_S1E1W_Xt;
1488 case 2:
1489 return MISCREG_AT_S1E0R_Xt;
1490 case 3:
1491 return MISCREG_AT_S1E0W_Xt;
1492 }
1493 break;
1494 case 10:
1495 switch (op2) {
1496 case 2:
1497 return MISCREG_DC_CSW_Xt;
1498 }
1499 break;
1500 case 14:
1501 switch (op2) {
1502 case 2:
1503 return MISCREG_DC_CISW_Xt;
1504 }
1505 break;
1506 }
1507 break;
1508 case 3:
1509 switch (crm) {
1510 case 4:
1511 switch (op2) {
1512 case 1:
1513 return MISCREG_DC_ZVA_Xt;
1514 }
1515 break;
1516 case 5:
1517 switch (op2) {
1518 case 1:
1519 return MISCREG_IC_IVAU_Xt;
1520 }
1521 break;
1522 case 10:
1523 switch (op2) {
1524 case 1:
1525 return MISCREG_DC_CVAC_Xt;
1526 }
1527 break;
1528 case 11:
1529 switch (op2) {
1530 case 1:
1531 return MISCREG_DC_CVAU_Xt;
1532 }
1533 break;
1534 case 14:
1535 switch (op2) {
1536 case 1:
1537 return MISCREG_DC_CIVAC_Xt;
1538 }
1539 break;
1540 }
1541 break;
1542 case 4:
1543 switch (crm) {
1544 case 8:
1545 switch (op2) {
1546 case 0:
1547 return MISCREG_AT_S1E2R_Xt;
1548 case 1:
1549 return MISCREG_AT_S1E2W_Xt;
1550 case 4:
1551 return MISCREG_AT_S12E1R_Xt;
1552 case 5:
1553 return MISCREG_AT_S12E1W_Xt;
1554 case 6:
1555 return MISCREG_AT_S12E0R_Xt;
1556 case 7:
1557 return MISCREG_AT_S12E0W_Xt;
1558 }
1559 break;
1560 }
1561 break;
1562 case 6:
1563 switch (crm) {
1564 case 8:
1565 switch (op2) {
1566 case 0:
1567 return MISCREG_AT_S1E3R_Xt;
1568 case 1:
1569 return MISCREG_AT_S1E3W_Xt;
1570 }
1571 break;
1572 }
1573 break;
1574 }
1575 break;
1576 case 8:
1577 switch (op1) {
1578 case 0:
1579 switch (crm) {
1580 case 3:
1581 switch (op2) {
1582 case 0:
1583 return MISCREG_TLBI_VMALLE1IS;
1584 case 1:
1585 return MISCREG_TLBI_VAE1IS_Xt;
1586 case 2:
1587 return MISCREG_TLBI_ASIDE1IS_Xt;
1588 case 3:
1589 return MISCREG_TLBI_VAAE1IS_Xt;
1590 case 5:
1591 return MISCREG_TLBI_VALE1IS_Xt;
1592 case 7:
1593 return MISCREG_TLBI_VAALE1IS_Xt;
1594 }
1595 break;
1596 case 7:
1597 switch (op2) {
1598 case 0:
1599 return MISCREG_TLBI_VMALLE1;
1600 case 1:
1601 return MISCREG_TLBI_VAE1_Xt;
1602 case 2:
1603 return MISCREG_TLBI_ASIDE1_Xt;
1604 case 3:
1605 return MISCREG_TLBI_VAAE1_Xt;
1606 case 5:
1607 return MISCREG_TLBI_VALE1_Xt;
1608 case 7:
1609 return MISCREG_TLBI_VAALE1_Xt;
1610 }
1611 break;
1612 }
1613 break;
1614 case 4:
1615 switch (crm) {
1616 case 0:
1617 switch (op2) {
1618 case 1:
1619 return MISCREG_TLBI_IPAS2E1IS_Xt;
1620 case 5:
1621 return MISCREG_TLBI_IPAS2LE1IS_Xt;
1622 }
1623 break;
1624 case 3:
1625 switch (op2) {
1626 case 0:
1627 return MISCREG_TLBI_ALLE2IS;
1628 case 1:
1629 return MISCREG_TLBI_VAE2IS_Xt;
1630 case 4:
1631 return MISCREG_TLBI_ALLE1IS;
1632 case 5:
1633 return MISCREG_TLBI_VALE2IS_Xt;
1634 case 6:
1635 return MISCREG_TLBI_VMALLS12E1IS;
1636 }
1637 break;
1638 case 4:
1639 switch (op2) {
1640 case 1:
1641 return MISCREG_TLBI_IPAS2E1_Xt;
1642 case 5:
1643 return MISCREG_TLBI_IPAS2LE1_Xt;
1644 }
1645 break;
1646 case 7:
1647 switch (op2) {
1648 case 0:
1649 return MISCREG_TLBI_ALLE2;
1650 case 1:
1651 return MISCREG_TLBI_VAE2_Xt;
1652 case 4:
1653 return MISCREG_TLBI_ALLE1;
1654 case 5:
1655 return MISCREG_TLBI_VALE2_Xt;
1656 case 6:
1657 return MISCREG_TLBI_VMALLS12E1;
1658 }
1659 break;
1660 }
1661 break;
1662 case 6:
1663 switch (crm) {
1664 case 3:
1665 switch (op2) {
1666 case 0:
1667 return MISCREG_TLBI_ALLE3IS;
1668 case 1:
1669 return MISCREG_TLBI_VAE3IS_Xt;
1670 case 5:
1671 return MISCREG_TLBI_VALE3IS_Xt;
1672 }
1673 break;
1674 case 7:
1675 switch (op2) {
1676 case 0:
1677 return MISCREG_TLBI_ALLE3;
1678 case 1:
1679 return MISCREG_TLBI_VAE3_Xt;
1680 case 5:
1681 return MISCREG_TLBI_VALE3_Xt;
1682 }
1683 break;
1684 }
1685 break;
1686 }
1687 break;
1688 case 11:
1689 case 15:
1690 // SYS Instruction with CRn = { 11, 15 }
1691 // (Trappable by HCR_EL2.TIDCP)
1692 return MISCREG_IMPDEF_UNIMPL;
1693 }
1694 break;
1695 case 2:
1696 switch (crn) {
1697 case 0:
1698 switch (op1) {
1699 case 0:
1700 switch (crm) {
1701 case 0:
1702 switch (op2) {
1703 case 2:
1704 return MISCREG_OSDTRRX_EL1;
1705 case 4:
1706 return MISCREG_DBGBVR0_EL1;
1707 case 5:
1708 return MISCREG_DBGBCR0_EL1;
1709 case 6:
1710 return MISCREG_DBGWVR0_EL1;
1711 case 7:
1712 return MISCREG_DBGWCR0_EL1;
1713 }
1714 break;
1715 case 1:
1716 switch (op2) {
1717 case 4:
1718 return MISCREG_DBGBVR1_EL1;
1719 case 5:
1720 return MISCREG_DBGBCR1_EL1;
1721 case 6:
1722 return MISCREG_DBGWVR1_EL1;
1723 case 7:
1724 return MISCREG_DBGWCR1_EL1;
1725 }
1726 break;
1727 case 2:
1728 switch (op2) {
1729 case 0:
1730 return MISCREG_MDCCINT_EL1;
1731 case 2:
1732 return MISCREG_MDSCR_EL1;
1733 case 4:
1734 return MISCREG_DBGBVR2_EL1;
1735 case 5:
1736 return MISCREG_DBGBCR2_EL1;
1737 case 6:
1738 return MISCREG_DBGWVR2_EL1;
1739 case 7:
1740 return MISCREG_DBGWCR2_EL1;
1741 }
1742 break;
1743 case 3:
1744 switch (op2) {
1745 case 2:
1746 return MISCREG_OSDTRTX_EL1;
1747 case 4:
1748 return MISCREG_DBGBVR3_EL1;
1749 case 5:
1750 return MISCREG_DBGBCR3_EL1;
1751 case 6:
1752 return MISCREG_DBGWVR3_EL1;
1753 case 7:
1754 return MISCREG_DBGWCR3_EL1;
1755 }
1756 break;
1757 case 4:
1758 switch (op2) {
1759 case 4:
1760 return MISCREG_DBGBVR4_EL1;
1761 case 5:
1762 return MISCREG_DBGBCR4_EL1;
1763 case 6:
1764 return MISCREG_DBGWVR4_EL1;
1765 case 7:
1766 return MISCREG_DBGWCR4_EL1;
1767 }
1768 break;
1769 case 5:
1770 switch (op2) {
1771 case 4:
1772 return MISCREG_DBGBVR5_EL1;
1773 case 5:
1774 return MISCREG_DBGBCR5_EL1;
1775 case 6:
1776 return MISCREG_DBGWVR5_EL1;
1777 case 7:
1778 return MISCREG_DBGWCR5_EL1;
1779 }
1780 break;
1781 case 6:
1782 switch (op2) {
1783 case 2:
1784 return MISCREG_OSECCR_EL1;
1785 case 4:
1786 return MISCREG_DBGBVR6_EL1;
1787 case 5:
1788 return MISCREG_DBGBCR6_EL1;
1789 case 6:
1790 return MISCREG_DBGWVR6_EL1;
1791 case 7:
1792 return MISCREG_DBGWCR6_EL1;
1793 }
1794 break;
1795 case 7:
1796 switch (op2) {
1797 case 4:
1798 return MISCREG_DBGBVR7_EL1;
1799 case 5:
1800 return MISCREG_DBGBCR7_EL1;
1801 case 6:
1802 return MISCREG_DBGWVR7_EL1;
1803 case 7:
1804 return MISCREG_DBGWCR7_EL1;
1805 }
1806 break;
1807 case 8:
1808 switch (op2) {
1809 case 4:
1810 return MISCREG_DBGBVR8_EL1;
1811 case 5:
1812 return MISCREG_DBGBCR8_EL1;
1813 case 6:
1814 return MISCREG_DBGWVR8_EL1;
1815 case 7:
1816 return MISCREG_DBGWCR8_EL1;
1817 }
1818 break;
1819 case 9:
1820 switch (op2) {
1821 case 4:
1822 return MISCREG_DBGBVR9_EL1;
1823 case 5:
1824 return MISCREG_DBGBCR9_EL1;
1825 case 6:
1826 return MISCREG_DBGWVR9_EL1;
1827 case 7:
1828 return MISCREG_DBGWCR9_EL1;
1829 }
1830 break;
1831 case 10:
1832 switch (op2) {
1833 case 4:
1834 return MISCREG_DBGBVR10_EL1;
1835 case 5:
1836 return MISCREG_DBGBCR10_EL1;
1837 case 6:
1838 return MISCREG_DBGWVR10_EL1;
1839 case 7:
1840 return MISCREG_DBGWCR10_EL1;
1841 }
1842 break;
1843 case 11:
1844 switch (op2) {
1845 case 4:
1846 return MISCREG_DBGBVR11_EL1;
1847 case 5:
1848 return MISCREG_DBGBCR11_EL1;
1849 case 6:
1850 return MISCREG_DBGWVR11_EL1;
1851 case 7:
1852 return MISCREG_DBGWCR11_EL1;
1853 }
1854 break;
1855 case 12:
1856 switch (op2) {
1857 case 4:
1858 return MISCREG_DBGBVR12_EL1;
1859 case 5:
1860 return MISCREG_DBGBCR12_EL1;
1861 case 6:
1862 return MISCREG_DBGWVR12_EL1;
1863 case 7:
1864 return MISCREG_DBGWCR12_EL1;
1865 }
1866 break;
1867 case 13:
1868 switch (op2) {
1869 case 4:
1870 return MISCREG_DBGBVR13_EL1;
1871 case 5:
1872 return MISCREG_DBGBCR13_EL1;
1873 case 6:
1874 return MISCREG_DBGWVR13_EL1;
1875 case 7:
1876 return MISCREG_DBGWCR13_EL1;
1877 }
1878 break;
1879 case 14:
1880 switch (op2) {
1881 case 4:
1882 return MISCREG_DBGBVR14_EL1;
1883 case 5:
1884 return MISCREG_DBGBCR14_EL1;
1885 case 6:
1886 return MISCREG_DBGWVR14_EL1;
1887 case 7:
1888 return MISCREG_DBGWCR14_EL1;
1889 }
1890 break;
1891 case 15:
1892 switch (op2) {
1893 case 4:
1894 return MISCREG_DBGBVR15_EL1;
1895 case 5:
1896 return MISCREG_DBGBCR15_EL1;
1897 case 6:
1898 return MISCREG_DBGWVR15_EL1;
1899 case 7:
1900 return MISCREG_DBGWCR15_EL1;
1901 }
1902 break;
1903 }
1904 break;
1905 case 2:
1906 switch (crm) {
1907 case 0:
1908 switch (op2) {
1909 case 0:
1910 return MISCREG_TEECR32_EL1;
1911 }
1912 break;
1913 }
1914 break;
1915 case 3:
1916 switch (crm) {
1917 case 1:
1918 switch (op2) {
1919 case 0:
1920 return MISCREG_MDCCSR_EL0;
1921 }
1922 break;
1923 case 4:
1924 switch (op2) {
1925 case 0:
1926 return MISCREG_MDDTR_EL0;
1927 }
1928 break;
1929 case 5:
1930 switch (op2) {
1931 case 0:
1932 return MISCREG_MDDTRRX_EL0;
1933 }
1934 break;
1935 }
1936 break;
1937 case 4:
1938 switch (crm) {
1939 case 7:
1940 switch (op2) {
1941 case 0:
1942 return MISCREG_DBGVCR32_EL2;
1943 }
1944 break;
1945 }
1946 break;
1947 }
1948 break;
1949 case 1:
1950 switch (op1) {
1951 case 0:
1952 switch (crm) {
1953 case 0:
1954 switch (op2) {
1955 case 0:
1956 return MISCREG_MDRAR_EL1;
1957 case 4:
1958 return MISCREG_OSLAR_EL1;
1959 }
1960 break;
1961 case 1:
1962 switch (op2) {
1963 case 4:
1964 return MISCREG_OSLSR_EL1;
1965 }
1966 break;
1967 case 3:
1968 switch (op2) {
1969 case 4:
1970 return MISCREG_OSDLR_EL1;
1971 }
1972 break;
1973 case 4:
1974 switch (op2) {
1975 case 4:
1976 return MISCREG_DBGPRCR_EL1;
1977 }
1978 break;
1979 }
1980 break;
1981 case 2:
1982 switch (crm) {
1983 case 0:
1984 switch (op2) {
1985 case 0:
1986 return MISCREG_TEEHBR32_EL1;
1987 }
1988 break;
1989 }
1990 break;
1991 }
1992 break;
1993 case 7:
1994 switch (op1) {
1995 case 0:
1996 switch (crm) {
1997 case 8:
1998 switch (op2) {
1999 case 6:
2000 return MISCREG_DBGCLAIMSET_EL1;
2001 }
2002 break;
2003 case 9:
2004 switch (op2) {
2005 case 6:
2006 return MISCREG_DBGCLAIMCLR_EL1;
2007 }
2008 break;
2009 case 14:
2010 switch (op2) {
2011 case 6:
2012 return MISCREG_DBGAUTHSTATUS_EL1;
2013 }
2014 break;
2015 }
2016 break;
2017 }
2018 break;
2019 }
2020 break;
2021 case 3:
2022 switch (crn) {
2023 case 0:
2024 switch (op1) {
2025 case 0:
2026 switch (crm) {
2027 case 0:
2028 switch (op2) {
2029 case 0:
2030 return MISCREG_MIDR_EL1;
2031 case 5:
2032 return MISCREG_MPIDR_EL1;
2033 case 6:
2034 return MISCREG_REVIDR_EL1;
2035 }
2036 break;
2037 case 1:
2038 switch (op2) {
2039 case 0:
2040 return MISCREG_ID_PFR0_EL1;
2041 case 1:
2042 return MISCREG_ID_PFR1_EL1;
2043 case 2:
2044 return MISCREG_ID_DFR0_EL1;
2045 case 3:
2046 return MISCREG_ID_AFR0_EL1;
2047 case 4:
2048 return MISCREG_ID_MMFR0_EL1;
2049 case 5:
2050 return MISCREG_ID_MMFR1_EL1;
2051 case 6:
2052 return MISCREG_ID_MMFR2_EL1;
2053 case 7:
2054 return MISCREG_ID_MMFR3_EL1;
2055 }
2056 break;
2057 case 2:
2058 switch (op2) {
2059 case 0:
2060 return MISCREG_ID_ISAR0_EL1;
2061 case 1:
2062 return MISCREG_ID_ISAR1_EL1;
2063 case 2:
2064 return MISCREG_ID_ISAR2_EL1;
2065 case 3:
2066 return MISCREG_ID_ISAR3_EL1;
2067 case 4:
2068 return MISCREG_ID_ISAR4_EL1;
2069 case 5:
2070 return MISCREG_ID_ISAR5_EL1;
2071 case 6:
2072 return MISCREG_ID_MMFR4_EL1;
2073 case 7:
2074 return MISCREG_ID_ISAR6_EL1;
2075 }
2076 break;
2077 case 3:
2078 switch (op2) {
2079 case 0:
2080 return MISCREG_MVFR0_EL1;
2081 case 1:
2082 return MISCREG_MVFR1_EL1;
2083 case 2:
2084 return MISCREG_MVFR2_EL1;
2085 case 3 ... 7:
2086 return MISCREG_RAZ;
2087 }
2088 break;
2089 case 4:
2090 switch (op2) {
2091 case 0:
2092 return MISCREG_ID_AA64PFR0_EL1;
2093 case 1:
2094 return MISCREG_ID_AA64PFR1_EL1;
2095 case 2 ... 3:
2096 return MISCREG_RAZ;
2097 case 4:
2098 return MISCREG_ID_AA64ZFR0_EL1;
2099 case 5 ... 7:
2100 return MISCREG_RAZ;
2101 }
2102 break;
2103 case 5:
2104 switch (op2) {
2105 case 0:
2106 return MISCREG_ID_AA64DFR0_EL1;
2107 case 1:
2108 return MISCREG_ID_AA64DFR1_EL1;
2109 case 4:
2110 return MISCREG_ID_AA64AFR0_EL1;
2111 case 5:
2112 return MISCREG_ID_AA64AFR1_EL1;
2113 case 2:
2114 case 3:
2115 case 6:
2116 case 7:
2117 return MISCREG_RAZ;
2118 }
2119 break;
2120 case 6:
2121 switch (op2) {
2122 case 0:
2123 return MISCREG_ID_AA64ISAR0_EL1;
2124 case 1:
2125 return MISCREG_ID_AA64ISAR1_EL1;
2126 case 2 ... 7:
2127 return MISCREG_RAZ;
2128 }
2129 break;
2130 case 7:
2131 switch (op2) {
2132 case 0:
2133 return MISCREG_ID_AA64MMFR0_EL1;
2134 case 1:
2135 return MISCREG_ID_AA64MMFR1_EL1;
2136 case 2:
2137 return MISCREG_ID_AA64MMFR2_EL1;
2138 case 3 ... 7:
2139 return MISCREG_RAZ;
2140 }
2141 break;
2142 }
2143 break;
2144 case 1:
2145 switch (crm) {
2146 case 0:
2147 switch (op2) {
2148 case 0:
2149 return MISCREG_CCSIDR_EL1;
2150 case 1:
2151 return MISCREG_CLIDR_EL1;
2152 case 7:
2153 return MISCREG_AIDR_EL1;
2154 }
2155 break;
2156 }
2157 break;
2158 case 2:
2159 switch (crm) {
2160 case 0:
2161 switch (op2) {
2162 case 0:
2163 return MISCREG_CSSELR_EL1;
2164 }
2165 break;
2166 }
2167 break;
2168 case 3:
2169 switch (crm) {
2170 case 0:
2171 switch (op2) {
2172 case 1:
2173 return MISCREG_CTR_EL0;
2174 case 7:
2175 return MISCREG_DCZID_EL0;
2176 }
2177 break;
2178 }
2179 break;
2180 case 4:
2181 switch (crm) {
2182 case 0:
2183 switch (op2) {
2184 case 0:
2185 return MISCREG_VPIDR_EL2;
2186 case 5:
2187 return MISCREG_VMPIDR_EL2;
2188 }
2189 break;
2190 }
2191 break;
2192 }
2193 break;
2194 case 1:
2195 switch (op1) {
2196 case 0:
2197 switch (crm) {
2198 case 0:
2199 switch (op2) {
2200 case 0:
2201 return MISCREG_SCTLR_EL1;
2202 case 1:
2203 return MISCREG_ACTLR_EL1;
2204 case 2:
2205 return MISCREG_CPACR_EL1;
2206 }
2207 break;
2208 case 2:
2209 switch (op2) {
2210 case 0:
2211 return MISCREG_ZCR_EL1;
2212 }
2213 break;
2214 }
2215 break;
2216 case 4:
2217 switch (crm) {
2218 case 0:
2219 switch (op2) {
2220 case 0:
2221 return MISCREG_SCTLR_EL2;
2222 case 1:
2223 return MISCREG_ACTLR_EL2;
2224 }
2225 break;
2226 case 1:
2227 switch (op2) {
2228 case 0:
2229 return MISCREG_HCR_EL2;
2230 case 1:
2231 return MISCREG_MDCR_EL2;
2232 case 2:
2233 return MISCREG_CPTR_EL2;
2234 case 3:
2235 return MISCREG_HSTR_EL2;
2236 case 7:
2237 return MISCREG_HACR_EL2;
2238 }
2239 break;
2240 case 2:
2241 switch (op2) {
2242 case 0:
2243 return MISCREG_ZCR_EL2;
2244 }
2245 break;
2246 }
2247 break;
2248 case 5:
2249 /* op0: 3 Crn:1 op1:5 */
2250 switch (crm) {
2251 case 0:
2252 switch (op2) {
2253 case 0:
2254 return MISCREG_SCTLR_EL12;
2255 case 2:
2256 return MISCREG_CPACR_EL12;
2257 }
2258 break;
2259 case 2:
2260 switch (op2) {
2261 case 0:
2262 return MISCREG_ZCR_EL12;
2263 }
2264 break;
2265 }
2266 break;
2267 case 6:
2268 switch (crm) {
2269 case 0:
2270 switch (op2) {
2271 case 0:
2272 return MISCREG_SCTLR_EL3;
2273 case 1:
2274 return MISCREG_ACTLR_EL3;
2275 }
2276 break;
2277 case 1:
2278 switch (op2) {
2279 case 0:
2280 return MISCREG_SCR_EL3;
2281 case 1:
2282 return MISCREG_SDER32_EL3;
2283 case 2:
2284 return MISCREG_CPTR_EL3;
2285 }
2286 break;
2287 case 2:
2288 switch (op2) {
2289 case 0:
2290 return MISCREG_ZCR_EL3;
2291 }
2292 break;
2293 case 3:
2294 switch (op2) {
2295 case 1:
2296 return MISCREG_MDCR_EL3;
2297 }
2298 break;
2299 }
2300 break;
2301 }
2302 break;
2303 case 2:
2304 switch (op1) {
2305 case 0:
2306 switch (crm) {
2307 case 0:
2308 switch (op2) {
2309 case 0:
2310 return MISCREG_TTBR0_EL1;
2311 case 1:
2312 return MISCREG_TTBR1_EL1;
2313 case 2:
2314 return MISCREG_TCR_EL1;
2315 }
2316 break;
2317 case 0x1:
2318 switch (op2) {
2319 case 0x0:
2320 return MISCREG_APIAKeyLo_EL1;
2321 case 0x1:
2322 return MISCREG_APIAKeyHi_EL1;
2323 case 0x2:
2324 return MISCREG_APIBKeyLo_EL1;
2325 case 0x3:
2326 return MISCREG_APIBKeyHi_EL1;
2327 }
2328 break;
2329 case 0x2:
2330 switch (op2) {
2331 case 0x0:
2332 return MISCREG_APDAKeyLo_EL1;
2333 case 0x1:
2334 return MISCREG_APDAKeyHi_EL1;
2335 case 0x2:
2336 return MISCREG_APDBKeyLo_EL1;
2337 case 0x3:
2338 return MISCREG_APDBKeyHi_EL1;
2339 }
2340 break;
2341
2342 case 0x3:
2343 switch (op2) {
2344 case 0x0:
2345 return MISCREG_APGAKeyLo_EL1;
2346 case 0x1:
2347 return MISCREG_APGAKeyHi_EL1;
2348 }
2349 break;
2350 }
2351 break;
2352 case 4:
2353 switch (crm) {
2354 case 0:
2355 switch (op2) {
2356 case 0:
2357 return MISCREG_TTBR0_EL2;
2358 case 1:
2359 return MISCREG_TTBR1_EL2;
2360 case 2:
2361 return MISCREG_TCR_EL2;
2362 }
2363 break;
2364 case 1:
2365 switch (op2) {
2366 case 0:
2367 return MISCREG_VTTBR_EL2;
2368 case 2:
2369 return MISCREG_VTCR_EL2;
2370 }
2371 break;
2372 case 6:
2373 switch (op2) {
2374 case 0:
2375 return MISCREG_VSTTBR_EL2;
2376 case 2:
2377 return MISCREG_VSTCR_EL2;
2378 }
2379 break;
2380 }
2381 break;
2382 case 5:
2383 /* op0: 3 Crn:2 op1:5 */
2384 switch (crm) {
2385 case 0:
2386 switch (op2) {
2387 case 0:
2388 return MISCREG_TTBR0_EL12;
2389 case 1:
2390 return MISCREG_TTBR1_EL12;
2391 case 2:
2392 return MISCREG_TCR_EL12;
2393 }
2394 break;
2395 }
2396 break;
2397 case 6:
2398 switch (crm) {
2399 case 0:
2400 switch (op2) {
2401 case 0:
2402 return MISCREG_TTBR0_EL3;
2403 case 2:
2404 return MISCREG_TCR_EL3;
2405 }
2406 break;
2407 }
2408 break;
2409 }
2410 break;
2411 case 3:
2412 switch (op1) {
2413 case 4:
2414 switch (crm) {
2415 case 0:
2416 switch (op2) {
2417 case 0:
2418 return MISCREG_DACR32_EL2;
2419 }
2420 break;
2421 }
2422 break;
2423 }
2424 break;
2425 case 4:
2426 switch (op1) {
2427 case 0:
2428 switch (crm) {
2429 case 0:
2430 switch (op2) {
2431 case 0:
2432 return MISCREG_SPSR_EL1;
2433 case 1:
2434 return MISCREG_ELR_EL1;
2435 }
2436 break;
2437 case 1:
2438 switch (op2) {
2439 case 0:
2440 return MISCREG_SP_EL0;
2441 }
2442 break;
2443 case 2:
2444 switch (op2) {
2445 case 0:
2446 return MISCREG_SPSEL;
2447 case 2:
2448 return MISCREG_CURRENTEL;
2449 case 3:
2450 return MISCREG_PAN;
2451 }
2452 break;
2453 case 6:
2454 switch (op2) {
2455 case 0:
2456 return MISCREG_ICC_PMR_EL1;
2457 }
2458 break;
2459 }
2460 break;
2461 case 3:
2462 switch (crm) {
2463 case 2:
2464 switch (op2) {
2465 case 0:
2466 return MISCREG_NZCV;
2467 case 1:
2468 return MISCREG_DAIF;
2469 }
2470 break;
2471 case 4:
2472 switch (op2) {
2473 case 0:
2474 return MISCREG_FPCR;
2475 case 1:
2476 return MISCREG_FPSR;
2477 }
2478 break;
2479 case 5:
2480 switch (op2) {
2481 case 0:
2482 return MISCREG_DSPSR_EL0;
2483 case 1:
2484 return MISCREG_DLR_EL0;
2485 }
2486 break;
2487 }
2488 break;
2489 case 4:
2490 switch (crm) {
2491 case 0:
2492 switch (op2) {
2493 case 0:
2494 return MISCREG_SPSR_EL2;
2495 case 1:
2496 return MISCREG_ELR_EL2;
2497 }
2498 break;
2499 case 1:
2500 switch (op2) {
2501 case 0:
2502 return MISCREG_SP_EL1;
2503 }
2504 break;
2505 case 3:
2506 switch (op2) {
2507 case 0:
2508 return MISCREG_SPSR_IRQ_AA64;
2509 case 1:
2510 return MISCREG_SPSR_ABT_AA64;
2511 case 2:
2512 return MISCREG_SPSR_UND_AA64;
2513 case 3:
2514 return MISCREG_SPSR_FIQ_AA64;
2515 }
2516 break;
2517 }
2518 break;
2519 case 5:
2520 switch (crm) {
2521 case 0:
2522 switch (op2) {
2523 case 0:
2524 return MISCREG_SPSR_EL12;
2525 case 1:
2526 return MISCREG_ELR_EL12;
2527 }
2528 break;
2529 }
2530 break;
2531 case 6:
2532 switch (crm) {
2533 case 0:
2534 switch (op2) {
2535 case 0:
2536 return MISCREG_SPSR_EL3;
2537 case 1:
2538 return MISCREG_ELR_EL3;
2539 }
2540 break;
2541 case 1:
2542 switch (op2) {
2543 case 0:
2544 return MISCREG_SP_EL2;
2545 }
2546 break;
2547 }
2548 break;
2549 }
2550 break;
2551 case 5:
2552 switch (op1) {
2553 case 0:
2554 switch (crm) {
2555 case 1:
2556 switch (op2) {
2557 case 0:
2558 return MISCREG_AFSR0_EL1;
2559 case 1:
2560 return MISCREG_AFSR1_EL1;
2561 }
2562 break;
2563 case 2:
2564 switch (op2) {
2565 case 0:
2566 return MISCREG_ESR_EL1;
2567 }
2568 break;
2569 case 3:
2570 switch (op2) {
2571 case 0:
2572 return MISCREG_ERRIDR_EL1;
2573 case 1:
2574 return MISCREG_ERRSELR_EL1;
2575 }
2576 break;
2577 case 4:
2578 switch (op2) {
2579 case 0:
2580 return MISCREG_ERXFR_EL1;
2581 case 1:
2582 return MISCREG_ERXCTLR_EL1;
2583 case 2:
2584 return MISCREG_ERXSTATUS_EL1;
2585 case 3:
2586 return MISCREG_ERXADDR_EL1;
2587 }
2588 break;
2589 case 5:
2590 switch (op2) {
2591 case 0:
2592 return MISCREG_ERXMISC0_EL1;
2593 case 1:
2594 return MISCREG_ERXMISC1_EL1;
2595 }
2596 break;
2597 }
2598 break;
2599 case 4:
2600 switch (crm) {
2601 case 0:
2602 switch (op2) {
2603 case 1:
2604 return MISCREG_IFSR32_EL2;
2605 }
2606 break;
2607 case 1:
2608 switch (op2) {
2609 case 0:
2610 return MISCREG_AFSR0_EL2;
2611 case 1:
2612 return MISCREG_AFSR1_EL2;
2613 }
2614 break;
2615 case 2:
2616 switch (op2) {
2617 case 0:
2618 return MISCREG_ESR_EL2;
2619 case 3:
2620 return MISCREG_VSESR_EL2;
2621 }
2622 break;
2623 case 3:
2624 switch (op2) {
2625 case 0:
2626 return MISCREG_FPEXC32_EL2;
2627 }
2628 break;
2629 }
2630 break;
2631 case 5:
2632 switch (crm) {
2633 case 1:
2634 switch (op2) {
2635 case 0:
2636 return MISCREG_AFSR0_EL12;
2637 case 1:
2638 return MISCREG_AFSR1_EL12;
2639 }
2640 break;
2641 case 2:
2642 switch (op2) {
2643 case 0:
2644 return MISCREG_ESR_EL12;
2645 }
2646 break;
2647 }
2648 break;
2649 case 6:
2650 switch (crm) {
2651 case 1:
2652 switch (op2) {
2653 case 0:
2654 return MISCREG_AFSR0_EL3;
2655 case 1:
2656 return MISCREG_AFSR1_EL3;
2657 }
2658 break;
2659 case 2:
2660 switch (op2) {
2661 case 0:
2662 return MISCREG_ESR_EL3;
2663 }
2664 break;
2665 }
2666 break;
2667 }
2668 break;
2669 case 6:
2670 switch (op1) {
2671 case 0:
2672 switch (crm) {
2673 case 0:
2674 switch (op2) {
2675 case 0:
2676 return MISCREG_FAR_EL1;
2677 }
2678 break;
2679 }
2680 break;
2681 case 4:
2682 switch (crm) {
2683 case 0:
2684 switch (op2) {
2685 case 0:
2686 return MISCREG_FAR_EL2;
2687 case 4:
2688 return MISCREG_HPFAR_EL2;
2689 }
2690 break;
2691 }
2692 break;
2693 case 5:
2694 switch (crm) {
2695 case 0:
2696 switch (op2) {
2697 case 0:
2698 return MISCREG_FAR_EL12;
2699 }
2700 break;
2701 }
2702 break;
2703 case 6:
2704 switch (crm) {
2705 case 0:
2706 switch (op2) {
2707 case 0:
2708 return MISCREG_FAR_EL3;
2709 }
2710 break;
2711 }
2712 break;
2713 }
2714 break;
2715 case 7:
2716 switch (op1) {
2717 case 0:
2718 switch (crm) {
2719 case 4:
2720 switch (op2) {
2721 case 0:
2722 return MISCREG_PAR_EL1;
2723 }
2724 break;
2725 }
2726 break;
2727 }
2728 break;
2729 case 9:
2730 switch (op1) {
2731 case 0:
2732 switch (crm) {
2733 case 14:
2734 switch (op2) {
2735 case 1:
2736 return MISCREG_PMINTENSET_EL1;
2737 case 2:
2738 return MISCREG_PMINTENCLR_EL1;
2739 }
2740 break;
2741 }
2742 break;
2743 case 3:
2744 switch (crm) {
2745 case 12:
2746 switch (op2) {
2747 case 0:
2748 return MISCREG_PMCR_EL0;
2749 case 1:
2750 return MISCREG_PMCNTENSET_EL0;
2751 case 2:
2752 return MISCREG_PMCNTENCLR_EL0;
2753 case 3:
2754 return MISCREG_PMOVSCLR_EL0;
2755 case 4:
2756 return MISCREG_PMSWINC_EL0;
2757 case 5:
2758 return MISCREG_PMSELR_EL0;
2759 case 6:
2760 return MISCREG_PMCEID0_EL0;
2761 case 7:
2762 return MISCREG_PMCEID1_EL0;
2763 }
2764 break;
2765 case 13:
2766 switch (op2) {
2767 case 0:
2768 return MISCREG_PMCCNTR_EL0;
2769 case 1:
2770 return MISCREG_PMXEVTYPER_EL0;
2771 case 2:
2772 return MISCREG_PMXEVCNTR_EL0;
2773 }
2774 break;
2775 case 14:
2776 switch (op2) {
2777 case 0:
2778 return MISCREG_PMUSERENR_EL0;
2779 case 3:
2780 return MISCREG_PMOVSSET_EL0;
2781 }
2782 break;
2783 }
2784 break;
2785 }
2786 break;
2787 case 10:
2788 switch (op1) {
2789 case 0:
2790 switch (crm) {
2791 case 2:
2792 switch (op2) {
2793 case 0:
2794 return MISCREG_MAIR_EL1;
2795 }
2796 break;
2797 case 3:
2798 switch (op2) {
2799 case 0:
2800 return MISCREG_AMAIR_EL1;
2801 }
2802 break;
2803 }
2804 break;
2805 case 4:
2806 switch (crm) {
2807 case 2:
2808 switch (op2) {
2809 case 0:
2810 return MISCREG_MAIR_EL2;
2811 }
2812 break;
2813 case 3:
2814 switch (op2) {
2815 case 0:
2816 return MISCREG_AMAIR_EL2;
2817 }
2818 break;
2819 }
2820 break;
2821 case 5:
2822 switch (crm) {
2823 case 2:
2824 switch (op2) {
2825 case 0:
2826 return MISCREG_MAIR_EL12;
2827 }
2828 break;
2829 case 3:
2830 switch (op2) {
2831 case 0:
2832 return MISCREG_AMAIR_EL12;
2833 }
2834 break;
2835 }
2836 break;
2837 case 6:
2838 switch (crm) {
2839 case 2:
2840 switch (op2) {
2841 case 0:
2842 return MISCREG_MAIR_EL3;
2843 }
2844 break;
2845 case 3:
2846 switch (op2) {
2847 case 0:
2848 return MISCREG_AMAIR_EL3;
2849 }
2850 break;
2851 }
2852 break;
2853 }
2854 break;
2855 case 11:
2856 switch (op1) {
2857 case 1:
2858 switch (crm) {
2859 case 0:
2860 switch (op2) {
2861 case 2:
2862 return MISCREG_L2CTLR_EL1;
2863 case 3:
2864 return MISCREG_L2ECTLR_EL1;
2865 }
2866 break;
2867 }
2868 M5_FALLTHROUGH;
2869 default:
2870 // S3_<op1>_11_<Cm>_<op2>
2871 return MISCREG_IMPDEF_UNIMPL;
2872 }
2873 M5_UNREACHABLE;
2874 case 12:
2875 switch (op1) {
2876 case 0:
2877 switch (crm) {
2878 case 0:
2879 switch (op2) {
2880 case 0:
2881 return MISCREG_VBAR_EL1;
2882 case 1:
2883 return MISCREG_RVBAR_EL1;
2884 }
2885 break;
2886 case 1:
2887 switch (op2) {
2888 case 0:
2889 return MISCREG_ISR_EL1;
2890 case 1:
2891 return MISCREG_DISR_EL1;
2892 }
2893 break;
2894 case 8:
2895 switch (op2) {
2896 case 0:
2897 return MISCREG_ICC_IAR0_EL1;
2898 case 1:
2899 return MISCREG_ICC_EOIR0_EL1;
2900 case 2:
2901 return MISCREG_ICC_HPPIR0_EL1;
2902 case 3:
2903 return MISCREG_ICC_BPR0_EL1;
2904 case 4:
2905 return MISCREG_ICC_AP0R0_EL1;
2906 case 5:
2907 return MISCREG_ICC_AP0R1_EL1;
2908 case 6:
2909 return MISCREG_ICC_AP0R2_EL1;
2910 case 7:
2911 return MISCREG_ICC_AP0R3_EL1;
2912 }
2913 break;
2914 case 9:
2915 switch (op2) {
2916 case 0:
2917 return MISCREG_ICC_AP1R0_EL1;
2918 case 1:
2919 return MISCREG_ICC_AP1R1_EL1;
2920 case 2:
2921 return MISCREG_ICC_AP1R2_EL1;
2922 case 3:
2923 return MISCREG_ICC_AP1R3_EL1;
2924 }
2925 break;
2926 case 11:
2927 switch (op2) {
2928 case 1:
2929 return MISCREG_ICC_DIR_EL1;
2930 case 3:
2931 return MISCREG_ICC_RPR_EL1;
2932 case 5:
2933 return MISCREG_ICC_SGI1R_EL1;
2934 case 6:
2935 return MISCREG_ICC_ASGI1R_EL1;
2936 case 7:
2937 return MISCREG_ICC_SGI0R_EL1;
2938 }
2939 break;
2940 case 12:
2941 switch (op2) {
2942 case 0:
2943 return MISCREG_ICC_IAR1_EL1;
2944 case 1:
2945 return MISCREG_ICC_EOIR1_EL1;
2946 case 2:
2947 return MISCREG_ICC_HPPIR1_EL1;
2948 case 3:
2949 return MISCREG_ICC_BPR1_EL1;
2950 case 4:
2951 return MISCREG_ICC_CTLR_EL1;
2952 case 5:
2953 return MISCREG_ICC_SRE_EL1;
2954 case 6:
2955 return MISCREG_ICC_IGRPEN0_EL1;
2956 case 7:
2957 return MISCREG_ICC_IGRPEN1_EL1;
2958 }
2959 break;
2960 }
2961 break;
2962 case 4:
2963 switch (crm) {
2964 case 0:
2965 switch (op2) {
2966 case 0:
2967 return MISCREG_VBAR_EL2;
2968 case 1:
2969 return MISCREG_RVBAR_EL2;
2970 }
2971 break;
2972 case 1:
2973 switch (op2) {
2974 case 1:
2975 return MISCREG_VDISR_EL2;
2976 }
2977 break;
2978 case 8:
2979 switch (op2) {
2980 case 0:
2981 return MISCREG_ICH_AP0R0_EL2;
2982 case 1:
2983 return MISCREG_ICH_AP0R1_EL2;
2984 case 2:
2985 return MISCREG_ICH_AP0R2_EL2;
2986 case 3:
2987 return MISCREG_ICH_AP0R3_EL2;
2988 }
2989 break;
2990 case 9:
2991 switch (op2) {
2992 case 0:
2993 return MISCREG_ICH_AP1R0_EL2;
2994 case 1:
2995 return MISCREG_ICH_AP1R1_EL2;
2996 case 2:
2997 return MISCREG_ICH_AP1R2_EL2;
2998 case 3:
2999 return MISCREG_ICH_AP1R3_EL2;
3000 case 5:
3001 return MISCREG_ICC_SRE_EL2;
3002 }
3003 break;
3004 case 11:
3005 switch (op2) {
3006 case 0:
3007 return MISCREG_ICH_HCR_EL2;
3008 case 1:
3009 return MISCREG_ICH_VTR_EL2;
3010 case 2:
3011 return MISCREG_ICH_MISR_EL2;
3012 case 3:
3013 return MISCREG_ICH_EISR_EL2;
3014 case 5:
3015 return MISCREG_ICH_ELRSR_EL2;
3016 case 7:
3017 return MISCREG_ICH_VMCR_EL2;
3018 }
3019 break;
3020 case 12:
3021 switch (op2) {
3022 case 0:
3023 return MISCREG_ICH_LR0_EL2;
3024 case 1:
3025 return MISCREG_ICH_LR1_EL2;
3026 case 2:
3027 return MISCREG_ICH_LR2_EL2;
3028 case 3:
3029 return MISCREG_ICH_LR3_EL2;
3030 case 4:
3031 return MISCREG_ICH_LR4_EL2;
3032 case 5:
3033 return MISCREG_ICH_LR5_EL2;
3034 case 6:
3035 return MISCREG_ICH_LR6_EL2;
3036 case 7:
3037 return MISCREG_ICH_LR7_EL2;
3038 }
3039 break;
3040 case 13:
3041 switch (op2) {
3042 case 0:
3043 return MISCREG_ICH_LR8_EL2;
3044 case 1:
3045 return MISCREG_ICH_LR9_EL2;
3046 case 2:
3047 return MISCREG_ICH_LR10_EL2;
3048 case 3:
3049 return MISCREG_ICH_LR11_EL2;
3050 case 4:
3051 return MISCREG_ICH_LR12_EL2;
3052 case 5:
3053 return MISCREG_ICH_LR13_EL2;
3054 case 6:
3055 return MISCREG_ICH_LR14_EL2;
3056 case 7:
3057 return MISCREG_ICH_LR15_EL2;
3058 }
3059 break;
3060 }
3061 break;
3062 case 5:
3063 switch (crm) {
3064 case 0:
3065 switch (op2) {
3066 case 0:
3067 return MISCREG_VBAR_EL12;
3068 }
3069 break;
3070 }
3071 break;
3072 case 6:
3073 switch (crm) {
3074 case 0:
3075 switch (op2) {
3076 case 0:
3077 return MISCREG_VBAR_EL3;
3078 case 1:
3079 return MISCREG_RVBAR_EL3;
3080 case 2:
3081 return MISCREG_RMR_EL3;
3082 }
3083 break;
3084 case 12:
3085 switch (op2) {
3086 case 4:
3087 return MISCREG_ICC_CTLR_EL3;
3088 case 5:
3089 return MISCREG_ICC_SRE_EL3;
3090 case 7:
3091 return MISCREG_ICC_IGRPEN1_EL3;
3092 }
3093 break;
3094 }
3095 break;
3096 }
3097 break;
3098 case 13:
3099 switch (op1) {
3100 case 0:
3101 switch (crm) {
3102 case 0:
3103 switch (op2) {
3104 case 1:
3105 return MISCREG_CONTEXTIDR_EL1;
3106 case 4:
3107 return MISCREG_TPIDR_EL1;
3108 }
3109 break;
3110 }
3111 break;
3112 case 3:
3113 switch (crm) {
3114 case 0:
3115 switch (op2) {
3116 case 2:
3117 return MISCREG_TPIDR_EL0;
3118 case 3:
3119 return MISCREG_TPIDRRO_EL0;
3120 }
3121 break;
3122 }
3123 break;
3124 case 4:
3125 switch (crm) {
3126 case 0:
3127 switch (op2) {
3128 case 1:
3129 return MISCREG_CONTEXTIDR_EL2;
3130 case 2:
3131 return MISCREG_TPIDR_EL2;
3132 }
3133 break;
3134 }
3135 break;
3136 case 5:
3137 switch (crm) {
3138 case 0:
3139 switch (op2) {
3140 case 1:
3141 return MISCREG_CONTEXTIDR_EL12;
3142 }
3143 break;
3144 }
3145 break;
3146 case 6:
3147 switch (crm) {
3148 case 0:
3149 switch (op2) {
3150 case 2:
3151 return MISCREG_TPIDR_EL3;
3152 }
3153 break;
3154 }
3155 break;
3156 }
3157 break;
3158 case 14:
3159 switch (op1) {
3160 case 0:
3161 switch (crm) {
3162 case 1:
3163 switch (op2) {
3164 case 0:
3165 return MISCREG_CNTKCTL_EL1;
3166 }
3167 break;
3168 }
3169 break;
3170 case 3:
3171 switch (crm) {
3172 case 0:
3173 switch (op2) {
3174 case 0:
3175 return MISCREG_CNTFRQ_EL0;
3176 case 1:
3177 return MISCREG_CNTPCT_EL0;
3178 case 2:
3179 return MISCREG_CNTVCT_EL0;
3180 }
3181 break;
3182 case 2:
3183 switch (op2) {
3184 case 0:
3185 return MISCREG_CNTP_TVAL_EL0;
3186 case 1:
3187 return MISCREG_CNTP_CTL_EL0;
3188 case 2:
3189 return MISCREG_CNTP_CVAL_EL0;
3190 }
3191 break;
3192 case 3:
3193 switch (op2) {
3194 case 0:
3195 return MISCREG_CNTV_TVAL_EL0;
3196 case 1:
3197 return MISCREG_CNTV_CTL_EL0;
3198 case 2:
3199 return MISCREG_CNTV_CVAL_EL0;
3200 }
3201 break;
3202 case 8:
3203 switch (op2) {
3204 case 0:
3205 return MISCREG_PMEVCNTR0_EL0;
3206 case 1:
3207 return MISCREG_PMEVCNTR1_EL0;
3208 case 2:
3209 return MISCREG_PMEVCNTR2_EL0;
3210 case 3:
3211 return MISCREG_PMEVCNTR3_EL0;
3212 case 4:
3213 return MISCREG_PMEVCNTR4_EL0;
3214 case 5:
3215 return MISCREG_PMEVCNTR5_EL0;
3216 }
3217 break;
3218 case 12:
3219 switch (op2) {
3220 case 0:
3221 return MISCREG_PMEVTYPER0_EL0;
3222 case 1:
3223 return MISCREG_PMEVTYPER1_EL0;
3224 case 2:
3225 return MISCREG_PMEVTYPER2_EL0;
3226 case 3:
3227 return MISCREG_PMEVTYPER3_EL0;
3228 case 4:
3229 return MISCREG_PMEVTYPER4_EL0;
3230 case 5:
3231 return MISCREG_PMEVTYPER5_EL0;
3232 }
3233 break;
3234 case 15:
3235 switch (op2) {
3236 case 7:
3237 return MISCREG_PMCCFILTR_EL0;
3238 }
3239 }
3240 break;
3241 case 4:
3242 switch (crm) {
3243 case 0:
3244 switch (op2) {
3245 case 3:
3246 return MISCREG_CNTVOFF_EL2;
3247 }
3248 break;
3249 case 1:
3250 switch (op2) {
3251 case 0:
3252 return MISCREG_CNTHCTL_EL2;
3253 }
3254 break;
3255 case 2:
3256 switch (op2) {
3257 case 0:
3258 return MISCREG_CNTHP_TVAL_EL2;
3259 case 1:
3260 return MISCREG_CNTHP_CTL_EL2;
3261 case 2:
3262 return MISCREG_CNTHP_CVAL_EL2;
3263 }
3264 break;
3265 case 3:
3266 switch (op2) {
3267 case 0:
3268 return MISCREG_CNTHV_TVAL_EL2;
3269 case 1:
3270 return MISCREG_CNTHV_CTL_EL2;
3271 case 2:
3272 return MISCREG_CNTHV_CVAL_EL2;
3273 }
3274 break;
3275 }
3276 break;
3277 case 5:
3278 switch (crm) {
3279 case 1:
3280 switch (op2) {
3281 case 0:
3282 return MISCREG_CNTKCTL_EL12;
3283 }
3284 break;
3285 case 2:
3286 switch (op2) {
3287 case 0:
3288 return MISCREG_CNTP_TVAL_EL02;
3289 case 1:
3290 return MISCREG_CNTP_CTL_EL02;
3291 case 2:
3292 return MISCREG_CNTP_CVAL_EL02;
3293 }
3294 break;
3295 case 3:
3296 switch (op2) {
3297 case 0:
3298 return MISCREG_CNTV_TVAL_EL02;
3299 case 1:
3300 return MISCREG_CNTV_CTL_EL02;
3301 case 2:
3302 return MISCREG_CNTV_CVAL_EL02;
3303 }
3304 break;
3305 }
3306 break;
3307 case 7:
3308 switch (crm) {
3309 case 2:
3310 switch (op2) {
3311 case 0:
3312 return MISCREG_CNTPS_TVAL_EL1;
3313 case 1:
3314 return MISCREG_CNTPS_CTL_EL1;
3315 case 2:
3316 return MISCREG_CNTPS_CVAL_EL1;
3317 }
3318 break;
3319 }
3320 break;
3321 }
3322 break;
3323 case 15:
3324 switch (op1) {
3325 case 0:
3326 switch (crm) {
3327 case 0:
3328 switch (op2) {
3329 case 0:
3330 return MISCREG_IL1DATA0_EL1;
3331 case 1:
3332 return MISCREG_IL1DATA1_EL1;
3333 case 2:
3334 return MISCREG_IL1DATA2_EL1;
3335 case 3:
3336 return MISCREG_IL1DATA3_EL1;
3337 }
3338 break;
3339 case 1:
3340 switch (op2) {
3341 case 0:
3342 return MISCREG_DL1DATA0_EL1;
3343 case 1:
3344 return MISCREG_DL1DATA1_EL1;
3345 case 2:
3346 return MISCREG_DL1DATA2_EL1;
3347 case 3:
3348 return MISCREG_DL1DATA3_EL1;
3349 case 4:
3350 return MISCREG_DL1DATA4_EL1;
3351 }
3352 break;
3353 }
3354 break;
3355 case 1:
3356 switch (crm) {
3357 case 0:
3358 switch (op2) {
3359 case 0:
3360 return MISCREG_L2ACTLR_EL1;
3361 }
3362 break;
3363 case 2:
3364 switch (op2) {
3365 case 0:
3366 return MISCREG_CPUACTLR_EL1;
3367 case 1:
3368 return MISCREG_CPUECTLR_EL1;
3369 case 2:
3370 return MISCREG_CPUMERRSR_EL1;
3371 case 3:
3372 return MISCREG_L2MERRSR_EL1;
3373 }
3374 break;
3375 case 3:
3376 switch (op2) {
3377 case 0:
3378 return MISCREG_CBAR_EL1;
3379
3380 }
3381 break;
3382 }
3383 break;
3384 }
3385 // S3_<op1>_15_<Cm>_<op2>
3386 return MISCREG_IMPDEF_UNIMPL;
3387 }
3388 break;
3389 }
3390
3391 return MISCREG_UNKNOWN;
3392 }
3393
3394 std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below
3395
3396 void
3397 ISA::initializeMiscRegMetadata()
3398 {
3399 // the MiscReg metadata tables are shared across all instances of the
3400 // ISA object, so there's no need to initialize them multiple times.
3401 static bool completed = false;
3402 if (completed)
3403 return;
3404
3405 // This boolean variable specifies if the system is running in aarch32 at
3406 // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
3407 // is running in aarch64 (aarch32EL3 = false)
3408 bool aarch32EL3 = haveSecurity && !highestELIs64;
3409
3410 // Set Privileged Access Never on taking an exception to EL1 (Arm 8.1+),
3411 // unsupported
3412 bool SPAN = false;
3413
3414 // Implicit error synchronization event enable (Arm 8.2+), unsupported
3415 bool IESB = false;
3416
3417 // Load Multiple and Store Multiple Atomicity and Ordering (Arm 8.2+),
3418 // unsupported
3419 bool LSMAOE = false;
3420
3421 // No Trap Load Multiple and Store Multiple (Arm 8.2+), unsupported
3422 bool nTLSMD = false;
3423
3424 // Pointer authentication (Arm 8.3+), unsupported
3425 bool EnDA = true; // using APDAKey_EL1 key of instr addrs in ELs 0,1
3426 bool EnDB = true; // using APDBKey_EL1 key of instr addrs in ELs 0,1
3427 bool EnIA = true; // using APIAKey_EL1 key of instr addrs in ELs 0,1
3428 bool EnIB = true; // using APIBKey_EL1 key of instr addrs in ELs 0,1
3429
3430 /**
3431 * Some registers alias with others, and therefore need to be translated.
3432 * When two mapping registers are given, they are the 32b lower and
3433 * upper halves, respectively, of the 64b register being mapped.
3434 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
3435 *
3436 * NAM = "not architecturally mandated",
3437 * from ARM DDI 0487A.i, template text
3438 * "AArch64 System register ___ can be mapped to
3439 * AArch32 System register ___, but this is not
3440 * architecturally mandated."
3441 */
3442
3443 InitReg(MISCREG_CPSR)
3444 .allPrivileges();
3445 InitReg(MISCREG_SPSR)
3446 .allPrivileges();
3447 InitReg(MISCREG_SPSR_FIQ)
3448 .allPrivileges();
3449 InitReg(MISCREG_SPSR_IRQ)
3450 .allPrivileges();
3451 InitReg(MISCREG_SPSR_SVC)
3452 .allPrivileges();
3453 InitReg(MISCREG_SPSR_MON)
3454 .allPrivileges();
3455 InitReg(MISCREG_SPSR_ABT)
3456 .allPrivileges();
3457 InitReg(MISCREG_SPSR_HYP)
3458 .allPrivileges();
3459 InitReg(MISCREG_SPSR_UND)
3460 .allPrivileges();
3461 InitReg(MISCREG_ELR_HYP)
3462 .allPrivileges();
3463 InitReg(MISCREG_FPSID)
3464 .allPrivileges();
3465 InitReg(MISCREG_FPSCR)
3466 .allPrivileges();
3467 InitReg(MISCREG_MVFR1)
3468 .allPrivileges();
3469 InitReg(MISCREG_MVFR0)
3470 .allPrivileges();
3471 InitReg(MISCREG_FPEXC)
3472 .allPrivileges();
3473
3474 // Helper registers
3475 InitReg(MISCREG_CPSR_MODE)
3476 .allPrivileges();
3477 InitReg(MISCREG_CPSR_Q)
3478 .allPrivileges();
3479 InitReg(MISCREG_FPSCR_EXC)
3480 .allPrivileges();
3481 InitReg(MISCREG_FPSCR_QC)
3482 .allPrivileges();
3483 InitReg(MISCREG_LOCKADDR)
3484 .allPrivileges();
3485 InitReg(MISCREG_LOCKFLAG)
3486 .allPrivileges();
3487 InitReg(MISCREG_PRRR_MAIR0)
3488 .mutex()
3489 .banked();
3490 InitReg(MISCREG_PRRR_MAIR0_NS)
3491 .mutex()
3492 .privSecure(!aarch32EL3)
3493 .bankedChild();
3494 InitReg(MISCREG_PRRR_MAIR0_S)
3495 .mutex()
3496 .bankedChild();
3497 InitReg(MISCREG_NMRR_MAIR1)
3498 .mutex()
3499 .banked();
3500 InitReg(MISCREG_NMRR_MAIR1_NS)
3501 .mutex()
3502 .privSecure(!aarch32EL3)
3503 .bankedChild();
3504 InitReg(MISCREG_NMRR_MAIR1_S)
3505 .mutex()
3506 .bankedChild();
3507 InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
3508 .mutex();
3509 InitReg(MISCREG_SCTLR_RST)
3510 .allPrivileges();
3511 InitReg(MISCREG_SEV_MAILBOX)
3512 .allPrivileges();
3513
3514 // AArch32 CP14 registers
3515 InitReg(MISCREG_DBGDIDR)
3516 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3517 InitReg(MISCREG_DBGDSCRint)
3518 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3519 InitReg(MISCREG_DBGDCCINT)
3520 .unimplemented()
3521 .allPrivileges();
3522 InitReg(MISCREG_DBGDTRTXint)
3523 .unimplemented()
3524 .allPrivileges();
3525 InitReg(MISCREG_DBGDTRRXint)
3526 .unimplemented()
3527 .allPrivileges();
3528 InitReg(MISCREG_DBGWFAR)
3529 .unimplemented()
3530 .allPrivileges();
3531 InitReg(MISCREG_DBGVCR)
3532 .allPrivileges().exceptUserMode();
3533 InitReg(MISCREG_DBGDTRRXext)
3534 .unimplemented()
3535 .allPrivileges();
3536 InitReg(MISCREG_DBGDSCRext)
3537 .allPrivileges();
3538 InitReg(MISCREG_DBGDTRTXext)
3539 .unimplemented()
3540 .allPrivileges();
3541 InitReg(MISCREG_DBGOSECCR)
3542 .unimplemented()
3543 .allPrivileges();
3544 InitReg(MISCREG_DBGBVR0)
3545 .allPrivileges().exceptUserMode();
3546 InitReg(MISCREG_DBGBVR1)
3547 .allPrivileges().exceptUserMode();
3548 InitReg(MISCREG_DBGBVR2)
3549 .allPrivileges().exceptUserMode();
3550 InitReg(MISCREG_DBGBVR3)
3551 .allPrivileges().exceptUserMode();
3552 InitReg(MISCREG_DBGBVR4)
3553 .allPrivileges().exceptUserMode();
3554 InitReg(MISCREG_DBGBVR5)
3555 .allPrivileges().exceptUserMode();
3556 InitReg(MISCREG_DBGBVR6)
3557 .allPrivileges().exceptUserMode();
3558 InitReg(MISCREG_DBGBVR7)
3559 .allPrivileges().exceptUserMode();
3560 InitReg(MISCREG_DBGBVR8)
3561 .allPrivileges().exceptUserMode();
3562 InitReg(MISCREG_DBGBVR9)
3563 .allPrivileges().exceptUserMode();
3564 InitReg(MISCREG_DBGBVR10)
3565 .allPrivileges().exceptUserMode();
3566 InitReg(MISCREG_DBGBVR11)
3567 .allPrivileges().exceptUserMode();
3568 InitReg(MISCREG_DBGBVR12)
3569 .allPrivileges().exceptUserMode();
3570 InitReg(MISCREG_DBGBVR13)
3571 .allPrivileges().exceptUserMode();
3572 InitReg(MISCREG_DBGBVR14)
3573 .allPrivileges().exceptUserMode();
3574 InitReg(MISCREG_DBGBVR15)
3575 .allPrivileges().exceptUserMode();
3576 InitReg(MISCREG_DBGBCR0)
3577 .allPrivileges().exceptUserMode();
3578 InitReg(MISCREG_DBGBCR1)
3579 .allPrivileges().exceptUserMode();
3580 InitReg(MISCREG_DBGBCR2)
3581 .allPrivileges().exceptUserMode();
3582 InitReg(MISCREG_DBGBCR3)
3583 .allPrivileges().exceptUserMode();
3584 InitReg(MISCREG_DBGBCR4)
3585 .allPrivileges().exceptUserMode();
3586 InitReg(MISCREG_DBGBCR5)
3587 .allPrivileges().exceptUserMode();
3588 InitReg(MISCREG_DBGBCR6)
3589 .allPrivileges().exceptUserMode();
3590 InitReg(MISCREG_DBGBCR7)
3591 .allPrivileges().exceptUserMode();
3592 InitReg(MISCREG_DBGBCR8)
3593 .allPrivileges().exceptUserMode();
3594 InitReg(MISCREG_DBGBCR9)
3595 .allPrivileges().exceptUserMode();
3596 InitReg(MISCREG_DBGBCR10)
3597 .allPrivileges().exceptUserMode();
3598 InitReg(MISCREG_DBGBCR11)
3599 .allPrivileges().exceptUserMode();
3600 InitReg(MISCREG_DBGBCR12)
3601 .allPrivileges().exceptUserMode();
3602 InitReg(MISCREG_DBGBCR13)
3603 .allPrivileges().exceptUserMode();
3604 InitReg(MISCREG_DBGBCR14)
3605 .allPrivileges().exceptUserMode();
3606 InitReg(MISCREG_DBGBCR15)
3607 .allPrivileges().exceptUserMode();
3608 InitReg(MISCREG_DBGWVR0)
3609 .allPrivileges().exceptUserMode();
3610 InitReg(MISCREG_DBGWVR1)
3611 .allPrivileges().exceptUserMode();
3612 InitReg(MISCREG_DBGWVR2)
3613 .allPrivileges().exceptUserMode();
3614 InitReg(MISCREG_DBGWVR3)
3615 .allPrivileges().exceptUserMode();
3616 InitReg(MISCREG_DBGWVR4)
3617 .allPrivileges().exceptUserMode();
3618 InitReg(MISCREG_DBGWVR5)
3619 .allPrivileges().exceptUserMode();
3620 InitReg(MISCREG_DBGWVR6)
3621 .allPrivileges().exceptUserMode();
3622 InitReg(MISCREG_DBGWVR7)
3623 .allPrivileges().exceptUserMode();
3624 InitReg(MISCREG_DBGWVR8)
3625 .allPrivileges().exceptUserMode();
3626 InitReg(MISCREG_DBGWVR9)
3627 .allPrivileges().exceptUserMode();
3628 InitReg(MISCREG_DBGWVR10)
3629 .allPrivileges().exceptUserMode();
3630 InitReg(MISCREG_DBGWVR11)
3631 .allPrivileges().exceptUserMode();
3632 InitReg(MISCREG_DBGWVR12)
3633 .allPrivileges().exceptUserMode();
3634 InitReg(MISCREG_DBGWVR13)
3635 .allPrivileges().exceptUserMode();
3636 InitReg(MISCREG_DBGWVR14)
3637 .allPrivileges().exceptUserMode();
3638 InitReg(MISCREG_DBGWVR15)
3639 .allPrivileges().exceptUserMode();
3640 InitReg(MISCREG_DBGWCR0)
3641 .allPrivileges().exceptUserMode();
3642 InitReg(MISCREG_DBGWCR1)
3643 .allPrivileges().exceptUserMode();
3644 InitReg(MISCREG_DBGWCR2)
3645 .allPrivileges().exceptUserMode();
3646 InitReg(MISCREG_DBGWCR3)
3647 .allPrivileges().exceptUserMode();
3648 InitReg(MISCREG_DBGWCR4)
3649 .allPrivileges().exceptUserMode();
3650 InitReg(MISCREG_DBGWCR5)
3651 .allPrivileges().exceptUserMode();
3652 InitReg(MISCREG_DBGWCR6)
3653 .allPrivileges().exceptUserMode();
3654 InitReg(MISCREG_DBGWCR7)
3655 .allPrivileges().exceptUserMode();
3656 InitReg(MISCREG_DBGWCR8)
3657 .allPrivileges().exceptUserMode();
3658 InitReg(MISCREG_DBGWCR9)
3659 .allPrivileges().exceptUserMode();
3660 InitReg(MISCREG_DBGWCR10)
3661 .allPrivileges().exceptUserMode();
3662 InitReg(MISCREG_DBGWCR11)
3663 .allPrivileges().exceptUserMode();
3664 InitReg(MISCREG_DBGWCR12)
3665 .allPrivileges().exceptUserMode();
3666 InitReg(MISCREG_DBGWCR13)
3667 .allPrivileges().exceptUserMode();
3668 InitReg(MISCREG_DBGWCR14)
3669 .allPrivileges().exceptUserMode();
3670 InitReg(MISCREG_DBGWCR15)
3671 .allPrivileges().exceptUserMode();
3672 InitReg(MISCREG_DBGDRAR)
3673 .unimplemented()
3674 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3675 InitReg(MISCREG_DBGBXVR0)
3676 .allPrivileges().exceptUserMode();
3677 InitReg(MISCREG_DBGBXVR1)
3678 .allPrivileges().exceptUserMode();
3679 InitReg(MISCREG_DBGBXVR2)
3680 .allPrivileges().exceptUserMode();
3681 InitReg(MISCREG_DBGBXVR3)
3682 .allPrivileges().exceptUserMode();
3683 InitReg(MISCREG_DBGBXVR4)
3684 .allPrivileges().exceptUserMode();
3685 InitReg(MISCREG_DBGBXVR5)
3686 .allPrivileges().exceptUserMode();
3687 InitReg(MISCREG_DBGBXVR0)
3688 .allPrivileges().exceptUserMode();
3689 InitReg(MISCREG_DBGBXVR6)
3690 .allPrivileges().exceptUserMode();
3691 InitReg(MISCREG_DBGBXVR7)
3692 .allPrivileges().exceptUserMode();
3693 InitReg(MISCREG_DBGBXVR8)
3694 .allPrivileges().exceptUserMode();
3695 InitReg(MISCREG_DBGBXVR9)
3696 .allPrivileges().exceptUserMode();
3697 InitReg(MISCREG_DBGBXVR10)
3698 .allPrivileges().exceptUserMode();
3699 InitReg(MISCREG_DBGBXVR11)
3700 .allPrivileges().exceptUserMode();
3701 InitReg(MISCREG_DBGBXVR12)
3702 .allPrivileges().exceptUserMode();
3703 InitReg(MISCREG_DBGBXVR13)
3704 .allPrivileges().exceptUserMode();
3705 InitReg(MISCREG_DBGBXVR14)
3706 .allPrivileges().exceptUserMode();
3707 InitReg(MISCREG_DBGBXVR15)
3708 .allPrivileges().exceptUserMode();
3709 InitReg(MISCREG_DBGOSLAR)
3710 .allPrivileges().monSecureRead(0).monNonSecureRead(0);
3711 InitReg(MISCREG_DBGOSLSR)
3712 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3713 InitReg(MISCREG_DBGOSDLR)
3714 .unimplemented()
3715 .warnNotFail()
3716 .allPrivileges();
3717 InitReg(MISCREG_DBGPRCR)
3718 .unimplemented()
3719 .allPrivileges();
3720 InitReg(MISCREG_DBGDSAR)
3721 .unimplemented()
3722 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3723 InitReg(MISCREG_DBGCLAIMSET)
3724 .unimplemented()
3725 .allPrivileges();
3726 InitReg(MISCREG_DBGCLAIMCLR)
3727 .unimplemented()
3728 .allPrivileges();
3729 InitReg(MISCREG_DBGAUTHSTATUS)
3730 .unimplemented()
3731 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3732 InitReg(MISCREG_DBGDEVID2)
3733 .unimplemented()
3734 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3735 InitReg(MISCREG_DBGDEVID1)
3736 .unimplemented()
3737 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3738 InitReg(MISCREG_DBGDEVID0)
3739 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3740 InitReg(MISCREG_TEECR)
3741 .unimplemented()
3742 .allPrivileges();
3743 InitReg(MISCREG_JIDR)
3744 .allPrivileges();
3745 InitReg(MISCREG_TEEHBR)
3746 .allPrivileges();
3747 InitReg(MISCREG_JOSCR)
3748 .allPrivileges();
3749 InitReg(MISCREG_JMCR)
3750 .allPrivileges();
3751
3752 // AArch32 CP15 registers
3753 InitReg(MISCREG_MIDR)
3754 .allPrivileges().exceptUserMode().writes(0);
3755 InitReg(MISCREG_CTR)
3756 .allPrivileges().exceptUserMode().writes(0);
3757 InitReg(MISCREG_TCMTR)
3758 .allPrivileges().exceptUserMode().writes(0);
3759 InitReg(MISCREG_TLBTR)
3760 .allPrivileges().exceptUserMode().writes(0);
3761 InitReg(MISCREG_MPIDR)
3762 .allPrivileges().exceptUserMode().writes(0);
3763 InitReg(MISCREG_REVIDR)
3764 .unimplemented()
3765 .warnNotFail()
3766 .allPrivileges().exceptUserMode().writes(0);
3767 InitReg(MISCREG_ID_PFR0)
3768 .allPrivileges().exceptUserMode().writes(0);
3769 InitReg(MISCREG_ID_PFR1)
3770 .allPrivileges().exceptUserMode().writes(0);
3771 InitReg(MISCREG_ID_DFR0)
3772 .allPrivileges().exceptUserMode().writes(0);
3773 InitReg(MISCREG_ID_AFR0)
3774 .allPrivileges().exceptUserMode().writes(0);
3775 InitReg(MISCREG_ID_MMFR0)
3776 .allPrivileges().exceptUserMode().writes(0);
3777 InitReg(MISCREG_ID_MMFR1)
3778 .allPrivileges().exceptUserMode().writes(0);
3779 InitReg(MISCREG_ID_MMFR2)
3780 .allPrivileges().exceptUserMode().writes(0);
3781 InitReg(MISCREG_ID_MMFR3)
3782 .allPrivileges().exceptUserMode().writes(0);
3783 InitReg(MISCREG_ID_MMFR4)
3784 .allPrivileges().exceptUserMode().writes(0);
3785 InitReg(MISCREG_ID_ISAR0)
3786 .allPrivileges().exceptUserMode().writes(0);
3787 InitReg(MISCREG_ID_ISAR1)
3788 .allPrivileges().exceptUserMode().writes(0);
3789 InitReg(MISCREG_ID_ISAR2)
3790 .allPrivileges().exceptUserMode().writes(0);
3791 InitReg(MISCREG_ID_ISAR3)
3792 .allPrivileges().exceptUserMode().writes(0);
3793 InitReg(MISCREG_ID_ISAR4)
3794 .allPrivileges().exceptUserMode().writes(0);
3795 InitReg(MISCREG_ID_ISAR5)
3796 .allPrivileges().exceptUserMode().writes(0);
3797 InitReg(MISCREG_ID_ISAR6)
3798 .allPrivileges().exceptUserMode().writes(0);
3799 InitReg(MISCREG_CCSIDR)
3800 .allPrivileges().exceptUserMode().writes(0);
3801 InitReg(MISCREG_CLIDR)
3802 .allPrivileges().exceptUserMode().writes(0);
3803 InitReg(MISCREG_AIDR)
3804 .allPrivileges().exceptUserMode().writes(0);
3805 InitReg(MISCREG_CSSELR)
3806 .banked();
3807 InitReg(MISCREG_CSSELR_NS)
3808 .bankedChild()
3809 .privSecure(!aarch32EL3)
3810 .nonSecure().exceptUserMode();
3811 InitReg(MISCREG_CSSELR_S)
3812 .bankedChild()
3813 .secure().exceptUserMode();
3814 InitReg(MISCREG_VPIDR)
3815 .hyp().monNonSecure();
3816 InitReg(MISCREG_VMPIDR)
3817 .hyp().monNonSecure();
3818 InitReg(MISCREG_SCTLR)
3819 .banked()
3820 // readMiscRegNoEffect() uses this metadata
3821 // despite using children (below) as backing store
3822 .res0(0x8d22c600)
3823 .res1(0x00400800 | (SPAN ? 0 : 0x800000)
3824 | (LSMAOE ? 0 : 0x10)
3825 | (nTLSMD ? 0 : 0x8));
3826 InitReg(MISCREG_SCTLR_NS)
3827 .bankedChild()
3828 .privSecure(!aarch32EL3)
3829 .nonSecure().exceptUserMode();
3830 InitReg(MISCREG_SCTLR_S)
3831 .bankedChild()
3832 .secure().exceptUserMode();
3833 InitReg(MISCREG_ACTLR)
3834 .banked();
3835 InitReg(MISCREG_ACTLR_NS)
3836 .bankedChild()
3837 .privSecure(!aarch32EL3)
3838 .nonSecure().exceptUserMode();
3839 InitReg(MISCREG_ACTLR_S)
3840 .bankedChild()
3841 .secure().exceptUserMode();
3842 InitReg(MISCREG_CPACR)
3843 .allPrivileges().exceptUserMode();
3844 InitReg(MISCREG_SDCR)
3845 .mon();
3846 InitReg(MISCREG_SCR)
3847 .mon().secure().exceptUserMode()
3848 .res0(0xff40) // [31:16], [6]
3849 .res1(0x0030); // [5:4]
3850 InitReg(MISCREG_SDER)
3851 .mon();
3852 InitReg(MISCREG_NSACR)
3853 .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
3854 InitReg(MISCREG_HSCTLR)
3855 .hyp().monNonSecure()
3856 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
3857 | (IESB ? 0 : 0x200000)
3858 | (EnDA ? 0 : 0x8000000)
3859 | (EnIB ? 0 : 0x40000000)
3860 | (EnIA ? 0 : 0x80000000))
3861 .res1(0x30c50830);
3862 InitReg(MISCREG_HACTLR)
3863 .hyp().monNonSecure();
3864 InitReg(MISCREG_HCR)
3865 .hyp().monNonSecure()
3866 .res0(0x90000000);
3867 InitReg(MISCREG_HCR2)
3868 .hyp().monNonSecure()
3869 .res0(0xffa9ff8c);
3870 InitReg(MISCREG_HDCR)
3871 .hyp().monNonSecure();
3872 InitReg(MISCREG_HCPTR)
3873 .hyp().monNonSecure();
3874 InitReg(MISCREG_HSTR)
3875 .hyp().monNonSecure();
3876 InitReg(MISCREG_HACR)
3877 .unimplemented()
3878 .warnNotFail()
3879 .hyp().monNonSecure();
3880 InitReg(MISCREG_TTBR0)
3881 .banked();
3882 InitReg(MISCREG_TTBR0_NS)
3883 .bankedChild()
3884 .privSecure(!aarch32EL3)
3885 .nonSecure().exceptUserMode();
3886 InitReg(MISCREG_TTBR0_S)
3887 .bankedChild()
3888 .secure().exceptUserMode();
3889 InitReg(MISCREG_TTBR1)
3890 .banked();
3891 InitReg(MISCREG_TTBR1_NS)
3892 .bankedChild()
3893 .privSecure(!aarch32EL3)
3894 .nonSecure().exceptUserMode();
3895 InitReg(MISCREG_TTBR1_S)
3896 .bankedChild()
3897 .secure().exceptUserMode();
3898 InitReg(MISCREG_TTBCR)
3899 .banked();
3900 InitReg(MISCREG_TTBCR_NS)
3901 .bankedChild()
3902 .privSecure(!aarch32EL3)
3903 .nonSecure().exceptUserMode();
3904 InitReg(MISCREG_TTBCR_S)
3905 .bankedChild()
3906 .secure().exceptUserMode();
3907 InitReg(MISCREG_HTCR)
3908 .hyp().monNonSecure();
3909 InitReg(MISCREG_VTCR)
3910 .hyp().monNonSecure();
3911 InitReg(MISCREG_DACR)
3912 .banked();
3913 InitReg(MISCREG_DACR_NS)
3914 .bankedChild()
3915 .privSecure(!aarch32EL3)
3916 .nonSecure().exceptUserMode();
3917 InitReg(MISCREG_DACR_S)
3918 .bankedChild()
3919 .secure().exceptUserMode();
3920 InitReg(MISCREG_DFSR)
3921 .banked();
3922 InitReg(MISCREG_DFSR_NS)
3923 .bankedChild()
3924 .privSecure(!aarch32EL3)
3925 .nonSecure().exceptUserMode();
3926 InitReg(MISCREG_DFSR_S)
3927 .bankedChild()
3928 .secure().exceptUserMode();
3929 InitReg(MISCREG_IFSR)
3930 .banked();
3931 InitReg(MISCREG_IFSR_NS)
3932 .bankedChild()
3933 .privSecure(!aarch32EL3)
3934 .nonSecure().exceptUserMode();
3935 InitReg(MISCREG_IFSR_S)
3936 .bankedChild()
3937 .secure().exceptUserMode();
3938 InitReg(MISCREG_ADFSR)
3939 .unimplemented()
3940 .warnNotFail()
3941 .banked();
3942 InitReg(MISCREG_ADFSR_NS)
3943 .unimplemented()
3944 .warnNotFail()
3945 .bankedChild()
3946 .privSecure(!aarch32EL3)
3947 .nonSecure().exceptUserMode();
3948 InitReg(MISCREG_ADFSR_S)
3949 .unimplemented()
3950 .warnNotFail()
3951 .bankedChild()
3952 .secure().exceptUserMode();
3953 InitReg(MISCREG_AIFSR)
3954 .unimplemented()
3955 .warnNotFail()
3956 .banked();
3957 InitReg(MISCREG_AIFSR_NS)
3958 .unimplemented()
3959 .warnNotFail()
3960 .bankedChild()
3961 .privSecure(!aarch32EL3)
3962 .nonSecure().exceptUserMode();
3963 InitReg(MISCREG_AIFSR_S)
3964 .unimplemented()
3965 .warnNotFail()
3966 .bankedChild()
3967 .secure().exceptUserMode();
3968 InitReg(MISCREG_HADFSR)
3969 .hyp().monNonSecure();
3970 InitReg(MISCREG_HAIFSR)
3971 .hyp().monNonSecure();
3972 InitReg(MISCREG_HSR)
3973 .hyp().monNonSecure();
3974 InitReg(MISCREG_DFAR)
3975 .banked();
3976 InitReg(MISCREG_DFAR_NS)
3977 .bankedChild()
3978 .privSecure(!aarch32EL3)
3979 .nonSecure().exceptUserMode();
3980 InitReg(MISCREG_DFAR_S)
3981 .bankedChild()
3982 .secure().exceptUserMode();
3983 InitReg(MISCREG_IFAR)
3984 .banked();
3985 InitReg(MISCREG_IFAR_NS)
3986 .bankedChild()
3987 .privSecure(!aarch32EL3)
3988 .nonSecure().exceptUserMode();
3989 InitReg(MISCREG_IFAR_S)
3990 .bankedChild()
3991 .secure().exceptUserMode();
3992 InitReg(MISCREG_HDFAR)
3993 .hyp().monNonSecure();
3994 InitReg(MISCREG_HIFAR)
3995 .hyp().monNonSecure();
3996 InitReg(MISCREG_HPFAR)
3997 .hyp().monNonSecure();
3998 InitReg(MISCREG_ICIALLUIS)
3999 .unimplemented()
4000 .warnNotFail()
4001 .writes(1).exceptUserMode();
4002 InitReg(MISCREG_BPIALLIS)
4003 .unimplemented()
4004 .warnNotFail()
4005 .writes(1).exceptUserMode();
4006 InitReg(MISCREG_PAR)
4007 .banked();
4008 InitReg(MISCREG_PAR_NS)
4009 .bankedChild()
4010 .privSecure(!aarch32EL3)
4011 .nonSecure().exceptUserMode();
4012 InitReg(MISCREG_PAR_S)
4013 .bankedChild()
4014 .secure().exceptUserMode();
4015 InitReg(MISCREG_ICIALLU)
4016 .writes(1).exceptUserMode();
4017 InitReg(MISCREG_ICIMVAU)
4018 .unimplemented()
4019 .warnNotFail()
4020 .writes(1).exceptUserMode();
4021 InitReg(MISCREG_CP15ISB)
4022 .writes(1);
4023 InitReg(MISCREG_BPIALL)
4024 .unimplemented()
4025 .warnNotFail()
4026 .writes(1).exceptUserMode();
4027 InitReg(MISCREG_BPIMVA)
4028 .unimplemented()
4029 .warnNotFail()
4030 .writes(1).exceptUserMode();
4031 InitReg(MISCREG_DCIMVAC)
4032 .unimplemented()
4033 .warnNotFail()
4034 .writes(1).exceptUserMode();
4035 InitReg(MISCREG_DCISW)
4036 .unimplemented()
4037 .warnNotFail()
4038 .writes(1).exceptUserMode();
4039 InitReg(MISCREG_ATS1CPR)
4040 .writes(1).exceptUserMode();
4041 InitReg(MISCREG_ATS1CPW)
4042 .writes(1).exceptUserMode();
4043 InitReg(MISCREG_ATS1CUR)
4044 .writes(1).exceptUserMode();
4045 InitReg(MISCREG_ATS1CUW)
4046 .writes(1).exceptUserMode();
4047 InitReg(MISCREG_ATS12NSOPR)
4048 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
4049 InitReg(MISCREG_ATS12NSOPW)
4050 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
4051 InitReg(MISCREG_ATS12NSOUR)
4052 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
4053 InitReg(MISCREG_ATS12NSOUW)
4054 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
4055 InitReg(MISCREG_DCCMVAC)
4056 .writes(1).exceptUserMode();
4057 InitReg(MISCREG_DCCSW)
4058 .unimplemented()
4059 .warnNotFail()
4060 .writes(1).exceptUserMode();
4061 InitReg(MISCREG_CP15DSB)
4062 .writes(1);
4063 InitReg(MISCREG_CP15DMB)
4064 .writes(1);
4065 InitReg(MISCREG_DCCMVAU)
4066 .unimplemented()
4067 .warnNotFail()
4068 .writes(1).exceptUserMode();
4069 InitReg(MISCREG_DCCIMVAC)
4070 .unimplemented()
4071 .warnNotFail()
4072 .writes(1).exceptUserMode();
4073 InitReg(MISCREG_DCCISW)
4074 .unimplemented()
4075 .warnNotFail()
4076 .writes(1).exceptUserMode();
4077 InitReg(MISCREG_ATS1HR)
4078 .monNonSecureWrite().hypWrite();
4079 InitReg(MISCREG_ATS1HW)
4080 .monNonSecureWrite().hypWrite();
4081 InitReg(MISCREG_TLBIALLIS)
4082 .writes(1).exceptUserMode();
4083 InitReg(MISCREG_TLBIMVAIS)
4084 .writes(1).exceptUserMode();
4085 InitReg(MISCREG_TLBIASIDIS)
4086 .writes(1).exceptUserMode();
4087 InitReg(MISCREG_TLBIMVAAIS)
4088 .writes(1).exceptUserMode();
4089 InitReg(MISCREG_TLBIMVALIS)
4090 .writes(1).exceptUserMode();
4091 InitReg(MISCREG_TLBIMVAALIS)
4092 .writes(1).exceptUserMode();
4093 InitReg(MISCREG_ITLBIALL)
4094 .writes(1).exceptUserMode();
4095 InitReg(MISCREG_ITLBIMVA)
4096 .writes(1).exceptUserMode();
4097 InitReg(MISCREG_ITLBIASID)
4098 .writes(1).exceptUserMode();
4099 InitReg(MISCREG_DTLBIALL)
4100 .writes(1).exceptUserMode();
4101 InitReg(MISCREG_DTLBIMVA)
4102 .writes(1).exceptUserMode();
4103 InitReg(MISCREG_DTLBIASID)
4104 .writes(1).exceptUserMode();
4105 InitReg(MISCREG_TLBIALL)
4106 .writes(1).exceptUserMode();
4107 InitReg(MISCREG_TLBIMVA)
4108 .writes(1).exceptUserMode();
4109 InitReg(MISCREG_TLBIASID)
4110 .writes(1).exceptUserMode();
4111 InitReg(MISCREG_TLBIMVAA)
4112 .writes(1).exceptUserMode();
4113 InitReg(MISCREG_TLBIMVAL)
4114 .writes(1).exceptUserMode();
4115 InitReg(MISCREG_TLBIMVAAL)
4116 .writes(1).exceptUserMode();
4117 InitReg(MISCREG_TLBIIPAS2IS)
4118 .monNonSecureWrite().hypWrite();
4119 InitReg(MISCREG_TLBIIPAS2LIS)
4120 .monNonSecureWrite().hypWrite();
4121 InitReg(MISCREG_TLBIALLHIS)
4122 .monNonSecureWrite().hypWrite();
4123 InitReg(MISCREG_TLBIMVAHIS)
4124 .monNonSecureWrite().hypWrite();
4125 InitReg(MISCREG_TLBIALLNSNHIS)
4126 .monNonSecureWrite().hypWrite();
4127 InitReg(MISCREG_TLBIMVALHIS)
4128 .monNonSecureWrite().hypWrite();
4129 InitReg(MISCREG_TLBIIPAS2)
4130 .monNonSecureWrite().hypWrite();
4131 InitReg(MISCREG_TLBIIPAS2L)
4132 .monNonSecureWrite().hypWrite();
4133 InitReg(MISCREG_TLBIALLH)
4134 .monNonSecureWrite().hypWrite();
4135 InitReg(MISCREG_TLBIMVAH)
4136 .monNonSecureWrite().hypWrite();
4137 InitReg(MISCREG_TLBIALLNSNH)
4138 .monNonSecureWrite().hypWrite();
4139 InitReg(MISCREG_TLBIMVALH)
4140 .monNonSecureWrite().hypWrite();
4141 InitReg(MISCREG_PMCR)
4142 .allPrivileges();
4143 InitReg(MISCREG_PMCNTENSET)
4144 .allPrivileges();
4145 InitReg(MISCREG_PMCNTENCLR)
4146 .allPrivileges();
4147 InitReg(MISCREG_PMOVSR)
4148 .allPrivileges();
4149 InitReg(MISCREG_PMSWINC)
4150 .allPrivileges();
4151 InitReg(MISCREG_PMSELR)
4152 .allPrivileges();
4153 InitReg(MISCREG_PMCEID0)
4154 .allPrivileges();
4155 InitReg(MISCREG_PMCEID1)
4156 .allPrivileges();
4157 InitReg(MISCREG_PMCCNTR)
4158 .allPrivileges();
4159 InitReg(MISCREG_PMXEVTYPER)
4160 .allPrivileges();
4161 InitReg(MISCREG_PMCCFILTR)
4162 .allPrivileges();
4163 InitReg(MISCREG_PMXEVCNTR)
4164 .allPrivileges();
4165 InitReg(MISCREG_PMUSERENR)
4166 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
4167 InitReg(MISCREG_PMINTENSET)
4168 .allPrivileges().exceptUserMode();
4169 InitReg(MISCREG_PMINTENCLR)
4170 .allPrivileges().exceptUserMode();
4171 InitReg(MISCREG_PMOVSSET)
4172 .unimplemented()
4173 .allPrivileges();
4174 InitReg(MISCREG_L2CTLR)
4175 .allPrivileges().exceptUserMode();
4176 InitReg(MISCREG_L2ECTLR)
4177 .unimplemented()
4178 .allPrivileges().exceptUserMode();
4179 InitReg(MISCREG_PRRR)
4180 .banked();
4181 InitReg(MISCREG_PRRR_NS)
4182 .bankedChild()
4183 .privSecure(!aarch32EL3)
4184 .nonSecure().exceptUserMode();
4185 InitReg(MISCREG_PRRR_S)
4186 .bankedChild()
4187 .secure().exceptUserMode();
4188 InitReg(MISCREG_MAIR0)
4189 .banked();
4190 InitReg(MISCREG_MAIR0_NS)
4191 .bankedChild()
4192 .privSecure(!aarch32EL3)
4193 .nonSecure().exceptUserMode();
4194 InitReg(MISCREG_MAIR0_S)
4195 .bankedChild()
4196 .secure().exceptUserMode();
4197 InitReg(MISCREG_NMRR)
4198 .banked();
4199 InitReg(MISCREG_NMRR_NS)
4200 .bankedChild()
4201 .privSecure(!aarch32EL3)
4202 .nonSecure().exceptUserMode();
4203 InitReg(MISCREG_NMRR_S)
4204 .bankedChild()
4205 .secure().exceptUserMode();
4206 InitReg(MISCREG_MAIR1)
4207 .banked();
4208 InitReg(MISCREG_MAIR1_NS)
4209 .bankedChild()
4210 .privSecure(!aarch32EL3)
4211 .nonSecure().exceptUserMode();
4212 InitReg(MISCREG_MAIR1_S)
4213 .bankedChild()
4214 .secure().exceptUserMode();
4215 InitReg(MISCREG_AMAIR0)
4216 .banked();
4217 InitReg(MISCREG_AMAIR0_NS)
4218 .bankedChild()
4219 .privSecure(!aarch32EL3)
4220 .nonSecure().exceptUserMode();
4221 InitReg(MISCREG_AMAIR0_S)
4222 .bankedChild()
4223 .secure().exceptUserMode();
4224 InitReg(MISCREG_AMAIR1)
4225 .banked();
4226 InitReg(MISCREG_AMAIR1_NS)
4227 .bankedChild()
4228 .privSecure(!aarch32EL3)
4229 .nonSecure().exceptUserMode();
4230 InitReg(MISCREG_AMAIR1_S)
4231 .bankedChild()
4232 .secure().exceptUserMode();
4233 InitReg(MISCREG_HMAIR0)
4234 .hyp().monNonSecure();
4235 InitReg(MISCREG_HMAIR1)
4236 .hyp().monNonSecure();
4237 InitReg(MISCREG_HAMAIR0)
4238 .unimplemented()
4239 .warnNotFail()
4240 .hyp().monNonSecure();
4241 InitReg(MISCREG_HAMAIR1)
4242 .unimplemented()
4243 .warnNotFail()
4244 .hyp().monNonSecure();
4245 InitReg(MISCREG_VBAR)
4246 .banked();
4247 InitReg(MISCREG_VBAR_NS)
4248 .bankedChild()
4249 .privSecure(!aarch32EL3)
4250 .nonSecure().exceptUserMode();
4251 InitReg(MISCREG_VBAR_S)
4252 .bankedChild()
4253 .secure().exceptUserMode();
4254 InitReg(MISCREG_MVBAR)
4255 .mon().secure()
4256 .hypRead(FullSystem && system->highestEL() == EL2)
4257 .privRead(FullSystem && system->highestEL() == EL1)
4258 .exceptUserMode();
4259 InitReg(MISCREG_RMR)
4260 .unimplemented()
4261 .mon().secure().exceptUserMode();
4262 InitReg(MISCREG_ISR)
4263 .allPrivileges().exceptUserMode().writes(0);
4264 InitReg(MISCREG_HVBAR)
4265 .hyp().monNonSecure()
4266 .res0(0x1f);
4267 InitReg(MISCREG_FCSEIDR)
4268 .unimplemented()
4269 .warnNotFail()
4270 .allPrivileges().exceptUserMode();
4271 InitReg(MISCREG_CONTEXTIDR)
4272 .banked();
4273 InitReg(MISCREG_CONTEXTIDR_NS)
4274 .bankedChild()
4275 .privSecure(!aarch32EL3)
4276 .nonSecure().exceptUserMode();
4277 InitReg(MISCREG_CONTEXTIDR_S)
4278 .bankedChild()
4279 .secure().exceptUserMode();
4280 InitReg(MISCREG_TPIDRURW)
4281 .banked();
4282 InitReg(MISCREG_TPIDRURW_NS)
4283 .bankedChild()
4284 .allPrivileges()
4285 .privSecure(!aarch32EL3)
4286 .monSecure(0);
4287 InitReg(MISCREG_TPIDRURW_S)
4288 .bankedChild()
4289 .secure();
4290 InitReg(MISCREG_TPIDRURO)
4291 .banked();
4292 InitReg(MISCREG_TPIDRURO_NS)
4293 .bankedChild()
4294 .allPrivileges()
4295 .userNonSecureWrite(0).userSecureRead(1)
4296 .privSecure(!aarch32EL3)
4297 .monSecure(0);
4298 InitReg(MISCREG_TPIDRURO_S)
4299 .bankedChild()
4300 .secure().userSecureWrite(0);
4301 InitReg(MISCREG_TPIDRPRW)
4302 .banked();
4303 InitReg(MISCREG_TPIDRPRW_NS)
4304 .bankedChild()
4305 .nonSecure().exceptUserMode()
4306 .privSecure(!aarch32EL3);
4307 InitReg(MISCREG_TPIDRPRW_S)
4308 .bankedChild()
4309 .secure().exceptUserMode();
4310 InitReg(MISCREG_HTPIDR)
4311 .hyp().monNonSecure();
4312 // BEGIN Generic Timer (AArch32)
4313 InitReg(MISCREG_CNTFRQ)
4314 .reads(1)
4315 .highest(system)
4316 .privSecureWrite(aarch32EL3);
4317 InitReg(MISCREG_CNTPCT)
4318 .unverifiable()
4319 .reads(1);
4320 InitReg(MISCREG_CNTVCT)
4321 .unverifiable()
4322 .reads(1);
4323 InitReg(MISCREG_CNTP_CTL)
4324 .banked();
4325 InitReg(MISCREG_CNTP_CTL_NS)
4326 .bankedChild()
4327 .nonSecure()
4328 .privSecure(!aarch32EL3)
4329 .res0(0xfffffff8);
4330 InitReg(MISCREG_CNTP_CTL_S)
4331 .bankedChild()
4332 .secure()
4333 .privSecure(aarch32EL3)
4334 .res0(0xfffffff8);
4335 InitReg(MISCREG_CNTP_CVAL)
4336 .banked();
4337 InitReg(MISCREG_CNTP_CVAL_NS)
4338 .bankedChild()
4339 .nonSecure()
4340 .privSecure(!aarch32EL3);
4341 InitReg(MISCREG_CNTP_CVAL_S)
4342 .bankedChild()
4343 .secure()
4344 .privSecure(aarch32EL3);
4345 InitReg(MISCREG_CNTP_TVAL)
4346 .banked();
4347 InitReg(MISCREG_CNTP_TVAL_NS)
4348 .bankedChild()
4349 .nonSecure()
4350 .privSecure(!aarch32EL3);
4351 InitReg(MISCREG_CNTP_TVAL_S)
4352 .bankedChild()
4353 .secure()
4354 .privSecure(aarch32EL3);
4355 InitReg(MISCREG_CNTV_CTL)
4356 .allPrivileges()
4357 .res0(0xfffffff8);
4358 InitReg(MISCREG_CNTV_CVAL)
4359 .allPrivileges();
4360 InitReg(MISCREG_CNTV_TVAL)
4361 .allPrivileges();
4362 InitReg(MISCREG_CNTKCTL)
4363 .allPrivileges()
4364 .exceptUserMode()
4365 .res0(0xfffdfc00);
4366 InitReg(MISCREG_CNTHCTL)
4367 .monNonSecure()
4368 .hyp()
4369 .res0(0xfffdff00);
4370 InitReg(MISCREG_CNTHP_CTL)
4371 .monNonSecure()
4372 .hyp()
4373 .res0(0xfffffff8);
4374 InitReg(MISCREG_CNTHP_CVAL)
4375 .monNonSecure()
4376 .hyp();
4377 InitReg(MISCREG_CNTHP_TVAL)
4378 .monNonSecure()
4379 .hyp();
4380 InitReg(MISCREG_CNTVOFF)
4381 .monNonSecure()
4382 .hyp();
4383 // END Generic Timer (AArch32)
4384 InitReg(MISCREG_IL1DATA0)
4385 .unimplemented()
4386 .allPrivileges().exceptUserMode();
4387 InitReg(MISCREG_IL1DATA1)
4388 .unimplemented()
4389 .allPrivileges().exceptUserMode();
4390 InitReg(MISCREG_IL1DATA2)
4391 .unimplemented()
4392 .allPrivileges().exceptUserMode();
4393 InitReg(MISCREG_IL1DATA3)
4394 .unimplemented()
4395 .allPrivileges().exceptUserMode();
4396 InitReg(MISCREG_DL1DATA0)
4397 .unimplemented()
4398 .allPrivileges().exceptUserMode();
4399 InitReg(MISCREG_DL1DATA1)
4400 .unimplemented()
4401 .allPrivileges().exceptUserMode();
4402 InitReg(MISCREG_DL1DATA2)
4403 .unimplemented()
4404 .allPrivileges().exceptUserMode();
4405 InitReg(MISCREG_DL1DATA3)
4406 .unimplemented()
4407 .allPrivileges().exceptUserMode();
4408 InitReg(MISCREG_DL1DATA4)
4409 .unimplemented()
4410 .allPrivileges().exceptUserMode();
4411 InitReg(MISCREG_RAMINDEX)
4412 .unimplemented()
4413 .writes(1).exceptUserMode();
4414 InitReg(MISCREG_L2ACTLR)
4415 .unimplemented()
4416 .allPrivileges().exceptUserMode();
4417 InitReg(MISCREG_CBAR)
4418 .unimplemented()
4419 .allPrivileges().exceptUserMode().writes(0);
4420 InitReg(MISCREG_HTTBR)
4421 .hyp().monNonSecure();
4422 InitReg(MISCREG_VTTBR)
4423 .hyp().monNonSecure();
4424 InitReg(MISCREG_CPUMERRSR)
4425 .unimplemented()
4426 .allPrivileges().exceptUserMode();
4427 InitReg(MISCREG_L2MERRSR)
4428 .unimplemented()
4429 .warnNotFail()
4430 .allPrivileges().exceptUserMode();
4431
4432 // AArch64 registers (Op0=2);
4433 InitReg(MISCREG_MDCCINT_EL1)
4434 .allPrivileges();
4435 InitReg(MISCREG_OSDTRRX_EL1)
4436 .allPrivileges()
4437 .mapsTo(MISCREG_DBGDTRRXext);
4438 InitReg(MISCREG_MDSCR_EL1)
4439 .allPrivileges()
4440 .mapsTo(MISCREG_DBGDSCRext);
4441 InitReg(MISCREG_OSDTRTX_EL1)
4442 .allPrivileges()
4443 .mapsTo(MISCREG_DBGDTRTXext);
4444 InitReg(MISCREG_OSECCR_EL1)
4445 .allPrivileges()
4446 .mapsTo(MISCREG_DBGOSECCR);
4447 InitReg(MISCREG_DBGBVR0_EL1)
4448 .allPrivileges().exceptUserMode()
4449 .mapsTo(MISCREG_DBGBVR0, MISCREG_DBGBXVR0);
4450 InitReg(MISCREG_DBGBVR1_EL1)
4451 .allPrivileges().exceptUserMode()
4452 .mapsTo(MISCREG_DBGBVR1, MISCREG_DBGBXVR1);
4453 InitReg(MISCREG_DBGBVR2_EL1)
4454 .allPrivileges().exceptUserMode()
4455 .mapsTo(MISCREG_DBGBVR2, MISCREG_DBGBXVR2);
4456 InitReg(MISCREG_DBGBVR3_EL1)
4457 .allPrivileges().exceptUserMode()
4458 .mapsTo(MISCREG_DBGBVR3, MISCREG_DBGBXVR3);
4459 InitReg(MISCREG_DBGBVR4_EL1)
4460 .allPrivileges().exceptUserMode()
4461 .mapsTo(MISCREG_DBGBVR4, MISCREG_DBGBXVR4);
4462 InitReg(MISCREG_DBGBVR5_EL1)
4463 .allPrivileges().exceptUserMode()
4464 .mapsTo(MISCREG_DBGBVR5, MISCREG_DBGBXVR5);
4465 InitReg(MISCREG_DBGBVR6_EL1)
4466 .allPrivileges().exceptUserMode()
4467 .mapsTo(MISCREG_DBGBVR6, MISCREG_DBGBXVR6);
4468 InitReg(MISCREG_DBGBVR7_EL1)
4469 .allPrivileges().exceptUserMode()
4470 .mapsTo(MISCREG_DBGBVR7, MISCREG_DBGBXVR7);
4471 InitReg(MISCREG_DBGBVR8_EL1)
4472 .allPrivileges().exceptUserMode()
4473 .mapsTo(MISCREG_DBGBVR8, MISCREG_DBGBXVR8);
4474 InitReg(MISCREG_DBGBVR9_EL1)
4475 .allPrivileges().exceptUserMode()
4476 .mapsTo(MISCREG_DBGBVR9, MISCREG_DBGBXVR9);
4477 InitReg(MISCREG_DBGBVR10_EL1)
4478 .allPrivileges().exceptUserMode()
4479 .mapsTo(MISCREG_DBGBVR10, MISCREG_DBGBXVR10);
4480 InitReg(MISCREG_DBGBVR11_EL1)
4481 .allPrivileges().exceptUserMode()
4482 .mapsTo(MISCREG_DBGBVR11, MISCREG_DBGBXVR11);
4483 InitReg(MISCREG_DBGBVR12_EL1)
4484 .allPrivileges().exceptUserMode()
4485 .mapsTo(MISCREG_DBGBVR12, MISCREG_DBGBXVR12);
4486 InitReg(MISCREG_DBGBVR13_EL1)
4487 .allPrivileges().exceptUserMode()
4488 .mapsTo(MISCREG_DBGBVR13, MISCREG_DBGBXVR13);
4489 InitReg(MISCREG_DBGBVR14_EL1)
4490 .allPrivileges().exceptUserMode()
4491 .mapsTo(MISCREG_DBGBVR14, MISCREG_DBGBXVR14);
4492 InitReg(MISCREG_DBGBVR15_EL1)
4493 .allPrivileges().exceptUserMode()
4494 .mapsTo(MISCREG_DBGBVR15, MISCREG_DBGBXVR15);
4495 InitReg(MISCREG_DBGBCR0_EL1)
4496 .allPrivileges().exceptUserMode()
4497 .mapsTo(MISCREG_DBGBCR0);
4498 InitReg(MISCREG_DBGBCR1_EL1)
4499 .allPrivileges().exceptUserMode()
4500 .mapsTo(MISCREG_DBGBCR1);
4501 InitReg(MISCREG_DBGBCR2_EL1)
4502 .allPrivileges().exceptUserMode()
4503 .mapsTo(MISCREG_DBGBCR2);
4504 InitReg(MISCREG_DBGBCR3_EL1)
4505 .allPrivileges().exceptUserMode()
4506 .mapsTo(MISCREG_DBGBCR3);
4507 InitReg(MISCREG_DBGBCR4_EL1)
4508 .allPrivileges().exceptUserMode()
4509 .mapsTo(MISCREG_DBGBCR4);
4510 InitReg(MISCREG_DBGBCR5_EL1)
4511 .allPrivileges().exceptUserMode()
4512 .mapsTo(MISCREG_DBGBCR5);
4513 InitReg(MISCREG_DBGBCR6_EL1)
4514 .allPrivileges().exceptUserMode()
4515 .mapsTo(MISCREG_DBGBCR6);
4516 InitReg(MISCREG_DBGBCR7_EL1)
4517 .allPrivileges().exceptUserMode()
4518 .mapsTo(MISCREG_DBGBCR7);
4519 InitReg(MISCREG_DBGBCR8_EL1)
4520 .allPrivileges().exceptUserMode()
4521 .mapsTo(MISCREG_DBGBCR8);
4522 InitReg(MISCREG_DBGBCR9_EL1)
4523 .allPrivileges().exceptUserMode()
4524 .mapsTo(MISCREG_DBGBCR9);
4525 InitReg(MISCREG_DBGBCR10_EL1)
4526 .allPrivileges().exceptUserMode()
4527 .mapsTo(MISCREG_DBGBCR10);
4528 InitReg(MISCREG_DBGBCR11_EL1)
4529 .allPrivileges().exceptUserMode()
4530 .mapsTo(MISCREG_DBGBCR11);
4531 InitReg(MISCREG_DBGBCR12_EL1)
4532 .allPrivileges().exceptUserMode()
4533 .mapsTo(MISCREG_DBGBCR12);
4534 InitReg(MISCREG_DBGBCR13_EL1)
4535 .allPrivileges().exceptUserMode()
4536 .mapsTo(MISCREG_DBGBCR13);
4537 InitReg(MISCREG_DBGBCR14_EL1)
4538 .allPrivileges().exceptUserMode()
4539 .mapsTo(MISCREG_DBGBCR14);
4540 InitReg(MISCREG_DBGBCR15_EL1)
4541 .allPrivileges().exceptUserMode()
4542 .mapsTo(MISCREG_DBGBCR15);
4543 InitReg(MISCREG_DBGWVR0_EL1)
4544 .allPrivileges().exceptUserMode()
4545 .mapsTo(MISCREG_DBGWVR0);
4546 InitReg(MISCREG_DBGWVR1_EL1)
4547 .allPrivileges().exceptUserMode()
4548 .mapsTo(MISCREG_DBGWVR1);
4549 InitReg(MISCREG_DBGWVR2_EL1)
4550 .allPrivileges().exceptUserMode()
4551 .mapsTo(MISCREG_DBGWVR2);
4552 InitReg(MISCREG_DBGWVR3_EL1)
4553 .allPrivileges().exceptUserMode()
4554 .mapsTo(MISCREG_DBGWVR3);
4555 InitReg(MISCREG_DBGWVR4_EL1)
4556 .allPrivileges().exceptUserMode()
4557 .mapsTo(MISCREG_DBGWVR4);
4558 InitReg(MISCREG_DBGWVR5_EL1)
4559 .allPrivileges().exceptUserMode()
4560 .mapsTo(MISCREG_DBGWVR5);
4561 InitReg(MISCREG_DBGWVR6_EL1)
4562 .allPrivileges().exceptUserMode()
4563 .mapsTo(MISCREG_DBGWVR6);
4564 InitReg(MISCREG_DBGWVR7_EL1)
4565 .allPrivileges().exceptUserMode()
4566 .mapsTo(MISCREG_DBGWVR7);
4567 InitReg(MISCREG_DBGWVR8_EL1)
4568 .allPrivileges().exceptUserMode()
4569 .mapsTo(MISCREG_DBGWVR8);
4570 InitReg(MISCREG_DBGWVR9_EL1)
4571 .allPrivileges().exceptUserMode()
4572 .mapsTo(MISCREG_DBGWVR9);
4573 InitReg(MISCREG_DBGWVR10_EL1)
4574 .allPrivileges().exceptUserMode()
4575 .mapsTo(MISCREG_DBGWVR10);
4576 InitReg(MISCREG_DBGWVR11_EL1)
4577 .allPrivileges().exceptUserMode()
4578 .mapsTo(MISCREG_DBGWVR11);
4579 InitReg(MISCREG_DBGWVR12_EL1)
4580 .allPrivileges().exceptUserMode()
4581 .mapsTo(MISCREG_DBGWVR12);
4582 InitReg(MISCREG_DBGWVR13_EL1)
4583 .allPrivileges().exceptUserMode()
4584 .mapsTo(MISCREG_DBGWVR13);
4585 InitReg(MISCREG_DBGWVR14_EL1)
4586 .allPrivileges().exceptUserMode()
4587 .mapsTo(MISCREG_DBGWVR14);
4588 InitReg(MISCREG_DBGWVR15_EL1)
4589 .allPrivileges().exceptUserMode()
4590 .mapsTo(MISCREG_DBGWVR15);
4591 InitReg(MISCREG_DBGWCR0_EL1)
4592 .allPrivileges().exceptUserMode()
4593 .mapsTo(MISCREG_DBGWCR0);
4594 InitReg(MISCREG_DBGWCR1_EL1)
4595 .allPrivileges().exceptUserMode()
4596 .mapsTo(MISCREG_DBGWCR1);
4597 InitReg(MISCREG_DBGWCR2_EL1)
4598 .allPrivileges().exceptUserMode()
4599 .mapsTo(MISCREG_DBGWCR2);
4600 InitReg(MISCREG_DBGWCR3_EL1)
4601 .allPrivileges().exceptUserMode()
4602 .mapsTo(MISCREG_DBGWCR3);
4603 InitReg(MISCREG_DBGWCR4_EL1)
4604 .allPrivileges().exceptUserMode()
4605 .mapsTo(MISCREG_DBGWCR4);
4606 InitReg(MISCREG_DBGWCR5_EL1)
4607 .allPrivileges().exceptUserMode()
4608 .mapsTo(MISCREG_DBGWCR5);
4609 InitReg(MISCREG_DBGWCR6_EL1)
4610 .allPrivileges().exceptUserMode()
4611 .mapsTo(MISCREG_DBGWCR6);
4612 InitReg(MISCREG_DBGWCR7_EL1)
4613 .allPrivileges().exceptUserMode()
4614 .mapsTo(MISCREG_DBGWCR7);
4615 InitReg(MISCREG_DBGWCR8_EL1)
4616 .allPrivileges().exceptUserMode()
4617 .mapsTo(MISCREG_DBGWCR8);
4618 InitReg(MISCREG_DBGWCR9_EL1)
4619 .allPrivileges().exceptUserMode()
4620 .mapsTo(MISCREG_DBGWCR9);
4621 InitReg(MISCREG_DBGWCR10_EL1)
4622 .allPrivileges().exceptUserMode()
4623 .mapsTo(MISCREG_DBGWCR10);
4624 InitReg(MISCREG_DBGWCR11_EL1)
4625 .allPrivileges().exceptUserMode()
4626 .mapsTo(MISCREG_DBGWCR11);
4627 InitReg(MISCREG_DBGWCR12_EL1)
4628 .allPrivileges().exceptUserMode()
4629 .mapsTo(MISCREG_DBGWCR12);
4630 InitReg(MISCREG_DBGWCR13_EL1)
4631 .allPrivileges().exceptUserMode()
4632 .mapsTo(MISCREG_DBGWCR13);
4633 InitReg(MISCREG_DBGWCR14_EL1)
4634 .allPrivileges().exceptUserMode()
4635 .mapsTo(MISCREG_DBGWCR14);
4636 InitReg(MISCREG_DBGWCR15_EL1)
4637 .allPrivileges().exceptUserMode()
4638 .mapsTo(MISCREG_DBGWCR15);
4639 InitReg(MISCREG_MDCCSR_EL0)
4640 .allPrivileges().writes(0)
4641 //monSecureWrite(0).monNonSecureWrite(0)
4642 .mapsTo(MISCREG_DBGDSCRint);
4643 InitReg(MISCREG_MDDTR_EL0)
4644 .allPrivileges();
4645 InitReg(MISCREG_MDDTRTX_EL0)
4646 .allPrivileges();
4647 InitReg(MISCREG_MDDTRRX_EL0)
4648 .allPrivileges();
4649 InitReg(MISCREG_DBGVCR32_EL2)
4650 .hyp().mon()
4651 .mapsTo(MISCREG_DBGVCR);
4652 InitReg(MISCREG_MDRAR_EL1)
4653 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
4654 .mapsTo(MISCREG_DBGDRAR);
4655 InitReg(MISCREG_OSLAR_EL1)
4656 .allPrivileges().monSecureRead(0).monNonSecureRead(0)
4657 .mapsTo(MISCREG_DBGOSLAR);
4658 InitReg(MISCREG_OSLSR_EL1)
4659 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
4660 .mapsTo(MISCREG_DBGOSLSR);
4661 InitReg(MISCREG_OSDLR_EL1)
4662 .allPrivileges()
4663 .mapsTo(MISCREG_DBGOSDLR);
4664 InitReg(MISCREG_DBGPRCR_EL1)
4665 .allPrivileges()
4666 .mapsTo(MISCREG_DBGPRCR);
4667 InitReg(MISCREG_DBGCLAIMSET_EL1)
4668 .allPrivileges()
4669 .mapsTo(MISCREG_DBGCLAIMSET);
4670 InitReg(MISCREG_DBGCLAIMCLR_EL1)
4671 .allPrivileges()
4672 .mapsTo(MISCREG_DBGCLAIMCLR);
4673 InitReg(MISCREG_DBGAUTHSTATUS_EL1)
4674 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
4675 .mapsTo(MISCREG_DBGAUTHSTATUS);
4676 InitReg(MISCREG_TEECR32_EL1);
4677 InitReg(MISCREG_TEEHBR32_EL1);
4678
4679 // AArch64 registers (Op0=1,3);
4680 InitReg(MISCREG_MIDR_EL1)
4681 .allPrivileges().exceptUserMode().writes(0);
4682 InitReg(MISCREG_MPIDR_EL1)
4683 .allPrivileges().exceptUserMode().writes(0);
4684 InitReg(MISCREG_REVIDR_EL1)
4685 .allPrivileges().exceptUserMode().writes(0);
4686 InitReg(MISCREG_ID_PFR0_EL1)
4687 .allPrivileges().exceptUserMode().writes(0)
4688 .mapsTo(MISCREG_ID_PFR0);
4689 InitReg(MISCREG_ID_PFR1_EL1)
4690 .allPrivileges().exceptUserMode().writes(0)
4691 .mapsTo(MISCREG_ID_PFR1);
4692 InitReg(MISCREG_ID_DFR0_EL1)
4693 .allPrivileges().exceptUserMode().writes(0)
4694 .mapsTo(MISCREG_ID_DFR0);
4695 InitReg(MISCREG_ID_AFR0_EL1)
4696 .allPrivileges().exceptUserMode().writes(0)
4697 .mapsTo(MISCREG_ID_AFR0);
4698 InitReg(MISCREG_ID_MMFR0_EL1)
4699 .allPrivileges().exceptUserMode().writes(0)
4700 .mapsTo(MISCREG_ID_MMFR0);
4701 InitReg(MISCREG_ID_MMFR1_EL1)
4702 .allPrivileges().exceptUserMode().writes(0)
4703 .mapsTo(MISCREG_ID_MMFR1);
4704 InitReg(MISCREG_ID_MMFR2_EL1)
4705 .allPrivileges().exceptUserMode().writes(0)
4706 .mapsTo(MISCREG_ID_MMFR2);
4707 InitReg(MISCREG_ID_MMFR3_EL1)
4708 .allPrivileges().exceptUserMode().writes(0)
4709 .mapsTo(MISCREG_ID_MMFR3);
4710 InitReg(MISCREG_ID_MMFR4_EL1)
4711 .allPrivileges().exceptUserMode().writes(0)
4712 .mapsTo(MISCREG_ID_MMFR4);
4713 InitReg(MISCREG_ID_ISAR0_EL1)
4714 .allPrivileges().exceptUserMode().writes(0)
4715 .mapsTo(MISCREG_ID_ISAR0);
4716 InitReg(MISCREG_ID_ISAR1_EL1)
4717 .allPrivileges().exceptUserMode().writes(0)
4718 .mapsTo(MISCREG_ID_ISAR1);
4719 InitReg(MISCREG_ID_ISAR2_EL1)
4720 .allPrivileges().exceptUserMode().writes(0)
4721 .mapsTo(MISCREG_ID_ISAR2);
4722 InitReg(MISCREG_ID_ISAR3_EL1)
4723 .allPrivileges().exceptUserMode().writes(0)
4724 .mapsTo(MISCREG_ID_ISAR3);
4725 InitReg(MISCREG_ID_ISAR4_EL1)
4726 .allPrivileges().exceptUserMode().writes(0)
4727 .mapsTo(MISCREG_ID_ISAR4);
4728 InitReg(MISCREG_ID_ISAR5_EL1)
4729 .allPrivileges().exceptUserMode().writes(0)
4730 .mapsTo(MISCREG_ID_ISAR5);
4731 InitReg(MISCREG_ID_ISAR6_EL1)
4732 .allPrivileges().exceptUserMode().writes(0)
4733 .mapsTo(MISCREG_ID_ISAR6);
4734 InitReg(MISCREG_MVFR0_EL1)
4735 .allPrivileges().exceptUserMode().writes(0);
4736 InitReg(MISCREG_MVFR1_EL1)
4737 .allPrivileges().exceptUserMode().writes(0);
4738 InitReg(MISCREG_MVFR2_EL1)
4739 .allPrivileges().exceptUserMode().writes(0);
4740 InitReg(MISCREG_ID_AA64PFR0_EL1)
4741 .allPrivileges().exceptUserMode().writes(0);
4742 InitReg(MISCREG_ID_AA64PFR1_EL1)
4743 .allPrivileges().exceptUserMode().writes(0);
4744 InitReg(MISCREG_ID_AA64DFR0_EL1)
4745 .allPrivileges().exceptUserMode().writes(0);
4746 InitReg(MISCREG_ID_AA64DFR1_EL1)
4747 .allPrivileges().exceptUserMode().writes(0);
4748 InitReg(MISCREG_ID_AA64AFR0_EL1)
4749 .allPrivileges().exceptUserMode().writes(0);
4750 InitReg(MISCREG_ID_AA64AFR1_EL1)
4751 .allPrivileges().exceptUserMode().writes(0);
4752 InitReg(MISCREG_ID_AA64ISAR0_EL1)
4753 .allPrivileges().exceptUserMode().writes(0);
4754 InitReg(MISCREG_ID_AA64ISAR1_EL1)
4755 .allPrivileges().exceptUserMode().writes(0);
4756 InitReg(MISCREG_ID_AA64MMFR0_EL1)
4757 .allPrivileges().exceptUserMode().writes(0);
4758 InitReg(MISCREG_ID_AA64MMFR1_EL1)
4759 .allPrivileges().exceptUserMode().writes(0);
4760 InitReg(MISCREG_ID_AA64MMFR2_EL1)
4761 .allPrivileges().exceptUserMode().writes(0);
4762
4763 InitReg(MISCREG_APDAKeyHi_EL1)
4764 .allPrivileges().exceptUserMode();
4765 InitReg(MISCREG_APDAKeyLo_EL1)
4766 .allPrivileges().exceptUserMode();
4767 InitReg(MISCREG_APDBKeyHi_EL1)
4768 .allPrivileges().exceptUserMode();
4769 InitReg(MISCREG_APDBKeyLo_EL1)
4770 .allPrivileges().exceptUserMode();
4771 InitReg(MISCREG_APGAKeyHi_EL1)
4772 .allPrivileges().exceptUserMode();
4773 InitReg(MISCREG_APGAKeyLo_EL1)
4774 .allPrivileges().exceptUserMode();
4775 InitReg(MISCREG_APIAKeyHi_EL1)
4776 .allPrivileges().exceptUserMode();
4777 InitReg(MISCREG_APIAKeyLo_EL1)
4778 .allPrivileges().exceptUserMode();
4779 InitReg(MISCREG_APIBKeyHi_EL1)
4780 .allPrivileges().exceptUserMode();
4781 InitReg(MISCREG_APIBKeyLo_EL1)
4782 .allPrivileges().exceptUserMode();
4783
4784 InitReg(MISCREG_CCSIDR_EL1)
4785 .allPrivileges().exceptUserMode().writes(0);
4786 InitReg(MISCREG_CLIDR_EL1)
4787 .allPrivileges().exceptUserMode().writes(0);
4788 InitReg(MISCREG_AIDR_EL1)
4789 .allPrivileges().exceptUserMode().writes(0);
4790 InitReg(MISCREG_CSSELR_EL1)
4791 .allPrivileges().exceptUserMode()
4792 .mapsTo(MISCREG_CSSELR_NS);
4793 InitReg(MISCREG_CTR_EL0)
4794 .reads(1);
4795 InitReg(MISCREG_DCZID_EL0)
4796 .reads(1);
4797 InitReg(MISCREG_VPIDR_EL2)
4798 .hyp().mon()
4799 .mapsTo(MISCREG_VPIDR);
4800 InitReg(MISCREG_VMPIDR_EL2)
4801 .hyp().mon()
4802 .mapsTo(MISCREG_VMPIDR);
4803 InitReg(MISCREG_SCTLR_EL1)
4804 .allPrivileges().exceptUserMode()
4805 .res0( 0x20440 | (EnDB ? 0 : 0x2000)
4806 | (IESB ? 0 : 0x200000)
4807 | (EnDA ? 0 : 0x8000000)
4808 | (EnIB ? 0 : 0x40000000)
4809 | (EnIA ? 0 : 0x80000000))
4810 .res1(0x500800 | (SPAN ? 0 : 0x800000)
4811 | (nTLSMD ? 0 : 0x8000000)
4812 | (LSMAOE ? 0 : 0x10000000))
4813 .mapsTo(MISCREG_SCTLR_NS);
4814 InitReg(MISCREG_SCTLR_EL12)
4815 .allPrivileges().exceptUserMode()
4816 .res0( 0x20440 | (EnDB ? 0 : 0x2000)
4817 | (IESB ? 0 : 0x200000)
4818 | (EnDA ? 0 : 0x8000000)
4819 | (EnIB ? 0 : 0x40000000)
4820 | (EnIA ? 0 : 0x80000000))
4821 .res1(0x500800 | (SPAN ? 0 : 0x800000)
4822 | (nTLSMD ? 0 : 0x8000000)
4823 | (LSMAOE ? 0 : 0x10000000))
4824 .mapsTo(MISCREG_SCTLR_EL1);
4825 InitReg(MISCREG_ACTLR_EL1)
4826 .allPrivileges().exceptUserMode()
4827 .mapsTo(MISCREG_ACTLR_NS);
4828 InitReg(MISCREG_CPACR_EL1)
4829 .allPrivileges().exceptUserMode()
4830 .mapsTo(MISCREG_CPACR);
4831 InitReg(MISCREG_CPACR_EL12)
4832 .allPrivileges().exceptUserMode()
4833 .mapsTo(MISCREG_CPACR_EL1);
4834 InitReg(MISCREG_SCTLR_EL2)
4835 .hyp().mon()
4836 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
4837 | (IESB ? 0 : 0x200000)
4838 | (EnDA ? 0 : 0x8000000)
4839 | (EnIB ? 0 : 0x40000000)
4840 | (EnIA ? 0 : 0x80000000))
4841 .res1(0x30c50830)
4842 .mapsTo(MISCREG_HSCTLR);
4843 InitReg(MISCREG_ACTLR_EL2)
4844 .hyp().mon()
4845 .mapsTo(MISCREG_HACTLR);
4846 InitReg(MISCREG_HCR_EL2)
4847 .hyp().mon()
4848 .mapsTo(MISCREG_HCR, MISCREG_HCR2);
4849 InitReg(MISCREG_MDCR_EL2)
4850 .hyp().mon()
4851 .mapsTo(MISCREG_HDCR);
4852 InitReg(MISCREG_CPTR_EL2)
4853 .hyp().mon()
4854 .mapsTo(MISCREG_HCPTR);
4855 InitReg(MISCREG_HSTR_EL2)
4856 .hyp().mon()
4857 .mapsTo(MISCREG_HSTR);
4858 InitReg(MISCREG_HACR_EL2)
4859 .hyp().mon()
4860 .mapsTo(MISCREG_HACR);
4861 InitReg(MISCREG_SCTLR_EL3)
4862 .mon()
4863 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
4864 | (IESB ? 0 : 0x200000)
4865 | (EnDA ? 0 : 0x8000000)
4866 | (EnIB ? 0 : 0x40000000)
4867 | (EnIA ? 0 : 0x80000000))
4868 .res1(0x30c50830);
4869 InitReg(MISCREG_ACTLR_EL3)
4870 .mon();
4871 InitReg(MISCREG_SCR_EL3)
4872 .mon()
4873 .mapsTo(MISCREG_SCR); // NAM D7-2005
4874 InitReg(MISCREG_SDER32_EL3)
4875 .mon()
4876 .mapsTo(MISCREG_SDER);
4877 InitReg(MISCREG_CPTR_EL3)
4878 .mon();
4879 InitReg(MISCREG_MDCR_EL3)
4880 .mon()
4881 .mapsTo(MISCREG_SDCR);
4882 InitReg(MISCREG_TTBR0_EL1)
4883 .allPrivileges().exceptUserMode()
4884 .mapsTo(MISCREG_TTBR0_NS);
4885 InitReg(MISCREG_TTBR0_EL12)
4886 .allPrivileges().exceptUserMode()
4887 .mapsTo(MISCREG_TTBR0_EL1);
4888 InitReg(MISCREG_TTBR1_EL1)
4889 .allPrivileges().exceptUserMode()
4890 .mapsTo(MISCREG_TTBR1_NS);
4891 InitReg(MISCREG_TTBR1_EL12)
4892 .allPrivileges().exceptUserMode()
4893 .mapsTo(MISCREG_TTBR1_EL1);
4894 InitReg(MISCREG_TCR_EL1)
4895 .allPrivileges().exceptUserMode()
4896 .mapsTo(MISCREG_TTBCR_NS);
4897 InitReg(MISCREG_TCR_EL12)
4898 .allPrivileges().exceptUserMode()
4899 .mapsTo(MISCREG_TTBCR_NS);
4900 InitReg(MISCREG_TTBR0_EL2)
4901 .hyp().mon()
4902 .mapsTo(MISCREG_HTTBR);
4903 InitReg(MISCREG_TTBR1_EL2)
4904 .hyp().mon();
4905 InitReg(MISCREG_TCR_EL2)
4906 .hyp().mon()
4907 .mapsTo(MISCREG_HTCR);
4908 InitReg(MISCREG_VTTBR_EL2)
4909 .hyp().mon()
4910 .mapsTo(MISCREG_VTTBR);
4911 InitReg(MISCREG_VTCR_EL2)
4912 .hyp().mon()
4913 .mapsTo(MISCREG_VTCR);
4914 InitReg(MISCREG_VSTTBR_EL2)
4915 .hypSecure().mon();
4916 InitReg(MISCREG_VSTCR_EL2)
4917 .hypSecure().mon();
4918 InitReg(MISCREG_TTBR0_EL3)
4919 .mon();
4920 InitReg(MISCREG_TCR_EL3)
4921 .mon();
4922 InitReg(MISCREG_DACR32_EL2)
4923 .hyp().mon()
4924 .mapsTo(MISCREG_DACR_NS);
4925 InitReg(MISCREG_SPSR_EL1)
4926 .allPrivileges().exceptUserMode()
4927 .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
4928 InitReg(MISCREG_SPSR_EL12)
4929 .allPrivileges().exceptUserMode()
4930 .mapsTo(MISCREG_SPSR_SVC);
4931 InitReg(MISCREG_ELR_EL1)
4932 .allPrivileges().exceptUserMode();
4933 InitReg(MISCREG_ELR_EL12)
4934 .allPrivileges().exceptUserMode()
4935 .mapsTo(MISCREG_ELR_EL1);
4936 InitReg(MISCREG_SP_EL0)
4937 .allPrivileges().exceptUserMode();
4938 InitReg(MISCREG_SPSEL)
4939 .allPrivileges().exceptUserMode();
4940 InitReg(MISCREG_CURRENTEL)
4941 .allPrivileges().exceptUserMode().writes(0);
4942 InitReg(MISCREG_PAN)
4943 .allPrivileges().exceptUserMode()
4944 .implemented(havePAN);
4945 InitReg(MISCREG_NZCV)
4946 .allPrivileges();
4947 InitReg(MISCREG_DAIF)
4948 .allPrivileges();
4949 InitReg(MISCREG_FPCR)
4950 .allPrivileges();
4951 InitReg(MISCREG_FPSR)
4952 .allPrivileges();
4953 InitReg(MISCREG_DSPSR_EL0)
4954 .allPrivileges();
4955 InitReg(MISCREG_DLR_EL0)
4956 .allPrivileges();
4957 InitReg(MISCREG_SPSR_EL2)
4958 .hyp().mon()
4959 .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2
4960 InitReg(MISCREG_ELR_EL2)
4961 .hyp().mon();
4962 InitReg(MISCREG_SP_EL1)
4963 .hyp().mon();
4964 InitReg(MISCREG_SPSR_IRQ_AA64)
4965 .hyp().mon();
4966 InitReg(MISCREG_SPSR_ABT_AA64)
4967 .hyp().mon();
4968 InitReg(MISCREG_SPSR_UND_AA64)
4969 .hyp().mon();
4970 InitReg(MISCREG_SPSR_FIQ_AA64)
4971 .hyp().mon();
4972 InitReg(MISCREG_SPSR_EL3)
4973 .mon()
4974 .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3
4975 InitReg(MISCREG_ELR_EL3)
4976 .mon();
4977 InitReg(MISCREG_SP_EL2)
4978 .mon();
4979 InitReg(MISCREG_AFSR0_EL1)
4980 .allPrivileges().exceptUserMode()
4981 .mapsTo(MISCREG_ADFSR_NS);
4982 InitReg(MISCREG_AFSR0_EL12)
4983 .allPrivileges().exceptUserMode()
4984 .mapsTo(MISCREG_ADFSR_NS);
4985 InitReg(MISCREG_AFSR1_EL1)
4986 .allPrivileges().exceptUserMode()
4987 .mapsTo(MISCREG_AIFSR_NS);
4988 InitReg(MISCREG_AFSR1_EL12)
4989 .allPrivileges().exceptUserMode()
4990 .mapsTo(MISCREG_AIFSR_NS);
4991 InitReg(MISCREG_ESR_EL1)
4992 .allPrivileges().exceptUserMode();
4993 InitReg(MISCREG_ESR_EL12)
4994 .allPrivileges().exceptUserMode()
4995 .mapsTo(MISCREG_ESR_EL1);
4996 InitReg(MISCREG_IFSR32_EL2)
4997 .hyp().mon()
4998 .mapsTo(MISCREG_IFSR_NS);
4999 InitReg(MISCREG_AFSR0_EL2)
5000 .hyp().mon()
5001 .mapsTo(MISCREG_HADFSR);
5002 InitReg(MISCREG_AFSR1_EL2)
5003 .hyp().mon()
5004 .mapsTo(MISCREG_HAIFSR);
5005 InitReg(MISCREG_ESR_EL2)
5006 .hyp().mon()
5007 .mapsTo(MISCREG_HSR);
5008 InitReg(MISCREG_FPEXC32_EL2)
5009 .hyp().mon().mapsTo(MISCREG_FPEXC);
5010 InitReg(MISCREG_AFSR0_EL3)
5011 .mon();
5012 InitReg(MISCREG_AFSR1_EL3)
5013 .mon();
5014 InitReg(MISCREG_ESR_EL3)
5015 .mon();
5016 InitReg(MISCREG_FAR_EL1)
5017 .allPrivileges().exceptUserMode()
5018 .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
5019 InitReg(MISCREG_FAR_EL12)
5020 .allPrivileges().exceptUserMode()
5021 .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
5022 InitReg(MISCREG_FAR_EL2)
5023 .hyp().mon()
5024 .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR);
5025 InitReg(MISCREG_HPFAR_EL2)
5026 .hyp().mon()
5027 .mapsTo(MISCREG_HPFAR);
5028 InitReg(MISCREG_FAR_EL3)
5029 .mon();
5030 InitReg(MISCREG_IC_IALLUIS)
5031 .warnNotFail()
5032 .writes(1).exceptUserMode();
5033 InitReg(MISCREG_PAR_EL1)
5034 .allPrivileges().exceptUserMode()
5035 .mapsTo(MISCREG_PAR_NS);
5036 InitReg(MISCREG_IC_IALLU)
5037 .warnNotFail()
5038 .writes(1).exceptUserMode();
5039 InitReg(MISCREG_DC_IVAC_Xt)
5040 .warnNotFail()
5041 .writes(1).exceptUserMode();
5042 InitReg(MISCREG_DC_ISW_Xt)
5043 .warnNotFail()
5044 .writes(1).exceptUserMode();
5045 InitReg(MISCREG_AT_S1E1R_Xt)
5046 .writes(1).exceptUserMode();
5047 InitReg(MISCREG_AT_S1E1W_Xt)
5048 .writes(1).exceptUserMode();
5049 InitReg(MISCREG_AT_S1E0R_Xt)
5050 .writes(1).exceptUserMode();
5051 InitReg(MISCREG_AT_S1E0W_Xt)
5052 .writes(1).exceptUserMode();
5053 InitReg(MISCREG_DC_CSW_Xt)
5054 .warnNotFail()
5055 .writes(1).exceptUserMode();
5056 InitReg(MISCREG_DC_CISW_Xt)
5057 .warnNotFail()
5058 .writes(1).exceptUserMode();
5059 InitReg(MISCREG_DC_ZVA_Xt)
5060 .warnNotFail()
5061 .writes(1).userSecureWrite(0);
5062 InitReg(MISCREG_IC_IVAU_Xt)
5063 .writes(1);
5064 InitReg(MISCREG_DC_CVAC_Xt)
5065 .warnNotFail()
5066 .writes(1);
5067 InitReg(MISCREG_DC_CVAU_Xt)
5068 .warnNotFail()
5069 .writes(1);
5070 InitReg(MISCREG_DC_CIVAC_Xt)
5071 .warnNotFail()
5072 .writes(1);
5073 InitReg(MISCREG_AT_S1E2R_Xt)
5074 .monNonSecureWrite().hypWrite();
5075 InitReg(MISCREG_AT_S1E2W_Xt)
5076 .monNonSecureWrite().hypWrite();
5077 InitReg(MISCREG_AT_S12E1R_Xt)
5078 .hypWrite().monSecureWrite().monNonSecureWrite();
5079 InitReg(MISCREG_AT_S12E1W_Xt)
5080 .hypWrite().monSecureWrite().monNonSecureWrite();
5081 InitReg(MISCREG_AT_S12E0R_Xt)
5082 .hypWrite().monSecureWrite().monNonSecureWrite();
5083 InitReg(MISCREG_AT_S12E0W_Xt)
5084 .hypWrite().monSecureWrite().monNonSecureWrite();
5085 InitReg(MISCREG_AT_S1E3R_Xt)
5086 .monSecureWrite().monNonSecureWrite();
5087 InitReg(MISCREG_AT_S1E3W_Xt)
5088 .monSecureWrite().monNonSecureWrite();
5089 InitReg(MISCREG_TLBI_VMALLE1IS)
5090 .writes(1).exceptUserMode();
5091 InitReg(MISCREG_TLBI_VAE1IS_Xt)
5092 .writes(1).exceptUserMode();
5093 InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
5094 .writes(1).exceptUserMode();
5095 InitReg(MISCREG_TLBI_VAAE1IS_Xt)
5096 .writes(1).exceptUserMode();
5097 InitReg(MISCREG_TLBI_VALE1IS_Xt)
5098 .writes(1).exceptUserMode();
5099 InitReg(MISCREG_TLBI_VAALE1IS_Xt)
5100 .writes(1).exceptUserMode();
5101 InitReg(MISCREG_TLBI_VMALLE1)
5102 .writes(1).exceptUserMode();
5103 InitReg(MISCREG_TLBI_VAE1_Xt)
5104 .writes(1).exceptUserMode();
5105 InitReg(MISCREG_TLBI_ASIDE1_Xt)
5106 .writes(1).exceptUserMode();
5107 InitReg(MISCREG_TLBI_VAAE1_Xt)
5108 .writes(1).exceptUserMode();
5109 InitReg(MISCREG_TLBI_VALE1_Xt)
5110 .writes(1).exceptUserMode();
5111 InitReg(MISCREG_TLBI_VAALE1_Xt)
5112 .writes(1).exceptUserMode();
5113 InitReg(MISCREG_TLBI_IPAS2E1IS_Xt)
5114 .hypWrite().monSecureWrite().monNonSecureWrite();
5115 InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt)
5116 .hypWrite().monSecureWrite().monNonSecureWrite();
5117 InitReg(MISCREG_TLBI_ALLE2IS)
5118 .monNonSecureWrite().hypWrite();
5119 InitReg(MISCREG_TLBI_VAE2IS_Xt)
5120 .monNonSecureWrite().hypWrite();
5121 InitReg(MISCREG_TLBI_ALLE1IS)
5122 .hypWrite().monSecureWrite().monNonSecureWrite();
5123 InitReg(MISCREG_TLBI_VALE2IS_Xt)
5124 .monNonSecureWrite().hypWrite();
5125 InitReg(MISCREG_TLBI_VMALLS12E1IS)
5126 .hypWrite().monSecureWrite().monNonSecureWrite();
5127 InitReg(MISCREG_TLBI_IPAS2E1_Xt)
5128 .hypWrite().monSecureWrite().monNonSecureWrite();
5129 InitReg(MISCREG_TLBI_IPAS2LE1_Xt)
5130 .hypWrite().monSecureWrite().monNonSecureWrite();
5131 InitReg(MISCREG_TLBI_ALLE2)
5132 .monNonSecureWrite().hypWrite();
5133 InitReg(MISCREG_TLBI_VAE2_Xt)
5134 .monNonSecureWrite().hypWrite();
5135 InitReg(MISCREG_TLBI_ALLE1)
5136 .hypWrite().monSecureWrite().monNonSecureWrite();
5137 InitReg(MISCREG_TLBI_VALE2_Xt)
5138 .monNonSecureWrite().hypWrite();
5139 InitReg(MISCREG_TLBI_VMALLS12E1)
5140 .hypWrite().monSecureWrite().monNonSecureWrite();
5141 InitReg(MISCREG_TLBI_ALLE3IS)
5142 .monSecureWrite().monNonSecureWrite();
5143 InitReg(MISCREG_TLBI_VAE3IS_Xt)
5144 .monSecureWrite().monNonSecureWrite();
5145 InitReg(MISCREG_TLBI_VALE3IS_Xt)
5146 .monSecureWrite().monNonSecureWrite();
5147 InitReg(MISCREG_TLBI_ALLE3)
5148 .monSecureWrite().monNonSecureWrite();
5149 InitReg(MISCREG_TLBI_VAE3_Xt)
5150 .monSecureWrite().monNonSecureWrite();
5151 InitReg(MISCREG_TLBI_VALE3_Xt)
5152 .monSecureWrite().monNonSecureWrite();
5153 InitReg(MISCREG_PMINTENSET_EL1)
5154 .allPrivileges().exceptUserMode()
5155 .mapsTo(MISCREG_PMINTENSET);
5156 InitReg(MISCREG_PMINTENCLR_EL1)
5157 .allPrivileges().exceptUserMode()
5158 .mapsTo(MISCREG_PMINTENCLR);
5159 InitReg(MISCREG_PMCR_EL0)
5160 .allPrivileges()
5161 .mapsTo(MISCREG_PMCR);
5162 InitReg(MISCREG_PMCNTENSET_EL0)
5163 .allPrivileges()
5164 .mapsTo(MISCREG_PMCNTENSET);
5165 InitReg(MISCREG_PMCNTENCLR_EL0)
5166 .allPrivileges()
5167 .mapsTo(MISCREG_PMCNTENCLR);
5168 InitReg(MISCREG_PMOVSCLR_EL0)
5169 .allPrivileges();
5170 // .mapsTo(MISCREG_PMOVSCLR);
5171 InitReg(MISCREG_PMSWINC_EL0)
5172 .writes(1).user()
5173 .mapsTo(MISCREG_PMSWINC);
5174 InitReg(MISCREG_PMSELR_EL0)
5175 .allPrivileges()
5176 .mapsTo(MISCREG_PMSELR);
5177 InitReg(MISCREG_PMCEID0_EL0)
5178 .reads(1).user()
5179 .mapsTo(MISCREG_PMCEID0);
5180 InitReg(MISCREG_PMCEID1_EL0)
5181 .reads(1).user()
5182 .mapsTo(MISCREG_PMCEID1);
5183 InitReg(MISCREG_PMCCNTR_EL0)
5184 .allPrivileges()
5185 .mapsTo(MISCREG_PMCCNTR);
5186 InitReg(MISCREG_PMXEVTYPER_EL0)
5187 .allPrivileges()
5188 .mapsTo(MISCREG_PMXEVTYPER);
5189 InitReg(MISCREG_PMCCFILTR_EL0)
5190 .allPrivileges();
5191 InitReg(MISCREG_PMXEVCNTR_EL0)
5192 .allPrivileges()
5193 .mapsTo(MISCREG_PMXEVCNTR);
5194 InitReg(MISCREG_PMUSERENR_EL0)
5195 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
5196 .mapsTo(MISCREG_PMUSERENR);
5197 InitReg(MISCREG_PMOVSSET_EL0)
5198 .allPrivileges()
5199 .mapsTo(MISCREG_PMOVSSET);
5200 InitReg(MISCREG_MAIR_EL1)
5201 .allPrivileges().exceptUserMode()
5202 .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
5203 InitReg(MISCREG_MAIR_EL12)
5204 .allPrivileges().exceptUserMode()
5205 .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
5206 InitReg(MISCREG_AMAIR_EL1)
5207 .allPrivileges().exceptUserMode()
5208 .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
5209 InitReg(MISCREG_AMAIR_EL12)
5210 .allPrivileges().exceptUserMode()
5211 .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
5212 InitReg(MISCREG_MAIR_EL2)
5213 .hyp().mon()
5214 .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1);
5215 InitReg(MISCREG_AMAIR_EL2)
5216 .hyp().mon()
5217 .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1);
5218 InitReg(MISCREG_MAIR_EL3)
5219 .mon();
5220 InitReg(MISCREG_AMAIR_EL3)
5221 .mon();
5222 InitReg(MISCREG_L2CTLR_EL1)
5223 .allPrivileges().exceptUserMode();
5224 InitReg(MISCREG_L2ECTLR_EL1)
5225 .allPrivileges().exceptUserMode();
5226 InitReg(MISCREG_VBAR_EL1)
5227 .allPrivileges().exceptUserMode()
5228 .mapsTo(MISCREG_VBAR_NS);
5229 InitReg(MISCREG_VBAR_EL12)
5230 .allPrivileges().exceptUserMode()
5231 .mapsTo(MISCREG_VBAR_NS);
5232 InitReg(MISCREG_RVBAR_EL1)
5233 .allPrivileges().exceptUserMode().writes(0);
5234 InitReg(MISCREG_ISR_EL1)
5235 .allPrivileges().exceptUserMode().writes(0);
5236 InitReg(MISCREG_VBAR_EL2)
5237 .hyp().mon()
5238 .res0(0x7ff)
5239 .mapsTo(MISCREG_HVBAR);
5240 InitReg(MISCREG_RVBAR_EL2)
5241 .mon().hyp().writes(0);
5242 InitReg(MISCREG_VBAR_EL3)
5243 .mon();
5244 InitReg(MISCREG_RVBAR_EL3)
5245 .mon().writes(0);
5246 InitReg(MISCREG_RMR_EL3)
5247 .mon();
5248 InitReg(MISCREG_CONTEXTIDR_EL1)
5249 .allPrivileges().exceptUserMode()
5250 .mapsTo(MISCREG_CONTEXTIDR_NS);
5251 InitReg(MISCREG_CONTEXTIDR_EL12)
5252 .allPrivileges().exceptUserMode()
5253 .mapsTo(MISCREG_CONTEXTIDR_NS);
5254 InitReg(MISCREG_TPIDR_EL1)
5255 .allPrivileges().exceptUserMode()
5256 .mapsTo(MISCREG_TPIDRPRW_NS);
5257 InitReg(MISCREG_TPIDR_EL0)
5258 .allPrivileges()
5259 .mapsTo(MISCREG_TPIDRURW_NS);
5260 InitReg(MISCREG_TPIDRRO_EL0)
5261 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
5262 .mapsTo(MISCREG_TPIDRURO_NS);
5263 InitReg(MISCREG_TPIDR_EL2)
5264 .hyp().mon()
5265 .mapsTo(MISCREG_HTPIDR);
5266 InitReg(MISCREG_TPIDR_EL3)
5267 .mon();
5268 // BEGIN Generic Timer (AArch64)
5269 InitReg(MISCREG_CNTFRQ_EL0)
5270 .reads(1)
5271 .highest(system)
5272 .privSecureWrite(aarch32EL3)
5273 .mapsTo(MISCREG_CNTFRQ);
5274 InitReg(MISCREG_CNTPCT_EL0)
5275 .unverifiable()
5276 .reads(1)
5277 .mapsTo(MISCREG_CNTPCT);
5278 InitReg(MISCREG_CNTVCT_EL0)
5279 .unverifiable()
5280 .reads(1)
5281 .mapsTo(MISCREG_CNTVCT);
5282 InitReg(MISCREG_CNTP_CTL_EL0)
5283 .allPrivileges()
5284 .res0(0xfffffffffffffff8)
5285 .mapsTo(MISCREG_CNTP_CTL_NS);
5286 InitReg(MISCREG_CNTP_CVAL_EL0)
5287 .allPrivileges()
5288 .mapsTo(MISCREG_CNTP_CVAL_NS);
5289 InitReg(MISCREG_CNTP_TVAL_EL0)
5290 .allPrivileges()
5291 .res0(0xffffffff00000000)
5292 .mapsTo(MISCREG_CNTP_TVAL_NS);
5293 InitReg(MISCREG_CNTV_CTL_EL0)
5294 .allPrivileges()
5295 .res0(0xfffffffffffffff8)
5296 .mapsTo(MISCREG_CNTV_CTL);
5297 InitReg(MISCREG_CNTV_CVAL_EL0)
5298 .allPrivileges()
5299 .mapsTo(MISCREG_CNTV_CVAL);
5300 InitReg(MISCREG_CNTV_TVAL_EL0)
5301 .allPrivileges()
5302 .res0(0xffffffff00000000)
5303 .mapsTo(MISCREG_CNTV_TVAL);
5304 InitReg(MISCREG_CNTP_CTL_EL02)
5305 .monE2H()
5306 .hypE2H()
5307 .res0(0xfffffffffffffff8)
5308 .mapsTo(MISCREG_CNTP_CTL_NS);
5309 InitReg(MISCREG_CNTP_CVAL_EL02)
5310 .monE2H()
5311 .hypE2H()
5312 .mapsTo(MISCREG_CNTP_CVAL_NS);
5313 InitReg(MISCREG_CNTP_TVAL_EL02)
5314 .monE2H()
5315 .hypE2H()
5316 .res0(0xffffffff00000000)
5317 .mapsTo(MISCREG_CNTP_TVAL_NS);
5318 InitReg(MISCREG_CNTV_CTL_EL02)
5319 .monE2H()
5320 .hypE2H()
5321 .res0(0xfffffffffffffff8)
5322 .mapsTo(MISCREG_CNTV_CTL);
5323 InitReg(MISCREG_CNTV_CVAL_EL02)
5324 .monE2H()
5325 .hypE2H()
5326 .mapsTo(MISCREG_CNTV_CVAL);
5327 InitReg(MISCREG_CNTV_TVAL_EL02)
5328 .monE2H()
5329 .hypE2H()
5330 .res0(0xffffffff00000000)
5331 .mapsTo(MISCREG_CNTV_TVAL);
5332 InitReg(MISCREG_CNTKCTL_EL1)
5333 .allPrivileges()
5334 .exceptUserMode()
5335 .res0(0xfffffffffffdfc00)
5336 .mapsTo(MISCREG_CNTKCTL);
5337 InitReg(MISCREG_CNTKCTL_EL12)
5338 .monE2H()
5339 .hypE2H()
5340 .res0(0xfffffffffffdfc00)
5341 .mapsTo(MISCREG_CNTKCTL);
5342 InitReg(MISCREG_CNTPS_CTL_EL1)
5343 .mon()
5344 .privSecure()
5345 .res0(0xfffffffffffffff8);
5346 InitReg(MISCREG_CNTPS_CVAL_EL1)
5347 .mon()
5348 .privSecure();
5349 InitReg(MISCREG_CNTPS_TVAL_EL1)
5350 .mon()
5351 .privSecure()
5352 .res0(0xffffffff00000000);
5353 InitReg(MISCREG_CNTHCTL_EL2)
5354 .mon()
5355 .hyp()
5356 .res0(0xfffffffffffc0000)
5357 .mapsTo(MISCREG_CNTHCTL);
5358 InitReg(MISCREG_CNTHP_CTL_EL2)
5359 .mon()
5360 .hyp()
5361 .res0(0xfffffffffffffff8)
5362 .mapsTo(MISCREG_CNTHP_CTL);
5363 InitReg(MISCREG_CNTHP_CVAL_EL2)
5364 .mon()
5365 .hyp()
5366 .mapsTo(MISCREG_CNTHP_CVAL);
5367 InitReg(MISCREG_CNTHP_TVAL_EL2)
5368 .mon()
5369 .hyp()
5370 .res0(0xffffffff00000000)
5371 .mapsTo(MISCREG_CNTHP_TVAL);
5372 InitReg(MISCREG_CNTHPS_CTL_EL2)
5373 .mon()
5374 .hyp()
5375 .res0(0xfffffffffffffff8)
5376 .unimplemented();
5377 InitReg(MISCREG_CNTHPS_CVAL_EL2)
5378 .mon()
5379 .hyp()
5380 .res0(0xfffffffffffffff8)
5381 .unimplemented();
5382 InitReg(MISCREG_CNTHPS_TVAL_EL2)
5383 .mon()
5384 .hyp()
5385 .res0(0xfffffffffffffff8)
5386 .unimplemented();
5387 InitReg(MISCREG_CNTHV_CTL_EL2)
5388 .mon()
5389 .hyp()
5390 .res0(0xfffffffffffffff8);
5391 InitReg(MISCREG_CNTHV_CVAL_EL2)
5392 .mon()
5393 .hyp();
5394 InitReg(MISCREG_CNTHV_TVAL_EL2)
5395 .mon()
5396 .hyp()
5397 .res0(0xffffffff00000000);
5398 InitReg(MISCREG_CNTHVS_CTL_EL2)
5399 .mon()
5400 .hyp()
5401 .res0(0xfffffffffffffff8)
5402 .unimplemented();
5403 InitReg(MISCREG_CNTHVS_CVAL_EL2)
5404 .mon()
5405 .hyp()
5406 .res0(0xfffffffffffffff8)
5407 .unimplemented();
5408 InitReg(MISCREG_CNTHVS_TVAL_EL2)
5409 .mon()
5410 .hyp()
5411 .res0(0xfffffffffffffff8)
5412 .unimplemented();
5413 // ENDIF Armv8.1-VHE
5414 InitReg(MISCREG_CNTVOFF_EL2)
5415 .mon()
5416 .hyp()
5417 .mapsTo(MISCREG_CNTVOFF);
5418 // END Generic Timer (AArch64)
5419 InitReg(MISCREG_PMEVCNTR0_EL0)
5420 .allPrivileges();
5421 // .mapsTo(MISCREG_PMEVCNTR0);
5422 InitReg(MISCREG_PMEVCNTR1_EL0)
5423 .allPrivileges();
5424 // .mapsTo(MISCREG_PMEVCNTR1);
5425 InitReg(MISCREG_PMEVCNTR2_EL0)
5426 .allPrivileges();
5427 // .mapsTo(MISCREG_PMEVCNTR2);
5428 InitReg(MISCREG_PMEVCNTR3_EL0)
5429 .allPrivileges();
5430 // .mapsTo(MISCREG_PMEVCNTR3);
5431 InitReg(MISCREG_PMEVCNTR4_EL0)
5432 .allPrivileges();
5433 // .mapsTo(MISCREG_PMEVCNTR4);
5434 InitReg(MISCREG_PMEVCNTR5_EL0)
5435 .allPrivileges();
5436 // .mapsTo(MISCREG_PMEVCNTR5);
5437 InitReg(MISCREG_PMEVTYPER0_EL0)
5438 .allPrivileges();
5439 // .mapsTo(MISCREG_PMEVTYPER0);
5440 InitReg(MISCREG_PMEVTYPER1_EL0)
5441 .allPrivileges();
5442 // .mapsTo(MISCREG_PMEVTYPER1);
5443 InitReg(MISCREG_PMEVTYPER2_EL0)
5444 .allPrivileges();
5445 // .mapsTo(MISCREG_PMEVTYPER2);
5446 InitReg(MISCREG_PMEVTYPER3_EL0)
5447 .allPrivileges();
5448 // .mapsTo(MISCREG_PMEVTYPER3);
5449 InitReg(MISCREG_PMEVTYPER4_EL0)
5450 .allPrivileges();
5451 // .mapsTo(MISCREG_PMEVTYPER4);
5452 InitReg(MISCREG_PMEVTYPER5_EL0)
5453 .allPrivileges();
5454 // .mapsTo(MISCREG_PMEVTYPER5);
5455 InitReg(MISCREG_IL1DATA0_EL1)
5456 .allPrivileges().exceptUserMode();
5457 InitReg(MISCREG_IL1DATA1_EL1)
5458 .allPrivileges().exceptUserMode();
5459 InitReg(MISCREG_IL1DATA2_EL1)
5460 .allPrivileges().exceptUserMode();
5461 InitReg(MISCREG_IL1DATA3_EL1)
5462 .allPrivileges().exceptUserMode();
5463 InitReg(MISCREG_DL1DATA0_EL1)
5464 .allPrivileges().exceptUserMode();
5465 InitReg(MISCREG_DL1DATA1_EL1)
5466 .allPrivileges().exceptUserMode();
5467 InitReg(MISCREG_DL1DATA2_EL1)
5468 .allPrivileges().exceptUserMode();
5469 InitReg(MISCREG_DL1DATA3_EL1)
5470 .allPrivileges().exceptUserMode();
5471 InitReg(MISCREG_DL1DATA4_EL1)
5472 .allPrivileges().exceptUserMode();
5473 InitReg(MISCREG_L2ACTLR_EL1)
5474 .allPrivileges().exceptUserMode();
5475 InitReg(MISCREG_CPUACTLR_EL1)
5476 .allPrivileges().exceptUserMode();
5477 InitReg(MISCREG_CPUECTLR_EL1)
5478 .allPrivileges().exceptUserMode();
5479 InitReg(MISCREG_CPUMERRSR_EL1)
5480 .allPrivileges().exceptUserMode();
5481 InitReg(MISCREG_L2MERRSR_EL1)
5482 .unimplemented()
5483 .warnNotFail()
5484 .allPrivileges().exceptUserMode();
5485 InitReg(MISCREG_CBAR_EL1)
5486 .allPrivileges().exceptUserMode().writes(0);
5487 InitReg(MISCREG_CONTEXTIDR_EL2)
5488 .mon().hyp();
5489
5490 // GICv3 AArch64
5491 InitReg(MISCREG_ICC_PMR_EL1)
5492 .res0(0xffffff00) // [31:8]
5493 .allPrivileges().exceptUserMode()
5494 .mapsTo(MISCREG_ICC_PMR);
5495 InitReg(MISCREG_ICC_IAR0_EL1)
5496 .allPrivileges().exceptUserMode().writes(0)
5497 .mapsTo(MISCREG_ICC_IAR0);
5498 InitReg(MISCREG_ICC_EOIR0_EL1)
5499 .allPrivileges().exceptUserMode().reads(0)
5500 .mapsTo(MISCREG_ICC_EOIR0);
5501 InitReg(MISCREG_ICC_HPPIR0_EL1)
5502 .allPrivileges().exceptUserMode().writes(0)
5503 .mapsTo(MISCREG_ICC_HPPIR0);
5504 InitReg(MISCREG_ICC_BPR0_EL1)
5505 .res0(0xfffffff8) // [31:3]
5506 .allPrivileges().exceptUserMode()
5507 .mapsTo(MISCREG_ICC_BPR0);
5508 InitReg(MISCREG_ICC_AP0R0_EL1)
5509 .allPrivileges().exceptUserMode()
5510 .mapsTo(MISCREG_ICC_AP0R0);
5511 InitReg(MISCREG_ICC_AP0R1_EL1)
5512 .allPrivileges().exceptUserMode()
5513 .mapsTo(MISCREG_ICC_AP0R1);
5514 InitReg(MISCREG_ICC_AP0R2_EL1)
5515 .allPrivileges().exceptUserMode()
5516 .mapsTo(MISCREG_ICC_AP0R2);
5517 InitReg(MISCREG_ICC_AP0R3_EL1)
5518 .allPrivileges().exceptUserMode()
5519 .mapsTo(MISCREG_ICC_AP0R3);
5520 InitReg(MISCREG_ICC_AP1R0_EL1)
5521 .banked64()
5522 .mapsTo(MISCREG_ICC_AP1R0);
5523 InitReg(MISCREG_ICC_AP1R0_EL1_NS)
5524 .bankedChild()
5525 .allPrivileges().exceptUserMode()
5526 .mapsTo(MISCREG_ICC_AP1R0_NS);
5527 InitReg(MISCREG_ICC_AP1R0_EL1_S)
5528 .bankedChild()
5529 .allPrivileges().exceptUserMode()
5530 .mapsTo(MISCREG_ICC_AP1R0_S);
5531 InitReg(MISCREG_ICC_AP1R1_EL1)
5532 .banked64()
5533 .mapsTo(MISCREG_ICC_AP1R1);
5534 InitReg(MISCREG_ICC_AP1R1_EL1_NS)
5535 .bankedChild()
5536 .allPrivileges().exceptUserMode()
5537 .mapsTo(MISCREG_ICC_AP1R1_NS);
5538 InitReg(MISCREG_ICC_AP1R1_EL1_S)
5539 .bankedChild()
5540 .allPrivileges().exceptUserMode()
5541 .mapsTo(MISCREG_ICC_AP1R1_S);
5542 InitReg(MISCREG_ICC_AP1R2_EL1)
5543 .banked64()
5544 .mapsTo(MISCREG_ICC_AP1R2);
5545 InitReg(MISCREG_ICC_AP1R2_EL1_NS)
5546 .bankedChild()
5547 .allPrivileges().exceptUserMode()
5548 .mapsTo(MISCREG_ICC_AP1R2_NS);
5549 InitReg(MISCREG_ICC_AP1R2_EL1_S)
5550 .bankedChild()
5551 .allPrivileges().exceptUserMode()
5552 .mapsTo(MISCREG_ICC_AP1R2_S);
5553 InitReg(MISCREG_ICC_AP1R3_EL1)
5554 .banked64()
5555 .mapsTo(MISCREG_ICC_AP1R3);
5556 InitReg(MISCREG_ICC_AP1R3_EL1_NS)
5557 .bankedChild()
5558 .allPrivileges().exceptUserMode()
5559 .mapsTo(MISCREG_ICC_AP1R3_NS);
5560 InitReg(MISCREG_ICC_AP1R3_EL1_S)
5561 .bankedChild()
5562 .allPrivileges().exceptUserMode()
5563 .mapsTo(MISCREG_ICC_AP1R3_S);
5564 InitReg(MISCREG_ICC_DIR_EL1)
5565 .res0(0xFF000000) // [31:24]
5566 .allPrivileges().exceptUserMode().reads(0)
5567 .mapsTo(MISCREG_ICC_DIR);
5568 InitReg(MISCREG_ICC_RPR_EL1)
5569 .allPrivileges().exceptUserMode().writes(0)
5570 .mapsTo(MISCREG_ICC_RPR);
5571 InitReg(MISCREG_ICC_SGI1R_EL1)
5572 .allPrivileges().exceptUserMode().reads(0)
5573 .mapsTo(MISCREG_ICC_SGI1R);
5574 InitReg(MISCREG_ICC_ASGI1R_EL1)
5575 .allPrivileges().exceptUserMode().reads(0)
5576 .mapsTo(MISCREG_ICC_ASGI1R);
5577 InitReg(MISCREG_ICC_SGI0R_EL1)
5578 .allPrivileges().exceptUserMode().reads(0)
5579 .mapsTo(MISCREG_ICC_SGI0R);
5580 InitReg(MISCREG_ICC_IAR1_EL1)
5581 .allPrivileges().exceptUserMode().writes(0)
5582 .mapsTo(MISCREG_ICC_IAR1);
5583 InitReg(MISCREG_ICC_EOIR1_EL1)
5584 .res0(0xFF000000) // [31:24]
5585 .allPrivileges().exceptUserMode().reads(0)
5586 .mapsTo(MISCREG_ICC_EOIR1);
5587 InitReg(MISCREG_ICC_HPPIR1_EL1)
5588 .allPrivileges().exceptUserMode().writes(0)
5589 .mapsTo(MISCREG_ICC_HPPIR1);
5590 InitReg(MISCREG_ICC_BPR1_EL1)
5591 .banked64()
5592 .mapsTo(MISCREG_ICC_BPR1);
5593 InitReg(MISCREG_ICC_BPR1_EL1_NS)
5594 .bankedChild()
5595 .res0(0xfffffff8) // [31:3]
5596 .allPrivileges().exceptUserMode()
5597 .mapsTo(MISCREG_ICC_BPR1_NS);
5598 InitReg(MISCREG_ICC_BPR1_EL1_S)
5599 .bankedChild()
5600 .res0(0xfffffff8) // [31:3]
5601 .secure().exceptUserMode()
5602 .mapsTo(MISCREG_ICC_BPR1_S);
5603 InitReg(MISCREG_ICC_CTLR_EL1)
5604 .banked64()
5605 .mapsTo(MISCREG_ICC_CTLR);
5606 InitReg(MISCREG_ICC_CTLR_EL1_NS)
5607 .bankedChild()
5608 .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
5609 .allPrivileges().exceptUserMode()
5610 .mapsTo(MISCREG_ICC_CTLR_NS);
5611 InitReg(MISCREG_ICC_CTLR_EL1_S)
5612 .bankedChild()
5613 .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
5614 .secure().exceptUserMode()
5615 .mapsTo(MISCREG_ICC_CTLR_S);
5616 InitReg(MISCREG_ICC_SRE_EL1)
5617 .banked()
5618 .mapsTo(MISCREG_ICC_SRE);
5619 InitReg(MISCREG_ICC_SRE_EL1_NS)
5620 .bankedChild()
5621 .res0(0xFFFFFFF8) // [31:3]
5622 .allPrivileges().exceptUserMode()
5623 .mapsTo(MISCREG_ICC_SRE_NS);
5624 InitReg(MISCREG_ICC_SRE_EL1_S)
5625 .bankedChild()
5626 .res0(0xFFFFFFF8) // [31:3]
5627 .secure().exceptUserMode()
5628 .mapsTo(MISCREG_ICC_SRE_S);
5629 InitReg(MISCREG_ICC_IGRPEN0_EL1)
5630 .res0(0xFFFFFFFE) // [31:1]
5631 .allPrivileges().exceptUserMode()
5632 .mapsTo(MISCREG_ICC_IGRPEN0);
5633 InitReg(MISCREG_ICC_IGRPEN1_EL1)
5634 .banked64()
5635 .mapsTo(MISCREG_ICC_IGRPEN1);
5636 InitReg(MISCREG_ICC_IGRPEN1_EL1_NS)
5637 .bankedChild()
5638 .res0(0xFFFFFFFE) // [31:1]
5639 .allPrivileges().exceptUserMode()
5640 .mapsTo(MISCREG_ICC_IGRPEN1_NS);
5641 InitReg(MISCREG_ICC_IGRPEN1_EL1_S)
5642 .bankedChild()
5643 .res0(0xFFFFFFFE) // [31:1]
5644 .secure().exceptUserMode()
5645 .mapsTo(MISCREG_ICC_IGRPEN1_S);
5646 InitReg(MISCREG_ICC_SRE_EL2)
5647 .hyp().mon()
5648 .mapsTo(MISCREG_ICC_HSRE);
5649 InitReg(MISCREG_ICC_CTLR_EL3)
5650 .allPrivileges().exceptUserMode()
5651 .mapsTo(MISCREG_ICC_MCTLR);
5652 InitReg(MISCREG_ICC_SRE_EL3)
5653 .allPrivileges().exceptUserMode()
5654 .mapsTo(MISCREG_ICC_MSRE);
5655 InitReg(MISCREG_ICC_IGRPEN1_EL3)
5656 .allPrivileges().exceptUserMode()
5657 .mapsTo(MISCREG_ICC_MGRPEN1);
5658
5659 InitReg(MISCREG_ICH_AP0R0_EL2)
5660 .hyp().mon()
5661 .mapsTo(MISCREG_ICH_AP0R0);
5662 InitReg(MISCREG_ICH_AP0R1_EL2)
5663 .hyp().mon()
5664 .unimplemented()
5665 .mapsTo(MISCREG_ICH_AP0R1);
5666 InitReg(MISCREG_ICH_AP0R2_EL2)
5667 .hyp().mon()
5668 .unimplemented()
5669 .mapsTo(MISCREG_ICH_AP0R2);
5670 InitReg(MISCREG_ICH_AP0R3_EL2)
5671 .hyp().mon()
5672 .unimplemented()
5673 .mapsTo(MISCREG_ICH_AP0R3);
5674 InitReg(MISCREG_ICH_AP1R0_EL2)
5675 .hyp().mon()
5676 .mapsTo(MISCREG_ICH_AP1R0);
5677 InitReg(MISCREG_ICH_AP1R1_EL2)
5678 .hyp().mon()
5679 .unimplemented()
5680 .mapsTo(MISCREG_ICH_AP1R1);
5681 InitReg(MISCREG_ICH_AP1R2_EL2)
5682 .hyp().mon()
5683 .unimplemented()
5684 .mapsTo(MISCREG_ICH_AP1R2);
5685 InitReg(MISCREG_ICH_AP1R3_EL2)
5686 .hyp().mon()
5687 .unimplemented()
5688 .mapsTo(MISCREG_ICH_AP1R3);
5689 InitReg(MISCREG_ICH_HCR_EL2)
5690 .hyp().mon()
5691 .mapsTo(MISCREG_ICH_HCR);
5692 InitReg(MISCREG_ICH_VTR_EL2)
5693 .hyp().mon().writes(0)
5694 .mapsTo(MISCREG_ICH_VTR);
5695 InitReg(MISCREG_ICH_MISR_EL2)
5696 .hyp().mon().writes(0)
5697 .mapsTo(MISCREG_ICH_MISR);
5698 InitReg(MISCREG_ICH_EISR_EL2)
5699 .hyp().mon().writes(0)
5700 .mapsTo(MISCREG_ICH_EISR);
5701 InitReg(MISCREG_ICH_ELRSR_EL2)
5702 .hyp().mon().writes(0)
5703 .mapsTo(MISCREG_ICH_ELRSR);
5704 InitReg(MISCREG_ICH_VMCR_EL2)
5705 .hyp().mon()
5706 .mapsTo(MISCREG_ICH_VMCR);
5707 InitReg(MISCREG_ICH_LR0_EL2)
5708 .hyp().mon()
5709 .allPrivileges().exceptUserMode();
5710 InitReg(MISCREG_ICH_LR1_EL2)
5711 .hyp().mon()
5712 .allPrivileges().exceptUserMode();
5713 InitReg(MISCREG_ICH_LR2_EL2)
5714 .hyp().mon()
5715 .allPrivileges().exceptUserMode();
5716 InitReg(MISCREG_ICH_LR3_EL2)
5717 .hyp().mon()
5718 .allPrivileges().exceptUserMode();
5719 InitReg(MISCREG_ICH_LR4_EL2)
5720 .hyp().mon()
5721 .allPrivileges().exceptUserMode();
5722 InitReg(MISCREG_ICH_LR5_EL2)
5723 .hyp().mon()
5724 .allPrivileges().exceptUserMode();
5725 InitReg(MISCREG_ICH_LR6_EL2)
5726 .hyp().mon()
5727 .allPrivileges().exceptUserMode();
5728 InitReg(MISCREG_ICH_LR7_EL2)
5729 .hyp().mon()
5730 .allPrivileges().exceptUserMode();
5731 InitReg(MISCREG_ICH_LR8_EL2)
5732 .hyp().mon()
5733 .allPrivileges().exceptUserMode();
5734 InitReg(MISCREG_ICH_LR9_EL2)
5735 .hyp().mon()
5736 .allPrivileges().exceptUserMode();
5737 InitReg(MISCREG_ICH_LR10_EL2)
5738 .hyp().mon()
5739 .allPrivileges().exceptUserMode();
5740 InitReg(MISCREG_ICH_LR11_EL2)
5741 .hyp().mon()
5742 .allPrivileges().exceptUserMode();
5743 InitReg(MISCREG_ICH_LR12_EL2)
5744 .hyp().mon()
5745 .allPrivileges().exceptUserMode();
5746 InitReg(MISCREG_ICH_LR13_EL2)
5747 .hyp().mon()
5748 .allPrivileges().exceptUserMode();
5749 InitReg(MISCREG_ICH_LR14_EL2)
5750 .hyp().mon()
5751 .allPrivileges().exceptUserMode();
5752 InitReg(MISCREG_ICH_LR15_EL2)
5753 .hyp().mon()
5754 .allPrivileges().exceptUserMode();
5755
5756 // GICv3 AArch32
5757 InitReg(MISCREG_ICC_AP0R0)
5758 .allPrivileges().exceptUserMode();
5759 InitReg(MISCREG_ICC_AP0R1)
5760 .allPrivileges().exceptUserMode();
5761 InitReg(MISCREG_ICC_AP0R2)
5762 .allPrivileges().exceptUserMode();
5763 InitReg(MISCREG_ICC_AP0R3)
5764 .allPrivileges().exceptUserMode();
5765 InitReg(MISCREG_ICC_AP1R0)
5766 .allPrivileges().exceptUserMode();
5767 InitReg(MISCREG_ICC_AP1R0_NS)
5768 .allPrivileges().exceptUserMode();
5769 InitReg(MISCREG_ICC_AP1R0_S)
5770 .allPrivileges().exceptUserMode();
5771 InitReg(MISCREG_ICC_AP1R1)
5772 .allPrivileges().exceptUserMode();
5773 InitReg(MISCREG_ICC_AP1R1_NS)
5774 .allPrivileges().exceptUserMode();
5775 InitReg(MISCREG_ICC_AP1R1_S)
5776 .allPrivileges().exceptUserMode();
5777 InitReg(MISCREG_ICC_AP1R2)
5778 .allPrivileges().exceptUserMode();
5779 InitReg(MISCREG_ICC_AP1R2_NS)
5780 .allPrivileges().exceptUserMode();
5781 InitReg(MISCREG_ICC_AP1R2_S)
5782 .allPrivileges().exceptUserMode();
5783 InitReg(MISCREG_ICC_AP1R3)
5784 .allPrivileges().exceptUserMode();
5785 InitReg(MISCREG_ICC_AP1R3_NS)
5786 .allPrivileges().exceptUserMode();
5787 InitReg(MISCREG_ICC_AP1R3_S)
5788 .allPrivileges().exceptUserMode();
5789 InitReg(MISCREG_ICC_ASGI1R)
5790 .allPrivileges().exceptUserMode().reads(0);
5791 InitReg(MISCREG_ICC_BPR0)
5792 .allPrivileges().exceptUserMode();
5793 InitReg(MISCREG_ICC_BPR1)
5794 .allPrivileges().exceptUserMode();
5795 InitReg(MISCREG_ICC_BPR1_NS)
5796 .allPrivileges().exceptUserMode();
5797 InitReg(MISCREG_ICC_BPR1_S)
5798 .allPrivileges().exceptUserMode();
5799 InitReg(MISCREG_ICC_CTLR)
5800 .allPrivileges().exceptUserMode();
5801 InitReg(MISCREG_ICC_CTLR_NS)
5802 .allPrivileges().exceptUserMode();
5803 InitReg(MISCREG_ICC_CTLR_S)
5804 .allPrivileges().exceptUserMode();
5805 InitReg(MISCREG_ICC_DIR)
5806 .allPrivileges().exceptUserMode().reads(0);
5807 InitReg(MISCREG_ICC_EOIR0)
5808 .allPrivileges().exceptUserMode().reads(0);
5809 InitReg(MISCREG_ICC_EOIR1)
5810 .allPrivileges().exceptUserMode().reads(0);
5811 InitReg(MISCREG_ICC_HPPIR0)
5812 .allPrivileges().exceptUserMode().writes(0);
5813 InitReg(MISCREG_ICC_HPPIR1)
5814 .allPrivileges().exceptUserMode().writes(0);
5815 InitReg(MISCREG_ICC_HSRE)
5816 .allPrivileges().exceptUserMode();
5817 InitReg(MISCREG_ICC_IAR0)
5818 .allPrivileges().exceptUserMode().writes(0);
5819 InitReg(MISCREG_ICC_IAR1)
5820 .allPrivileges().exceptUserMode().writes(0);
5821 InitReg(MISCREG_ICC_IGRPEN0)
5822 .allPrivileges().exceptUserMode();
5823 InitReg(MISCREG_ICC_IGRPEN1)
5824 .allPrivileges().exceptUserMode();
5825 InitReg(MISCREG_ICC_IGRPEN1_NS)
5826 .allPrivileges().exceptUserMode();
5827 InitReg(MISCREG_ICC_IGRPEN1_S)
5828 .allPrivileges().exceptUserMode();
5829 InitReg(MISCREG_ICC_MCTLR)
5830 .allPrivileges().exceptUserMode();
5831 InitReg(MISCREG_ICC_MGRPEN1)
5832 .allPrivileges().exceptUserMode();
5833 InitReg(MISCREG_ICC_MSRE)
5834 .allPrivileges().exceptUserMode();
5835 InitReg(MISCREG_ICC_PMR)
5836 .allPrivileges().exceptUserMode();
5837 InitReg(MISCREG_ICC_RPR)
5838 .allPrivileges().exceptUserMode().writes(0);
5839 InitReg(MISCREG_ICC_SGI0R)
5840 .allPrivileges().exceptUserMode().reads(0);
5841 InitReg(MISCREG_ICC_SGI1R)
5842 .allPrivileges().exceptUserMode().reads(0);
5843 InitReg(MISCREG_ICC_SRE)
5844 .allPrivileges().exceptUserMode();
5845 InitReg(MISCREG_ICC_SRE_NS)
5846 .allPrivileges().exceptUserMode();
5847 InitReg(MISCREG_ICC_SRE_S)
5848 .allPrivileges().exceptUserMode();
5849
5850 InitReg(MISCREG_ICH_AP0R0)
5851 .hyp().mon();
5852 InitReg(MISCREG_ICH_AP0R1)
5853 .hyp().mon();
5854 InitReg(MISCREG_ICH_AP0R2)
5855 .hyp().mon();
5856 InitReg(MISCREG_ICH_AP0R3)
5857 .hyp().mon();
5858 InitReg(MISCREG_ICH_AP1R0)
5859 .hyp().mon();
5860 InitReg(MISCREG_ICH_AP1R1)
5861 .hyp().mon();
5862 InitReg(MISCREG_ICH_AP1R2)
5863 .hyp().mon();
5864 InitReg(MISCREG_ICH_AP1R3)
5865 .hyp().mon();
5866 InitReg(MISCREG_ICH_HCR)
5867 .hyp().mon();
5868 InitReg(MISCREG_ICH_VTR)
5869 .hyp().mon().writes(0);
5870 InitReg(MISCREG_ICH_MISR)
5871 .hyp().mon().writes(0);
5872 InitReg(MISCREG_ICH_EISR)
5873 .hyp().mon().writes(0);
5874 InitReg(MISCREG_ICH_ELRSR)
5875 .hyp().mon().writes(0);
5876 InitReg(MISCREG_ICH_VMCR)
5877 .hyp().mon();
5878 InitReg(MISCREG_ICH_LR0)
5879 .hyp().mon();
5880 InitReg(MISCREG_ICH_LR1)
5881 .hyp().mon();
5882 InitReg(MISCREG_ICH_LR2)
5883 .hyp().mon();
5884 InitReg(MISCREG_ICH_LR3)
5885 .hyp().mon();
5886 InitReg(MISCREG_ICH_LR4)
5887 .hyp().mon();
5888 InitReg(MISCREG_ICH_LR5)
5889 .hyp().mon();
5890 InitReg(MISCREG_ICH_LR6)
5891 .hyp().mon();
5892 InitReg(MISCREG_ICH_LR7)
5893 .hyp().mon();
5894 InitReg(MISCREG_ICH_LR8)
5895 .hyp().mon();
5896 InitReg(MISCREG_ICH_LR9)
5897 .hyp().mon();
5898 InitReg(MISCREG_ICH_LR10)
5899 .hyp().mon();
5900 InitReg(MISCREG_ICH_LR11)
5901 .hyp().mon();
5902 InitReg(MISCREG_ICH_LR12)
5903 .hyp().mon();
5904 InitReg(MISCREG_ICH_LR13)
5905 .hyp().mon();
5906 InitReg(MISCREG_ICH_LR14)
5907 .hyp().mon();
5908 InitReg(MISCREG_ICH_LR15)
5909 .hyp().mon();
5910 InitReg(MISCREG_ICH_LRC0)
5911 .mapsTo(MISCREG_ICH_LR0)
5912 .hyp().mon();
5913 InitReg(MISCREG_ICH_LRC1)
5914 .mapsTo(MISCREG_ICH_LR1)
5915 .hyp().mon();
5916 InitReg(MISCREG_ICH_LRC2)
5917 .mapsTo(MISCREG_ICH_LR2)
5918 .hyp().mon();
5919 InitReg(MISCREG_ICH_LRC3)
5920 .mapsTo(MISCREG_ICH_LR3)
5921 .hyp().mon();
5922 InitReg(MISCREG_ICH_LRC4)
5923 .mapsTo(MISCREG_ICH_LR4)
5924 .hyp().mon();
5925 InitReg(MISCREG_ICH_LRC5)
5926 .mapsTo(MISCREG_ICH_LR5)
5927 .hyp().mon();
5928 InitReg(MISCREG_ICH_LRC6)
5929 .mapsTo(MISCREG_ICH_LR6)
5930 .hyp().mon();
5931 InitReg(MISCREG_ICH_LRC7)
5932 .mapsTo(MISCREG_ICH_LR7)
5933 .hyp().mon();
5934 InitReg(MISCREG_ICH_LRC8)
5935 .mapsTo(MISCREG_ICH_LR8)
5936 .hyp().mon();
5937 InitReg(MISCREG_ICH_LRC9)
5938 .mapsTo(MISCREG_ICH_LR9)
5939 .hyp().mon();
5940 InitReg(MISCREG_ICH_LRC10)
5941 .mapsTo(MISCREG_ICH_LR10)
5942 .hyp().mon();
5943 InitReg(MISCREG_ICH_LRC11)
5944 .mapsTo(MISCREG_ICH_LR11)
5945 .hyp().mon();
5946 InitReg(MISCREG_ICH_LRC12)
5947 .mapsTo(MISCREG_ICH_LR12)
5948 .hyp().mon();
5949 InitReg(MISCREG_ICH_LRC13)
5950 .mapsTo(MISCREG_ICH_LR13)
5951 .hyp().mon();
5952 InitReg(MISCREG_ICH_LRC14)
5953 .mapsTo(MISCREG_ICH_LR14)
5954 .hyp().mon();
5955 InitReg(MISCREG_ICH_LRC15)
5956 .mapsTo(MISCREG_ICH_LR15)
5957 .hyp().mon();
5958
5959 // SVE
5960 InitReg(MISCREG_ID_AA64ZFR0_EL1)
5961 .allPrivileges().exceptUserMode().writes(0);
5962 InitReg(MISCREG_ZCR_EL3)
5963 .mon();
5964 InitReg(MISCREG_ZCR_EL2)
5965 .hyp().mon();
5966 InitReg(MISCREG_ZCR_EL12)
5967 .allPrivileges().exceptUserMode()
5968 .mapsTo(MISCREG_ZCR_EL1);
5969 InitReg(MISCREG_ZCR_EL1)
5970 .allPrivileges().exceptUserMode();
5971
5972 // Dummy registers
5973 InitReg(MISCREG_NOP)
5974 .allPrivileges();
5975 InitReg(MISCREG_RAZ)
5976 .allPrivileges().exceptUserMode().writes(0);
5977 InitReg(MISCREG_CP14_UNIMPL)
5978 .unimplemented()
5979 .warnNotFail();
5980 InitReg(MISCREG_CP15_UNIMPL)
5981 .unimplemented()
5982 .warnNotFail();
5983 InitReg(MISCREG_UNKNOWN);
5984 InitReg(MISCREG_IMPDEF_UNIMPL)
5985 .unimplemented()
5986 .warnNotFail(impdefAsNop);
5987
5988 // RAS extension (unimplemented)
5989 InitReg(MISCREG_ERRIDR_EL1)
5990 .unimplemented()
5991 .warnNotFail();
5992 InitReg(MISCREG_ERRSELR_EL1)
5993 .unimplemented()
5994 .warnNotFail();
5995 InitReg(MISCREG_ERXFR_EL1)
5996 .unimplemented()
5997 .warnNotFail();
5998 InitReg(MISCREG_ERXCTLR_EL1)
5999 .unimplemented()
6000 .warnNotFail();
6001 InitReg(MISCREG_ERXSTATUS_EL1)
6002 .unimplemented()
6003 .warnNotFail();
6004 InitReg(MISCREG_ERXADDR_EL1)
6005 .unimplemented()
6006 .warnNotFail();
6007 InitReg(MISCREG_ERXMISC0_EL1)
6008 .unimplemented()
6009 .warnNotFail();
6010 InitReg(MISCREG_ERXMISC1_EL1)
6011 .unimplemented()
6012 .warnNotFail();
6013 InitReg(MISCREG_DISR_EL1)
6014 .unimplemented()
6015 .warnNotFail();
6016 InitReg(MISCREG_VSESR_EL2)
6017 .unimplemented()
6018 .warnNotFail();
6019 InitReg(MISCREG_VDISR_EL2)
6020 .unimplemented()
6021 .warnNotFail();
6022
6023 // Register mappings for some unimplemented registers:
6024 // ESR_EL1 -> DFSR
6025 // RMR_EL1 -> RMR
6026 // RMR_EL2 -> HRMR
6027 // DBGDTR_EL0 -> DBGDTR{R or T}Xint
6028 // DBGDTRRX_EL0 -> DBGDTRRXint
6029 // DBGDTRTX_EL0 -> DBGDTRRXint
6030 // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
6031
6032 completed = true;
6033 }
6034
6035 } // namespace ArmISA