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mem-cache: Add multiple eviction stats
[gem5.git] / src / arch / arm / miscregs.cc
1 /*
2 * Copyright (c) 2010-2013, 2015-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 * Giacomo Gabrielli
40 */
41
42 #include "arch/arm/miscregs.hh"
43
44 #include <tuple>
45
46 #include "arch/arm/isa.hh"
47 #include "base/logging.hh"
48 #include "cpu/thread_context.hh"
49 #include "sim/full_system.hh"
50
51 namespace ArmISA
52 {
53
54 MiscRegIndex
55 decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
56 {
57 switch(crn) {
58 case 0:
59 switch (opc1) {
60 case 0:
61 switch (opc2) {
62 case 0:
63 switch (crm) {
64 case 0:
65 return MISCREG_DBGDIDR;
66 case 1:
67 return MISCREG_DBGDSCRint;
68 }
69 break;
70 }
71 break;
72 case 7:
73 switch (opc2) {
74 case 0:
75 switch (crm) {
76 case 0:
77 return MISCREG_JIDR;
78 }
79 break;
80 }
81 break;
82 }
83 break;
84 case 1:
85 switch (opc1) {
86 case 6:
87 switch (crm) {
88 case 0:
89 switch (opc2) {
90 case 0:
91 return MISCREG_TEEHBR;
92 }
93 break;
94 }
95 break;
96 case 7:
97 switch (crm) {
98 case 0:
99 switch (opc2) {
100 case 0:
101 return MISCREG_JOSCR;
102 }
103 break;
104 }
105 break;
106 }
107 break;
108 case 2:
109 switch (opc1) {
110 case 7:
111 switch (crm) {
112 case 0:
113 switch (opc2) {
114 case 0:
115 return MISCREG_JMCR;
116 }
117 break;
118 }
119 break;
120 }
121 break;
122 }
123 // If we get here then it must be a register that we haven't implemented
124 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
125 crn, opc1, crm, opc2);
126 return MISCREG_CP14_UNIMPL;
127 }
128
129 using namespace std;
130
131 MiscRegIndex
132 decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
133 {
134 switch (crn) {
135 case 0:
136 switch (opc1) {
137 case 0:
138 switch (crm) {
139 case 0:
140 switch (opc2) {
141 case 1:
142 return MISCREG_CTR;
143 case 2:
144 return MISCREG_TCMTR;
145 case 3:
146 return MISCREG_TLBTR;
147 case 5:
148 return MISCREG_MPIDR;
149 case 6:
150 return MISCREG_REVIDR;
151 default:
152 return MISCREG_MIDR;
153 }
154 break;
155 case 1:
156 switch (opc2) {
157 case 0:
158 return MISCREG_ID_PFR0;
159 case 1:
160 return MISCREG_ID_PFR1;
161 case 2:
162 return MISCREG_ID_DFR0;
163 case 3:
164 return MISCREG_ID_AFR0;
165 case 4:
166 return MISCREG_ID_MMFR0;
167 case 5:
168 return MISCREG_ID_MMFR1;
169 case 6:
170 return MISCREG_ID_MMFR2;
171 case 7:
172 return MISCREG_ID_MMFR3;
173 }
174 break;
175 case 2:
176 switch (opc2) {
177 case 0:
178 return MISCREG_ID_ISAR0;
179 case 1:
180 return MISCREG_ID_ISAR1;
181 case 2:
182 return MISCREG_ID_ISAR2;
183 case 3:
184 return MISCREG_ID_ISAR3;
185 case 4:
186 return MISCREG_ID_ISAR4;
187 case 5:
188 return MISCREG_ID_ISAR5;
189 case 6:
190 case 7:
191 return MISCREG_RAZ; // read as zero
192 }
193 break;
194 default:
195 return MISCREG_RAZ; // read as zero
196 }
197 break;
198 case 1:
199 if (crm == 0) {
200 switch (opc2) {
201 case 0:
202 return MISCREG_CCSIDR;
203 case 1:
204 return MISCREG_CLIDR;
205 case 7:
206 return MISCREG_AIDR;
207 }
208 }
209 break;
210 case 2:
211 if (crm == 0 && opc2 == 0) {
212 return MISCREG_CSSELR;
213 }
214 break;
215 case 4:
216 if (crm == 0) {
217 if (opc2 == 0)
218 return MISCREG_VPIDR;
219 else if (opc2 == 5)
220 return MISCREG_VMPIDR;
221 }
222 break;
223 }
224 break;
225 case 1:
226 if (opc1 == 0) {
227 if (crm == 0) {
228 switch (opc2) {
229 case 0:
230 return MISCREG_SCTLR;
231 case 1:
232 return MISCREG_ACTLR;
233 case 0x2:
234 return MISCREG_CPACR;
235 }
236 } else if (crm == 1) {
237 switch (opc2) {
238 case 0:
239 return MISCREG_SCR;
240 case 1:
241 return MISCREG_SDER;
242 case 2:
243 return MISCREG_NSACR;
244 }
245 }
246 } else if (opc1 == 4) {
247 if (crm == 0) {
248 if (opc2 == 0)
249 return MISCREG_HSCTLR;
250 else if (opc2 == 1)
251 return MISCREG_HACTLR;
252 } else if (crm == 1) {
253 switch (opc2) {
254 case 0:
255 return MISCREG_HCR;
256 case 1:
257 return MISCREG_HDCR;
258 case 2:
259 return MISCREG_HCPTR;
260 case 4:
261 return MISCREG_HCR2;
262 case 3:
263 return MISCREG_HSTR;
264 case 7:
265 return MISCREG_HACR;
266 }
267 }
268 }
269 break;
270 case 2:
271 if (opc1 == 0 && crm == 0) {
272 switch (opc2) {
273 case 0:
274 return MISCREG_TTBR0;
275 case 1:
276 return MISCREG_TTBR1;
277 case 2:
278 return MISCREG_TTBCR;
279 }
280 } else if (opc1 == 4) {
281 if (crm == 0 && opc2 == 2)
282 return MISCREG_HTCR;
283 else if (crm == 1 && opc2 == 2)
284 return MISCREG_VTCR;
285 }
286 break;
287 case 3:
288 if (opc1 == 0 && crm == 0 && opc2 == 0) {
289 return MISCREG_DACR;
290 }
291 break;
292 case 4:
293 if (opc1 == 0 && crm == 6 && opc2 == 0) {
294 return MISCREG_ICC_PMR;
295 }
296 break;
297 case 5:
298 if (opc1 == 0) {
299 if (crm == 0) {
300 if (opc2 == 0) {
301 return MISCREG_DFSR;
302 } else if (opc2 == 1) {
303 return MISCREG_IFSR;
304 }
305 } else if (crm == 1) {
306 if (opc2 == 0) {
307 return MISCREG_ADFSR;
308 } else if (opc2 == 1) {
309 return MISCREG_AIFSR;
310 }
311 }
312 } else if (opc1 == 4) {
313 if (crm == 1) {
314 if (opc2 == 0)
315 return MISCREG_HADFSR;
316 else if (opc2 == 1)
317 return MISCREG_HAIFSR;
318 } else if (crm == 2 && opc2 == 0) {
319 return MISCREG_HSR;
320 }
321 }
322 break;
323 case 6:
324 if (opc1 == 0 && crm == 0) {
325 switch (opc2) {
326 case 0:
327 return MISCREG_DFAR;
328 case 2:
329 return MISCREG_IFAR;
330 }
331 } else if (opc1 == 4 && crm == 0) {
332 switch (opc2) {
333 case 0:
334 return MISCREG_HDFAR;
335 case 2:
336 return MISCREG_HIFAR;
337 case 4:
338 return MISCREG_HPFAR;
339 }
340 }
341 break;
342 case 7:
343 if (opc1 == 0) {
344 switch (crm) {
345 case 0:
346 if (opc2 == 4) {
347 return MISCREG_NOP;
348 }
349 break;
350 case 1:
351 switch (opc2) {
352 case 0:
353 return MISCREG_ICIALLUIS;
354 case 6:
355 return MISCREG_BPIALLIS;
356 }
357 break;
358 case 4:
359 if (opc2 == 0) {
360 return MISCREG_PAR;
361 }
362 break;
363 case 5:
364 switch (opc2) {
365 case 0:
366 return MISCREG_ICIALLU;
367 case 1:
368 return MISCREG_ICIMVAU;
369 case 4:
370 return MISCREG_CP15ISB;
371 case 6:
372 return MISCREG_BPIALL;
373 case 7:
374 return MISCREG_BPIMVA;
375 }
376 break;
377 case 6:
378 if (opc2 == 1) {
379 return MISCREG_DCIMVAC;
380 } else if (opc2 == 2) {
381 return MISCREG_DCISW;
382 }
383 break;
384 case 8:
385 switch (opc2) {
386 case 0:
387 return MISCREG_ATS1CPR;
388 case 1:
389 return MISCREG_ATS1CPW;
390 case 2:
391 return MISCREG_ATS1CUR;
392 case 3:
393 return MISCREG_ATS1CUW;
394 case 4:
395 return MISCREG_ATS12NSOPR;
396 case 5:
397 return MISCREG_ATS12NSOPW;
398 case 6:
399 return MISCREG_ATS12NSOUR;
400 case 7:
401 return MISCREG_ATS12NSOUW;
402 }
403 break;
404 case 10:
405 switch (opc2) {
406 case 1:
407 return MISCREG_DCCMVAC;
408 case 2:
409 return MISCREG_DCCSW;
410 case 4:
411 return MISCREG_CP15DSB;
412 case 5:
413 return MISCREG_CP15DMB;
414 }
415 break;
416 case 11:
417 if (opc2 == 1) {
418 return MISCREG_DCCMVAU;
419 }
420 break;
421 case 13:
422 if (opc2 == 1) {
423 return MISCREG_NOP;
424 }
425 break;
426 case 14:
427 if (opc2 == 1) {
428 return MISCREG_DCCIMVAC;
429 } else if (opc2 == 2) {
430 return MISCREG_DCCISW;
431 }
432 break;
433 }
434 } else if (opc1 == 4 && crm == 8) {
435 if (opc2 == 0)
436 return MISCREG_ATS1HR;
437 else if (opc2 == 1)
438 return MISCREG_ATS1HW;
439 }
440 break;
441 case 8:
442 if (opc1 == 0) {
443 switch (crm) {
444 case 3:
445 switch (opc2) {
446 case 0:
447 return MISCREG_TLBIALLIS;
448 case 1:
449 return MISCREG_TLBIMVAIS;
450 case 2:
451 return MISCREG_TLBIASIDIS;
452 case 3:
453 return MISCREG_TLBIMVAAIS;
454 case 5:
455 return MISCREG_TLBIMVALIS;
456 case 7:
457 return MISCREG_TLBIMVAALIS;
458 }
459 break;
460 case 5:
461 switch (opc2) {
462 case 0:
463 return MISCREG_ITLBIALL;
464 case 1:
465 return MISCREG_ITLBIMVA;
466 case 2:
467 return MISCREG_ITLBIASID;
468 }
469 break;
470 case 6:
471 switch (opc2) {
472 case 0:
473 return MISCREG_DTLBIALL;
474 case 1:
475 return MISCREG_DTLBIMVA;
476 case 2:
477 return MISCREG_DTLBIASID;
478 }
479 break;
480 case 7:
481 switch (opc2) {
482 case 0:
483 return MISCREG_TLBIALL;
484 case 1:
485 return MISCREG_TLBIMVA;
486 case 2:
487 return MISCREG_TLBIASID;
488 case 3:
489 return MISCREG_TLBIMVAA;
490 case 5:
491 return MISCREG_TLBIMVAL;
492 case 7:
493 return MISCREG_TLBIMVAAL;
494 }
495 break;
496 }
497 } else if (opc1 == 4) {
498 if (crm == 0) {
499 switch (opc2) {
500 case 1:
501 return MISCREG_TLBIIPAS2IS;
502 case 5:
503 return MISCREG_TLBIIPAS2LIS;
504 }
505 } else if (crm == 3) {
506 switch (opc2) {
507 case 0:
508 return MISCREG_TLBIALLHIS;
509 case 1:
510 return MISCREG_TLBIMVAHIS;
511 case 4:
512 return MISCREG_TLBIALLNSNHIS;
513 case 5:
514 return MISCREG_TLBIMVALHIS;
515 }
516 } else if (crm == 4) {
517 switch (opc2) {
518 case 1:
519 return MISCREG_TLBIIPAS2;
520 case 5:
521 return MISCREG_TLBIIPAS2L;
522 }
523 } else if (crm == 7) {
524 switch (opc2) {
525 case 0:
526 return MISCREG_TLBIALLH;
527 case 1:
528 return MISCREG_TLBIMVAH;
529 case 4:
530 return MISCREG_TLBIALLNSNH;
531 case 5:
532 return MISCREG_TLBIMVALH;
533 }
534 }
535 }
536 break;
537 case 9:
538 // Every cop register with CRn = 9 and CRm in
539 // {0-2}, {5-8} is implementation defined regardless
540 // of opc1 and opc2.
541 switch (crm) {
542 case 0:
543 case 1:
544 case 2:
545 case 5:
546 case 6:
547 case 7:
548 case 8:
549 return MISCREG_IMPDEF_UNIMPL;
550 }
551 if (opc1 == 0) {
552 switch (crm) {
553 case 12:
554 switch (opc2) {
555 case 0:
556 return MISCREG_PMCR;
557 case 1:
558 return MISCREG_PMCNTENSET;
559 case 2:
560 return MISCREG_PMCNTENCLR;
561 case 3:
562 return MISCREG_PMOVSR;
563 case 4:
564 return MISCREG_PMSWINC;
565 case 5:
566 return MISCREG_PMSELR;
567 case 6:
568 return MISCREG_PMCEID0;
569 case 7:
570 return MISCREG_PMCEID1;
571 }
572 break;
573 case 13:
574 switch (opc2) {
575 case 0:
576 return MISCREG_PMCCNTR;
577 case 1:
578 // Selector is PMSELR.SEL
579 return MISCREG_PMXEVTYPER_PMCCFILTR;
580 case 2:
581 return MISCREG_PMXEVCNTR;
582 }
583 break;
584 case 14:
585 switch (opc2) {
586 case 0:
587 return MISCREG_PMUSERENR;
588 case 1:
589 return MISCREG_PMINTENSET;
590 case 2:
591 return MISCREG_PMINTENCLR;
592 case 3:
593 return MISCREG_PMOVSSET;
594 }
595 break;
596 }
597 } else if (opc1 == 1) {
598 switch (crm) {
599 case 0:
600 switch (opc2) {
601 case 2: // L2CTLR, L2 Control Register
602 return MISCREG_L2CTLR;
603 case 3:
604 return MISCREG_L2ECTLR;
605 }
606 break;
607 break;
608 }
609 }
610 break;
611 case 10:
612 if (opc1 == 0) {
613 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
614 if (crm < 2) {
615 return MISCREG_IMPDEF_UNIMPL;
616 } else if (crm == 2) { // TEX Remap Registers
617 if (opc2 == 0) {
618 // Selector is TTBCR.EAE
619 return MISCREG_PRRR_MAIR0;
620 } else if (opc2 == 1) {
621 // Selector is TTBCR.EAE
622 return MISCREG_NMRR_MAIR1;
623 }
624 } else if (crm == 3) {
625 if (opc2 == 0) {
626 return MISCREG_AMAIR0;
627 } else if (opc2 == 1) {
628 return MISCREG_AMAIR1;
629 }
630 }
631 } else if (opc1 == 4) {
632 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
633 if (crm == 2) {
634 if (opc2 == 0)
635 return MISCREG_HMAIR0;
636 else if (opc2 == 1)
637 return MISCREG_HMAIR1;
638 } else if (crm == 3) {
639 if (opc2 == 0)
640 return MISCREG_HAMAIR0;
641 else if (opc2 == 1)
642 return MISCREG_HAMAIR1;
643 }
644 }
645 break;
646 case 11:
647 if (opc1 <=7) {
648 switch (crm) {
649 case 0:
650 case 1:
651 case 2:
652 case 3:
653 case 4:
654 case 5:
655 case 6:
656 case 7:
657 case 8:
658 case 15:
659 // Reserved for DMA operations for TCM access
660 return MISCREG_IMPDEF_UNIMPL;
661 default:
662 break;
663 }
664 }
665 break;
666 case 12:
667 if (opc1 == 0) {
668 if (crm == 0) {
669 if (opc2 == 0) {
670 return MISCREG_VBAR;
671 } else if (opc2 == 1) {
672 return MISCREG_MVBAR;
673 }
674 } else if (crm == 1) {
675 if (opc2 == 0) {
676 return MISCREG_ISR;
677 }
678 } else if (crm == 8) {
679 switch (opc2) {
680 case 0:
681 return MISCREG_ICC_IAR0;
682 case 1:
683 return MISCREG_ICC_EOIR0;
684 case 2:
685 return MISCREG_ICC_HPPIR0;
686 case 3:
687 return MISCREG_ICC_BPR0;
688 case 4:
689 return MISCREG_ICC_AP0R0;
690 case 5:
691 return MISCREG_ICC_AP0R1;
692 case 6:
693 return MISCREG_ICC_AP0R2;
694 case 7:
695 return MISCREG_ICC_AP0R3;
696 }
697 } else if (crm == 9) {
698 switch (opc2) {
699 case 0:
700 return MISCREG_ICC_AP1R0;
701 case 1:
702 return MISCREG_ICC_AP1R1;
703 case 2:
704 return MISCREG_ICC_AP1R2;
705 case 3:
706 return MISCREG_ICC_AP1R3;
707 }
708 } else if (crm == 11) {
709 switch (opc2) {
710 case 1:
711 return MISCREG_ICC_DIR;
712 case 3:
713 return MISCREG_ICC_RPR;
714 }
715 } else if (crm == 12) {
716 switch (opc2) {
717 case 0:
718 return MISCREG_ICC_IAR1;
719 case 1:
720 return MISCREG_ICC_EOIR1;
721 case 2:
722 return MISCREG_ICC_HPPIR1;
723 case 3:
724 return MISCREG_ICC_BPR1;
725 case 4:
726 return MISCREG_ICC_CTLR;
727 case 5:
728 return MISCREG_ICC_SRE;
729 case 6:
730 return MISCREG_ICC_IGRPEN0;
731 case 7:
732 return MISCREG_ICC_IGRPEN1;
733 }
734 }
735 } else if (opc1 == 4) {
736 if (crm == 0 && opc2 == 0) {
737 return MISCREG_HVBAR;
738 } else if (crm == 8) {
739 switch (opc2) {
740 case 0:
741 return MISCREG_ICH_AP0R0;
742 case 1:
743 return MISCREG_ICH_AP0R1;
744 case 2:
745 return MISCREG_ICH_AP0R2;
746 case 3:
747 return MISCREG_ICH_AP0R3;
748 }
749 } else if (crm == 9) {
750 switch (opc2) {
751 case 0:
752 return MISCREG_ICH_AP1R0;
753 case 1:
754 return MISCREG_ICH_AP1R1;
755 case 2:
756 return MISCREG_ICH_AP1R2;
757 case 3:
758 return MISCREG_ICH_AP1R3;
759 case 5:
760 return MISCREG_ICC_HSRE;
761 }
762 } else if (crm == 11) {
763 switch (opc2) {
764 case 0:
765 return MISCREG_ICH_HCR;
766 case 1:
767 return MISCREG_ICH_VTR;
768 case 2:
769 return MISCREG_ICH_MISR;
770 case 3:
771 return MISCREG_ICH_EISR;
772 case 5:
773 return MISCREG_ICH_ELRSR;
774 case 7:
775 return MISCREG_ICH_VMCR;
776 }
777 } else if (crm == 12) {
778 switch (opc2) {
779 case 0:
780 return MISCREG_ICH_LR0;
781 case 1:
782 return MISCREG_ICH_LR1;
783 case 2:
784 return MISCREG_ICH_LR2;
785 case 3:
786 return MISCREG_ICH_LR3;
787 case 4:
788 return MISCREG_ICH_LR4;
789 case 5:
790 return MISCREG_ICH_LR5;
791 case 6:
792 return MISCREG_ICH_LR6;
793 case 7:
794 return MISCREG_ICH_LR7;
795 }
796 } else if (crm == 13) {
797 switch (opc2) {
798 case 0:
799 return MISCREG_ICH_LR8;
800 case 1:
801 return MISCREG_ICH_LR9;
802 case 2:
803 return MISCREG_ICH_LR10;
804 case 3:
805 return MISCREG_ICH_LR11;
806 case 4:
807 return MISCREG_ICH_LR12;
808 case 5:
809 return MISCREG_ICH_LR13;
810 case 6:
811 return MISCREG_ICH_LR14;
812 case 7:
813 return MISCREG_ICH_LR15;
814 }
815 } else if (crm == 14) {
816 switch (opc2) {
817 case 0:
818 return MISCREG_ICH_LRC0;
819 case 1:
820 return MISCREG_ICH_LRC1;
821 case 2:
822 return MISCREG_ICH_LRC2;
823 case 3:
824 return MISCREG_ICH_LRC3;
825 case 4:
826 return MISCREG_ICH_LRC4;
827 case 5:
828 return MISCREG_ICH_LRC5;
829 case 6:
830 return MISCREG_ICH_LRC6;
831 case 7:
832 return MISCREG_ICH_LRC7;
833 }
834 } else if (crm == 15) {
835 switch (opc2) {
836 case 0:
837 return MISCREG_ICH_LRC8;
838 case 1:
839 return MISCREG_ICH_LRC9;
840 case 2:
841 return MISCREG_ICH_LRC10;
842 case 3:
843 return MISCREG_ICH_LRC11;
844 case 4:
845 return MISCREG_ICH_LRC12;
846 case 5:
847 return MISCREG_ICH_LRC13;
848 case 6:
849 return MISCREG_ICH_LRC14;
850 case 7:
851 return MISCREG_ICH_LRC15;
852 }
853 }
854 } else if (opc1 == 6) {
855 if (crm == 12) {
856 switch (opc2) {
857 case 4:
858 return MISCREG_ICC_MCTLR;
859 case 5:
860 return MISCREG_ICC_MSRE;
861 case 7:
862 return MISCREG_ICC_MGRPEN1;
863 }
864 }
865 }
866 break;
867 case 13:
868 if (opc1 == 0) {
869 if (crm == 0) {
870 switch (opc2) {
871 case 0:
872 return MISCREG_FCSEIDR;
873 case 1:
874 return MISCREG_CONTEXTIDR;
875 case 2:
876 return MISCREG_TPIDRURW;
877 case 3:
878 return MISCREG_TPIDRURO;
879 case 4:
880 return MISCREG_TPIDRPRW;
881 }
882 }
883 } else if (opc1 == 4) {
884 if (crm == 0 && opc2 == 2)
885 return MISCREG_HTPIDR;
886 }
887 break;
888 case 14:
889 if (opc1 == 0) {
890 switch (crm) {
891 case 0:
892 if (opc2 == 0)
893 return MISCREG_CNTFRQ;
894 break;
895 case 1:
896 if (opc2 == 0)
897 return MISCREG_CNTKCTL;
898 break;
899 case 2:
900 if (opc2 == 0)
901 return MISCREG_CNTP_TVAL;
902 else if (opc2 == 1)
903 return MISCREG_CNTP_CTL;
904 break;
905 case 3:
906 if (opc2 == 0)
907 return MISCREG_CNTV_TVAL;
908 else if (opc2 == 1)
909 return MISCREG_CNTV_CTL;
910 break;
911 }
912 } else if (opc1 == 4) {
913 if (crm == 1 && opc2 == 0) {
914 return MISCREG_CNTHCTL;
915 } else if (crm == 2) {
916 if (opc2 == 0)
917 return MISCREG_CNTHP_TVAL;
918 else if (opc2 == 1)
919 return MISCREG_CNTHP_CTL;
920 }
921 }
922 break;
923 case 15:
924 // Implementation defined
925 return MISCREG_IMPDEF_UNIMPL;
926 }
927 // Unrecognized register
928 return MISCREG_CP15_UNIMPL;
929 }
930
931 MiscRegIndex
932 decodeCP15Reg64(unsigned crm, unsigned opc1)
933 {
934 switch (crm) {
935 case 2:
936 switch (opc1) {
937 case 0:
938 return MISCREG_TTBR0;
939 case 1:
940 return MISCREG_TTBR1;
941 case 4:
942 return MISCREG_HTTBR;
943 case 6:
944 return MISCREG_VTTBR;
945 }
946 break;
947 case 7:
948 if (opc1 == 0)
949 return MISCREG_PAR;
950 break;
951 case 14:
952 switch (opc1) {
953 case 0:
954 return MISCREG_CNTPCT;
955 case 1:
956 return MISCREG_CNTVCT;
957 case 2:
958 return MISCREG_CNTP_CVAL;
959 case 3:
960 return MISCREG_CNTV_CVAL;
961 case 4:
962 return MISCREG_CNTVOFF;
963 case 6:
964 return MISCREG_CNTHP_CVAL;
965 }
966 break;
967 case 12:
968 switch (opc1) {
969 case 0:
970 return MISCREG_ICC_SGI1R;
971 case 1:
972 return MISCREG_ICC_ASGI1R;
973 case 2:
974 return MISCREG_ICC_SGI0R;
975 default:
976 break;
977 }
978 break;
979 case 15:
980 if (opc1 == 0)
981 return MISCREG_CPUMERRSR;
982 else if (opc1 == 1)
983 return MISCREG_L2MERRSR;
984 break;
985 }
986 // Unrecognized register
987 return MISCREG_CP15_UNIMPL;
988 }
989
990 std::tuple<bool, bool>
991 canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
992 {
993 bool secure = !scr.ns;
994 bool canRead = false;
995 bool undefined = false;
996
997 switch (cpsr.mode) {
998 case MODE_USER:
999 canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
1000 miscRegInfo[reg][MISCREG_USR_NS_RD];
1001 break;
1002 case MODE_FIQ:
1003 case MODE_IRQ:
1004 case MODE_SVC:
1005 case MODE_ABORT:
1006 case MODE_UNDEFINED:
1007 case MODE_SYSTEM:
1008 canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1009 miscRegInfo[reg][MISCREG_PRI_NS_RD];
1010 break;
1011 case MODE_MON:
1012 canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1013 miscRegInfo[reg][MISCREG_MON_NS1_RD];
1014 break;
1015 case MODE_HYP:
1016 canRead = miscRegInfo[reg][MISCREG_HYP_RD];
1017 break;
1018 default:
1019 undefined = true;
1020 }
1021 // can't do permissions checkes on the root of a banked pair of regs
1022 assert(!miscRegInfo[reg][MISCREG_BANKED]);
1023 return std::make_tuple(canRead, undefined);
1024 }
1025
1026 std::tuple<bool, bool>
1027 canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
1028 {
1029 bool secure = !scr.ns;
1030 bool canWrite = false;
1031 bool undefined = false;
1032
1033 switch (cpsr.mode) {
1034 case MODE_USER:
1035 canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1036 miscRegInfo[reg][MISCREG_USR_NS_WR];
1037 break;
1038 case MODE_FIQ:
1039 case MODE_IRQ:
1040 case MODE_SVC:
1041 case MODE_ABORT:
1042 case MODE_UNDEFINED:
1043 case MODE_SYSTEM:
1044 canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1045 miscRegInfo[reg][MISCREG_PRI_NS_WR];
1046 break;
1047 case MODE_MON:
1048 canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1049 miscRegInfo[reg][MISCREG_MON_NS1_WR];
1050 break;
1051 case MODE_HYP:
1052 canWrite = miscRegInfo[reg][MISCREG_HYP_WR];
1053 break;
1054 default:
1055 undefined = true;
1056 }
1057 // can't do permissions checkes on the root of a banked pair of regs
1058 assert(!miscRegInfo[reg][MISCREG_BANKED]);
1059 return std::make_tuple(canWrite, undefined);
1060 }
1061
1062 int
1063 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
1064 {
1065 SCR scr = tc->readMiscReg(MISCREG_SCR);
1066 return snsBankedIndex(reg, tc, scr.ns);
1067 }
1068
1069 int
1070 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
1071 {
1072 int reg_as_int = static_cast<int>(reg);
1073 if (miscRegInfo[reg][MISCREG_BANKED]) {
1074 reg_as_int += (ArmSystem::haveSecurity(tc) &&
1075 !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
1076 }
1077 return reg_as_int;
1078 }
1079
1080 int
1081 snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc)
1082 {
1083 SCR scr = tc->readMiscReg(MISCREG_SCR);
1084 return tc->getIsaPtr()->snsBankedIndex64(reg, scr.ns);
1085 }
1086
1087 /**
1088 * If the reg is a child reg of a banked set, then the parent is the last
1089 * banked one in the list. This is messy, and the wish is to eventually have
1090 * the bitmap replaced with a better data structure. the preUnflatten function
1091 * initializes a lookup table to speed up the search for these banked
1092 * registers.
1093 */
1094
1095 int unflattenResultMiscReg[NUM_MISCREGS];
1096
1097 void
1098 preUnflattenMiscReg()
1099 {
1100 int reg = -1;
1101 for (int i = 0 ; i < NUM_MISCREGS; i++){
1102 if (miscRegInfo[i][MISCREG_BANKED])
1103 reg = i;
1104 if (miscRegInfo[i][MISCREG_BANKED_CHILD])
1105 unflattenResultMiscReg[i] = reg;
1106 else
1107 unflattenResultMiscReg[i] = i;
1108 // if this assert fails, no parent was found, and something is broken
1109 assert(unflattenResultMiscReg[i] > -1);
1110 }
1111 }
1112
1113 int
1114 unflattenMiscReg(int reg)
1115 {
1116 return unflattenResultMiscReg[reg];
1117 }
1118
1119 bool
1120 canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1121 {
1122 // Check for SP_EL0 access while SPSEL == 0
1123 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1124 return false;
1125
1126 // Check for RVBAR access
1127 if (reg == MISCREG_RVBAR_EL1) {
1128 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1129 if (highest_el == EL2 || highest_el == EL3)
1130 return false;
1131 }
1132 if (reg == MISCREG_RVBAR_EL2) {
1133 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1134 if (highest_el == EL3)
1135 return false;
1136 }
1137
1138 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
1139
1140 switch (currEL(cpsr)) {
1141 case EL0:
1142 return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
1143 miscRegInfo[reg][MISCREG_USR_NS_RD];
1144 case EL1:
1145 return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1146 miscRegInfo[reg][MISCREG_PRI_NS_RD];
1147 case EL2:
1148 return miscRegInfo[reg][MISCREG_HYP_RD];
1149 case EL3:
1150 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1151 miscRegInfo[reg][MISCREG_MON_NS1_RD];
1152 default:
1153 panic("Invalid exception level");
1154 }
1155 }
1156
1157 bool
1158 canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1159 {
1160 // Check for SP_EL0 access while SPSEL == 0
1161 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1162 return false;
1163 ExceptionLevel el = currEL(cpsr);
1164 if (reg == MISCREG_DAIF) {
1165 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1166 if (el == EL0 && !sctlr.uma)
1167 return false;
1168 }
1169 if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
1170 // In syscall-emulation mode, this test is skipped and DCZVA is always
1171 // allowed at EL0
1172 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1173 if (el == EL0 && !sctlr.dze)
1174 return false;
1175 }
1176 if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
1177 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1178 if (el == EL0 && !sctlr.uci)
1179 return false;
1180 }
1181
1182 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
1183
1184 switch (el) {
1185 case EL0:
1186 return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1187 miscRegInfo[reg][MISCREG_USR_NS_WR];
1188 case EL1:
1189 return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1190 miscRegInfo[reg][MISCREG_PRI_NS_WR];
1191 case EL2:
1192 return miscRegInfo[reg][MISCREG_HYP_WR];
1193 case EL3:
1194 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1195 miscRegInfo[reg][MISCREG_MON_NS1_WR];
1196 default:
1197 panic("Invalid exception level");
1198 }
1199 }
1200
1201 MiscRegIndex
1202 decodeAArch64SysReg(unsigned op0, unsigned op1,
1203 unsigned crn, unsigned crm,
1204 unsigned op2)
1205 {
1206 switch (op0) {
1207 case 1:
1208 switch (crn) {
1209 case 7:
1210 switch (op1) {
1211 case 0:
1212 switch (crm) {
1213 case 1:
1214 switch (op2) {
1215 case 0:
1216 return MISCREG_IC_IALLUIS;
1217 }
1218 break;
1219 case 5:
1220 switch (op2) {
1221 case 0:
1222 return MISCREG_IC_IALLU;
1223 }
1224 break;
1225 case 6:
1226 switch (op2) {
1227 case 1:
1228 return MISCREG_DC_IVAC_Xt;
1229 case 2:
1230 return MISCREG_DC_ISW_Xt;
1231 }
1232 break;
1233 case 8:
1234 switch (op2) {
1235 case 0:
1236 return MISCREG_AT_S1E1R_Xt;
1237 case 1:
1238 return MISCREG_AT_S1E1W_Xt;
1239 case 2:
1240 return MISCREG_AT_S1E0R_Xt;
1241 case 3:
1242 return MISCREG_AT_S1E0W_Xt;
1243 }
1244 break;
1245 case 10:
1246 switch (op2) {
1247 case 2:
1248 return MISCREG_DC_CSW_Xt;
1249 }
1250 break;
1251 case 14:
1252 switch (op2) {
1253 case 2:
1254 return MISCREG_DC_CISW_Xt;
1255 }
1256 break;
1257 }
1258 break;
1259 case 3:
1260 switch (crm) {
1261 case 4:
1262 switch (op2) {
1263 case 1:
1264 return MISCREG_DC_ZVA_Xt;
1265 }
1266 break;
1267 case 5:
1268 switch (op2) {
1269 case 1:
1270 return MISCREG_IC_IVAU_Xt;
1271 }
1272 break;
1273 case 10:
1274 switch (op2) {
1275 case 1:
1276 return MISCREG_DC_CVAC_Xt;
1277 }
1278 break;
1279 case 11:
1280 switch (op2) {
1281 case 1:
1282 return MISCREG_DC_CVAU_Xt;
1283 }
1284 break;
1285 case 14:
1286 switch (op2) {
1287 case 1:
1288 return MISCREG_DC_CIVAC_Xt;
1289 }
1290 break;
1291 }
1292 break;
1293 case 4:
1294 switch (crm) {
1295 case 8:
1296 switch (op2) {
1297 case 0:
1298 return MISCREG_AT_S1E2R_Xt;
1299 case 1:
1300 return MISCREG_AT_S1E2W_Xt;
1301 case 4:
1302 return MISCREG_AT_S12E1R_Xt;
1303 case 5:
1304 return MISCREG_AT_S12E1W_Xt;
1305 case 6:
1306 return MISCREG_AT_S12E0R_Xt;
1307 case 7:
1308 return MISCREG_AT_S12E0W_Xt;
1309 }
1310 break;
1311 }
1312 break;
1313 case 6:
1314 switch (crm) {
1315 case 8:
1316 switch (op2) {
1317 case 0:
1318 return MISCREG_AT_S1E3R_Xt;
1319 case 1:
1320 return MISCREG_AT_S1E3W_Xt;
1321 }
1322 break;
1323 }
1324 break;
1325 }
1326 break;
1327 case 8:
1328 switch (op1) {
1329 case 0:
1330 switch (crm) {
1331 case 3:
1332 switch (op2) {
1333 case 0:
1334 return MISCREG_TLBI_VMALLE1IS;
1335 case 1:
1336 return MISCREG_TLBI_VAE1IS_Xt;
1337 case 2:
1338 return MISCREG_TLBI_ASIDE1IS_Xt;
1339 case 3:
1340 return MISCREG_TLBI_VAAE1IS_Xt;
1341 case 5:
1342 return MISCREG_TLBI_VALE1IS_Xt;
1343 case 7:
1344 return MISCREG_TLBI_VAALE1IS_Xt;
1345 }
1346 break;
1347 case 7:
1348 switch (op2) {
1349 case 0:
1350 return MISCREG_TLBI_VMALLE1;
1351 case 1:
1352 return MISCREG_TLBI_VAE1_Xt;
1353 case 2:
1354 return MISCREG_TLBI_ASIDE1_Xt;
1355 case 3:
1356 return MISCREG_TLBI_VAAE1_Xt;
1357 case 5:
1358 return MISCREG_TLBI_VALE1_Xt;
1359 case 7:
1360 return MISCREG_TLBI_VAALE1_Xt;
1361 }
1362 break;
1363 }
1364 break;
1365 case 4:
1366 switch (crm) {
1367 case 0:
1368 switch (op2) {
1369 case 1:
1370 return MISCREG_TLBI_IPAS2E1IS_Xt;
1371 case 5:
1372 return MISCREG_TLBI_IPAS2LE1IS_Xt;
1373 }
1374 break;
1375 case 3:
1376 switch (op2) {
1377 case 0:
1378 return MISCREG_TLBI_ALLE2IS;
1379 case 1:
1380 return MISCREG_TLBI_VAE2IS_Xt;
1381 case 4:
1382 return MISCREG_TLBI_ALLE1IS;
1383 case 5:
1384 return MISCREG_TLBI_VALE2IS_Xt;
1385 case 6:
1386 return MISCREG_TLBI_VMALLS12E1IS;
1387 }
1388 break;
1389 case 4:
1390 switch (op2) {
1391 case 1:
1392 return MISCREG_TLBI_IPAS2E1_Xt;
1393 case 5:
1394 return MISCREG_TLBI_IPAS2LE1_Xt;
1395 }
1396 break;
1397 case 7:
1398 switch (op2) {
1399 case 0:
1400 return MISCREG_TLBI_ALLE2;
1401 case 1:
1402 return MISCREG_TLBI_VAE2_Xt;
1403 case 4:
1404 return MISCREG_TLBI_ALLE1;
1405 case 5:
1406 return MISCREG_TLBI_VALE2_Xt;
1407 case 6:
1408 return MISCREG_TLBI_VMALLS12E1;
1409 }
1410 break;
1411 }
1412 break;
1413 case 6:
1414 switch (crm) {
1415 case 3:
1416 switch (op2) {
1417 case 0:
1418 return MISCREG_TLBI_ALLE3IS;
1419 case 1:
1420 return MISCREG_TLBI_VAE3IS_Xt;
1421 case 5:
1422 return MISCREG_TLBI_VALE3IS_Xt;
1423 }
1424 break;
1425 case 7:
1426 switch (op2) {
1427 case 0:
1428 return MISCREG_TLBI_ALLE3;
1429 case 1:
1430 return MISCREG_TLBI_VAE3_Xt;
1431 case 5:
1432 return MISCREG_TLBI_VALE3_Xt;
1433 }
1434 break;
1435 }
1436 break;
1437 }
1438 break;
1439 case 11:
1440 case 15:
1441 // SYS Instruction with CRn = { 11, 15 }
1442 // (Trappable by HCR_EL2.TIDCP)
1443 return MISCREG_IMPDEF_UNIMPL;
1444 }
1445 break;
1446 case 2:
1447 switch (crn) {
1448 case 0:
1449 switch (op1) {
1450 case 0:
1451 switch (crm) {
1452 case 0:
1453 switch (op2) {
1454 case 2:
1455 return MISCREG_OSDTRRX_EL1;
1456 case 4:
1457 return MISCREG_DBGBVR0_EL1;
1458 case 5:
1459 return MISCREG_DBGBCR0_EL1;
1460 case 6:
1461 return MISCREG_DBGWVR0_EL1;
1462 case 7:
1463 return MISCREG_DBGWCR0_EL1;
1464 }
1465 break;
1466 case 1:
1467 switch (op2) {
1468 case 4:
1469 return MISCREG_DBGBVR1_EL1;
1470 case 5:
1471 return MISCREG_DBGBCR1_EL1;
1472 case 6:
1473 return MISCREG_DBGWVR1_EL1;
1474 case 7:
1475 return MISCREG_DBGWCR1_EL1;
1476 }
1477 break;
1478 case 2:
1479 switch (op2) {
1480 case 0:
1481 return MISCREG_MDCCINT_EL1;
1482 case 2:
1483 return MISCREG_MDSCR_EL1;
1484 case 4:
1485 return MISCREG_DBGBVR2_EL1;
1486 case 5:
1487 return MISCREG_DBGBCR2_EL1;
1488 case 6:
1489 return MISCREG_DBGWVR2_EL1;
1490 case 7:
1491 return MISCREG_DBGWCR2_EL1;
1492 }
1493 break;
1494 case 3:
1495 switch (op2) {
1496 case 2:
1497 return MISCREG_OSDTRTX_EL1;
1498 case 4:
1499 return MISCREG_DBGBVR3_EL1;
1500 case 5:
1501 return MISCREG_DBGBCR3_EL1;
1502 case 6:
1503 return MISCREG_DBGWVR3_EL1;
1504 case 7:
1505 return MISCREG_DBGWCR3_EL1;
1506 }
1507 break;
1508 case 4:
1509 switch (op2) {
1510 case 4:
1511 return MISCREG_DBGBVR4_EL1;
1512 case 5:
1513 return MISCREG_DBGBCR4_EL1;
1514 }
1515 break;
1516 case 5:
1517 switch (op2) {
1518 case 4:
1519 return MISCREG_DBGBVR5_EL1;
1520 case 5:
1521 return MISCREG_DBGBCR5_EL1;
1522 }
1523 break;
1524 case 6:
1525 switch (op2) {
1526 case 2:
1527 return MISCREG_OSECCR_EL1;
1528 }
1529 break;
1530 }
1531 break;
1532 case 2:
1533 switch (crm) {
1534 case 0:
1535 switch (op2) {
1536 case 0:
1537 return MISCREG_TEECR32_EL1;
1538 }
1539 break;
1540 }
1541 break;
1542 case 3:
1543 switch (crm) {
1544 case 1:
1545 switch (op2) {
1546 case 0:
1547 return MISCREG_MDCCSR_EL0;
1548 }
1549 break;
1550 case 4:
1551 switch (op2) {
1552 case 0:
1553 return MISCREG_MDDTR_EL0;
1554 }
1555 break;
1556 case 5:
1557 switch (op2) {
1558 case 0:
1559 return MISCREG_MDDTRRX_EL0;
1560 }
1561 break;
1562 }
1563 break;
1564 case 4:
1565 switch (crm) {
1566 case 7:
1567 switch (op2) {
1568 case 0:
1569 return MISCREG_DBGVCR32_EL2;
1570 }
1571 break;
1572 }
1573 break;
1574 }
1575 break;
1576 case 1:
1577 switch (op1) {
1578 case 0:
1579 switch (crm) {
1580 case 0:
1581 switch (op2) {
1582 case 0:
1583 return MISCREG_MDRAR_EL1;
1584 case 4:
1585 return MISCREG_OSLAR_EL1;
1586 }
1587 break;
1588 case 1:
1589 switch (op2) {
1590 case 4:
1591 return MISCREG_OSLSR_EL1;
1592 }
1593 break;
1594 case 3:
1595 switch (op2) {
1596 case 4:
1597 return MISCREG_OSDLR_EL1;
1598 }
1599 break;
1600 case 4:
1601 switch (op2) {
1602 case 4:
1603 return MISCREG_DBGPRCR_EL1;
1604 }
1605 break;
1606 }
1607 break;
1608 case 2:
1609 switch (crm) {
1610 case 0:
1611 switch (op2) {
1612 case 0:
1613 return MISCREG_TEEHBR32_EL1;
1614 }
1615 break;
1616 }
1617 break;
1618 }
1619 break;
1620 case 7:
1621 switch (op1) {
1622 case 0:
1623 switch (crm) {
1624 case 8:
1625 switch (op2) {
1626 case 6:
1627 return MISCREG_DBGCLAIMSET_EL1;
1628 }
1629 break;
1630 case 9:
1631 switch (op2) {
1632 case 6:
1633 return MISCREG_DBGCLAIMCLR_EL1;
1634 }
1635 break;
1636 case 14:
1637 switch (op2) {
1638 case 6:
1639 return MISCREG_DBGAUTHSTATUS_EL1;
1640 }
1641 break;
1642 }
1643 break;
1644 }
1645 break;
1646 }
1647 break;
1648 case 3:
1649 switch (crn) {
1650 case 0:
1651 switch (op1) {
1652 case 0:
1653 switch (crm) {
1654 case 0:
1655 switch (op2) {
1656 case 0:
1657 return MISCREG_MIDR_EL1;
1658 case 5:
1659 return MISCREG_MPIDR_EL1;
1660 case 6:
1661 return MISCREG_REVIDR_EL1;
1662 }
1663 break;
1664 case 1:
1665 switch (op2) {
1666 case 0:
1667 return MISCREG_ID_PFR0_EL1;
1668 case 1:
1669 return MISCREG_ID_PFR1_EL1;
1670 case 2:
1671 return MISCREG_ID_DFR0_EL1;
1672 case 3:
1673 return MISCREG_ID_AFR0_EL1;
1674 case 4:
1675 return MISCREG_ID_MMFR0_EL1;
1676 case 5:
1677 return MISCREG_ID_MMFR1_EL1;
1678 case 6:
1679 return MISCREG_ID_MMFR2_EL1;
1680 case 7:
1681 return MISCREG_ID_MMFR3_EL1;
1682 }
1683 break;
1684 case 2:
1685 switch (op2) {
1686 case 0:
1687 return MISCREG_ID_ISAR0_EL1;
1688 case 1:
1689 return MISCREG_ID_ISAR1_EL1;
1690 case 2:
1691 return MISCREG_ID_ISAR2_EL1;
1692 case 3:
1693 return MISCREG_ID_ISAR3_EL1;
1694 case 4:
1695 return MISCREG_ID_ISAR4_EL1;
1696 case 5:
1697 return MISCREG_ID_ISAR5_EL1;
1698 }
1699 break;
1700 case 3:
1701 switch (op2) {
1702 case 0:
1703 return MISCREG_MVFR0_EL1;
1704 case 1:
1705 return MISCREG_MVFR1_EL1;
1706 case 2:
1707 return MISCREG_MVFR2_EL1;
1708 case 3 ... 7:
1709 return MISCREG_RAZ;
1710 }
1711 break;
1712 case 4:
1713 switch (op2) {
1714 case 0:
1715 return MISCREG_ID_AA64PFR0_EL1;
1716 case 1:
1717 return MISCREG_ID_AA64PFR1_EL1;
1718 case 2 ... 3:
1719 return MISCREG_RAZ;
1720 case 4:
1721 return MISCREG_ID_AA64ZFR0_EL1;
1722 case 5 ... 7:
1723 return MISCREG_RAZ;
1724 }
1725 break;
1726 case 5:
1727 switch (op2) {
1728 case 0:
1729 return MISCREG_ID_AA64DFR0_EL1;
1730 case 1:
1731 return MISCREG_ID_AA64DFR1_EL1;
1732 case 4:
1733 return MISCREG_ID_AA64AFR0_EL1;
1734 case 5:
1735 return MISCREG_ID_AA64AFR1_EL1;
1736 case 2:
1737 case 3:
1738 case 6:
1739 case 7:
1740 return MISCREG_RAZ;
1741 }
1742 break;
1743 case 6:
1744 switch (op2) {
1745 case 0:
1746 return MISCREG_ID_AA64ISAR0_EL1;
1747 case 1:
1748 return MISCREG_ID_AA64ISAR1_EL1;
1749 case 2 ... 7:
1750 return MISCREG_RAZ;
1751 }
1752 break;
1753 case 7:
1754 switch (op2) {
1755 case 0:
1756 return MISCREG_ID_AA64MMFR0_EL1;
1757 case 1:
1758 return MISCREG_ID_AA64MMFR1_EL1;
1759 case 2:
1760 return MISCREG_ID_AA64MMFR2_EL1;
1761 case 3 ... 7:
1762 return MISCREG_RAZ;
1763 }
1764 break;
1765 }
1766 break;
1767 case 1:
1768 switch (crm) {
1769 case 0:
1770 switch (op2) {
1771 case 0:
1772 return MISCREG_CCSIDR_EL1;
1773 case 1:
1774 return MISCREG_CLIDR_EL1;
1775 case 7:
1776 return MISCREG_AIDR_EL1;
1777 }
1778 break;
1779 }
1780 break;
1781 case 2:
1782 switch (crm) {
1783 case 0:
1784 switch (op2) {
1785 case 0:
1786 return MISCREG_CSSELR_EL1;
1787 }
1788 break;
1789 }
1790 break;
1791 case 3:
1792 switch (crm) {
1793 case 0:
1794 switch (op2) {
1795 case 1:
1796 return MISCREG_CTR_EL0;
1797 case 7:
1798 return MISCREG_DCZID_EL0;
1799 }
1800 break;
1801 }
1802 break;
1803 case 4:
1804 switch (crm) {
1805 case 0:
1806 switch (op2) {
1807 case 0:
1808 return MISCREG_VPIDR_EL2;
1809 case 5:
1810 return MISCREG_VMPIDR_EL2;
1811 }
1812 break;
1813 }
1814 break;
1815 }
1816 break;
1817 case 1:
1818 switch (op1) {
1819 case 0:
1820 switch (crm) {
1821 case 0:
1822 switch (op2) {
1823 case 0:
1824 return MISCREG_SCTLR_EL1;
1825 case 1:
1826 return MISCREG_ACTLR_EL1;
1827 case 2:
1828 return MISCREG_CPACR_EL1;
1829 }
1830 break;
1831 case 2:
1832 switch (op2) {
1833 case 0:
1834 return MISCREG_ZCR_EL1;
1835 }
1836 break;
1837 }
1838 break;
1839 case 4:
1840 switch (crm) {
1841 case 0:
1842 switch (op2) {
1843 case 0:
1844 return MISCREG_SCTLR_EL2;
1845 case 1:
1846 return MISCREG_ACTLR_EL2;
1847 }
1848 break;
1849 case 1:
1850 switch (op2) {
1851 case 0:
1852 return MISCREG_HCR_EL2;
1853 case 1:
1854 return MISCREG_MDCR_EL2;
1855 case 2:
1856 return MISCREG_CPTR_EL2;
1857 case 3:
1858 return MISCREG_HSTR_EL2;
1859 case 7:
1860 return MISCREG_HACR_EL2;
1861 }
1862 break;
1863 case 2:
1864 switch (op2) {
1865 case 0:
1866 return MISCREG_ZCR_EL2;
1867 }
1868 break;
1869 }
1870 break;
1871 case 5:
1872 switch (crm) {
1873 case 2:
1874 switch (op2) {
1875 case 0:
1876 return MISCREG_ZCR_EL12;
1877 }
1878 break;
1879 }
1880 break;
1881 case 6:
1882 switch (crm) {
1883 case 0:
1884 switch (op2) {
1885 case 0:
1886 return MISCREG_SCTLR_EL3;
1887 case 1:
1888 return MISCREG_ACTLR_EL3;
1889 }
1890 break;
1891 case 1:
1892 switch (op2) {
1893 case 0:
1894 return MISCREG_SCR_EL3;
1895 case 1:
1896 return MISCREG_SDER32_EL3;
1897 case 2:
1898 return MISCREG_CPTR_EL3;
1899 }
1900 break;
1901 case 2:
1902 switch (op2) {
1903 case 0:
1904 return MISCREG_ZCR_EL3;
1905 }
1906 break;
1907 case 3:
1908 switch (op2) {
1909 case 1:
1910 return MISCREG_MDCR_EL3;
1911 }
1912 break;
1913 }
1914 break;
1915 }
1916 break;
1917 case 2:
1918 switch (op1) {
1919 case 0:
1920 switch (crm) {
1921 case 0:
1922 switch (op2) {
1923 case 0:
1924 return MISCREG_TTBR0_EL1;
1925 case 1:
1926 return MISCREG_TTBR1_EL1;
1927 case 2:
1928 return MISCREG_TCR_EL1;
1929 }
1930 break;
1931 }
1932 break;
1933 case 4:
1934 switch (crm) {
1935 case 0:
1936 switch (op2) {
1937 case 0:
1938 return MISCREG_TTBR0_EL2;
1939 case 1:
1940 return MISCREG_TTBR1_EL2;
1941 case 2:
1942 return MISCREG_TCR_EL2;
1943 }
1944 break;
1945 case 1:
1946 switch (op2) {
1947 case 0:
1948 return MISCREG_VTTBR_EL2;
1949 case 2:
1950 return MISCREG_VTCR_EL2;
1951 }
1952 break;
1953 }
1954 break;
1955 case 6:
1956 switch (crm) {
1957 case 0:
1958 switch (op2) {
1959 case 0:
1960 return MISCREG_TTBR0_EL3;
1961 case 2:
1962 return MISCREG_TCR_EL3;
1963 }
1964 break;
1965 }
1966 break;
1967 }
1968 break;
1969 case 3:
1970 switch (op1) {
1971 case 4:
1972 switch (crm) {
1973 case 0:
1974 switch (op2) {
1975 case 0:
1976 return MISCREG_DACR32_EL2;
1977 }
1978 break;
1979 }
1980 break;
1981 }
1982 break;
1983 case 4:
1984 switch (op1) {
1985 case 0:
1986 switch (crm) {
1987 case 0:
1988 switch (op2) {
1989 case 0:
1990 return MISCREG_SPSR_EL1;
1991 case 1:
1992 return MISCREG_ELR_EL1;
1993 }
1994 break;
1995 case 1:
1996 switch (op2) {
1997 case 0:
1998 return MISCREG_SP_EL0;
1999 }
2000 break;
2001 case 2:
2002 switch (op2) {
2003 case 0:
2004 return MISCREG_SPSEL;
2005 case 2:
2006 return MISCREG_CURRENTEL;
2007 case 3:
2008 return MISCREG_PAN;
2009 }
2010 break;
2011 case 6:
2012 switch (op2) {
2013 case 0:
2014 return MISCREG_ICC_PMR_EL1;
2015 }
2016 break;
2017 }
2018 break;
2019 case 3:
2020 switch (crm) {
2021 case 2:
2022 switch (op2) {
2023 case 0:
2024 return MISCREG_NZCV;
2025 case 1:
2026 return MISCREG_DAIF;
2027 }
2028 break;
2029 case 4:
2030 switch (op2) {
2031 case 0:
2032 return MISCREG_FPCR;
2033 case 1:
2034 return MISCREG_FPSR;
2035 }
2036 break;
2037 case 5:
2038 switch (op2) {
2039 case 0:
2040 return MISCREG_DSPSR_EL0;
2041 case 1:
2042 return MISCREG_DLR_EL0;
2043 }
2044 break;
2045 }
2046 break;
2047 case 4:
2048 switch (crm) {
2049 case 0:
2050 switch (op2) {
2051 case 0:
2052 return MISCREG_SPSR_EL2;
2053 case 1:
2054 return MISCREG_ELR_EL2;
2055 }
2056 break;
2057 case 1:
2058 switch (op2) {
2059 case 0:
2060 return MISCREG_SP_EL1;
2061 }
2062 break;
2063 case 3:
2064 switch (op2) {
2065 case 0:
2066 return MISCREG_SPSR_IRQ_AA64;
2067 case 1:
2068 return MISCREG_SPSR_ABT_AA64;
2069 case 2:
2070 return MISCREG_SPSR_UND_AA64;
2071 case 3:
2072 return MISCREG_SPSR_FIQ_AA64;
2073 }
2074 break;
2075 }
2076 break;
2077 case 6:
2078 switch (crm) {
2079 case 0:
2080 switch (op2) {
2081 case 0:
2082 return MISCREG_SPSR_EL3;
2083 case 1:
2084 return MISCREG_ELR_EL3;
2085 }
2086 break;
2087 case 1:
2088 switch (op2) {
2089 case 0:
2090 return MISCREG_SP_EL2;
2091 }
2092 break;
2093 }
2094 break;
2095 }
2096 break;
2097 case 5:
2098 switch (op1) {
2099 case 0:
2100 switch (crm) {
2101 case 1:
2102 switch (op2) {
2103 case 0:
2104 return MISCREG_AFSR0_EL1;
2105 case 1:
2106 return MISCREG_AFSR1_EL1;
2107 }
2108 break;
2109 case 2:
2110 switch (op2) {
2111 case 0:
2112 return MISCREG_ESR_EL1;
2113 }
2114 break;
2115 case 3:
2116 switch (op2) {
2117 case 0:
2118 return MISCREG_ERRIDR_EL1;
2119 case 1:
2120 return MISCREG_ERRSELR_EL1;
2121 }
2122 break;
2123 case 4:
2124 switch (op2) {
2125 case 0:
2126 return MISCREG_ERXFR_EL1;
2127 case 1:
2128 return MISCREG_ERXCTLR_EL1;
2129 case 2:
2130 return MISCREG_ERXSTATUS_EL1;
2131 case 3:
2132 return MISCREG_ERXADDR_EL1;
2133 }
2134 break;
2135 case 5:
2136 switch (op2) {
2137 case 0:
2138 return MISCREG_ERXMISC0_EL1;
2139 case 1:
2140 return MISCREG_ERXMISC1_EL1;
2141 }
2142 break;
2143 }
2144 break;
2145 case 4:
2146 switch (crm) {
2147 case 0:
2148 switch (op2) {
2149 case 1:
2150 return MISCREG_IFSR32_EL2;
2151 }
2152 break;
2153 case 1:
2154 switch (op2) {
2155 case 0:
2156 return MISCREG_AFSR0_EL2;
2157 case 1:
2158 return MISCREG_AFSR1_EL2;
2159 }
2160 break;
2161 case 2:
2162 switch (op2) {
2163 case 0:
2164 return MISCREG_ESR_EL2;
2165 case 3:
2166 return MISCREG_VSESR_EL2;
2167 }
2168 break;
2169 case 3:
2170 switch (op2) {
2171 case 0:
2172 return MISCREG_FPEXC32_EL2;
2173 }
2174 break;
2175 }
2176 break;
2177 case 6:
2178 switch (crm) {
2179 case 1:
2180 switch (op2) {
2181 case 0:
2182 return MISCREG_AFSR0_EL3;
2183 case 1:
2184 return MISCREG_AFSR1_EL3;
2185 }
2186 break;
2187 case 2:
2188 switch (op2) {
2189 case 0:
2190 return MISCREG_ESR_EL3;
2191 }
2192 break;
2193 }
2194 break;
2195 }
2196 break;
2197 case 6:
2198 switch (op1) {
2199 case 0:
2200 switch (crm) {
2201 case 0:
2202 switch (op2) {
2203 case 0:
2204 return MISCREG_FAR_EL1;
2205 }
2206 break;
2207 }
2208 break;
2209 case 4:
2210 switch (crm) {
2211 case 0:
2212 switch (op2) {
2213 case 0:
2214 return MISCREG_FAR_EL2;
2215 case 4:
2216 return MISCREG_HPFAR_EL2;
2217 }
2218 break;
2219 }
2220 break;
2221 case 6:
2222 switch (crm) {
2223 case 0:
2224 switch (op2) {
2225 case 0:
2226 return MISCREG_FAR_EL3;
2227 }
2228 break;
2229 }
2230 break;
2231 }
2232 break;
2233 case 7:
2234 switch (op1) {
2235 case 0:
2236 switch (crm) {
2237 case 4:
2238 switch (op2) {
2239 case 0:
2240 return MISCREG_PAR_EL1;
2241 }
2242 break;
2243 }
2244 break;
2245 }
2246 break;
2247 case 9:
2248 switch (op1) {
2249 case 0:
2250 switch (crm) {
2251 case 14:
2252 switch (op2) {
2253 case 1:
2254 return MISCREG_PMINTENSET_EL1;
2255 case 2:
2256 return MISCREG_PMINTENCLR_EL1;
2257 }
2258 break;
2259 }
2260 break;
2261 case 3:
2262 switch (crm) {
2263 case 12:
2264 switch (op2) {
2265 case 0:
2266 return MISCREG_PMCR_EL0;
2267 case 1:
2268 return MISCREG_PMCNTENSET_EL0;
2269 case 2:
2270 return MISCREG_PMCNTENCLR_EL0;
2271 case 3:
2272 return MISCREG_PMOVSCLR_EL0;
2273 case 4:
2274 return MISCREG_PMSWINC_EL0;
2275 case 5:
2276 return MISCREG_PMSELR_EL0;
2277 case 6:
2278 return MISCREG_PMCEID0_EL0;
2279 case 7:
2280 return MISCREG_PMCEID1_EL0;
2281 }
2282 break;
2283 case 13:
2284 switch (op2) {
2285 case 0:
2286 return MISCREG_PMCCNTR_EL0;
2287 case 1:
2288 return MISCREG_PMXEVTYPER_EL0;
2289 case 2:
2290 return MISCREG_PMXEVCNTR_EL0;
2291 }
2292 break;
2293 case 14:
2294 switch (op2) {
2295 case 0:
2296 return MISCREG_PMUSERENR_EL0;
2297 case 3:
2298 return MISCREG_PMOVSSET_EL0;
2299 }
2300 break;
2301 }
2302 break;
2303 }
2304 break;
2305 case 10:
2306 switch (op1) {
2307 case 0:
2308 switch (crm) {
2309 case 2:
2310 switch (op2) {
2311 case 0:
2312 return MISCREG_MAIR_EL1;
2313 }
2314 break;
2315 case 3:
2316 switch (op2) {
2317 case 0:
2318 return MISCREG_AMAIR_EL1;
2319 }
2320 break;
2321 }
2322 break;
2323 case 4:
2324 switch (crm) {
2325 case 2:
2326 switch (op2) {
2327 case 0:
2328 return MISCREG_MAIR_EL2;
2329 }
2330 break;
2331 case 3:
2332 switch (op2) {
2333 case 0:
2334 return MISCREG_AMAIR_EL2;
2335 }
2336 break;
2337 }
2338 break;
2339 case 6:
2340 switch (crm) {
2341 case 2:
2342 switch (op2) {
2343 case 0:
2344 return MISCREG_MAIR_EL3;
2345 }
2346 break;
2347 case 3:
2348 switch (op2) {
2349 case 0:
2350 return MISCREG_AMAIR_EL3;
2351 }
2352 break;
2353 }
2354 break;
2355 }
2356 break;
2357 case 11:
2358 switch (op1) {
2359 case 1:
2360 switch (crm) {
2361 case 0:
2362 switch (op2) {
2363 case 2:
2364 return MISCREG_L2CTLR_EL1;
2365 case 3:
2366 return MISCREG_L2ECTLR_EL1;
2367 }
2368 break;
2369 }
2370 M5_FALLTHROUGH;
2371 default:
2372 // S3_<op1>_11_<Cm>_<op2>
2373 return MISCREG_IMPDEF_UNIMPL;
2374 }
2375 M5_UNREACHABLE;
2376 case 12:
2377 switch (op1) {
2378 case 0:
2379 switch (crm) {
2380 case 0:
2381 switch (op2) {
2382 case 0:
2383 return MISCREG_VBAR_EL1;
2384 case 1:
2385 return MISCREG_RVBAR_EL1;
2386 }
2387 break;
2388 case 1:
2389 switch (op2) {
2390 case 0:
2391 return MISCREG_ISR_EL1;
2392 case 1:
2393 return MISCREG_DISR_EL1;
2394 }
2395 break;
2396 case 8:
2397 switch (op2) {
2398 case 0:
2399 return MISCREG_ICC_IAR0_EL1;
2400 case 1:
2401 return MISCREG_ICC_EOIR0_EL1;
2402 case 2:
2403 return MISCREG_ICC_HPPIR0_EL1;
2404 case 3:
2405 return MISCREG_ICC_BPR0_EL1;
2406 case 4:
2407 return MISCREG_ICC_AP0R0_EL1;
2408 case 5:
2409 return MISCREG_ICC_AP0R1_EL1;
2410 case 6:
2411 return MISCREG_ICC_AP0R2_EL1;
2412 case 7:
2413 return MISCREG_ICC_AP0R3_EL1;
2414 }
2415 break;
2416 case 9:
2417 switch (op2) {
2418 case 0:
2419 return MISCREG_ICC_AP1R0_EL1;
2420 case 1:
2421 return MISCREG_ICC_AP1R1_EL1;
2422 case 2:
2423 return MISCREG_ICC_AP1R2_EL1;
2424 case 3:
2425 return MISCREG_ICC_AP1R3_EL1;
2426 }
2427 break;
2428 case 11:
2429 switch (op2) {
2430 case 1:
2431 return MISCREG_ICC_DIR_EL1;
2432 case 3:
2433 return MISCREG_ICC_RPR_EL1;
2434 case 5:
2435 return MISCREG_ICC_SGI1R_EL1;
2436 case 6:
2437 return MISCREG_ICC_ASGI1R_EL1;
2438 case 7:
2439 return MISCREG_ICC_SGI0R_EL1;
2440 }
2441 break;
2442 case 12:
2443 switch (op2) {
2444 case 0:
2445 return MISCREG_ICC_IAR1_EL1;
2446 case 1:
2447 return MISCREG_ICC_EOIR1_EL1;
2448 case 2:
2449 return MISCREG_ICC_HPPIR1_EL1;
2450 case 3:
2451 return MISCREG_ICC_BPR1_EL1;
2452 case 4:
2453 return MISCREG_ICC_CTLR_EL1;
2454 case 5:
2455 return MISCREG_ICC_SRE_EL1;
2456 case 6:
2457 return MISCREG_ICC_IGRPEN0_EL1;
2458 case 7:
2459 return MISCREG_ICC_IGRPEN1_EL1;
2460 }
2461 break;
2462 }
2463 break;
2464 case 4:
2465 switch (crm) {
2466 case 0:
2467 switch (op2) {
2468 case 0:
2469 return MISCREG_VBAR_EL2;
2470 case 1:
2471 return MISCREG_RVBAR_EL2;
2472 }
2473 break;
2474 case 1:
2475 switch (op2) {
2476 case 1:
2477 return MISCREG_VDISR_EL2;
2478 }
2479 break;
2480 case 8:
2481 switch (op2) {
2482 case 0:
2483 return MISCREG_ICH_AP0R0_EL2;
2484 case 1:
2485 return MISCREG_ICH_AP0R1_EL2;
2486 case 2:
2487 return MISCREG_ICH_AP0R2_EL2;
2488 case 3:
2489 return MISCREG_ICH_AP0R3_EL2;
2490 }
2491 break;
2492 case 9:
2493 switch (op2) {
2494 case 0:
2495 return MISCREG_ICH_AP1R0_EL2;
2496 case 1:
2497 return MISCREG_ICH_AP1R1_EL2;
2498 case 2:
2499 return MISCREG_ICH_AP1R2_EL2;
2500 case 3:
2501 return MISCREG_ICH_AP1R3_EL2;
2502 case 5:
2503 return MISCREG_ICC_SRE_EL2;
2504 }
2505 break;
2506 case 11:
2507 switch (op2) {
2508 case 0:
2509 return MISCREG_ICH_HCR_EL2;
2510 case 1:
2511 return MISCREG_ICH_VTR_EL2;
2512 case 2:
2513 return MISCREG_ICH_MISR_EL2;
2514 case 3:
2515 return MISCREG_ICH_EISR_EL2;
2516 case 5:
2517 return MISCREG_ICH_ELRSR_EL2;
2518 case 7:
2519 return MISCREG_ICH_VMCR_EL2;
2520 }
2521 break;
2522 case 12:
2523 switch (op2) {
2524 case 0:
2525 return MISCREG_ICH_LR0_EL2;
2526 case 1:
2527 return MISCREG_ICH_LR1_EL2;
2528 case 2:
2529 return MISCREG_ICH_LR2_EL2;
2530 case 3:
2531 return MISCREG_ICH_LR3_EL2;
2532 case 4:
2533 return MISCREG_ICH_LR4_EL2;
2534 case 5:
2535 return MISCREG_ICH_LR5_EL2;
2536 case 6:
2537 return MISCREG_ICH_LR6_EL2;
2538 case 7:
2539 return MISCREG_ICH_LR7_EL2;
2540 }
2541 break;
2542 case 13:
2543 switch (op2) {
2544 case 0:
2545 return MISCREG_ICH_LR8_EL2;
2546 case 1:
2547 return MISCREG_ICH_LR9_EL2;
2548 case 2:
2549 return MISCREG_ICH_LR10_EL2;
2550 case 3:
2551 return MISCREG_ICH_LR11_EL2;
2552 case 4:
2553 return MISCREG_ICH_LR12_EL2;
2554 case 5:
2555 return MISCREG_ICH_LR13_EL2;
2556 case 6:
2557 return MISCREG_ICH_LR14_EL2;
2558 case 7:
2559 return MISCREG_ICH_LR15_EL2;
2560 }
2561 break;
2562 }
2563 break;
2564 case 6:
2565 switch (crm) {
2566 case 0:
2567 switch (op2) {
2568 case 0:
2569 return MISCREG_VBAR_EL3;
2570 case 1:
2571 return MISCREG_RVBAR_EL3;
2572 case 2:
2573 return MISCREG_RMR_EL3;
2574 }
2575 break;
2576 case 12:
2577 switch (op2) {
2578 case 4:
2579 return MISCREG_ICC_CTLR_EL3;
2580 case 5:
2581 return MISCREG_ICC_SRE_EL3;
2582 case 7:
2583 return MISCREG_ICC_IGRPEN1_EL3;
2584 }
2585 break;
2586 }
2587 break;
2588 }
2589 break;
2590 case 13:
2591 switch (op1) {
2592 case 0:
2593 switch (crm) {
2594 case 0:
2595 switch (op2) {
2596 case 1:
2597 return MISCREG_CONTEXTIDR_EL1;
2598 case 4:
2599 return MISCREG_TPIDR_EL1;
2600 }
2601 break;
2602 }
2603 break;
2604 case 3:
2605 switch (crm) {
2606 case 0:
2607 switch (op2) {
2608 case 2:
2609 return MISCREG_TPIDR_EL0;
2610 case 3:
2611 return MISCREG_TPIDRRO_EL0;
2612 }
2613 break;
2614 }
2615 break;
2616 case 4:
2617 switch (crm) {
2618 case 0:
2619 switch (op2) {
2620 case 1:
2621 return MISCREG_CONTEXTIDR_EL2;
2622 case 2:
2623 return MISCREG_TPIDR_EL2;
2624 }
2625 break;
2626 }
2627 break;
2628 case 6:
2629 switch (crm) {
2630 case 0:
2631 switch (op2) {
2632 case 2:
2633 return MISCREG_TPIDR_EL3;
2634 }
2635 break;
2636 }
2637 break;
2638 }
2639 break;
2640 case 14:
2641 switch (op1) {
2642 case 0:
2643 switch (crm) {
2644 case 1:
2645 switch (op2) {
2646 case 0:
2647 return MISCREG_CNTKCTL_EL1;
2648 }
2649 break;
2650 }
2651 break;
2652 case 3:
2653 switch (crm) {
2654 case 0:
2655 switch (op2) {
2656 case 0:
2657 return MISCREG_CNTFRQ_EL0;
2658 case 1:
2659 return MISCREG_CNTPCT_EL0;
2660 case 2:
2661 return MISCREG_CNTVCT_EL0;
2662 }
2663 break;
2664 case 2:
2665 switch (op2) {
2666 case 0:
2667 return MISCREG_CNTP_TVAL_EL0;
2668 case 1:
2669 return MISCREG_CNTP_CTL_EL0;
2670 case 2:
2671 return MISCREG_CNTP_CVAL_EL0;
2672 }
2673 break;
2674 case 3:
2675 switch (op2) {
2676 case 0:
2677 return MISCREG_CNTV_TVAL_EL0;
2678 case 1:
2679 return MISCREG_CNTV_CTL_EL0;
2680 case 2:
2681 return MISCREG_CNTV_CVAL_EL0;
2682 }
2683 break;
2684 case 8:
2685 switch (op2) {
2686 case 0:
2687 return MISCREG_PMEVCNTR0_EL0;
2688 case 1:
2689 return MISCREG_PMEVCNTR1_EL0;
2690 case 2:
2691 return MISCREG_PMEVCNTR2_EL0;
2692 case 3:
2693 return MISCREG_PMEVCNTR3_EL0;
2694 case 4:
2695 return MISCREG_PMEVCNTR4_EL0;
2696 case 5:
2697 return MISCREG_PMEVCNTR5_EL0;
2698 }
2699 break;
2700 case 12:
2701 switch (op2) {
2702 case 0:
2703 return MISCREG_PMEVTYPER0_EL0;
2704 case 1:
2705 return MISCREG_PMEVTYPER1_EL0;
2706 case 2:
2707 return MISCREG_PMEVTYPER2_EL0;
2708 case 3:
2709 return MISCREG_PMEVTYPER3_EL0;
2710 case 4:
2711 return MISCREG_PMEVTYPER4_EL0;
2712 case 5:
2713 return MISCREG_PMEVTYPER5_EL0;
2714 }
2715 break;
2716 case 15:
2717 switch (op2) {
2718 case 7:
2719 return MISCREG_PMCCFILTR_EL0;
2720 }
2721 }
2722 break;
2723 case 4:
2724 switch (crm) {
2725 case 0:
2726 switch (op2) {
2727 case 3:
2728 return MISCREG_CNTVOFF_EL2;
2729 }
2730 break;
2731 case 1:
2732 switch (op2) {
2733 case 0:
2734 return MISCREG_CNTHCTL_EL2;
2735 }
2736 break;
2737 case 2:
2738 switch (op2) {
2739 case 0:
2740 return MISCREG_CNTHP_TVAL_EL2;
2741 case 1:
2742 return MISCREG_CNTHP_CTL_EL2;
2743 case 2:
2744 return MISCREG_CNTHP_CVAL_EL2;
2745 }
2746 break;
2747 case 3:
2748 switch (op2) {
2749 case 0:
2750 return MISCREG_CNTHV_TVAL_EL2;
2751 case 1:
2752 return MISCREG_CNTHV_CTL_EL2;
2753 case 2:
2754 return MISCREG_CNTHV_CVAL_EL2;
2755 }
2756 break;
2757 }
2758 break;
2759 case 7:
2760 switch (crm) {
2761 case 2:
2762 switch (op2) {
2763 case 0:
2764 return MISCREG_CNTPS_TVAL_EL1;
2765 case 1:
2766 return MISCREG_CNTPS_CTL_EL1;
2767 case 2:
2768 return MISCREG_CNTPS_CVAL_EL1;
2769 }
2770 break;
2771 }
2772 break;
2773 }
2774 break;
2775 case 15:
2776 switch (op1) {
2777 case 0:
2778 switch (crm) {
2779 case 0:
2780 switch (op2) {
2781 case 0:
2782 return MISCREG_IL1DATA0_EL1;
2783 case 1:
2784 return MISCREG_IL1DATA1_EL1;
2785 case 2:
2786 return MISCREG_IL1DATA2_EL1;
2787 case 3:
2788 return MISCREG_IL1DATA3_EL1;
2789 }
2790 break;
2791 case 1:
2792 switch (op2) {
2793 case 0:
2794 return MISCREG_DL1DATA0_EL1;
2795 case 1:
2796 return MISCREG_DL1DATA1_EL1;
2797 case 2:
2798 return MISCREG_DL1DATA2_EL1;
2799 case 3:
2800 return MISCREG_DL1DATA3_EL1;
2801 case 4:
2802 return MISCREG_DL1DATA4_EL1;
2803 }
2804 break;
2805 }
2806 break;
2807 case 1:
2808 switch (crm) {
2809 case 0:
2810 switch (op2) {
2811 case 0:
2812 return MISCREG_L2ACTLR_EL1;
2813 }
2814 break;
2815 case 2:
2816 switch (op2) {
2817 case 0:
2818 return MISCREG_CPUACTLR_EL1;
2819 case 1:
2820 return MISCREG_CPUECTLR_EL1;
2821 case 2:
2822 return MISCREG_CPUMERRSR_EL1;
2823 case 3:
2824 return MISCREG_L2MERRSR_EL1;
2825 }
2826 break;
2827 case 3:
2828 switch (op2) {
2829 case 0:
2830 return MISCREG_CBAR_EL1;
2831
2832 }
2833 break;
2834 }
2835 break;
2836 }
2837 // S3_<op1>_15_<Cm>_<op2>
2838 return MISCREG_IMPDEF_UNIMPL;
2839 }
2840 break;
2841 }
2842
2843 return MISCREG_UNKNOWN;
2844 }
2845
2846 bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below
2847
2848 void
2849 ISA::initializeMiscRegMetadata()
2850 {
2851 // the MiscReg metadata tables are shared across all instances of the
2852 // ISA object, so there's no need to initialize them multiple times.
2853 static bool completed = false;
2854 if (completed)
2855 return;
2856
2857 // This boolean variable specifies if the system is running in aarch32 at
2858 // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
2859 // is running in aarch64 (aarch32EL3 = false)
2860 bool aarch32EL3 = haveSecurity && !highestELIs64;
2861
2862 // Set Privileged Access Never on taking an exception to EL1 (Arm 8.1+),
2863 // unsupported
2864 bool SPAN = false;
2865
2866 // Implicit error synchronization event enable (Arm 8.2+), unsupported
2867 bool IESB = false;
2868
2869 // Load Multiple and Store Multiple Atomicity and Ordering (Arm 8.2+),
2870 // unsupported
2871 bool LSMAOE = false;
2872
2873 // No Trap Load Multiple and Store Multiple (Arm 8.2+), unsupported
2874 bool nTLSMD = false;
2875
2876 // Pointer authentication (Arm 8.3+), unsupported
2877 bool EnDA = false; // using APDAKey_EL1 key of instr addrs in ELs 0,1
2878 bool EnDB = false; // using APDBKey_EL1 key of instr addrs in ELs 0,1
2879 bool EnIA = false; // using APIAKey_EL1 key of instr addrs in ELs 0,1
2880 bool EnIB = false; // using APIBKey_EL1 key of instr addrs in ELs 0,1
2881
2882 /**
2883 * Some registers alias with others, and therefore need to be translated.
2884 * When two mapping registers are given, they are the 32b lower and
2885 * upper halves, respectively, of the 64b register being mapped.
2886 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
2887 *
2888 * NAM = "not architecturally mandated",
2889 * from ARM DDI 0487A.i, template text
2890 * "AArch64 System register ___ can be mapped to
2891 * AArch32 System register ___, but this is not
2892 * architecturally mandated."
2893 */
2894
2895 InitReg(MISCREG_CPSR)
2896 .allPrivileges();
2897 InitReg(MISCREG_SPSR)
2898 .allPrivileges();
2899 InitReg(MISCREG_SPSR_FIQ)
2900 .allPrivileges();
2901 InitReg(MISCREG_SPSR_IRQ)
2902 .allPrivileges();
2903 InitReg(MISCREG_SPSR_SVC)
2904 .allPrivileges();
2905 InitReg(MISCREG_SPSR_MON)
2906 .allPrivileges();
2907 InitReg(MISCREG_SPSR_ABT)
2908 .allPrivileges();
2909 InitReg(MISCREG_SPSR_HYP)
2910 .allPrivileges();
2911 InitReg(MISCREG_SPSR_UND)
2912 .allPrivileges();
2913 InitReg(MISCREG_ELR_HYP)
2914 .allPrivileges();
2915 InitReg(MISCREG_FPSID)
2916 .allPrivileges();
2917 InitReg(MISCREG_FPSCR)
2918 .allPrivileges();
2919 InitReg(MISCREG_MVFR1)
2920 .allPrivileges();
2921 InitReg(MISCREG_MVFR0)
2922 .allPrivileges();
2923 InitReg(MISCREG_FPEXC)
2924 .allPrivileges();
2925
2926 // Helper registers
2927 InitReg(MISCREG_CPSR_MODE)
2928 .allPrivileges();
2929 InitReg(MISCREG_CPSR_Q)
2930 .allPrivileges();
2931 InitReg(MISCREG_FPSCR_EXC)
2932 .allPrivileges();
2933 InitReg(MISCREG_FPSCR_QC)
2934 .allPrivileges();
2935 InitReg(MISCREG_LOCKADDR)
2936 .allPrivileges();
2937 InitReg(MISCREG_LOCKFLAG)
2938 .allPrivileges();
2939 InitReg(MISCREG_PRRR_MAIR0)
2940 .mutex()
2941 .banked();
2942 InitReg(MISCREG_PRRR_MAIR0_NS)
2943 .mutex()
2944 .privSecure(!aarch32EL3)
2945 .bankedChild();
2946 InitReg(MISCREG_PRRR_MAIR0_S)
2947 .mutex()
2948 .bankedChild();
2949 InitReg(MISCREG_NMRR_MAIR1)
2950 .mutex()
2951 .banked();
2952 InitReg(MISCREG_NMRR_MAIR1_NS)
2953 .mutex()
2954 .privSecure(!aarch32EL3)
2955 .bankedChild();
2956 InitReg(MISCREG_NMRR_MAIR1_S)
2957 .mutex()
2958 .bankedChild();
2959 InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
2960 .mutex();
2961 InitReg(MISCREG_SCTLR_RST)
2962 .allPrivileges();
2963 InitReg(MISCREG_SEV_MAILBOX)
2964 .allPrivileges();
2965
2966 // AArch32 CP14 registers
2967 InitReg(MISCREG_DBGDIDR)
2968 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2969 InitReg(MISCREG_DBGDSCRint)
2970 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2971 InitReg(MISCREG_DBGDCCINT)
2972 .unimplemented()
2973 .allPrivileges();
2974 InitReg(MISCREG_DBGDTRTXint)
2975 .unimplemented()
2976 .allPrivileges();
2977 InitReg(MISCREG_DBGDTRRXint)
2978 .unimplemented()
2979 .allPrivileges();
2980 InitReg(MISCREG_DBGWFAR)
2981 .unimplemented()
2982 .allPrivileges();
2983 InitReg(MISCREG_DBGVCR)
2984 .unimplemented()
2985 .allPrivileges();
2986 InitReg(MISCREG_DBGDTRRXext)
2987 .unimplemented()
2988 .allPrivileges();
2989 InitReg(MISCREG_DBGDSCRext)
2990 .unimplemented()
2991 .warnNotFail()
2992 .allPrivileges();
2993 InitReg(MISCREG_DBGDTRTXext)
2994 .unimplemented()
2995 .allPrivileges();
2996 InitReg(MISCREG_DBGOSECCR)
2997 .unimplemented()
2998 .allPrivileges();
2999 InitReg(MISCREG_DBGBVR0)
3000 .unimplemented()
3001 .allPrivileges();
3002 InitReg(MISCREG_DBGBVR1)
3003 .unimplemented()
3004 .allPrivileges();
3005 InitReg(MISCREG_DBGBVR2)
3006 .unimplemented()
3007 .allPrivileges();
3008 InitReg(MISCREG_DBGBVR3)
3009 .unimplemented()
3010 .allPrivileges();
3011 InitReg(MISCREG_DBGBVR4)
3012 .unimplemented()
3013 .allPrivileges();
3014 InitReg(MISCREG_DBGBVR5)
3015 .unimplemented()
3016 .allPrivileges();
3017 InitReg(MISCREG_DBGBCR0)
3018 .unimplemented()
3019 .allPrivileges();
3020 InitReg(MISCREG_DBGBCR1)
3021 .unimplemented()
3022 .allPrivileges();
3023 InitReg(MISCREG_DBGBCR2)
3024 .unimplemented()
3025 .allPrivileges();
3026 InitReg(MISCREG_DBGBCR3)
3027 .unimplemented()
3028 .allPrivileges();
3029 InitReg(MISCREG_DBGBCR4)
3030 .unimplemented()
3031 .allPrivileges();
3032 InitReg(MISCREG_DBGBCR5)
3033 .unimplemented()
3034 .allPrivileges();
3035 InitReg(MISCREG_DBGWVR0)
3036 .unimplemented()
3037 .allPrivileges();
3038 InitReg(MISCREG_DBGWVR1)
3039 .unimplemented()
3040 .allPrivileges();
3041 InitReg(MISCREG_DBGWVR2)
3042 .unimplemented()
3043 .allPrivileges();
3044 InitReg(MISCREG_DBGWVR3)
3045 .unimplemented()
3046 .allPrivileges();
3047 InitReg(MISCREG_DBGWCR0)
3048 .unimplemented()
3049 .allPrivileges();
3050 InitReg(MISCREG_DBGWCR1)
3051 .unimplemented()
3052 .allPrivileges();
3053 InitReg(MISCREG_DBGWCR2)
3054 .unimplemented()
3055 .allPrivileges();
3056 InitReg(MISCREG_DBGWCR3)
3057 .unimplemented()
3058 .allPrivileges();
3059 InitReg(MISCREG_DBGDRAR)
3060 .unimplemented()
3061 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3062 InitReg(MISCREG_DBGBXVR4)
3063 .unimplemented()
3064 .allPrivileges();
3065 InitReg(MISCREG_DBGBXVR5)
3066 .unimplemented()
3067 .allPrivileges();
3068 InitReg(MISCREG_DBGOSLAR)
3069 .unimplemented()
3070 .allPrivileges().monSecureRead(0).monNonSecureRead(0);
3071 InitReg(MISCREG_DBGOSLSR)
3072 .unimplemented()
3073 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3074 InitReg(MISCREG_DBGOSDLR)
3075 .unimplemented()
3076 .allPrivileges();
3077 InitReg(MISCREG_DBGPRCR)
3078 .unimplemented()
3079 .allPrivileges();
3080 InitReg(MISCREG_DBGDSAR)
3081 .unimplemented()
3082 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3083 InitReg(MISCREG_DBGCLAIMSET)
3084 .unimplemented()
3085 .allPrivileges();
3086 InitReg(MISCREG_DBGCLAIMCLR)
3087 .unimplemented()
3088 .allPrivileges();
3089 InitReg(MISCREG_DBGAUTHSTATUS)
3090 .unimplemented()
3091 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3092 InitReg(MISCREG_DBGDEVID2)
3093 .unimplemented()
3094 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3095 InitReg(MISCREG_DBGDEVID1)
3096 .unimplemented()
3097 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3098 InitReg(MISCREG_DBGDEVID0)
3099 .unimplemented()
3100 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3101 InitReg(MISCREG_TEECR)
3102 .unimplemented()
3103 .allPrivileges();
3104 InitReg(MISCREG_JIDR)
3105 .allPrivileges();
3106 InitReg(MISCREG_TEEHBR)
3107 .allPrivileges();
3108 InitReg(MISCREG_JOSCR)
3109 .allPrivileges();
3110 InitReg(MISCREG_JMCR)
3111 .allPrivileges();
3112
3113 // AArch32 CP15 registers
3114 InitReg(MISCREG_MIDR)
3115 .allPrivileges().exceptUserMode().writes(0);
3116 InitReg(MISCREG_CTR)
3117 .allPrivileges().exceptUserMode().writes(0);
3118 InitReg(MISCREG_TCMTR)
3119 .allPrivileges().exceptUserMode().writes(0);
3120 InitReg(MISCREG_TLBTR)
3121 .allPrivileges().exceptUserMode().writes(0);
3122 InitReg(MISCREG_MPIDR)
3123 .allPrivileges().exceptUserMode().writes(0);
3124 InitReg(MISCREG_REVIDR)
3125 .unimplemented()
3126 .warnNotFail()
3127 .allPrivileges().exceptUserMode().writes(0);
3128 InitReg(MISCREG_ID_PFR0)
3129 .allPrivileges().exceptUserMode().writes(0);
3130 InitReg(MISCREG_ID_PFR1)
3131 .allPrivileges().exceptUserMode().writes(0);
3132 InitReg(MISCREG_ID_DFR0)
3133 .allPrivileges().exceptUserMode().writes(0);
3134 InitReg(MISCREG_ID_AFR0)
3135 .allPrivileges().exceptUserMode().writes(0);
3136 InitReg(MISCREG_ID_MMFR0)
3137 .allPrivileges().exceptUserMode().writes(0);
3138 InitReg(MISCREG_ID_MMFR1)
3139 .allPrivileges().exceptUserMode().writes(0);
3140 InitReg(MISCREG_ID_MMFR2)
3141 .allPrivileges().exceptUserMode().writes(0);
3142 InitReg(MISCREG_ID_MMFR3)
3143 .allPrivileges().exceptUserMode().writes(0);
3144 InitReg(MISCREG_ID_ISAR0)
3145 .allPrivileges().exceptUserMode().writes(0);
3146 InitReg(MISCREG_ID_ISAR1)
3147 .allPrivileges().exceptUserMode().writes(0);
3148 InitReg(MISCREG_ID_ISAR2)
3149 .allPrivileges().exceptUserMode().writes(0);
3150 InitReg(MISCREG_ID_ISAR3)
3151 .allPrivileges().exceptUserMode().writes(0);
3152 InitReg(MISCREG_ID_ISAR4)
3153 .allPrivileges().exceptUserMode().writes(0);
3154 InitReg(MISCREG_ID_ISAR5)
3155 .allPrivileges().exceptUserMode().writes(0);
3156 InitReg(MISCREG_CCSIDR)
3157 .allPrivileges().exceptUserMode().writes(0);
3158 InitReg(MISCREG_CLIDR)
3159 .allPrivileges().exceptUserMode().writes(0);
3160 InitReg(MISCREG_AIDR)
3161 .allPrivileges().exceptUserMode().writes(0);
3162 InitReg(MISCREG_CSSELR)
3163 .banked();
3164 InitReg(MISCREG_CSSELR_NS)
3165 .bankedChild()
3166 .privSecure(!aarch32EL3)
3167 .nonSecure().exceptUserMode();
3168 InitReg(MISCREG_CSSELR_S)
3169 .bankedChild()
3170 .secure().exceptUserMode();
3171 InitReg(MISCREG_VPIDR)
3172 .hyp().monNonSecure();
3173 InitReg(MISCREG_VMPIDR)
3174 .hyp().monNonSecure();
3175 InitReg(MISCREG_SCTLR)
3176 .banked()
3177 // readMiscRegNoEffect() uses this metadata
3178 // despite using children (below) as backing store
3179 .res0(0x8d22c600)
3180 .res1(0x00400800 | (SPAN ? 0 : 0x800000)
3181 | (LSMAOE ? 0 : 0x10)
3182 | (nTLSMD ? 0 : 0x8));
3183 InitReg(MISCREG_SCTLR_NS)
3184 .bankedChild()
3185 .privSecure(!aarch32EL3)
3186 .nonSecure().exceptUserMode();
3187 InitReg(MISCREG_SCTLR_S)
3188 .bankedChild()
3189 .secure().exceptUserMode();
3190 InitReg(MISCREG_ACTLR)
3191 .banked();
3192 InitReg(MISCREG_ACTLR_NS)
3193 .bankedChild()
3194 .privSecure(!aarch32EL3)
3195 .nonSecure().exceptUserMode();
3196 InitReg(MISCREG_ACTLR_S)
3197 .bankedChild()
3198 .secure().exceptUserMode();
3199 InitReg(MISCREG_CPACR)
3200 .allPrivileges().exceptUserMode();
3201 InitReg(MISCREG_SCR)
3202 .mon().secure().exceptUserMode()
3203 .res0(0xff40) // [31:16], [6]
3204 .res1(0x0030); // [5:4]
3205 InitReg(MISCREG_SDER)
3206 .mon();
3207 InitReg(MISCREG_NSACR)
3208 .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
3209 InitReg(MISCREG_HSCTLR)
3210 .hyp().monNonSecure()
3211 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
3212 | (IESB ? 0 : 0x200000)
3213 | (EnDA ? 0 : 0x8000000)
3214 | (EnIB ? 0 : 0x40000000)
3215 | (EnIA ? 0 : 0x80000000))
3216 .res1(0x30c50830);
3217 InitReg(MISCREG_HACTLR)
3218 .hyp().monNonSecure();
3219 InitReg(MISCREG_HCR)
3220 .hyp().monNonSecure()
3221 .res0(0x90000000);
3222 InitReg(MISCREG_HCR2)
3223 .hyp().monNonSecure()
3224 .res0(0xffa9ff8c);
3225 InitReg(MISCREG_HDCR)
3226 .hyp().monNonSecure();
3227 InitReg(MISCREG_HCPTR)
3228 .hyp().monNonSecure();
3229 InitReg(MISCREG_HSTR)
3230 .hyp().monNonSecure();
3231 InitReg(MISCREG_HACR)
3232 .unimplemented()
3233 .warnNotFail()
3234 .hyp().monNonSecure();
3235 InitReg(MISCREG_TTBR0)
3236 .banked();
3237 InitReg(MISCREG_TTBR0_NS)
3238 .bankedChild()
3239 .privSecure(!aarch32EL3)
3240 .nonSecure().exceptUserMode();
3241 InitReg(MISCREG_TTBR0_S)
3242 .bankedChild()
3243 .secure().exceptUserMode();
3244 InitReg(MISCREG_TTBR1)
3245 .banked();
3246 InitReg(MISCREG_TTBR1_NS)
3247 .bankedChild()
3248 .privSecure(!aarch32EL3)
3249 .nonSecure().exceptUserMode();
3250 InitReg(MISCREG_TTBR1_S)
3251 .bankedChild()
3252 .secure().exceptUserMode();
3253 InitReg(MISCREG_TTBCR)
3254 .banked();
3255 InitReg(MISCREG_TTBCR_NS)
3256 .bankedChild()
3257 .privSecure(!aarch32EL3)
3258 .nonSecure().exceptUserMode();
3259 InitReg(MISCREG_TTBCR_S)
3260 .bankedChild()
3261 .secure().exceptUserMode();
3262 InitReg(MISCREG_HTCR)
3263 .hyp().monNonSecure();
3264 InitReg(MISCREG_VTCR)
3265 .hyp().monNonSecure();
3266 InitReg(MISCREG_DACR)
3267 .banked();
3268 InitReg(MISCREG_DACR_NS)
3269 .bankedChild()
3270 .privSecure(!aarch32EL3)
3271 .nonSecure().exceptUserMode();
3272 InitReg(MISCREG_DACR_S)
3273 .bankedChild()
3274 .secure().exceptUserMode();
3275 InitReg(MISCREG_DFSR)
3276 .banked();
3277 InitReg(MISCREG_DFSR_NS)
3278 .bankedChild()
3279 .privSecure(!aarch32EL3)
3280 .nonSecure().exceptUserMode();
3281 InitReg(MISCREG_DFSR_S)
3282 .bankedChild()
3283 .secure().exceptUserMode();
3284 InitReg(MISCREG_IFSR)
3285 .banked();
3286 InitReg(MISCREG_IFSR_NS)
3287 .bankedChild()
3288 .privSecure(!aarch32EL3)
3289 .nonSecure().exceptUserMode();
3290 InitReg(MISCREG_IFSR_S)
3291 .bankedChild()
3292 .secure().exceptUserMode();
3293 InitReg(MISCREG_ADFSR)
3294 .unimplemented()
3295 .warnNotFail()
3296 .banked();
3297 InitReg(MISCREG_ADFSR_NS)
3298 .unimplemented()
3299 .warnNotFail()
3300 .bankedChild()
3301 .privSecure(!aarch32EL3)
3302 .nonSecure().exceptUserMode();
3303 InitReg(MISCREG_ADFSR_S)
3304 .unimplemented()
3305 .warnNotFail()
3306 .bankedChild()
3307 .secure().exceptUserMode();
3308 InitReg(MISCREG_AIFSR)
3309 .unimplemented()
3310 .warnNotFail()
3311 .banked();
3312 InitReg(MISCREG_AIFSR_NS)
3313 .unimplemented()
3314 .warnNotFail()
3315 .bankedChild()
3316 .privSecure(!aarch32EL3)
3317 .nonSecure().exceptUserMode();
3318 InitReg(MISCREG_AIFSR_S)
3319 .unimplemented()
3320 .warnNotFail()
3321 .bankedChild()
3322 .secure().exceptUserMode();
3323 InitReg(MISCREG_HADFSR)
3324 .hyp().monNonSecure();
3325 InitReg(MISCREG_HAIFSR)
3326 .hyp().monNonSecure();
3327 InitReg(MISCREG_HSR)
3328 .hyp().monNonSecure();
3329 InitReg(MISCREG_DFAR)
3330 .banked();
3331 InitReg(MISCREG_DFAR_NS)
3332 .bankedChild()
3333 .privSecure(!aarch32EL3)
3334 .nonSecure().exceptUserMode();
3335 InitReg(MISCREG_DFAR_S)
3336 .bankedChild()
3337 .secure().exceptUserMode();
3338 InitReg(MISCREG_IFAR)
3339 .banked();
3340 InitReg(MISCREG_IFAR_NS)
3341 .bankedChild()
3342 .privSecure(!aarch32EL3)
3343 .nonSecure().exceptUserMode();
3344 InitReg(MISCREG_IFAR_S)
3345 .bankedChild()
3346 .secure().exceptUserMode();
3347 InitReg(MISCREG_HDFAR)
3348 .hyp().monNonSecure();
3349 InitReg(MISCREG_HIFAR)
3350 .hyp().monNonSecure();
3351 InitReg(MISCREG_HPFAR)
3352 .hyp().monNonSecure();
3353 InitReg(MISCREG_ICIALLUIS)
3354 .unimplemented()
3355 .warnNotFail()
3356 .writes(1).exceptUserMode();
3357 InitReg(MISCREG_BPIALLIS)
3358 .unimplemented()
3359 .warnNotFail()
3360 .writes(1).exceptUserMode();
3361 InitReg(MISCREG_PAR)
3362 .banked();
3363 InitReg(MISCREG_PAR_NS)
3364 .bankedChild()
3365 .privSecure(!aarch32EL3)
3366 .nonSecure().exceptUserMode();
3367 InitReg(MISCREG_PAR_S)
3368 .bankedChild()
3369 .secure().exceptUserMode();
3370 InitReg(MISCREG_ICIALLU)
3371 .writes(1).exceptUserMode();
3372 InitReg(MISCREG_ICIMVAU)
3373 .unimplemented()
3374 .warnNotFail()
3375 .writes(1).exceptUserMode();
3376 InitReg(MISCREG_CP15ISB)
3377 .writes(1);
3378 InitReg(MISCREG_BPIALL)
3379 .unimplemented()
3380 .warnNotFail()
3381 .writes(1).exceptUserMode();
3382 InitReg(MISCREG_BPIMVA)
3383 .unimplemented()
3384 .warnNotFail()
3385 .writes(1).exceptUserMode();
3386 InitReg(MISCREG_DCIMVAC)
3387 .unimplemented()
3388 .warnNotFail()
3389 .writes(1).exceptUserMode();
3390 InitReg(MISCREG_DCISW)
3391 .unimplemented()
3392 .warnNotFail()
3393 .writes(1).exceptUserMode();
3394 InitReg(MISCREG_ATS1CPR)
3395 .writes(1).exceptUserMode();
3396 InitReg(MISCREG_ATS1CPW)
3397 .writes(1).exceptUserMode();
3398 InitReg(MISCREG_ATS1CUR)
3399 .writes(1).exceptUserMode();
3400 InitReg(MISCREG_ATS1CUW)
3401 .writes(1).exceptUserMode();
3402 InitReg(MISCREG_ATS12NSOPR)
3403 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3404 InitReg(MISCREG_ATS12NSOPW)
3405 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3406 InitReg(MISCREG_ATS12NSOUR)
3407 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3408 InitReg(MISCREG_ATS12NSOUW)
3409 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3410 InitReg(MISCREG_DCCMVAC)
3411 .writes(1).exceptUserMode();
3412 InitReg(MISCREG_DCCSW)
3413 .unimplemented()
3414 .warnNotFail()
3415 .writes(1).exceptUserMode();
3416 InitReg(MISCREG_CP15DSB)
3417 .writes(1);
3418 InitReg(MISCREG_CP15DMB)
3419 .writes(1);
3420 InitReg(MISCREG_DCCMVAU)
3421 .unimplemented()
3422 .warnNotFail()
3423 .writes(1).exceptUserMode();
3424 InitReg(MISCREG_DCCIMVAC)
3425 .unimplemented()
3426 .warnNotFail()
3427 .writes(1).exceptUserMode();
3428 InitReg(MISCREG_DCCISW)
3429 .unimplemented()
3430 .warnNotFail()
3431 .writes(1).exceptUserMode();
3432 InitReg(MISCREG_ATS1HR)
3433 .monNonSecureWrite().hypWrite();
3434 InitReg(MISCREG_ATS1HW)
3435 .monNonSecureWrite().hypWrite();
3436 InitReg(MISCREG_TLBIALLIS)
3437 .writes(1).exceptUserMode();
3438 InitReg(MISCREG_TLBIMVAIS)
3439 .writes(1).exceptUserMode();
3440 InitReg(MISCREG_TLBIASIDIS)
3441 .writes(1).exceptUserMode();
3442 InitReg(MISCREG_TLBIMVAAIS)
3443 .writes(1).exceptUserMode();
3444 InitReg(MISCREG_TLBIMVALIS)
3445 .writes(1).exceptUserMode();
3446 InitReg(MISCREG_TLBIMVAALIS)
3447 .writes(1).exceptUserMode();
3448 InitReg(MISCREG_ITLBIALL)
3449 .writes(1).exceptUserMode();
3450 InitReg(MISCREG_ITLBIMVA)
3451 .writes(1).exceptUserMode();
3452 InitReg(MISCREG_ITLBIASID)
3453 .writes(1).exceptUserMode();
3454 InitReg(MISCREG_DTLBIALL)
3455 .writes(1).exceptUserMode();
3456 InitReg(MISCREG_DTLBIMVA)
3457 .writes(1).exceptUserMode();
3458 InitReg(MISCREG_DTLBIASID)
3459 .writes(1).exceptUserMode();
3460 InitReg(MISCREG_TLBIALL)
3461 .writes(1).exceptUserMode();
3462 InitReg(MISCREG_TLBIMVA)
3463 .writes(1).exceptUserMode();
3464 InitReg(MISCREG_TLBIASID)
3465 .writes(1).exceptUserMode();
3466 InitReg(MISCREG_TLBIMVAA)
3467 .writes(1).exceptUserMode();
3468 InitReg(MISCREG_TLBIMVAL)
3469 .writes(1).exceptUserMode();
3470 InitReg(MISCREG_TLBIMVAAL)
3471 .writes(1).exceptUserMode();
3472 InitReg(MISCREG_TLBIIPAS2IS)
3473 .monNonSecureWrite().hypWrite();
3474 InitReg(MISCREG_TLBIIPAS2LIS)
3475 .monNonSecureWrite().hypWrite();
3476 InitReg(MISCREG_TLBIALLHIS)
3477 .monNonSecureWrite().hypWrite();
3478 InitReg(MISCREG_TLBIMVAHIS)
3479 .monNonSecureWrite().hypWrite();
3480 InitReg(MISCREG_TLBIALLNSNHIS)
3481 .monNonSecureWrite().hypWrite();
3482 InitReg(MISCREG_TLBIMVALHIS)
3483 .monNonSecureWrite().hypWrite();
3484 InitReg(MISCREG_TLBIIPAS2)
3485 .monNonSecureWrite().hypWrite();
3486 InitReg(MISCREG_TLBIIPAS2L)
3487 .monNonSecureWrite().hypWrite();
3488 InitReg(MISCREG_TLBIALLH)
3489 .monNonSecureWrite().hypWrite();
3490 InitReg(MISCREG_TLBIMVAH)
3491 .monNonSecureWrite().hypWrite();
3492 InitReg(MISCREG_TLBIALLNSNH)
3493 .monNonSecureWrite().hypWrite();
3494 InitReg(MISCREG_TLBIMVALH)
3495 .monNonSecureWrite().hypWrite();
3496 InitReg(MISCREG_PMCR)
3497 .allPrivileges();
3498 InitReg(MISCREG_PMCNTENSET)
3499 .allPrivileges();
3500 InitReg(MISCREG_PMCNTENCLR)
3501 .allPrivileges();
3502 InitReg(MISCREG_PMOVSR)
3503 .allPrivileges();
3504 InitReg(MISCREG_PMSWINC)
3505 .allPrivileges();
3506 InitReg(MISCREG_PMSELR)
3507 .allPrivileges();
3508 InitReg(MISCREG_PMCEID0)
3509 .allPrivileges();
3510 InitReg(MISCREG_PMCEID1)
3511 .allPrivileges();
3512 InitReg(MISCREG_PMCCNTR)
3513 .allPrivileges();
3514 InitReg(MISCREG_PMXEVTYPER)
3515 .allPrivileges();
3516 InitReg(MISCREG_PMCCFILTR)
3517 .allPrivileges();
3518 InitReg(MISCREG_PMXEVCNTR)
3519 .allPrivileges();
3520 InitReg(MISCREG_PMUSERENR)
3521 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
3522 InitReg(MISCREG_PMINTENSET)
3523 .allPrivileges().exceptUserMode();
3524 InitReg(MISCREG_PMINTENCLR)
3525 .allPrivileges().exceptUserMode();
3526 InitReg(MISCREG_PMOVSSET)
3527 .unimplemented()
3528 .allPrivileges();
3529 InitReg(MISCREG_L2CTLR)
3530 .allPrivileges().exceptUserMode();
3531 InitReg(MISCREG_L2ECTLR)
3532 .unimplemented()
3533 .allPrivileges().exceptUserMode();
3534 InitReg(MISCREG_PRRR)
3535 .banked();
3536 InitReg(MISCREG_PRRR_NS)
3537 .bankedChild()
3538 .privSecure(!aarch32EL3)
3539 .nonSecure().exceptUserMode();
3540 InitReg(MISCREG_PRRR_S)
3541 .bankedChild()
3542 .secure().exceptUserMode();
3543 InitReg(MISCREG_MAIR0)
3544 .banked();
3545 InitReg(MISCREG_MAIR0_NS)
3546 .bankedChild()
3547 .privSecure(!aarch32EL3)
3548 .nonSecure().exceptUserMode();
3549 InitReg(MISCREG_MAIR0_S)
3550 .bankedChild()
3551 .secure().exceptUserMode();
3552 InitReg(MISCREG_NMRR)
3553 .banked();
3554 InitReg(MISCREG_NMRR_NS)
3555 .bankedChild()
3556 .privSecure(!aarch32EL3)
3557 .nonSecure().exceptUserMode();
3558 InitReg(MISCREG_NMRR_S)
3559 .bankedChild()
3560 .secure().exceptUserMode();
3561 InitReg(MISCREG_MAIR1)
3562 .banked();
3563 InitReg(MISCREG_MAIR1_NS)
3564 .bankedChild()
3565 .privSecure(!aarch32EL3)
3566 .nonSecure().exceptUserMode();
3567 InitReg(MISCREG_MAIR1_S)
3568 .bankedChild()
3569 .secure().exceptUserMode();
3570 InitReg(MISCREG_AMAIR0)
3571 .banked();
3572 InitReg(MISCREG_AMAIR0_NS)
3573 .bankedChild()
3574 .privSecure(!aarch32EL3)
3575 .nonSecure().exceptUserMode();
3576 InitReg(MISCREG_AMAIR0_S)
3577 .bankedChild()
3578 .secure().exceptUserMode();
3579 InitReg(MISCREG_AMAIR1)
3580 .banked();
3581 InitReg(MISCREG_AMAIR1_NS)
3582 .bankedChild()
3583 .privSecure(!aarch32EL3)
3584 .nonSecure().exceptUserMode();
3585 InitReg(MISCREG_AMAIR1_S)
3586 .bankedChild()
3587 .secure().exceptUserMode();
3588 InitReg(MISCREG_HMAIR0)
3589 .hyp().monNonSecure();
3590 InitReg(MISCREG_HMAIR1)
3591 .hyp().monNonSecure();
3592 InitReg(MISCREG_HAMAIR0)
3593 .unimplemented()
3594 .warnNotFail()
3595 .hyp().monNonSecure();
3596 InitReg(MISCREG_HAMAIR1)
3597 .unimplemented()
3598 .warnNotFail()
3599 .hyp().monNonSecure();
3600 InitReg(MISCREG_VBAR)
3601 .banked();
3602 InitReg(MISCREG_VBAR_NS)
3603 .bankedChild()
3604 .privSecure(!aarch32EL3)
3605 .nonSecure().exceptUserMode();
3606 InitReg(MISCREG_VBAR_S)
3607 .bankedChild()
3608 .secure().exceptUserMode();
3609 InitReg(MISCREG_MVBAR)
3610 .mon().secure()
3611 .hypRead(FullSystem && system->highestEL() == EL2)
3612 .privRead(FullSystem && system->highestEL() == EL1)
3613 .exceptUserMode();
3614 InitReg(MISCREG_RMR)
3615 .unimplemented()
3616 .mon().secure().exceptUserMode();
3617 InitReg(MISCREG_ISR)
3618 .allPrivileges().exceptUserMode().writes(0);
3619 InitReg(MISCREG_HVBAR)
3620 .hyp().monNonSecure()
3621 .res0(0x1f);
3622 InitReg(MISCREG_FCSEIDR)
3623 .unimplemented()
3624 .warnNotFail()
3625 .allPrivileges().exceptUserMode();
3626 InitReg(MISCREG_CONTEXTIDR)
3627 .banked();
3628 InitReg(MISCREG_CONTEXTIDR_NS)
3629 .bankedChild()
3630 .privSecure(!aarch32EL3)
3631 .nonSecure().exceptUserMode();
3632 InitReg(MISCREG_CONTEXTIDR_S)
3633 .bankedChild()
3634 .secure().exceptUserMode();
3635 InitReg(MISCREG_TPIDRURW)
3636 .banked();
3637 InitReg(MISCREG_TPIDRURW_NS)
3638 .bankedChild()
3639 .allPrivileges()
3640 .privSecure(!aarch32EL3)
3641 .monSecure(0);
3642 InitReg(MISCREG_TPIDRURW_S)
3643 .bankedChild()
3644 .secure();
3645 InitReg(MISCREG_TPIDRURO)
3646 .banked();
3647 InitReg(MISCREG_TPIDRURO_NS)
3648 .bankedChild()
3649 .allPrivileges()
3650 .userNonSecureWrite(0).userSecureRead(1)
3651 .privSecure(!aarch32EL3)
3652 .monSecure(0);
3653 InitReg(MISCREG_TPIDRURO_S)
3654 .bankedChild()
3655 .secure().userSecureWrite(0);
3656 InitReg(MISCREG_TPIDRPRW)
3657 .banked();
3658 InitReg(MISCREG_TPIDRPRW_NS)
3659 .bankedChild()
3660 .nonSecure().exceptUserMode()
3661 .privSecure(!aarch32EL3);
3662 InitReg(MISCREG_TPIDRPRW_S)
3663 .bankedChild()
3664 .secure().exceptUserMode();
3665 InitReg(MISCREG_HTPIDR)
3666 .hyp().monNonSecure();
3667 InitReg(MISCREG_CNTFRQ)
3668 .unverifiable()
3669 .reads(1).mon();
3670 InitReg(MISCREG_CNTKCTL)
3671 .allPrivileges().exceptUserMode();
3672 InitReg(MISCREG_CNTP_TVAL)
3673 .banked();
3674 InitReg(MISCREG_CNTP_TVAL_NS)
3675 .bankedChild()
3676 .allPrivileges()
3677 .privSecure(!aarch32EL3)
3678 .monSecure(0);
3679 InitReg(MISCREG_CNTP_TVAL_S)
3680 .bankedChild()
3681 .secure().user(1);
3682 InitReg(MISCREG_CNTP_CTL)
3683 .banked();
3684 InitReg(MISCREG_CNTP_CTL_NS)
3685 .bankedChild()
3686 .allPrivileges()
3687 .privSecure(!aarch32EL3)
3688 .monSecure(0);
3689 InitReg(MISCREG_CNTP_CTL_S)
3690 .bankedChild()
3691 .secure().user(1);
3692 InitReg(MISCREG_CNTV_TVAL)
3693 .allPrivileges();
3694 InitReg(MISCREG_CNTV_CTL)
3695 .allPrivileges();
3696 InitReg(MISCREG_CNTHCTL)
3697 .hypWrite().monNonSecureRead();
3698 InitReg(MISCREG_CNTHP_TVAL)
3699 .hypWrite().monNonSecureRead();
3700 InitReg(MISCREG_CNTHP_CTL)
3701 .hypWrite().monNonSecureRead();
3702 InitReg(MISCREG_IL1DATA0)
3703 .unimplemented()
3704 .allPrivileges().exceptUserMode();
3705 InitReg(MISCREG_IL1DATA1)
3706 .unimplemented()
3707 .allPrivileges().exceptUserMode();
3708 InitReg(MISCREG_IL1DATA2)
3709 .unimplemented()
3710 .allPrivileges().exceptUserMode();
3711 InitReg(MISCREG_IL1DATA3)
3712 .unimplemented()
3713 .allPrivileges().exceptUserMode();
3714 InitReg(MISCREG_DL1DATA0)
3715 .unimplemented()
3716 .allPrivileges().exceptUserMode();
3717 InitReg(MISCREG_DL1DATA1)
3718 .unimplemented()
3719 .allPrivileges().exceptUserMode();
3720 InitReg(MISCREG_DL1DATA2)
3721 .unimplemented()
3722 .allPrivileges().exceptUserMode();
3723 InitReg(MISCREG_DL1DATA3)
3724 .unimplemented()
3725 .allPrivileges().exceptUserMode();
3726 InitReg(MISCREG_DL1DATA4)
3727 .unimplemented()
3728 .allPrivileges().exceptUserMode();
3729 InitReg(MISCREG_RAMINDEX)
3730 .unimplemented()
3731 .writes(1).exceptUserMode();
3732 InitReg(MISCREG_L2ACTLR)
3733 .unimplemented()
3734 .allPrivileges().exceptUserMode();
3735 InitReg(MISCREG_CBAR)
3736 .unimplemented()
3737 .allPrivileges().exceptUserMode().writes(0);
3738 InitReg(MISCREG_HTTBR)
3739 .hyp().monNonSecure();
3740 InitReg(MISCREG_VTTBR)
3741 .hyp().monNonSecure();
3742 InitReg(MISCREG_CNTPCT)
3743 .reads(1);
3744 InitReg(MISCREG_CNTVCT)
3745 .unverifiable()
3746 .reads(1);
3747 InitReg(MISCREG_CNTP_CVAL)
3748 .banked();
3749 InitReg(MISCREG_CNTP_CVAL_NS)
3750 .bankedChild()
3751 .allPrivileges()
3752 .privSecure(!aarch32EL3)
3753 .monSecure(0);
3754 InitReg(MISCREG_CNTP_CVAL_S)
3755 .bankedChild()
3756 .secure().user(1);
3757 InitReg(MISCREG_CNTV_CVAL)
3758 .allPrivileges();
3759 InitReg(MISCREG_CNTVOFF)
3760 .hyp().monNonSecure();
3761 InitReg(MISCREG_CNTHP_CVAL)
3762 .hypWrite().monNonSecureRead();
3763 InitReg(MISCREG_CPUMERRSR)
3764 .unimplemented()
3765 .allPrivileges().exceptUserMode();
3766 InitReg(MISCREG_L2MERRSR)
3767 .unimplemented()
3768 .warnNotFail()
3769 .allPrivileges().exceptUserMode();
3770
3771 // AArch64 registers (Op0=2);
3772 InitReg(MISCREG_MDCCINT_EL1)
3773 .allPrivileges();
3774 InitReg(MISCREG_OSDTRRX_EL1)
3775 .allPrivileges()
3776 .mapsTo(MISCREG_DBGDTRRXext);
3777 InitReg(MISCREG_MDSCR_EL1)
3778 .allPrivileges()
3779 .mapsTo(MISCREG_DBGDSCRext);
3780 InitReg(MISCREG_OSDTRTX_EL1)
3781 .allPrivileges()
3782 .mapsTo(MISCREG_DBGDTRTXext);
3783 InitReg(MISCREG_OSECCR_EL1)
3784 .allPrivileges()
3785 .mapsTo(MISCREG_DBGOSECCR);
3786 InitReg(MISCREG_DBGBVR0_EL1)
3787 .allPrivileges()
3788 .mapsTo(MISCREG_DBGBVR0 /*, MISCREG_DBGBXVR0 */);
3789 InitReg(MISCREG_DBGBVR1_EL1)
3790 .allPrivileges()
3791 .mapsTo(MISCREG_DBGBVR1 /*, MISCREG_DBGBXVR1 */);
3792 InitReg(MISCREG_DBGBVR2_EL1)
3793 .allPrivileges()
3794 .mapsTo(MISCREG_DBGBVR2 /*, MISCREG_DBGBXVR2 */);
3795 InitReg(MISCREG_DBGBVR3_EL1)
3796 .allPrivileges()
3797 .mapsTo(MISCREG_DBGBVR3 /*, MISCREG_DBGBXVR3 */);
3798 InitReg(MISCREG_DBGBVR4_EL1)
3799 .allPrivileges()
3800 .mapsTo(MISCREG_DBGBVR4 /*, MISCREG_DBGBXVR4 */);
3801 InitReg(MISCREG_DBGBVR5_EL1)
3802 .allPrivileges()
3803 .mapsTo(MISCREG_DBGBVR5 /*, MISCREG_DBGBXVR5 */);
3804 InitReg(MISCREG_DBGBCR0_EL1)
3805 .allPrivileges()
3806 .mapsTo(MISCREG_DBGBCR0);
3807 InitReg(MISCREG_DBGBCR1_EL1)
3808 .allPrivileges()
3809 .mapsTo(MISCREG_DBGBCR1);
3810 InitReg(MISCREG_DBGBCR2_EL1)
3811 .allPrivileges()
3812 .mapsTo(MISCREG_DBGBCR2);
3813 InitReg(MISCREG_DBGBCR3_EL1)
3814 .allPrivileges()
3815 .mapsTo(MISCREG_DBGBCR3);
3816 InitReg(MISCREG_DBGBCR4_EL1)
3817 .allPrivileges()
3818 .mapsTo(MISCREG_DBGBCR4);
3819 InitReg(MISCREG_DBGBCR5_EL1)
3820 .allPrivileges()
3821 .mapsTo(MISCREG_DBGBCR5);
3822 InitReg(MISCREG_DBGWVR0_EL1)
3823 .allPrivileges()
3824 .mapsTo(MISCREG_DBGWVR0);
3825 InitReg(MISCREG_DBGWVR1_EL1)
3826 .allPrivileges()
3827 .mapsTo(MISCREG_DBGWVR1);
3828 InitReg(MISCREG_DBGWVR2_EL1)
3829 .allPrivileges()
3830 .mapsTo(MISCREG_DBGWVR2);
3831 InitReg(MISCREG_DBGWVR3_EL1)
3832 .allPrivileges()
3833 .mapsTo(MISCREG_DBGWVR3);
3834 InitReg(MISCREG_DBGWCR0_EL1)
3835 .allPrivileges()
3836 .mapsTo(MISCREG_DBGWCR0);
3837 InitReg(MISCREG_DBGWCR1_EL1)
3838 .allPrivileges()
3839 .mapsTo(MISCREG_DBGWCR1);
3840 InitReg(MISCREG_DBGWCR2_EL1)
3841 .allPrivileges()
3842 .mapsTo(MISCREG_DBGWCR2);
3843 InitReg(MISCREG_DBGWCR3_EL1)
3844 .allPrivileges()
3845 .mapsTo(MISCREG_DBGWCR3);
3846 InitReg(MISCREG_MDCCSR_EL0)
3847 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3848 .mapsTo(MISCREG_DBGDSCRint);
3849 InitReg(MISCREG_MDDTR_EL0)
3850 .allPrivileges();
3851 InitReg(MISCREG_MDDTRTX_EL0)
3852 .allPrivileges();
3853 InitReg(MISCREG_MDDTRRX_EL0)
3854 .allPrivileges();
3855 InitReg(MISCREG_DBGVCR32_EL2)
3856 .allPrivileges()
3857 .mapsTo(MISCREG_DBGVCR);
3858 InitReg(MISCREG_MDRAR_EL1)
3859 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3860 .mapsTo(MISCREG_DBGDRAR);
3861 InitReg(MISCREG_OSLAR_EL1)
3862 .allPrivileges().monSecureRead(0).monNonSecureRead(0)
3863 .mapsTo(MISCREG_DBGOSLAR);
3864 InitReg(MISCREG_OSLSR_EL1)
3865 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3866 .mapsTo(MISCREG_DBGOSLSR);
3867 InitReg(MISCREG_OSDLR_EL1)
3868 .allPrivileges()
3869 .mapsTo(MISCREG_DBGOSDLR);
3870 InitReg(MISCREG_DBGPRCR_EL1)
3871 .allPrivileges()
3872 .mapsTo(MISCREG_DBGPRCR);
3873 InitReg(MISCREG_DBGCLAIMSET_EL1)
3874 .allPrivileges()
3875 .mapsTo(MISCREG_DBGCLAIMSET);
3876 InitReg(MISCREG_DBGCLAIMCLR_EL1)
3877 .allPrivileges()
3878 .mapsTo(MISCREG_DBGCLAIMCLR);
3879 InitReg(MISCREG_DBGAUTHSTATUS_EL1)
3880 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3881 .mapsTo(MISCREG_DBGAUTHSTATUS);
3882 InitReg(MISCREG_TEECR32_EL1);
3883 InitReg(MISCREG_TEEHBR32_EL1);
3884
3885 // AArch64 registers (Op0=1,3);
3886 InitReg(MISCREG_MIDR_EL1)
3887 .allPrivileges().exceptUserMode().writes(0);
3888 InitReg(MISCREG_MPIDR_EL1)
3889 .allPrivileges().exceptUserMode().writes(0);
3890 InitReg(MISCREG_REVIDR_EL1)
3891 .allPrivileges().exceptUserMode().writes(0);
3892 InitReg(MISCREG_ID_PFR0_EL1)
3893 .allPrivileges().exceptUserMode().writes(0)
3894 .mapsTo(MISCREG_ID_PFR0);
3895 InitReg(MISCREG_ID_PFR1_EL1)
3896 .allPrivileges().exceptUserMode().writes(0)
3897 .mapsTo(MISCREG_ID_PFR1);
3898 InitReg(MISCREG_ID_DFR0_EL1)
3899 .allPrivileges().exceptUserMode().writes(0)
3900 .mapsTo(MISCREG_ID_DFR0);
3901 InitReg(MISCREG_ID_AFR0_EL1)
3902 .allPrivileges().exceptUserMode().writes(0)
3903 .mapsTo(MISCREG_ID_AFR0);
3904 InitReg(MISCREG_ID_MMFR0_EL1)
3905 .allPrivileges().exceptUserMode().writes(0)
3906 .mapsTo(MISCREG_ID_MMFR0);
3907 InitReg(MISCREG_ID_MMFR1_EL1)
3908 .allPrivileges().exceptUserMode().writes(0)
3909 .mapsTo(MISCREG_ID_MMFR1);
3910 InitReg(MISCREG_ID_MMFR2_EL1)
3911 .allPrivileges().exceptUserMode().writes(0)
3912 .mapsTo(MISCREG_ID_MMFR2);
3913 InitReg(MISCREG_ID_MMFR3_EL1)
3914 .allPrivileges().exceptUserMode().writes(0)
3915 .mapsTo(MISCREG_ID_MMFR3);
3916 InitReg(MISCREG_ID_ISAR0_EL1)
3917 .allPrivileges().exceptUserMode().writes(0)
3918 .mapsTo(MISCREG_ID_ISAR0);
3919 InitReg(MISCREG_ID_ISAR1_EL1)
3920 .allPrivileges().exceptUserMode().writes(0)
3921 .mapsTo(MISCREG_ID_ISAR1);
3922 InitReg(MISCREG_ID_ISAR2_EL1)
3923 .allPrivileges().exceptUserMode().writes(0)
3924 .mapsTo(MISCREG_ID_ISAR2);
3925 InitReg(MISCREG_ID_ISAR3_EL1)
3926 .allPrivileges().exceptUserMode().writes(0)
3927 .mapsTo(MISCREG_ID_ISAR3);
3928 InitReg(MISCREG_ID_ISAR4_EL1)
3929 .allPrivileges().exceptUserMode().writes(0)
3930 .mapsTo(MISCREG_ID_ISAR4);
3931 InitReg(MISCREG_ID_ISAR5_EL1)
3932 .allPrivileges().exceptUserMode().writes(0)
3933 .mapsTo(MISCREG_ID_ISAR5);
3934 InitReg(MISCREG_MVFR0_EL1)
3935 .allPrivileges().exceptUserMode().writes(0);
3936 InitReg(MISCREG_MVFR1_EL1)
3937 .allPrivileges().exceptUserMode().writes(0);
3938 InitReg(MISCREG_MVFR2_EL1)
3939 .allPrivileges().exceptUserMode().writes(0);
3940 InitReg(MISCREG_ID_AA64PFR0_EL1)
3941 .allPrivileges().exceptUserMode().writes(0);
3942 InitReg(MISCREG_ID_AA64PFR1_EL1)
3943 .allPrivileges().exceptUserMode().writes(0);
3944 InitReg(MISCREG_ID_AA64DFR0_EL1)
3945 .allPrivileges().exceptUserMode().writes(0);
3946 InitReg(MISCREG_ID_AA64DFR1_EL1)
3947 .allPrivileges().exceptUserMode().writes(0);
3948 InitReg(MISCREG_ID_AA64AFR0_EL1)
3949 .allPrivileges().exceptUserMode().writes(0);
3950 InitReg(MISCREG_ID_AA64AFR1_EL1)
3951 .allPrivileges().exceptUserMode().writes(0);
3952 InitReg(MISCREG_ID_AA64ISAR0_EL1)
3953 .allPrivileges().exceptUserMode().writes(0);
3954 InitReg(MISCREG_ID_AA64ISAR1_EL1)
3955 .allPrivileges().exceptUserMode().writes(0);
3956 InitReg(MISCREG_ID_AA64MMFR0_EL1)
3957 .allPrivileges().exceptUserMode().writes(0);
3958 InitReg(MISCREG_ID_AA64MMFR1_EL1)
3959 .allPrivileges().exceptUserMode().writes(0);
3960 InitReg(MISCREG_ID_AA64MMFR2_EL1)
3961 .allPrivileges().exceptUserMode().writes(0);
3962 InitReg(MISCREG_CCSIDR_EL1)
3963 .allPrivileges().exceptUserMode().writes(0);
3964 InitReg(MISCREG_CLIDR_EL1)
3965 .allPrivileges().exceptUserMode().writes(0);
3966 InitReg(MISCREG_AIDR_EL1)
3967 .allPrivileges().exceptUserMode().writes(0);
3968 InitReg(MISCREG_CSSELR_EL1)
3969 .allPrivileges().exceptUserMode()
3970 .mapsTo(MISCREG_CSSELR_NS);
3971 InitReg(MISCREG_CTR_EL0)
3972 .reads(1);
3973 InitReg(MISCREG_DCZID_EL0)
3974 .reads(1);
3975 InitReg(MISCREG_VPIDR_EL2)
3976 .hyp().mon()
3977 .mapsTo(MISCREG_VPIDR);
3978 InitReg(MISCREG_VMPIDR_EL2)
3979 .hyp().mon()
3980 .mapsTo(MISCREG_VMPIDR);
3981 InitReg(MISCREG_SCTLR_EL1)
3982 .allPrivileges().exceptUserMode()
3983 .res0( 0x20440 | (EnDB ? 0 : 0x2000)
3984 | (IESB ? 0 : 0x200000)
3985 | (EnDA ? 0 : 0x8000000)
3986 | (EnIB ? 0 : 0x40000000)
3987 | (EnIA ? 0 : 0x80000000))
3988 .res1(0x500800 | (SPAN ? 0 : 0x800000)
3989 | (nTLSMD ? 0 : 0x8000000)
3990 | (LSMAOE ? 0 : 0x10000000))
3991 .mapsTo(MISCREG_SCTLR_NS);
3992 InitReg(MISCREG_ACTLR_EL1)
3993 .allPrivileges().exceptUserMode()
3994 .mapsTo(MISCREG_ACTLR_NS);
3995 InitReg(MISCREG_CPACR_EL1)
3996 .allPrivileges().exceptUserMode()
3997 .mapsTo(MISCREG_CPACR);
3998 InitReg(MISCREG_SCTLR_EL2)
3999 .hyp().mon()
4000 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
4001 | (IESB ? 0 : 0x200000)
4002 | (EnDA ? 0 : 0x8000000)
4003 | (EnIB ? 0 : 0x40000000)
4004 | (EnIA ? 0 : 0x80000000))
4005 .res1(0x30c50830)
4006 .mapsTo(MISCREG_HSCTLR);
4007 InitReg(MISCREG_ACTLR_EL2)
4008 .hyp().mon()
4009 .mapsTo(MISCREG_HACTLR);
4010 InitReg(MISCREG_HCR_EL2)
4011 .hyp().mon()
4012 .mapsTo(MISCREG_HCR, MISCREG_HCR2);
4013 InitReg(MISCREG_MDCR_EL2)
4014 .hyp().mon()
4015 .mapsTo(MISCREG_HDCR);
4016 InitReg(MISCREG_CPTR_EL2)
4017 .hyp().mon()
4018 .mapsTo(MISCREG_HCPTR);
4019 InitReg(MISCREG_HSTR_EL2)
4020 .hyp().mon()
4021 .mapsTo(MISCREG_HSTR);
4022 InitReg(MISCREG_HACR_EL2)
4023 .hyp().mon()
4024 .mapsTo(MISCREG_HACR);
4025 InitReg(MISCREG_SCTLR_EL3)
4026 .mon()
4027 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
4028 | (IESB ? 0 : 0x200000)
4029 | (EnDA ? 0 : 0x8000000)
4030 | (EnIB ? 0 : 0x40000000)
4031 | (EnIA ? 0 : 0x80000000))
4032 .res1(0x30c50830);
4033 InitReg(MISCREG_ACTLR_EL3)
4034 .mon();
4035 InitReg(MISCREG_SCR_EL3)
4036 .mon()
4037 .mapsTo(MISCREG_SCR); // NAM D7-2005
4038 InitReg(MISCREG_SDER32_EL3)
4039 .mon()
4040 .mapsTo(MISCREG_SDER);
4041 InitReg(MISCREG_CPTR_EL3)
4042 .mon();
4043 InitReg(MISCREG_MDCR_EL3)
4044 .mon();
4045 InitReg(MISCREG_TTBR0_EL1)
4046 .allPrivileges().exceptUserMode()
4047 .mapsTo(MISCREG_TTBR0_NS);
4048 InitReg(MISCREG_TTBR1_EL1)
4049 .allPrivileges().exceptUserMode()
4050 .mapsTo(MISCREG_TTBR1_NS);
4051 InitReg(MISCREG_TCR_EL1)
4052 .allPrivileges().exceptUserMode()
4053 .mapsTo(MISCREG_TTBCR_NS);
4054 InitReg(MISCREG_TTBR0_EL2)
4055 .hyp().mon()
4056 .mapsTo(MISCREG_HTTBR);
4057 InitReg(MISCREG_TTBR1_EL2)
4058 .hyp().mon();
4059 InitReg(MISCREG_TCR_EL2)
4060 .hyp().mon()
4061 .mapsTo(MISCREG_HTCR);
4062 InitReg(MISCREG_VTTBR_EL2)
4063 .hyp().mon()
4064 .mapsTo(MISCREG_VTTBR);
4065 InitReg(MISCREG_VTCR_EL2)
4066 .hyp().mon()
4067 .mapsTo(MISCREG_VTCR);
4068 InitReg(MISCREG_TTBR0_EL3)
4069 .mon();
4070 InitReg(MISCREG_TCR_EL3)
4071 .mon();
4072 InitReg(MISCREG_DACR32_EL2)
4073 .hyp().mon()
4074 .mapsTo(MISCREG_DACR_NS);
4075 InitReg(MISCREG_SPSR_EL1)
4076 .allPrivileges().exceptUserMode()
4077 .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
4078 InitReg(MISCREG_ELR_EL1)
4079 .allPrivileges().exceptUserMode();
4080 InitReg(MISCREG_SP_EL0)
4081 .allPrivileges().exceptUserMode();
4082 InitReg(MISCREG_SPSEL)
4083 .allPrivileges().exceptUserMode();
4084 InitReg(MISCREG_CURRENTEL)
4085 .allPrivileges().exceptUserMode().writes(0);
4086 InitReg(MISCREG_PAN)
4087 .allPrivileges().exceptUserMode()
4088 .implemented(havePAN);
4089 InitReg(MISCREG_NZCV)
4090 .allPrivileges();
4091 InitReg(MISCREG_DAIF)
4092 .allPrivileges();
4093 InitReg(MISCREG_FPCR)
4094 .allPrivileges();
4095 InitReg(MISCREG_FPSR)
4096 .allPrivileges();
4097 InitReg(MISCREG_DSPSR_EL0)
4098 .allPrivileges();
4099 InitReg(MISCREG_DLR_EL0)
4100 .allPrivileges();
4101 InitReg(MISCREG_SPSR_EL2)
4102 .hyp().mon()
4103 .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2
4104 InitReg(MISCREG_ELR_EL2)
4105 .hyp().mon();
4106 InitReg(MISCREG_SP_EL1)
4107 .hyp().mon();
4108 InitReg(MISCREG_SPSR_IRQ_AA64)
4109 .hyp().mon();
4110 InitReg(MISCREG_SPSR_ABT_AA64)
4111 .hyp().mon();
4112 InitReg(MISCREG_SPSR_UND_AA64)
4113 .hyp().mon();
4114 InitReg(MISCREG_SPSR_FIQ_AA64)
4115 .hyp().mon();
4116 InitReg(MISCREG_SPSR_EL3)
4117 .mon()
4118 .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3
4119 InitReg(MISCREG_ELR_EL3)
4120 .mon();
4121 InitReg(MISCREG_SP_EL2)
4122 .mon();
4123 InitReg(MISCREG_AFSR0_EL1)
4124 .allPrivileges().exceptUserMode()
4125 .mapsTo(MISCREG_ADFSR_NS);
4126 InitReg(MISCREG_AFSR1_EL1)
4127 .allPrivileges().exceptUserMode()
4128 .mapsTo(MISCREG_AIFSR_NS);
4129 InitReg(MISCREG_ESR_EL1)
4130 .allPrivileges().exceptUserMode();
4131 InitReg(MISCREG_IFSR32_EL2)
4132 .hyp().mon()
4133 .mapsTo(MISCREG_IFSR_NS);
4134 InitReg(MISCREG_AFSR0_EL2)
4135 .hyp().mon()
4136 .mapsTo(MISCREG_HADFSR);
4137 InitReg(MISCREG_AFSR1_EL2)
4138 .hyp().mon()
4139 .mapsTo(MISCREG_HAIFSR);
4140 InitReg(MISCREG_ESR_EL2)
4141 .hyp().mon()
4142 .mapsTo(MISCREG_HSR);
4143 InitReg(MISCREG_FPEXC32_EL2)
4144 .hyp().mon().mapsTo(MISCREG_FPEXC);
4145 InitReg(MISCREG_AFSR0_EL3)
4146 .mon();
4147 InitReg(MISCREG_AFSR1_EL3)
4148 .mon();
4149 InitReg(MISCREG_ESR_EL3)
4150 .mon();
4151 InitReg(MISCREG_FAR_EL1)
4152 .allPrivileges().exceptUserMode()
4153 .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
4154 InitReg(MISCREG_FAR_EL2)
4155 .hyp().mon()
4156 .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR);
4157 InitReg(MISCREG_HPFAR_EL2)
4158 .hyp().mon()
4159 .mapsTo(MISCREG_HPFAR);
4160 InitReg(MISCREG_FAR_EL3)
4161 .mon();
4162 InitReg(MISCREG_IC_IALLUIS)
4163 .warnNotFail()
4164 .writes(1).exceptUserMode();
4165 InitReg(MISCREG_PAR_EL1)
4166 .allPrivileges().exceptUserMode()
4167 .mapsTo(MISCREG_PAR_NS);
4168 InitReg(MISCREG_IC_IALLU)
4169 .warnNotFail()
4170 .writes(1).exceptUserMode();
4171 InitReg(MISCREG_DC_IVAC_Xt)
4172 .warnNotFail()
4173 .writes(1).exceptUserMode();
4174 InitReg(MISCREG_DC_ISW_Xt)
4175 .warnNotFail()
4176 .writes(1).exceptUserMode();
4177 InitReg(MISCREG_AT_S1E1R_Xt)
4178 .writes(1).exceptUserMode();
4179 InitReg(MISCREG_AT_S1E1W_Xt)
4180 .writes(1).exceptUserMode();
4181 InitReg(MISCREG_AT_S1E0R_Xt)
4182 .writes(1).exceptUserMode();
4183 InitReg(MISCREG_AT_S1E0W_Xt)
4184 .writes(1).exceptUserMode();
4185 InitReg(MISCREG_DC_CSW_Xt)
4186 .warnNotFail()
4187 .writes(1).exceptUserMode();
4188 InitReg(MISCREG_DC_CISW_Xt)
4189 .warnNotFail()
4190 .writes(1).exceptUserMode();
4191 InitReg(MISCREG_DC_ZVA_Xt)
4192 .warnNotFail()
4193 .writes(1).userSecureWrite(0);
4194 InitReg(MISCREG_IC_IVAU_Xt)
4195 .writes(1);
4196 InitReg(MISCREG_DC_CVAC_Xt)
4197 .warnNotFail()
4198 .writes(1);
4199 InitReg(MISCREG_DC_CVAU_Xt)
4200 .warnNotFail()
4201 .writes(1);
4202 InitReg(MISCREG_DC_CIVAC_Xt)
4203 .warnNotFail()
4204 .writes(1);
4205 InitReg(MISCREG_AT_S1E2R_Xt)
4206 .monNonSecureWrite().hypWrite();
4207 InitReg(MISCREG_AT_S1E2W_Xt)
4208 .monNonSecureWrite().hypWrite();
4209 InitReg(MISCREG_AT_S12E1R_Xt)
4210 .hypWrite().monSecureWrite().monNonSecureWrite();
4211 InitReg(MISCREG_AT_S12E1W_Xt)
4212 .hypWrite().monSecureWrite().monNonSecureWrite();
4213 InitReg(MISCREG_AT_S12E0R_Xt)
4214 .hypWrite().monSecureWrite().monNonSecureWrite();
4215 InitReg(MISCREG_AT_S12E0W_Xt)
4216 .hypWrite().monSecureWrite().monNonSecureWrite();
4217 InitReg(MISCREG_AT_S1E3R_Xt)
4218 .monSecureWrite().monNonSecureWrite();
4219 InitReg(MISCREG_AT_S1E3W_Xt)
4220 .monSecureWrite().monNonSecureWrite();
4221 InitReg(MISCREG_TLBI_VMALLE1IS)
4222 .writes(1).exceptUserMode();
4223 InitReg(MISCREG_TLBI_VAE1IS_Xt)
4224 .writes(1).exceptUserMode();
4225 InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
4226 .writes(1).exceptUserMode();
4227 InitReg(MISCREG_TLBI_VAAE1IS_Xt)
4228 .writes(1).exceptUserMode();
4229 InitReg(MISCREG_TLBI_VALE1IS_Xt)
4230 .writes(1).exceptUserMode();
4231 InitReg(MISCREG_TLBI_VAALE1IS_Xt)
4232 .writes(1).exceptUserMode();
4233 InitReg(MISCREG_TLBI_VMALLE1)
4234 .writes(1).exceptUserMode();
4235 InitReg(MISCREG_TLBI_VAE1_Xt)
4236 .writes(1).exceptUserMode();
4237 InitReg(MISCREG_TLBI_ASIDE1_Xt)
4238 .writes(1).exceptUserMode();
4239 InitReg(MISCREG_TLBI_VAAE1_Xt)
4240 .writes(1).exceptUserMode();
4241 InitReg(MISCREG_TLBI_VALE1_Xt)
4242 .writes(1).exceptUserMode();
4243 InitReg(MISCREG_TLBI_VAALE1_Xt)
4244 .writes(1).exceptUserMode();
4245 InitReg(MISCREG_TLBI_IPAS2E1IS_Xt)
4246 .hypWrite().monSecureWrite().monNonSecureWrite();
4247 InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt)
4248 .hypWrite().monSecureWrite().monNonSecureWrite();
4249 InitReg(MISCREG_TLBI_ALLE2IS)
4250 .monNonSecureWrite().hypWrite();
4251 InitReg(MISCREG_TLBI_VAE2IS_Xt)
4252 .monNonSecureWrite().hypWrite();
4253 InitReg(MISCREG_TLBI_ALLE1IS)
4254 .hypWrite().monSecureWrite().monNonSecureWrite();
4255 InitReg(MISCREG_TLBI_VALE2IS_Xt)
4256 .monNonSecureWrite().hypWrite();
4257 InitReg(MISCREG_TLBI_VMALLS12E1IS)
4258 .hypWrite().monSecureWrite().monNonSecureWrite();
4259 InitReg(MISCREG_TLBI_IPAS2E1_Xt)
4260 .hypWrite().monSecureWrite().monNonSecureWrite();
4261 InitReg(MISCREG_TLBI_IPAS2LE1_Xt)
4262 .hypWrite().monSecureWrite().monNonSecureWrite();
4263 InitReg(MISCREG_TLBI_ALLE2)
4264 .monNonSecureWrite().hypWrite();
4265 InitReg(MISCREG_TLBI_VAE2_Xt)
4266 .monNonSecureWrite().hypWrite();
4267 InitReg(MISCREG_TLBI_ALLE1)
4268 .hypWrite().monSecureWrite().monNonSecureWrite();
4269 InitReg(MISCREG_TLBI_VALE2_Xt)
4270 .monNonSecureWrite().hypWrite();
4271 InitReg(MISCREG_TLBI_VMALLS12E1)
4272 .hypWrite().monSecureWrite().monNonSecureWrite();
4273 InitReg(MISCREG_TLBI_ALLE3IS)
4274 .monSecureWrite().monNonSecureWrite();
4275 InitReg(MISCREG_TLBI_VAE3IS_Xt)
4276 .monSecureWrite().monNonSecureWrite();
4277 InitReg(MISCREG_TLBI_VALE3IS_Xt)
4278 .monSecureWrite().monNonSecureWrite();
4279 InitReg(MISCREG_TLBI_ALLE3)
4280 .monSecureWrite().monNonSecureWrite();
4281 InitReg(MISCREG_TLBI_VAE3_Xt)
4282 .monSecureWrite().monNonSecureWrite();
4283 InitReg(MISCREG_TLBI_VALE3_Xt)
4284 .monSecureWrite().monNonSecureWrite();
4285 InitReg(MISCREG_PMINTENSET_EL1)
4286 .allPrivileges().exceptUserMode()
4287 .mapsTo(MISCREG_PMINTENSET);
4288 InitReg(MISCREG_PMINTENCLR_EL1)
4289 .allPrivileges().exceptUserMode()
4290 .mapsTo(MISCREG_PMINTENCLR);
4291 InitReg(MISCREG_PMCR_EL0)
4292 .allPrivileges()
4293 .mapsTo(MISCREG_PMCR);
4294 InitReg(MISCREG_PMCNTENSET_EL0)
4295 .allPrivileges()
4296 .mapsTo(MISCREG_PMCNTENSET);
4297 InitReg(MISCREG_PMCNTENCLR_EL0)
4298 .allPrivileges()
4299 .mapsTo(MISCREG_PMCNTENCLR);
4300 InitReg(MISCREG_PMOVSCLR_EL0)
4301 .allPrivileges();
4302 // .mapsTo(MISCREG_PMOVSCLR);
4303 InitReg(MISCREG_PMSWINC_EL0)
4304 .writes(1).user()
4305 .mapsTo(MISCREG_PMSWINC);
4306 InitReg(MISCREG_PMSELR_EL0)
4307 .allPrivileges()
4308 .mapsTo(MISCREG_PMSELR);
4309 InitReg(MISCREG_PMCEID0_EL0)
4310 .reads(1).user()
4311 .mapsTo(MISCREG_PMCEID0);
4312 InitReg(MISCREG_PMCEID1_EL0)
4313 .reads(1).user()
4314 .mapsTo(MISCREG_PMCEID1);
4315 InitReg(MISCREG_PMCCNTR_EL0)
4316 .allPrivileges()
4317 .mapsTo(MISCREG_PMCCNTR);
4318 InitReg(MISCREG_PMXEVTYPER_EL0)
4319 .allPrivileges()
4320 .mapsTo(MISCREG_PMXEVTYPER);
4321 InitReg(MISCREG_PMCCFILTR_EL0)
4322 .allPrivileges();
4323 InitReg(MISCREG_PMXEVCNTR_EL0)
4324 .allPrivileges()
4325 .mapsTo(MISCREG_PMXEVCNTR);
4326 InitReg(MISCREG_PMUSERENR_EL0)
4327 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
4328 .mapsTo(MISCREG_PMUSERENR);
4329 InitReg(MISCREG_PMOVSSET_EL0)
4330 .allPrivileges()
4331 .mapsTo(MISCREG_PMOVSSET);
4332 InitReg(MISCREG_MAIR_EL1)
4333 .allPrivileges().exceptUserMode()
4334 .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
4335 InitReg(MISCREG_AMAIR_EL1)
4336 .allPrivileges().exceptUserMode()
4337 .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
4338 InitReg(MISCREG_MAIR_EL2)
4339 .hyp().mon()
4340 .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1);
4341 InitReg(MISCREG_AMAIR_EL2)
4342 .hyp().mon()
4343 .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1);
4344 InitReg(MISCREG_MAIR_EL3)
4345 .mon();
4346 InitReg(MISCREG_AMAIR_EL3)
4347 .mon();
4348 InitReg(MISCREG_L2CTLR_EL1)
4349 .allPrivileges().exceptUserMode();
4350 InitReg(MISCREG_L2ECTLR_EL1)
4351 .allPrivileges().exceptUserMode();
4352 InitReg(MISCREG_VBAR_EL1)
4353 .allPrivileges().exceptUserMode()
4354 .mapsTo(MISCREG_VBAR_NS);
4355 InitReg(MISCREG_RVBAR_EL1)
4356 .allPrivileges().exceptUserMode().writes(0);
4357 InitReg(MISCREG_ISR_EL1)
4358 .allPrivileges().exceptUserMode().writes(0);
4359 InitReg(MISCREG_VBAR_EL2)
4360 .hyp().mon()
4361 .res0(0x7ff)
4362 .mapsTo(MISCREG_HVBAR);
4363 InitReg(MISCREG_RVBAR_EL2)
4364 .mon().hyp().writes(0);
4365 InitReg(MISCREG_VBAR_EL3)
4366 .mon();
4367 InitReg(MISCREG_RVBAR_EL3)
4368 .mon().writes(0);
4369 InitReg(MISCREG_RMR_EL3)
4370 .mon();
4371 InitReg(MISCREG_CONTEXTIDR_EL1)
4372 .allPrivileges().exceptUserMode()
4373 .mapsTo(MISCREG_CONTEXTIDR_NS);
4374 InitReg(MISCREG_TPIDR_EL1)
4375 .allPrivileges().exceptUserMode()
4376 .mapsTo(MISCREG_TPIDRPRW_NS);
4377 InitReg(MISCREG_TPIDR_EL0)
4378 .allPrivileges()
4379 .mapsTo(MISCREG_TPIDRURW_NS);
4380 InitReg(MISCREG_TPIDRRO_EL0)
4381 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
4382 .mapsTo(MISCREG_TPIDRURO_NS);
4383 InitReg(MISCREG_TPIDR_EL2)
4384 .hyp().mon()
4385 .mapsTo(MISCREG_HTPIDR);
4386 InitReg(MISCREG_TPIDR_EL3)
4387 .mon();
4388 InitReg(MISCREG_CNTKCTL_EL1)
4389 .allPrivileges().exceptUserMode()
4390 .mapsTo(MISCREG_CNTKCTL);
4391 InitReg(MISCREG_CNTFRQ_EL0)
4392 .reads(1).mon()
4393 .mapsTo(MISCREG_CNTFRQ);
4394 InitReg(MISCREG_CNTPCT_EL0)
4395 .reads(1)
4396 .mapsTo(MISCREG_CNTPCT); /* 64b */
4397 InitReg(MISCREG_CNTVCT_EL0)
4398 .unverifiable()
4399 .reads(1)
4400 .mapsTo(MISCREG_CNTVCT); /* 64b */
4401 InitReg(MISCREG_CNTP_TVAL_EL0)
4402 .allPrivileges()
4403 .mapsTo(MISCREG_CNTP_TVAL_NS);
4404 InitReg(MISCREG_CNTP_CTL_EL0)
4405 .allPrivileges()
4406 .mapsTo(MISCREG_CNTP_CTL_NS);
4407 InitReg(MISCREG_CNTP_CVAL_EL0)
4408 .allPrivileges()
4409 .mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b */
4410 InitReg(MISCREG_CNTV_TVAL_EL0)
4411 .allPrivileges()
4412 .mapsTo(MISCREG_CNTV_TVAL);
4413 InitReg(MISCREG_CNTV_CTL_EL0)
4414 .allPrivileges()
4415 .mapsTo(MISCREG_CNTV_CTL);
4416 InitReg(MISCREG_CNTV_CVAL_EL0)
4417 .allPrivileges()
4418 .mapsTo(MISCREG_CNTV_CVAL); /* 64b */
4419 InitReg(MISCREG_PMEVCNTR0_EL0)
4420 .allPrivileges();
4421 // .mapsTo(MISCREG_PMEVCNTR0);
4422 InitReg(MISCREG_PMEVCNTR1_EL0)
4423 .allPrivileges();
4424 // .mapsTo(MISCREG_PMEVCNTR1);
4425 InitReg(MISCREG_PMEVCNTR2_EL0)
4426 .allPrivileges();
4427 // .mapsTo(MISCREG_PMEVCNTR2);
4428 InitReg(MISCREG_PMEVCNTR3_EL0)
4429 .allPrivileges();
4430 // .mapsTo(MISCREG_PMEVCNTR3);
4431 InitReg(MISCREG_PMEVCNTR4_EL0)
4432 .allPrivileges();
4433 // .mapsTo(MISCREG_PMEVCNTR4);
4434 InitReg(MISCREG_PMEVCNTR5_EL0)
4435 .allPrivileges();
4436 // .mapsTo(MISCREG_PMEVCNTR5);
4437 InitReg(MISCREG_PMEVTYPER0_EL0)
4438 .allPrivileges();
4439 // .mapsTo(MISCREG_PMEVTYPER0);
4440 InitReg(MISCREG_PMEVTYPER1_EL0)
4441 .allPrivileges();
4442 // .mapsTo(MISCREG_PMEVTYPER1);
4443 InitReg(MISCREG_PMEVTYPER2_EL0)
4444 .allPrivileges();
4445 // .mapsTo(MISCREG_PMEVTYPER2);
4446 InitReg(MISCREG_PMEVTYPER3_EL0)
4447 .allPrivileges();
4448 // .mapsTo(MISCREG_PMEVTYPER3);
4449 InitReg(MISCREG_PMEVTYPER4_EL0)
4450 .allPrivileges();
4451 // .mapsTo(MISCREG_PMEVTYPER4);
4452 InitReg(MISCREG_PMEVTYPER5_EL0)
4453 .allPrivileges();
4454 // .mapsTo(MISCREG_PMEVTYPER5);
4455 InitReg(MISCREG_CNTVOFF_EL2)
4456 .hyp().mon()
4457 .mapsTo(MISCREG_CNTVOFF); /* 64b */
4458 InitReg(MISCREG_CNTHCTL_EL2)
4459 .mon().hyp()
4460 .mapsTo(MISCREG_CNTHCTL);
4461 InitReg(MISCREG_CNTHP_TVAL_EL2)
4462 .mon().hyp()
4463 .mapsTo(MISCREG_CNTHP_TVAL);
4464 InitReg(MISCREG_CNTHP_CTL_EL2)
4465 .mon().hyp()
4466 .mapsTo(MISCREG_CNTHP_CTL);
4467 InitReg(MISCREG_CNTHP_CVAL_EL2)
4468 .mon().hyp()
4469 .mapsTo(MISCREG_CNTHP_CVAL); /* 64b */
4470 InitReg(MISCREG_CNTPS_TVAL_EL1)
4471 .mon().privSecure();
4472 InitReg(MISCREG_CNTPS_CTL_EL1)
4473 .mon().privSecure();
4474 InitReg(MISCREG_CNTPS_CVAL_EL1)
4475 .mon().privSecure();
4476 InitReg(MISCREG_IL1DATA0_EL1)
4477 .allPrivileges().exceptUserMode();
4478 InitReg(MISCREG_IL1DATA1_EL1)
4479 .allPrivileges().exceptUserMode();
4480 InitReg(MISCREG_IL1DATA2_EL1)
4481 .allPrivileges().exceptUserMode();
4482 InitReg(MISCREG_IL1DATA3_EL1)
4483 .allPrivileges().exceptUserMode();
4484 InitReg(MISCREG_DL1DATA0_EL1)
4485 .allPrivileges().exceptUserMode();
4486 InitReg(MISCREG_DL1DATA1_EL1)
4487 .allPrivileges().exceptUserMode();
4488 InitReg(MISCREG_DL1DATA2_EL1)
4489 .allPrivileges().exceptUserMode();
4490 InitReg(MISCREG_DL1DATA3_EL1)
4491 .allPrivileges().exceptUserMode();
4492 InitReg(MISCREG_DL1DATA4_EL1)
4493 .allPrivileges().exceptUserMode();
4494 InitReg(MISCREG_L2ACTLR_EL1)
4495 .allPrivileges().exceptUserMode();
4496 InitReg(MISCREG_CPUACTLR_EL1)
4497 .allPrivileges().exceptUserMode();
4498 InitReg(MISCREG_CPUECTLR_EL1)
4499 .allPrivileges().exceptUserMode();
4500 InitReg(MISCREG_CPUMERRSR_EL1)
4501 .allPrivileges().exceptUserMode();
4502 InitReg(MISCREG_L2MERRSR_EL1)
4503 .unimplemented()
4504 .warnNotFail()
4505 .allPrivileges().exceptUserMode();
4506 InitReg(MISCREG_CBAR_EL1)
4507 .allPrivileges().exceptUserMode().writes(0);
4508 InitReg(MISCREG_CONTEXTIDR_EL2)
4509 .mon().hyp();
4510
4511 // GICv3 AArch64
4512 InitReg(MISCREG_ICC_PMR_EL1)
4513 .res0(0xffffff00) // [31:8]
4514 .allPrivileges().exceptUserMode()
4515 .mapsTo(MISCREG_ICC_PMR);
4516 InitReg(MISCREG_ICC_IAR0_EL1)
4517 .allPrivileges().exceptUserMode().writes(0)
4518 .mapsTo(MISCREG_ICC_IAR0);
4519 InitReg(MISCREG_ICC_EOIR0_EL1)
4520 .allPrivileges().exceptUserMode().reads(0)
4521 .mapsTo(MISCREG_ICC_EOIR0);
4522 InitReg(MISCREG_ICC_HPPIR0_EL1)
4523 .allPrivileges().exceptUserMode().writes(0)
4524 .mapsTo(MISCREG_ICC_HPPIR0);
4525 InitReg(MISCREG_ICC_BPR0_EL1)
4526 .res0(0xfffffff8) // [31:3]
4527 .allPrivileges().exceptUserMode()
4528 .mapsTo(MISCREG_ICC_BPR0);
4529 InitReg(MISCREG_ICC_AP0R0_EL1)
4530 .allPrivileges().exceptUserMode()
4531 .mapsTo(MISCREG_ICC_AP0R0);
4532 InitReg(MISCREG_ICC_AP0R1_EL1)
4533 .allPrivileges().exceptUserMode()
4534 .mapsTo(MISCREG_ICC_AP0R1);
4535 InitReg(MISCREG_ICC_AP0R2_EL1)
4536 .allPrivileges().exceptUserMode()
4537 .mapsTo(MISCREG_ICC_AP0R2);
4538 InitReg(MISCREG_ICC_AP0R3_EL1)
4539 .allPrivileges().exceptUserMode()
4540 .mapsTo(MISCREG_ICC_AP0R3);
4541 InitReg(MISCREG_ICC_AP1R0_EL1)
4542 .banked64()
4543 .mapsTo(MISCREG_ICC_AP1R0);
4544 InitReg(MISCREG_ICC_AP1R0_EL1_NS)
4545 .bankedChild()
4546 .allPrivileges().exceptUserMode()
4547 .mapsTo(MISCREG_ICC_AP1R0_NS);
4548 InitReg(MISCREG_ICC_AP1R0_EL1_S)
4549 .bankedChild()
4550 .allPrivileges().exceptUserMode()
4551 .mapsTo(MISCREG_ICC_AP1R0_S);
4552 InitReg(MISCREG_ICC_AP1R1_EL1)
4553 .banked64()
4554 .mapsTo(MISCREG_ICC_AP1R1);
4555 InitReg(MISCREG_ICC_AP1R1_EL1_NS)
4556 .bankedChild()
4557 .allPrivileges().exceptUserMode()
4558 .mapsTo(MISCREG_ICC_AP1R1_NS);
4559 InitReg(MISCREG_ICC_AP1R1_EL1_S)
4560 .bankedChild()
4561 .allPrivileges().exceptUserMode()
4562 .mapsTo(MISCREG_ICC_AP1R1_S);
4563 InitReg(MISCREG_ICC_AP1R2_EL1)
4564 .banked64()
4565 .mapsTo(MISCREG_ICC_AP1R2);
4566 InitReg(MISCREG_ICC_AP1R2_EL1_NS)
4567 .bankedChild()
4568 .allPrivileges().exceptUserMode()
4569 .mapsTo(MISCREG_ICC_AP1R2_NS);
4570 InitReg(MISCREG_ICC_AP1R2_EL1_S)
4571 .bankedChild()
4572 .allPrivileges().exceptUserMode()
4573 .mapsTo(MISCREG_ICC_AP1R2_S);
4574 InitReg(MISCREG_ICC_AP1R3_EL1)
4575 .banked64()
4576 .mapsTo(MISCREG_ICC_AP1R3);
4577 InitReg(MISCREG_ICC_AP1R3_EL1_NS)
4578 .bankedChild()
4579 .allPrivileges().exceptUserMode()
4580 .mapsTo(MISCREG_ICC_AP1R3_NS);
4581 InitReg(MISCREG_ICC_AP1R3_EL1_S)
4582 .bankedChild()
4583 .allPrivileges().exceptUserMode()
4584 .mapsTo(MISCREG_ICC_AP1R3_S);
4585 InitReg(MISCREG_ICC_DIR_EL1)
4586 .res0(0xFF000000) // [31:24]
4587 .allPrivileges().exceptUserMode().reads(0)
4588 .mapsTo(MISCREG_ICC_DIR);
4589 InitReg(MISCREG_ICC_RPR_EL1)
4590 .allPrivileges().exceptUserMode().writes(0)
4591 .mapsTo(MISCREG_ICC_RPR);
4592 InitReg(MISCREG_ICC_SGI1R_EL1)
4593 .allPrivileges().exceptUserMode().reads(0)
4594 .mapsTo(MISCREG_ICC_SGI1R);
4595 InitReg(MISCREG_ICC_ASGI1R_EL1)
4596 .allPrivileges().exceptUserMode().reads(0)
4597 .mapsTo(MISCREG_ICC_ASGI1R);
4598 InitReg(MISCREG_ICC_SGI0R_EL1)
4599 .allPrivileges().exceptUserMode().reads(0)
4600 .mapsTo(MISCREG_ICC_SGI0R);
4601 InitReg(MISCREG_ICC_IAR1_EL1)
4602 .allPrivileges().exceptUserMode().writes(0)
4603 .mapsTo(MISCREG_ICC_IAR1);
4604 InitReg(MISCREG_ICC_EOIR1_EL1)
4605 .res0(0xFF000000) // [31:24]
4606 .allPrivileges().exceptUserMode().reads(0)
4607 .mapsTo(MISCREG_ICC_EOIR1);
4608 InitReg(MISCREG_ICC_HPPIR1_EL1)
4609 .allPrivileges().exceptUserMode().writes(0)
4610 .mapsTo(MISCREG_ICC_HPPIR1);
4611 InitReg(MISCREG_ICC_BPR1_EL1)
4612 .banked64()
4613 .mapsTo(MISCREG_ICC_BPR1);
4614 InitReg(MISCREG_ICC_BPR1_EL1_NS)
4615 .bankedChild()
4616 .res0(0xfffffff8) // [31:3]
4617 .allPrivileges().exceptUserMode()
4618 .mapsTo(MISCREG_ICC_BPR1_NS);
4619 InitReg(MISCREG_ICC_BPR1_EL1_S)
4620 .bankedChild()
4621 .res0(0xfffffff8) // [31:3]
4622 .secure().exceptUserMode()
4623 .mapsTo(MISCREG_ICC_BPR1_S);
4624 InitReg(MISCREG_ICC_CTLR_EL1)
4625 .banked64()
4626 .mapsTo(MISCREG_ICC_CTLR);
4627 InitReg(MISCREG_ICC_CTLR_EL1_NS)
4628 .bankedChild()
4629 .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
4630 .allPrivileges().exceptUserMode()
4631 .mapsTo(MISCREG_ICC_CTLR_NS);
4632 InitReg(MISCREG_ICC_CTLR_EL1_S)
4633 .bankedChild()
4634 .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
4635 .secure().exceptUserMode()
4636 .mapsTo(MISCREG_ICC_CTLR_S);
4637 InitReg(MISCREG_ICC_SRE_EL1)
4638 .banked()
4639 .mapsTo(MISCREG_ICC_SRE);
4640 InitReg(MISCREG_ICC_SRE_EL1_NS)
4641 .bankedChild()
4642 .res0(0xFFFFFFF8) // [31:3]
4643 .allPrivileges().exceptUserMode()
4644 .mapsTo(MISCREG_ICC_SRE_NS);
4645 InitReg(MISCREG_ICC_SRE_EL1_S)
4646 .bankedChild()
4647 .res0(0xFFFFFFF8) // [31:3]
4648 .secure().exceptUserMode()
4649 .mapsTo(MISCREG_ICC_SRE_S);
4650 InitReg(MISCREG_ICC_IGRPEN0_EL1)
4651 .res0(0xFFFFFFFE) // [31:1]
4652 .allPrivileges().exceptUserMode()
4653 .mapsTo(MISCREG_ICC_IGRPEN0);
4654 InitReg(MISCREG_ICC_IGRPEN1_EL1)
4655 .banked64()
4656 .mapsTo(MISCREG_ICC_IGRPEN1);
4657 InitReg(MISCREG_ICC_IGRPEN1_EL1_NS)
4658 .bankedChild()
4659 .res0(0xFFFFFFFE) // [31:1]
4660 .allPrivileges().exceptUserMode()
4661 .mapsTo(MISCREG_ICC_IGRPEN1_NS);
4662 InitReg(MISCREG_ICC_IGRPEN1_EL1_S)
4663 .bankedChild()
4664 .res0(0xFFFFFFFE) // [31:1]
4665 .secure().exceptUserMode()
4666 .mapsTo(MISCREG_ICC_IGRPEN1_S);
4667 InitReg(MISCREG_ICC_SRE_EL2)
4668 .hyp().mon()
4669 .mapsTo(MISCREG_ICC_HSRE);
4670 InitReg(MISCREG_ICC_CTLR_EL3)
4671 .allPrivileges().exceptUserMode()
4672 .mapsTo(MISCREG_ICC_MCTLR);
4673 InitReg(MISCREG_ICC_SRE_EL3)
4674 .allPrivileges().exceptUserMode()
4675 .mapsTo(MISCREG_ICC_MSRE);
4676 InitReg(MISCREG_ICC_IGRPEN1_EL3)
4677 .allPrivileges().exceptUserMode()
4678 .mapsTo(MISCREG_ICC_MGRPEN1);
4679
4680 InitReg(MISCREG_ICH_AP0R0_EL2)
4681 .hyp().mon()
4682 .mapsTo(MISCREG_ICH_AP0R0);
4683 InitReg(MISCREG_ICH_AP0R1_EL2)
4684 .hyp().mon()
4685 .unimplemented()
4686 .mapsTo(MISCREG_ICH_AP0R1);
4687 InitReg(MISCREG_ICH_AP0R2_EL2)
4688 .hyp().mon()
4689 .unimplemented()
4690 .mapsTo(MISCREG_ICH_AP0R2);
4691 InitReg(MISCREG_ICH_AP0R3_EL2)
4692 .hyp().mon()
4693 .unimplemented()
4694 .mapsTo(MISCREG_ICH_AP0R3);
4695 InitReg(MISCREG_ICH_AP1R0_EL2)
4696 .hyp().mon()
4697 .mapsTo(MISCREG_ICH_AP1R0);
4698 InitReg(MISCREG_ICH_AP1R1_EL2)
4699 .hyp().mon()
4700 .unimplemented()
4701 .mapsTo(MISCREG_ICH_AP1R1);
4702 InitReg(MISCREG_ICH_AP1R2_EL2)
4703 .hyp().mon()
4704 .unimplemented()
4705 .mapsTo(MISCREG_ICH_AP1R2);
4706 InitReg(MISCREG_ICH_AP1R3_EL2)
4707 .hyp().mon()
4708 .unimplemented()
4709 .mapsTo(MISCREG_ICH_AP1R3);
4710 InitReg(MISCREG_ICH_HCR_EL2)
4711 .hyp().mon()
4712 .mapsTo(MISCREG_ICH_HCR);
4713 InitReg(MISCREG_ICH_VTR_EL2)
4714 .hyp().mon().writes(0)
4715 .mapsTo(MISCREG_ICH_VTR);
4716 InitReg(MISCREG_ICH_MISR_EL2)
4717 .hyp().mon().writes(0)
4718 .mapsTo(MISCREG_ICH_MISR);
4719 InitReg(MISCREG_ICH_EISR_EL2)
4720 .hyp().mon().writes(0)
4721 .mapsTo(MISCREG_ICH_EISR);
4722 InitReg(MISCREG_ICH_ELRSR_EL2)
4723 .hyp().mon().writes(0)
4724 .mapsTo(MISCREG_ICH_ELRSR);
4725 InitReg(MISCREG_ICH_VMCR_EL2)
4726 .hyp().mon()
4727 .mapsTo(MISCREG_ICH_VMCR);
4728 InitReg(MISCREG_ICH_LR0_EL2)
4729 .hyp().mon()
4730 .allPrivileges().exceptUserMode();
4731 InitReg(MISCREG_ICH_LR1_EL2)
4732 .hyp().mon()
4733 .allPrivileges().exceptUserMode();
4734 InitReg(MISCREG_ICH_LR2_EL2)
4735 .hyp().mon()
4736 .allPrivileges().exceptUserMode();
4737 InitReg(MISCREG_ICH_LR3_EL2)
4738 .hyp().mon()
4739 .allPrivileges().exceptUserMode();
4740 InitReg(MISCREG_ICH_LR4_EL2)
4741 .hyp().mon()
4742 .allPrivileges().exceptUserMode();
4743 InitReg(MISCREG_ICH_LR5_EL2)
4744 .hyp().mon()
4745 .allPrivileges().exceptUserMode();
4746 InitReg(MISCREG_ICH_LR6_EL2)
4747 .hyp().mon()
4748 .allPrivileges().exceptUserMode();
4749 InitReg(MISCREG_ICH_LR7_EL2)
4750 .hyp().mon()
4751 .allPrivileges().exceptUserMode();
4752 InitReg(MISCREG_ICH_LR8_EL2)
4753 .hyp().mon()
4754 .allPrivileges().exceptUserMode();
4755 InitReg(MISCREG_ICH_LR9_EL2)
4756 .hyp().mon()
4757 .allPrivileges().exceptUserMode();
4758 InitReg(MISCREG_ICH_LR10_EL2)
4759 .hyp().mon()
4760 .allPrivileges().exceptUserMode();
4761 InitReg(MISCREG_ICH_LR11_EL2)
4762 .hyp().mon()
4763 .allPrivileges().exceptUserMode();
4764 InitReg(MISCREG_ICH_LR12_EL2)
4765 .hyp().mon()
4766 .allPrivileges().exceptUserMode();
4767 InitReg(MISCREG_ICH_LR13_EL2)
4768 .hyp().mon()
4769 .allPrivileges().exceptUserMode();
4770 InitReg(MISCREG_ICH_LR14_EL2)
4771 .hyp().mon()
4772 .allPrivileges().exceptUserMode();
4773 InitReg(MISCREG_ICH_LR15_EL2)
4774 .hyp().mon()
4775 .allPrivileges().exceptUserMode();
4776
4777 // GICv3 AArch32
4778 InitReg(MISCREG_ICC_AP0R0)
4779 .allPrivileges().exceptUserMode();
4780 InitReg(MISCREG_ICC_AP0R1)
4781 .allPrivileges().exceptUserMode();
4782 InitReg(MISCREG_ICC_AP0R2)
4783 .allPrivileges().exceptUserMode();
4784 InitReg(MISCREG_ICC_AP0R3)
4785 .allPrivileges().exceptUserMode();
4786 InitReg(MISCREG_ICC_AP1R0)
4787 .allPrivileges().exceptUserMode();
4788 InitReg(MISCREG_ICC_AP1R0_NS)
4789 .allPrivileges().exceptUserMode();
4790 InitReg(MISCREG_ICC_AP1R0_S)
4791 .allPrivileges().exceptUserMode();
4792 InitReg(MISCREG_ICC_AP1R1)
4793 .allPrivileges().exceptUserMode();
4794 InitReg(MISCREG_ICC_AP1R1_NS)
4795 .allPrivileges().exceptUserMode();
4796 InitReg(MISCREG_ICC_AP1R1_S)
4797 .allPrivileges().exceptUserMode();
4798 InitReg(MISCREG_ICC_AP1R2)
4799 .allPrivileges().exceptUserMode();
4800 InitReg(MISCREG_ICC_AP1R2_NS)
4801 .allPrivileges().exceptUserMode();
4802 InitReg(MISCREG_ICC_AP1R2_S)
4803 .allPrivileges().exceptUserMode();
4804 InitReg(MISCREG_ICC_AP1R3)
4805 .allPrivileges().exceptUserMode();
4806 InitReg(MISCREG_ICC_AP1R3_NS)
4807 .allPrivileges().exceptUserMode();
4808 InitReg(MISCREG_ICC_AP1R3_S)
4809 .allPrivileges().exceptUserMode();
4810 InitReg(MISCREG_ICC_ASGI1R)
4811 .allPrivileges().exceptUserMode().reads(0);
4812 InitReg(MISCREG_ICC_BPR0)
4813 .allPrivileges().exceptUserMode();
4814 InitReg(MISCREG_ICC_BPR1)
4815 .allPrivileges().exceptUserMode();
4816 InitReg(MISCREG_ICC_BPR1_NS)
4817 .allPrivileges().exceptUserMode();
4818 InitReg(MISCREG_ICC_BPR1_S)
4819 .allPrivileges().exceptUserMode();
4820 InitReg(MISCREG_ICC_CTLR)
4821 .allPrivileges().exceptUserMode();
4822 InitReg(MISCREG_ICC_CTLR_NS)
4823 .allPrivileges().exceptUserMode();
4824 InitReg(MISCREG_ICC_CTLR_S)
4825 .allPrivileges().exceptUserMode();
4826 InitReg(MISCREG_ICC_DIR)
4827 .allPrivileges().exceptUserMode().reads(0);
4828 InitReg(MISCREG_ICC_EOIR0)
4829 .allPrivileges().exceptUserMode().reads(0);
4830 InitReg(MISCREG_ICC_EOIR1)
4831 .allPrivileges().exceptUserMode().reads(0);
4832 InitReg(MISCREG_ICC_HPPIR0)
4833 .allPrivileges().exceptUserMode().writes(0);
4834 InitReg(MISCREG_ICC_HPPIR1)
4835 .allPrivileges().exceptUserMode().writes(0);
4836 InitReg(MISCREG_ICC_HSRE)
4837 .allPrivileges().exceptUserMode();
4838 InitReg(MISCREG_ICC_IAR0)
4839 .allPrivileges().exceptUserMode().writes(0);
4840 InitReg(MISCREG_ICC_IAR1)
4841 .allPrivileges().exceptUserMode().writes(0);
4842 InitReg(MISCREG_ICC_IGRPEN0)
4843 .allPrivileges().exceptUserMode();
4844 InitReg(MISCREG_ICC_IGRPEN1)
4845 .allPrivileges().exceptUserMode();
4846 InitReg(MISCREG_ICC_IGRPEN1_NS)
4847 .allPrivileges().exceptUserMode();
4848 InitReg(MISCREG_ICC_IGRPEN1_S)
4849 .allPrivileges().exceptUserMode();
4850 InitReg(MISCREG_ICC_MCTLR)
4851 .allPrivileges().exceptUserMode();
4852 InitReg(MISCREG_ICC_MGRPEN1)
4853 .allPrivileges().exceptUserMode();
4854 InitReg(MISCREG_ICC_MSRE)
4855 .allPrivileges().exceptUserMode();
4856 InitReg(MISCREG_ICC_PMR)
4857 .allPrivileges().exceptUserMode();
4858 InitReg(MISCREG_ICC_RPR)
4859 .allPrivileges().exceptUserMode().writes(0);
4860 InitReg(MISCREG_ICC_SGI0R)
4861 .allPrivileges().exceptUserMode().reads(0);
4862 InitReg(MISCREG_ICC_SGI1R)
4863 .allPrivileges().exceptUserMode().reads(0);
4864 InitReg(MISCREG_ICC_SRE)
4865 .allPrivileges().exceptUserMode();
4866 InitReg(MISCREG_ICC_SRE_NS)
4867 .allPrivileges().exceptUserMode();
4868 InitReg(MISCREG_ICC_SRE_S)
4869 .allPrivileges().exceptUserMode();
4870
4871 InitReg(MISCREG_ICH_AP0R0)
4872 .hyp().mon();
4873 InitReg(MISCREG_ICH_AP0R1)
4874 .hyp().mon();
4875 InitReg(MISCREG_ICH_AP0R2)
4876 .hyp().mon();
4877 InitReg(MISCREG_ICH_AP0R3)
4878 .hyp().mon();
4879 InitReg(MISCREG_ICH_AP1R0)
4880 .hyp().mon();
4881 InitReg(MISCREG_ICH_AP1R1)
4882 .hyp().mon();
4883 InitReg(MISCREG_ICH_AP1R2)
4884 .hyp().mon();
4885 InitReg(MISCREG_ICH_AP1R3)
4886 .hyp().mon();
4887 InitReg(MISCREG_ICH_HCR)
4888 .hyp().mon();
4889 InitReg(MISCREG_ICH_VTR)
4890 .hyp().mon().writes(0);
4891 InitReg(MISCREG_ICH_MISR)
4892 .hyp().mon().writes(0);
4893 InitReg(MISCREG_ICH_EISR)
4894 .hyp().mon().writes(0);
4895 InitReg(MISCREG_ICH_ELRSR)
4896 .hyp().mon().writes(0);
4897 InitReg(MISCREG_ICH_VMCR)
4898 .hyp().mon();
4899 InitReg(MISCREG_ICH_LR0)
4900 .hyp().mon();
4901 InitReg(MISCREG_ICH_LR1)
4902 .hyp().mon();
4903 InitReg(MISCREG_ICH_LR2)
4904 .hyp().mon();
4905 InitReg(MISCREG_ICH_LR3)
4906 .hyp().mon();
4907 InitReg(MISCREG_ICH_LR4)
4908 .hyp().mon();
4909 InitReg(MISCREG_ICH_LR5)
4910 .hyp().mon();
4911 InitReg(MISCREG_ICH_LR6)
4912 .hyp().mon();
4913 InitReg(MISCREG_ICH_LR7)
4914 .hyp().mon();
4915 InitReg(MISCREG_ICH_LR8)
4916 .hyp().mon();
4917 InitReg(MISCREG_ICH_LR9)
4918 .hyp().mon();
4919 InitReg(MISCREG_ICH_LR10)
4920 .hyp().mon();
4921 InitReg(MISCREG_ICH_LR11)
4922 .hyp().mon();
4923 InitReg(MISCREG_ICH_LR12)
4924 .hyp().mon();
4925 InitReg(MISCREG_ICH_LR13)
4926 .hyp().mon();
4927 InitReg(MISCREG_ICH_LR14)
4928 .hyp().mon();
4929 InitReg(MISCREG_ICH_LR15)
4930 .hyp().mon();
4931 InitReg(MISCREG_ICH_LRC0)
4932 .mapsTo(MISCREG_ICH_LR0)
4933 .hyp().mon();
4934 InitReg(MISCREG_ICH_LRC1)
4935 .mapsTo(MISCREG_ICH_LR1)
4936 .hyp().mon();
4937 InitReg(MISCREG_ICH_LRC2)
4938 .mapsTo(MISCREG_ICH_LR2)
4939 .hyp().mon();
4940 InitReg(MISCREG_ICH_LRC3)
4941 .mapsTo(MISCREG_ICH_LR3)
4942 .hyp().mon();
4943 InitReg(MISCREG_ICH_LRC4)
4944 .mapsTo(MISCREG_ICH_LR4)
4945 .hyp().mon();
4946 InitReg(MISCREG_ICH_LRC5)
4947 .mapsTo(MISCREG_ICH_LR5)
4948 .hyp().mon();
4949 InitReg(MISCREG_ICH_LRC6)
4950 .mapsTo(MISCREG_ICH_LR6)
4951 .hyp().mon();
4952 InitReg(MISCREG_ICH_LRC7)
4953 .mapsTo(MISCREG_ICH_LR7)
4954 .hyp().mon();
4955 InitReg(MISCREG_ICH_LRC8)
4956 .mapsTo(MISCREG_ICH_LR8)
4957 .hyp().mon();
4958 InitReg(MISCREG_ICH_LRC9)
4959 .mapsTo(MISCREG_ICH_LR9)
4960 .hyp().mon();
4961 InitReg(MISCREG_ICH_LRC10)
4962 .mapsTo(MISCREG_ICH_LR10)
4963 .hyp().mon();
4964 InitReg(MISCREG_ICH_LRC11)
4965 .mapsTo(MISCREG_ICH_LR11)
4966 .hyp().mon();
4967 InitReg(MISCREG_ICH_LRC12)
4968 .mapsTo(MISCREG_ICH_LR12)
4969 .hyp().mon();
4970 InitReg(MISCREG_ICH_LRC13)
4971 .mapsTo(MISCREG_ICH_LR13)
4972 .hyp().mon();
4973 InitReg(MISCREG_ICH_LRC14)
4974 .mapsTo(MISCREG_ICH_LR14)
4975 .hyp().mon();
4976 InitReg(MISCREG_ICH_LRC15)
4977 .mapsTo(MISCREG_ICH_LR15)
4978 .hyp().mon();
4979
4980 InitReg(MISCREG_CNTHV_CTL_EL2)
4981 .mon().hyp();
4982 InitReg(MISCREG_CNTHV_CVAL_EL2)
4983 .mon().hyp();
4984 InitReg(MISCREG_CNTHV_TVAL_EL2)
4985 .mon().hyp();
4986
4987 // SVE
4988 InitReg(MISCREG_ID_AA64ZFR0_EL1)
4989 .allPrivileges().exceptUserMode().writes(0);
4990 InitReg(MISCREG_ZCR_EL3)
4991 .mon();
4992 InitReg(MISCREG_ZCR_EL2)
4993 .hyp().mon();
4994 InitReg(MISCREG_ZCR_EL12)
4995 .unimplemented().warnNotFail();
4996 InitReg(MISCREG_ZCR_EL1)
4997 .allPrivileges().exceptUserMode();
4998
4999 // Dummy registers
5000 InitReg(MISCREG_NOP)
5001 .allPrivileges();
5002 InitReg(MISCREG_RAZ)
5003 .allPrivileges().exceptUserMode().writes(0);
5004 InitReg(MISCREG_CP14_UNIMPL)
5005 .unimplemented()
5006 .warnNotFail();
5007 InitReg(MISCREG_CP15_UNIMPL)
5008 .unimplemented()
5009 .warnNotFail();
5010 InitReg(MISCREG_UNKNOWN);
5011 InitReg(MISCREG_IMPDEF_UNIMPL)
5012 .unimplemented()
5013 .warnNotFail(impdefAsNop);
5014
5015 // RAS extension (unimplemented)
5016 InitReg(MISCREG_ERRIDR_EL1)
5017 .unimplemented()
5018 .warnNotFail();
5019 InitReg(MISCREG_ERRSELR_EL1)
5020 .unimplemented()
5021 .warnNotFail();
5022 InitReg(MISCREG_ERXFR_EL1)
5023 .unimplemented()
5024 .warnNotFail();
5025 InitReg(MISCREG_ERXCTLR_EL1)
5026 .unimplemented()
5027 .warnNotFail();
5028 InitReg(MISCREG_ERXSTATUS_EL1)
5029 .unimplemented()
5030 .warnNotFail();
5031 InitReg(MISCREG_ERXADDR_EL1)
5032 .unimplemented()
5033 .warnNotFail();
5034 InitReg(MISCREG_ERXMISC0_EL1)
5035 .unimplemented()
5036 .warnNotFail();
5037 InitReg(MISCREG_ERXMISC1_EL1)
5038 .unimplemented()
5039 .warnNotFail();
5040 InitReg(MISCREG_DISR_EL1)
5041 .unimplemented()
5042 .warnNotFail();
5043 InitReg(MISCREG_VSESR_EL2)
5044 .unimplemented()
5045 .warnNotFail();
5046 InitReg(MISCREG_VDISR_EL2)
5047 .unimplemented()
5048 .warnNotFail();
5049
5050 // Register mappings for some unimplemented registers:
5051 // ESR_EL1 -> DFSR
5052 // RMR_EL1 -> RMR
5053 // RMR_EL2 -> HRMR
5054 // DBGDTR_EL0 -> DBGDTR{R or T}Xint
5055 // DBGDTRRX_EL0 -> DBGDTRRXint
5056 // DBGDTRTX_EL0 -> DBGDTRRXint
5057 // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
5058
5059 completed = true;
5060 }
5061
5062 } // namespace ArmISA