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misc: Merged release-staging-v19.0.0.0 into develop
[gem5.git] / src / arch / arm / miscregs.cc
1 /*
2 * Copyright (c) 2010-2013, 2015-2020 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 #include "arch/arm/miscregs.hh"
39
40 #include <tuple>
41
42 #include "arch/arm/isa.hh"
43 #include "base/logging.hh"
44 #include "cpu/thread_context.hh"
45 #include "sim/full_system.hh"
46
47 namespace ArmISA
48 {
49
50 MiscRegIndex
51 decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
52 {
53 switch(crn) {
54 case 0:
55 switch (opc1) {
56 case 0:
57 switch (opc2) {
58 case 0:
59 switch (crm) {
60 case 0:
61 return MISCREG_DBGDIDR;
62 case 1:
63 return MISCREG_DBGDSCRint;
64 }
65 break;
66 }
67 break;
68 case 7:
69 switch (opc2) {
70 case 0:
71 switch (crm) {
72 case 0:
73 return MISCREG_JIDR;
74 }
75 break;
76 }
77 break;
78 }
79 break;
80 case 1:
81 switch (opc1) {
82 case 6:
83 switch (crm) {
84 case 0:
85 switch (opc2) {
86 case 0:
87 return MISCREG_TEEHBR;
88 }
89 break;
90 }
91 break;
92 case 7:
93 switch (crm) {
94 case 0:
95 switch (opc2) {
96 case 0:
97 return MISCREG_JOSCR;
98 }
99 break;
100 }
101 break;
102 }
103 break;
104 case 2:
105 switch (opc1) {
106 case 7:
107 switch (crm) {
108 case 0:
109 switch (opc2) {
110 case 0:
111 return MISCREG_JMCR;
112 }
113 break;
114 }
115 break;
116 }
117 break;
118 }
119 // If we get here then it must be a register that we haven't implemented
120 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
121 crn, opc1, crm, opc2);
122 return MISCREG_CP14_UNIMPL;
123 }
124
125 using namespace std;
126
127 MiscRegIndex
128 decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
129 {
130 switch (crn) {
131 case 0:
132 switch (opc1) {
133 case 0:
134 switch (crm) {
135 case 0:
136 switch (opc2) {
137 case 1:
138 return MISCREG_CTR;
139 case 2:
140 return MISCREG_TCMTR;
141 case 3:
142 return MISCREG_TLBTR;
143 case 5:
144 return MISCREG_MPIDR;
145 case 6:
146 return MISCREG_REVIDR;
147 default:
148 return MISCREG_MIDR;
149 }
150 break;
151 case 1:
152 switch (opc2) {
153 case 0:
154 return MISCREG_ID_PFR0;
155 case 1:
156 return MISCREG_ID_PFR1;
157 case 2:
158 return MISCREG_ID_DFR0;
159 case 3:
160 return MISCREG_ID_AFR0;
161 case 4:
162 return MISCREG_ID_MMFR0;
163 case 5:
164 return MISCREG_ID_MMFR1;
165 case 6:
166 return MISCREG_ID_MMFR2;
167 case 7:
168 return MISCREG_ID_MMFR3;
169 }
170 break;
171 case 2:
172 switch (opc2) {
173 case 0:
174 return MISCREG_ID_ISAR0;
175 case 1:
176 return MISCREG_ID_ISAR1;
177 case 2:
178 return MISCREG_ID_ISAR2;
179 case 3:
180 return MISCREG_ID_ISAR3;
181 case 4:
182 return MISCREG_ID_ISAR4;
183 case 5:
184 return MISCREG_ID_ISAR5;
185 case 6:
186 case 7:
187 return MISCREG_RAZ; // read as zero
188 }
189 break;
190 default:
191 return MISCREG_RAZ; // read as zero
192 }
193 break;
194 case 1:
195 if (crm == 0) {
196 switch (opc2) {
197 case 0:
198 return MISCREG_CCSIDR;
199 case 1:
200 return MISCREG_CLIDR;
201 case 7:
202 return MISCREG_AIDR;
203 }
204 }
205 break;
206 case 2:
207 if (crm == 0 && opc2 == 0) {
208 return MISCREG_CSSELR;
209 }
210 break;
211 case 4:
212 if (crm == 0) {
213 if (opc2 == 0)
214 return MISCREG_VPIDR;
215 else if (opc2 == 5)
216 return MISCREG_VMPIDR;
217 }
218 break;
219 }
220 break;
221 case 1:
222 if (opc1 == 0) {
223 if (crm == 0) {
224 switch (opc2) {
225 case 0:
226 return MISCREG_SCTLR;
227 case 1:
228 return MISCREG_ACTLR;
229 case 0x2:
230 return MISCREG_CPACR;
231 }
232 } else if (crm == 1) {
233 switch (opc2) {
234 case 0:
235 return MISCREG_SCR;
236 case 1:
237 return MISCREG_SDER;
238 case 2:
239 return MISCREG_NSACR;
240 }
241 }
242 } else if (opc1 == 4) {
243 if (crm == 0) {
244 if (opc2 == 0)
245 return MISCREG_HSCTLR;
246 else if (opc2 == 1)
247 return MISCREG_HACTLR;
248 } else if (crm == 1) {
249 switch (opc2) {
250 case 0:
251 return MISCREG_HCR;
252 case 1:
253 return MISCREG_HDCR;
254 case 2:
255 return MISCREG_HCPTR;
256 case 4:
257 return MISCREG_HCR2;
258 case 3:
259 return MISCREG_HSTR;
260 case 7:
261 return MISCREG_HACR;
262 }
263 }
264 }
265 break;
266 case 2:
267 if (opc1 == 0 && crm == 0) {
268 switch (opc2) {
269 case 0:
270 return MISCREG_TTBR0;
271 case 1:
272 return MISCREG_TTBR1;
273 case 2:
274 return MISCREG_TTBCR;
275 }
276 } else if (opc1 == 4) {
277 if (crm == 0 && opc2 == 2)
278 return MISCREG_HTCR;
279 else if (crm == 1 && opc2 == 2)
280 return MISCREG_VTCR;
281 }
282 break;
283 case 3:
284 if (opc1 == 0 && crm == 0 && opc2 == 0) {
285 return MISCREG_DACR;
286 }
287 break;
288 case 4:
289 if (opc1 == 0 && crm == 6 && opc2 == 0) {
290 return MISCREG_ICC_PMR;
291 }
292 break;
293 case 5:
294 if (opc1 == 0) {
295 if (crm == 0) {
296 if (opc2 == 0) {
297 return MISCREG_DFSR;
298 } else if (opc2 == 1) {
299 return MISCREG_IFSR;
300 }
301 } else if (crm == 1) {
302 if (opc2 == 0) {
303 return MISCREG_ADFSR;
304 } else if (opc2 == 1) {
305 return MISCREG_AIFSR;
306 }
307 }
308 } else if (opc1 == 4) {
309 if (crm == 1) {
310 if (opc2 == 0)
311 return MISCREG_HADFSR;
312 else if (opc2 == 1)
313 return MISCREG_HAIFSR;
314 } else if (crm == 2 && opc2 == 0) {
315 return MISCREG_HSR;
316 }
317 }
318 break;
319 case 6:
320 if (opc1 == 0 && crm == 0) {
321 switch (opc2) {
322 case 0:
323 return MISCREG_DFAR;
324 case 2:
325 return MISCREG_IFAR;
326 }
327 } else if (opc1 == 4 && crm == 0) {
328 switch (opc2) {
329 case 0:
330 return MISCREG_HDFAR;
331 case 2:
332 return MISCREG_HIFAR;
333 case 4:
334 return MISCREG_HPFAR;
335 }
336 }
337 break;
338 case 7:
339 if (opc1 == 0) {
340 switch (crm) {
341 case 0:
342 if (opc2 == 4) {
343 return MISCREG_NOP;
344 }
345 break;
346 case 1:
347 switch (opc2) {
348 case 0:
349 return MISCREG_ICIALLUIS;
350 case 6:
351 return MISCREG_BPIALLIS;
352 }
353 break;
354 case 4:
355 if (opc2 == 0) {
356 return MISCREG_PAR;
357 }
358 break;
359 case 5:
360 switch (opc2) {
361 case 0:
362 return MISCREG_ICIALLU;
363 case 1:
364 return MISCREG_ICIMVAU;
365 case 4:
366 return MISCREG_CP15ISB;
367 case 6:
368 return MISCREG_BPIALL;
369 case 7:
370 return MISCREG_BPIMVA;
371 }
372 break;
373 case 6:
374 if (opc2 == 1) {
375 return MISCREG_DCIMVAC;
376 } else if (opc2 == 2) {
377 return MISCREG_DCISW;
378 }
379 break;
380 case 8:
381 switch (opc2) {
382 case 0:
383 return MISCREG_ATS1CPR;
384 case 1:
385 return MISCREG_ATS1CPW;
386 case 2:
387 return MISCREG_ATS1CUR;
388 case 3:
389 return MISCREG_ATS1CUW;
390 case 4:
391 return MISCREG_ATS12NSOPR;
392 case 5:
393 return MISCREG_ATS12NSOPW;
394 case 6:
395 return MISCREG_ATS12NSOUR;
396 case 7:
397 return MISCREG_ATS12NSOUW;
398 }
399 break;
400 case 10:
401 switch (opc2) {
402 case 1:
403 return MISCREG_DCCMVAC;
404 case 2:
405 return MISCREG_DCCSW;
406 case 4:
407 return MISCREG_CP15DSB;
408 case 5:
409 return MISCREG_CP15DMB;
410 }
411 break;
412 case 11:
413 if (opc2 == 1) {
414 return MISCREG_DCCMVAU;
415 }
416 break;
417 case 13:
418 if (opc2 == 1) {
419 return MISCREG_NOP;
420 }
421 break;
422 case 14:
423 if (opc2 == 1) {
424 return MISCREG_DCCIMVAC;
425 } else if (opc2 == 2) {
426 return MISCREG_DCCISW;
427 }
428 break;
429 }
430 } else if (opc1 == 4 && crm == 8) {
431 if (opc2 == 0)
432 return MISCREG_ATS1HR;
433 else if (opc2 == 1)
434 return MISCREG_ATS1HW;
435 }
436 break;
437 case 8:
438 if (opc1 == 0) {
439 switch (crm) {
440 case 3:
441 switch (opc2) {
442 case 0:
443 return MISCREG_TLBIALLIS;
444 case 1:
445 return MISCREG_TLBIMVAIS;
446 case 2:
447 return MISCREG_TLBIASIDIS;
448 case 3:
449 return MISCREG_TLBIMVAAIS;
450 case 5:
451 return MISCREG_TLBIMVALIS;
452 case 7:
453 return MISCREG_TLBIMVAALIS;
454 }
455 break;
456 case 5:
457 switch (opc2) {
458 case 0:
459 return MISCREG_ITLBIALL;
460 case 1:
461 return MISCREG_ITLBIMVA;
462 case 2:
463 return MISCREG_ITLBIASID;
464 }
465 break;
466 case 6:
467 switch (opc2) {
468 case 0:
469 return MISCREG_DTLBIALL;
470 case 1:
471 return MISCREG_DTLBIMVA;
472 case 2:
473 return MISCREG_DTLBIASID;
474 }
475 break;
476 case 7:
477 switch (opc2) {
478 case 0:
479 return MISCREG_TLBIALL;
480 case 1:
481 return MISCREG_TLBIMVA;
482 case 2:
483 return MISCREG_TLBIASID;
484 case 3:
485 return MISCREG_TLBIMVAA;
486 case 5:
487 return MISCREG_TLBIMVAL;
488 case 7:
489 return MISCREG_TLBIMVAAL;
490 }
491 break;
492 }
493 } else if (opc1 == 4) {
494 if (crm == 0) {
495 switch (opc2) {
496 case 1:
497 return MISCREG_TLBIIPAS2IS;
498 case 5:
499 return MISCREG_TLBIIPAS2LIS;
500 }
501 } else if (crm == 3) {
502 switch (opc2) {
503 case 0:
504 return MISCREG_TLBIALLHIS;
505 case 1:
506 return MISCREG_TLBIMVAHIS;
507 case 4:
508 return MISCREG_TLBIALLNSNHIS;
509 case 5:
510 return MISCREG_TLBIMVALHIS;
511 }
512 } else if (crm == 4) {
513 switch (opc2) {
514 case 1:
515 return MISCREG_TLBIIPAS2;
516 case 5:
517 return MISCREG_TLBIIPAS2L;
518 }
519 } else if (crm == 7) {
520 switch (opc2) {
521 case 0:
522 return MISCREG_TLBIALLH;
523 case 1:
524 return MISCREG_TLBIMVAH;
525 case 4:
526 return MISCREG_TLBIALLNSNH;
527 case 5:
528 return MISCREG_TLBIMVALH;
529 }
530 }
531 }
532 break;
533 case 9:
534 // Every cop register with CRn = 9 and CRm in
535 // {0-2}, {5-8} is implementation defined regardless
536 // of opc1 and opc2.
537 switch (crm) {
538 case 0:
539 case 1:
540 case 2:
541 case 5:
542 case 6:
543 case 7:
544 case 8:
545 return MISCREG_IMPDEF_UNIMPL;
546 }
547 if (opc1 == 0) {
548 switch (crm) {
549 case 12:
550 switch (opc2) {
551 case 0:
552 return MISCREG_PMCR;
553 case 1:
554 return MISCREG_PMCNTENSET;
555 case 2:
556 return MISCREG_PMCNTENCLR;
557 case 3:
558 return MISCREG_PMOVSR;
559 case 4:
560 return MISCREG_PMSWINC;
561 case 5:
562 return MISCREG_PMSELR;
563 case 6:
564 return MISCREG_PMCEID0;
565 case 7:
566 return MISCREG_PMCEID1;
567 }
568 break;
569 case 13:
570 switch (opc2) {
571 case 0:
572 return MISCREG_PMCCNTR;
573 case 1:
574 // Selector is PMSELR.SEL
575 return MISCREG_PMXEVTYPER_PMCCFILTR;
576 case 2:
577 return MISCREG_PMXEVCNTR;
578 }
579 break;
580 case 14:
581 switch (opc2) {
582 case 0:
583 return MISCREG_PMUSERENR;
584 case 1:
585 return MISCREG_PMINTENSET;
586 case 2:
587 return MISCREG_PMINTENCLR;
588 case 3:
589 return MISCREG_PMOVSSET;
590 }
591 break;
592 }
593 } else if (opc1 == 1) {
594 switch (crm) {
595 case 0:
596 switch (opc2) {
597 case 2: // L2CTLR, L2 Control Register
598 return MISCREG_L2CTLR;
599 case 3:
600 return MISCREG_L2ECTLR;
601 }
602 break;
603 break;
604 }
605 }
606 break;
607 case 10:
608 if (opc1 == 0) {
609 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
610 if (crm < 2) {
611 return MISCREG_IMPDEF_UNIMPL;
612 } else if (crm == 2) { // TEX Remap Registers
613 if (opc2 == 0) {
614 // Selector is TTBCR.EAE
615 return MISCREG_PRRR_MAIR0;
616 } else if (opc2 == 1) {
617 // Selector is TTBCR.EAE
618 return MISCREG_NMRR_MAIR1;
619 }
620 } else if (crm == 3) {
621 if (opc2 == 0) {
622 return MISCREG_AMAIR0;
623 } else if (opc2 == 1) {
624 return MISCREG_AMAIR1;
625 }
626 }
627 } else if (opc1 == 4) {
628 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
629 if (crm == 2) {
630 if (opc2 == 0)
631 return MISCREG_HMAIR0;
632 else if (opc2 == 1)
633 return MISCREG_HMAIR1;
634 } else if (crm == 3) {
635 if (opc2 == 0)
636 return MISCREG_HAMAIR0;
637 else if (opc2 == 1)
638 return MISCREG_HAMAIR1;
639 }
640 }
641 break;
642 case 11:
643 if (opc1 <=7) {
644 switch (crm) {
645 case 0:
646 case 1:
647 case 2:
648 case 3:
649 case 4:
650 case 5:
651 case 6:
652 case 7:
653 case 8:
654 case 15:
655 // Reserved for DMA operations for TCM access
656 return MISCREG_IMPDEF_UNIMPL;
657 default:
658 break;
659 }
660 }
661 break;
662 case 12:
663 if (opc1 == 0) {
664 if (crm == 0) {
665 if (opc2 == 0) {
666 return MISCREG_VBAR;
667 } else if (opc2 == 1) {
668 return MISCREG_MVBAR;
669 }
670 } else if (crm == 1) {
671 if (opc2 == 0) {
672 return MISCREG_ISR;
673 }
674 } else if (crm == 8) {
675 switch (opc2) {
676 case 0:
677 return MISCREG_ICC_IAR0;
678 case 1:
679 return MISCREG_ICC_EOIR0;
680 case 2:
681 return MISCREG_ICC_HPPIR0;
682 case 3:
683 return MISCREG_ICC_BPR0;
684 case 4:
685 return MISCREG_ICC_AP0R0;
686 case 5:
687 return MISCREG_ICC_AP0R1;
688 case 6:
689 return MISCREG_ICC_AP0R2;
690 case 7:
691 return MISCREG_ICC_AP0R3;
692 }
693 } else if (crm == 9) {
694 switch (opc2) {
695 case 0:
696 return MISCREG_ICC_AP1R0;
697 case 1:
698 return MISCREG_ICC_AP1R1;
699 case 2:
700 return MISCREG_ICC_AP1R2;
701 case 3:
702 return MISCREG_ICC_AP1R3;
703 }
704 } else if (crm == 11) {
705 switch (opc2) {
706 case 1:
707 return MISCREG_ICC_DIR;
708 case 3:
709 return MISCREG_ICC_RPR;
710 }
711 } else if (crm == 12) {
712 switch (opc2) {
713 case 0:
714 return MISCREG_ICC_IAR1;
715 case 1:
716 return MISCREG_ICC_EOIR1;
717 case 2:
718 return MISCREG_ICC_HPPIR1;
719 case 3:
720 return MISCREG_ICC_BPR1;
721 case 4:
722 return MISCREG_ICC_CTLR;
723 case 5:
724 return MISCREG_ICC_SRE;
725 case 6:
726 return MISCREG_ICC_IGRPEN0;
727 case 7:
728 return MISCREG_ICC_IGRPEN1;
729 }
730 }
731 } else if (opc1 == 4) {
732 if (crm == 0 && opc2 == 0) {
733 return MISCREG_HVBAR;
734 } else if (crm == 8) {
735 switch (opc2) {
736 case 0:
737 return MISCREG_ICH_AP0R0;
738 case 1:
739 return MISCREG_ICH_AP0R1;
740 case 2:
741 return MISCREG_ICH_AP0R2;
742 case 3:
743 return MISCREG_ICH_AP0R3;
744 }
745 } else if (crm == 9) {
746 switch (opc2) {
747 case 0:
748 return MISCREG_ICH_AP1R0;
749 case 1:
750 return MISCREG_ICH_AP1R1;
751 case 2:
752 return MISCREG_ICH_AP1R2;
753 case 3:
754 return MISCREG_ICH_AP1R3;
755 case 5:
756 return MISCREG_ICC_HSRE;
757 }
758 } else if (crm == 11) {
759 switch (opc2) {
760 case 0:
761 return MISCREG_ICH_HCR;
762 case 1:
763 return MISCREG_ICH_VTR;
764 case 2:
765 return MISCREG_ICH_MISR;
766 case 3:
767 return MISCREG_ICH_EISR;
768 case 5:
769 return MISCREG_ICH_ELRSR;
770 case 7:
771 return MISCREG_ICH_VMCR;
772 }
773 } else if (crm == 12) {
774 switch (opc2) {
775 case 0:
776 return MISCREG_ICH_LR0;
777 case 1:
778 return MISCREG_ICH_LR1;
779 case 2:
780 return MISCREG_ICH_LR2;
781 case 3:
782 return MISCREG_ICH_LR3;
783 case 4:
784 return MISCREG_ICH_LR4;
785 case 5:
786 return MISCREG_ICH_LR5;
787 case 6:
788 return MISCREG_ICH_LR6;
789 case 7:
790 return MISCREG_ICH_LR7;
791 }
792 } else if (crm == 13) {
793 switch (opc2) {
794 case 0:
795 return MISCREG_ICH_LR8;
796 case 1:
797 return MISCREG_ICH_LR9;
798 case 2:
799 return MISCREG_ICH_LR10;
800 case 3:
801 return MISCREG_ICH_LR11;
802 case 4:
803 return MISCREG_ICH_LR12;
804 case 5:
805 return MISCREG_ICH_LR13;
806 case 6:
807 return MISCREG_ICH_LR14;
808 case 7:
809 return MISCREG_ICH_LR15;
810 }
811 } else if (crm == 14) {
812 switch (opc2) {
813 case 0:
814 return MISCREG_ICH_LRC0;
815 case 1:
816 return MISCREG_ICH_LRC1;
817 case 2:
818 return MISCREG_ICH_LRC2;
819 case 3:
820 return MISCREG_ICH_LRC3;
821 case 4:
822 return MISCREG_ICH_LRC4;
823 case 5:
824 return MISCREG_ICH_LRC5;
825 case 6:
826 return MISCREG_ICH_LRC6;
827 case 7:
828 return MISCREG_ICH_LRC7;
829 }
830 } else if (crm == 15) {
831 switch (opc2) {
832 case 0:
833 return MISCREG_ICH_LRC8;
834 case 1:
835 return MISCREG_ICH_LRC9;
836 case 2:
837 return MISCREG_ICH_LRC10;
838 case 3:
839 return MISCREG_ICH_LRC11;
840 case 4:
841 return MISCREG_ICH_LRC12;
842 case 5:
843 return MISCREG_ICH_LRC13;
844 case 6:
845 return MISCREG_ICH_LRC14;
846 case 7:
847 return MISCREG_ICH_LRC15;
848 }
849 }
850 } else if (opc1 == 6) {
851 if (crm == 12) {
852 switch (opc2) {
853 case 4:
854 return MISCREG_ICC_MCTLR;
855 case 5:
856 return MISCREG_ICC_MSRE;
857 case 7:
858 return MISCREG_ICC_MGRPEN1;
859 }
860 }
861 }
862 break;
863 case 13:
864 if (opc1 == 0) {
865 if (crm == 0) {
866 switch (opc2) {
867 case 0:
868 return MISCREG_FCSEIDR;
869 case 1:
870 return MISCREG_CONTEXTIDR;
871 case 2:
872 return MISCREG_TPIDRURW;
873 case 3:
874 return MISCREG_TPIDRURO;
875 case 4:
876 return MISCREG_TPIDRPRW;
877 }
878 }
879 } else if (opc1 == 4) {
880 if (crm == 0 && opc2 == 2)
881 return MISCREG_HTPIDR;
882 }
883 break;
884 case 14:
885 if (opc1 == 0) {
886 switch (crm) {
887 case 0:
888 if (opc2 == 0)
889 return MISCREG_CNTFRQ;
890 break;
891 case 1:
892 if (opc2 == 0)
893 return MISCREG_CNTKCTL;
894 break;
895 case 2:
896 if (opc2 == 0)
897 return MISCREG_CNTP_TVAL;
898 else if (opc2 == 1)
899 return MISCREG_CNTP_CTL;
900 break;
901 case 3:
902 if (opc2 == 0)
903 return MISCREG_CNTV_TVAL;
904 else if (opc2 == 1)
905 return MISCREG_CNTV_CTL;
906 break;
907 }
908 } else if (opc1 == 4) {
909 if (crm == 1 && opc2 == 0) {
910 return MISCREG_CNTHCTL;
911 } else if (crm == 2) {
912 if (opc2 == 0)
913 return MISCREG_CNTHP_TVAL;
914 else if (opc2 == 1)
915 return MISCREG_CNTHP_CTL;
916 }
917 }
918 break;
919 case 15:
920 // Implementation defined
921 return MISCREG_IMPDEF_UNIMPL;
922 }
923 // Unrecognized register
924 return MISCREG_CP15_UNIMPL;
925 }
926
927 MiscRegIndex
928 decodeCP15Reg64(unsigned crm, unsigned opc1)
929 {
930 switch (crm) {
931 case 2:
932 switch (opc1) {
933 case 0:
934 return MISCREG_TTBR0;
935 case 1:
936 return MISCREG_TTBR1;
937 case 4:
938 return MISCREG_HTTBR;
939 case 6:
940 return MISCREG_VTTBR;
941 }
942 break;
943 case 7:
944 if (opc1 == 0)
945 return MISCREG_PAR;
946 break;
947 case 14:
948 switch (opc1) {
949 case 0:
950 return MISCREG_CNTPCT;
951 case 1:
952 return MISCREG_CNTVCT;
953 case 2:
954 return MISCREG_CNTP_CVAL;
955 case 3:
956 return MISCREG_CNTV_CVAL;
957 case 4:
958 return MISCREG_CNTVOFF;
959 case 6:
960 return MISCREG_CNTHP_CVAL;
961 }
962 break;
963 case 12:
964 switch (opc1) {
965 case 0:
966 return MISCREG_ICC_SGI1R;
967 case 1:
968 return MISCREG_ICC_ASGI1R;
969 case 2:
970 return MISCREG_ICC_SGI0R;
971 default:
972 break;
973 }
974 break;
975 case 15:
976 if (opc1 == 0)
977 return MISCREG_CPUMERRSR;
978 else if (opc1 == 1)
979 return MISCREG_L2MERRSR;
980 break;
981 }
982 // Unrecognized register
983 return MISCREG_CP15_UNIMPL;
984 }
985
986 std::tuple<bool, bool>
987 canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
988 {
989 bool secure = !scr.ns;
990 bool canRead = false;
991 bool undefined = false;
992
993 switch (cpsr.mode) {
994 case MODE_USER:
995 canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
996 miscRegInfo[reg][MISCREG_USR_NS_RD];
997 break;
998 case MODE_FIQ:
999 case MODE_IRQ:
1000 case MODE_SVC:
1001 case MODE_ABORT:
1002 case MODE_UNDEFINED:
1003 case MODE_SYSTEM:
1004 canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1005 miscRegInfo[reg][MISCREG_PRI_NS_RD];
1006 break;
1007 case MODE_MON:
1008 canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1009 miscRegInfo[reg][MISCREG_MON_NS1_RD];
1010 break;
1011 case MODE_HYP:
1012 canRead = miscRegInfo[reg][MISCREG_HYP_RD];
1013 break;
1014 default:
1015 undefined = true;
1016 }
1017 // can't do permissions checkes on the root of a banked pair of regs
1018 assert(!miscRegInfo[reg][MISCREG_BANKED]);
1019 return std::make_tuple(canRead, undefined);
1020 }
1021
1022 std::tuple<bool, bool>
1023 canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
1024 {
1025 bool secure = !scr.ns;
1026 bool canWrite = false;
1027 bool undefined = false;
1028
1029 switch (cpsr.mode) {
1030 case MODE_USER:
1031 canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1032 miscRegInfo[reg][MISCREG_USR_NS_WR];
1033 break;
1034 case MODE_FIQ:
1035 case MODE_IRQ:
1036 case MODE_SVC:
1037 case MODE_ABORT:
1038 case MODE_UNDEFINED:
1039 case MODE_SYSTEM:
1040 canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1041 miscRegInfo[reg][MISCREG_PRI_NS_WR];
1042 break;
1043 case MODE_MON:
1044 canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1045 miscRegInfo[reg][MISCREG_MON_NS1_WR];
1046 break;
1047 case MODE_HYP:
1048 canWrite = miscRegInfo[reg][MISCREG_HYP_WR];
1049 break;
1050 default:
1051 undefined = true;
1052 }
1053 // can't do permissions checkes on the root of a banked pair of regs
1054 assert(!miscRegInfo[reg][MISCREG_BANKED]);
1055 return std::make_tuple(canWrite, undefined);
1056 }
1057
1058 int
1059 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
1060 {
1061 SCR scr = tc->readMiscReg(MISCREG_SCR);
1062 return snsBankedIndex(reg, tc, scr.ns);
1063 }
1064
1065 int
1066 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
1067 {
1068 int reg_as_int = static_cast<int>(reg);
1069 if (miscRegInfo[reg][MISCREG_BANKED]) {
1070 reg_as_int += (ArmSystem::haveSecurity(tc) &&
1071 !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
1072 }
1073 return reg_as_int;
1074 }
1075
1076 int
1077 snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc)
1078 {
1079 auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
1080 SCR scr = tc->readMiscReg(MISCREG_SCR);
1081 return isa->snsBankedIndex64(reg, scr.ns);
1082 }
1083
1084 /**
1085 * If the reg is a child reg of a banked set, then the parent is the last
1086 * banked one in the list. This is messy, and the wish is to eventually have
1087 * the bitmap replaced with a better data structure. the preUnflatten function
1088 * initializes a lookup table to speed up the search for these banked
1089 * registers.
1090 */
1091
1092 int unflattenResultMiscReg[NUM_MISCREGS];
1093
1094 void
1095 preUnflattenMiscReg()
1096 {
1097 int reg = -1;
1098 for (int i = 0 ; i < NUM_MISCREGS; i++){
1099 if (miscRegInfo[i][MISCREG_BANKED])
1100 reg = i;
1101 if (miscRegInfo[i][MISCREG_BANKED_CHILD])
1102 unflattenResultMiscReg[i] = reg;
1103 else
1104 unflattenResultMiscReg[i] = i;
1105 // if this assert fails, no parent was found, and something is broken
1106 assert(unflattenResultMiscReg[i] > -1);
1107 }
1108 }
1109
1110 int
1111 unflattenMiscReg(int reg)
1112 {
1113 return unflattenResultMiscReg[reg];
1114 }
1115
1116 bool
1117 canReadAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
1118 ThreadContext *tc)
1119 {
1120 // Check for SP_EL0 access while SPSEL == 0
1121 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1122 return false;
1123
1124 // Check for RVBAR access
1125 if (reg == MISCREG_RVBAR_EL1) {
1126 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1127 if (highest_el == EL2 || highest_el == EL3)
1128 return false;
1129 }
1130 if (reg == MISCREG_RVBAR_EL2) {
1131 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1132 if (highest_el == EL3)
1133 return false;
1134 }
1135
1136 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
1137 bool el2_host = EL2Enabled(tc) && hcr.e2h;
1138
1139 switch (currEL(cpsr)) {
1140 case EL0:
1141 return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
1142 miscRegInfo[reg][MISCREG_USR_NS_RD];
1143 case EL1:
1144 return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1145 miscRegInfo[reg][MISCREG_PRI_NS_RD];
1146 case EL2:
1147 return el2_host ? miscRegInfo[reg][MISCREG_HYP_E2H_RD] :
1148 miscRegInfo[reg][MISCREG_HYP_RD];
1149 case EL3:
1150 return el2_host ? miscRegInfo[reg][MISCREG_MON_E2H_RD] :
1151 secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1152 miscRegInfo[reg][MISCREG_MON_NS1_RD];
1153 default:
1154 panic("Invalid exception level");
1155 }
1156 }
1157
1158 bool
1159 canWriteAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
1160 ThreadContext *tc)
1161 {
1162 // Check for SP_EL0 access while SPSEL == 0
1163 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1164 return false;
1165 ExceptionLevel el = currEL(cpsr);
1166 if (reg == MISCREG_DAIF) {
1167 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1168 if (el == EL0 && !sctlr.uma)
1169 return false;
1170 }
1171 if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
1172 // In syscall-emulation mode, this test is skipped and DCZVA is always
1173 // allowed at EL0
1174 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1175 if (el == EL0 && !sctlr.dze)
1176 return false;
1177 }
1178 if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
1179 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1180 if (el == EL0 && !sctlr.uci)
1181 return false;
1182 }
1183
1184 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
1185 bool el2_host = EL2Enabled(tc) && hcr.e2h;
1186
1187 switch (el) {
1188 case EL0:
1189 return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1190 miscRegInfo[reg][MISCREG_USR_NS_WR];
1191 case EL1:
1192 return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1193 miscRegInfo[reg][MISCREG_PRI_NS_WR];
1194 case EL2:
1195 return el2_host ? miscRegInfo[reg][MISCREG_HYP_E2H_WR] :
1196 miscRegInfo[reg][MISCREG_HYP_WR];
1197 case EL3:
1198 return el2_host ? miscRegInfo[reg][MISCREG_MON_E2H_WR] :
1199 secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1200 miscRegInfo[reg][MISCREG_MON_NS1_WR];
1201 default:
1202 panic("Invalid exception level");
1203 }
1204 }
1205
1206 MiscRegIndex
1207 decodeAArch64SysReg(unsigned op0, unsigned op1,
1208 unsigned crn, unsigned crm,
1209 unsigned op2)
1210 {
1211 switch (op0) {
1212 case 1:
1213 switch (crn) {
1214 case 7:
1215 switch (op1) {
1216 case 0:
1217 switch (crm) {
1218 case 1:
1219 switch (op2) {
1220 case 0:
1221 return MISCREG_IC_IALLUIS;
1222 }
1223 break;
1224 case 5:
1225 switch (op2) {
1226 case 0:
1227 return MISCREG_IC_IALLU;
1228 }
1229 break;
1230 case 6:
1231 switch (op2) {
1232 case 1:
1233 return MISCREG_DC_IVAC_Xt;
1234 case 2:
1235 return MISCREG_DC_ISW_Xt;
1236 }
1237 break;
1238 case 8:
1239 switch (op2) {
1240 case 0:
1241 return MISCREG_AT_S1E1R_Xt;
1242 case 1:
1243 return MISCREG_AT_S1E1W_Xt;
1244 case 2:
1245 return MISCREG_AT_S1E0R_Xt;
1246 case 3:
1247 return MISCREG_AT_S1E0W_Xt;
1248 }
1249 break;
1250 case 10:
1251 switch (op2) {
1252 case 2:
1253 return MISCREG_DC_CSW_Xt;
1254 }
1255 break;
1256 case 14:
1257 switch (op2) {
1258 case 2:
1259 return MISCREG_DC_CISW_Xt;
1260 }
1261 break;
1262 }
1263 break;
1264 case 3:
1265 switch (crm) {
1266 case 4:
1267 switch (op2) {
1268 case 1:
1269 return MISCREG_DC_ZVA_Xt;
1270 }
1271 break;
1272 case 5:
1273 switch (op2) {
1274 case 1:
1275 return MISCREG_IC_IVAU_Xt;
1276 }
1277 break;
1278 case 10:
1279 switch (op2) {
1280 case 1:
1281 return MISCREG_DC_CVAC_Xt;
1282 }
1283 break;
1284 case 11:
1285 switch (op2) {
1286 case 1:
1287 return MISCREG_DC_CVAU_Xt;
1288 }
1289 break;
1290 case 14:
1291 switch (op2) {
1292 case 1:
1293 return MISCREG_DC_CIVAC_Xt;
1294 }
1295 break;
1296 }
1297 break;
1298 case 4:
1299 switch (crm) {
1300 case 8:
1301 switch (op2) {
1302 case 0:
1303 return MISCREG_AT_S1E2R_Xt;
1304 case 1:
1305 return MISCREG_AT_S1E2W_Xt;
1306 case 4:
1307 return MISCREG_AT_S12E1R_Xt;
1308 case 5:
1309 return MISCREG_AT_S12E1W_Xt;
1310 case 6:
1311 return MISCREG_AT_S12E0R_Xt;
1312 case 7:
1313 return MISCREG_AT_S12E0W_Xt;
1314 }
1315 break;
1316 }
1317 break;
1318 case 6:
1319 switch (crm) {
1320 case 8:
1321 switch (op2) {
1322 case 0:
1323 return MISCREG_AT_S1E3R_Xt;
1324 case 1:
1325 return MISCREG_AT_S1E3W_Xt;
1326 }
1327 break;
1328 }
1329 break;
1330 }
1331 break;
1332 case 8:
1333 switch (op1) {
1334 case 0:
1335 switch (crm) {
1336 case 3:
1337 switch (op2) {
1338 case 0:
1339 return MISCREG_TLBI_VMALLE1IS;
1340 case 1:
1341 return MISCREG_TLBI_VAE1IS_Xt;
1342 case 2:
1343 return MISCREG_TLBI_ASIDE1IS_Xt;
1344 case 3:
1345 return MISCREG_TLBI_VAAE1IS_Xt;
1346 case 5:
1347 return MISCREG_TLBI_VALE1IS_Xt;
1348 case 7:
1349 return MISCREG_TLBI_VAALE1IS_Xt;
1350 }
1351 break;
1352 case 7:
1353 switch (op2) {
1354 case 0:
1355 return MISCREG_TLBI_VMALLE1;
1356 case 1:
1357 return MISCREG_TLBI_VAE1_Xt;
1358 case 2:
1359 return MISCREG_TLBI_ASIDE1_Xt;
1360 case 3:
1361 return MISCREG_TLBI_VAAE1_Xt;
1362 case 5:
1363 return MISCREG_TLBI_VALE1_Xt;
1364 case 7:
1365 return MISCREG_TLBI_VAALE1_Xt;
1366 }
1367 break;
1368 }
1369 break;
1370 case 4:
1371 switch (crm) {
1372 case 0:
1373 switch (op2) {
1374 case 1:
1375 return MISCREG_TLBI_IPAS2E1IS_Xt;
1376 case 5:
1377 return MISCREG_TLBI_IPAS2LE1IS_Xt;
1378 }
1379 break;
1380 case 3:
1381 switch (op2) {
1382 case 0:
1383 return MISCREG_TLBI_ALLE2IS;
1384 case 1:
1385 return MISCREG_TLBI_VAE2IS_Xt;
1386 case 4:
1387 return MISCREG_TLBI_ALLE1IS;
1388 case 5:
1389 return MISCREG_TLBI_VALE2IS_Xt;
1390 case 6:
1391 return MISCREG_TLBI_VMALLS12E1IS;
1392 }
1393 break;
1394 case 4:
1395 switch (op2) {
1396 case 1:
1397 return MISCREG_TLBI_IPAS2E1_Xt;
1398 case 5:
1399 return MISCREG_TLBI_IPAS2LE1_Xt;
1400 }
1401 break;
1402 case 7:
1403 switch (op2) {
1404 case 0:
1405 return MISCREG_TLBI_ALLE2;
1406 case 1:
1407 return MISCREG_TLBI_VAE2_Xt;
1408 case 4:
1409 return MISCREG_TLBI_ALLE1;
1410 case 5:
1411 return MISCREG_TLBI_VALE2_Xt;
1412 case 6:
1413 return MISCREG_TLBI_VMALLS12E1;
1414 }
1415 break;
1416 }
1417 break;
1418 case 6:
1419 switch (crm) {
1420 case 3:
1421 switch (op2) {
1422 case 0:
1423 return MISCREG_TLBI_ALLE3IS;
1424 case 1:
1425 return MISCREG_TLBI_VAE3IS_Xt;
1426 case 5:
1427 return MISCREG_TLBI_VALE3IS_Xt;
1428 }
1429 break;
1430 case 7:
1431 switch (op2) {
1432 case 0:
1433 return MISCREG_TLBI_ALLE3;
1434 case 1:
1435 return MISCREG_TLBI_VAE3_Xt;
1436 case 5:
1437 return MISCREG_TLBI_VALE3_Xt;
1438 }
1439 break;
1440 }
1441 break;
1442 }
1443 break;
1444 case 11:
1445 case 15:
1446 // SYS Instruction with CRn = { 11, 15 }
1447 // (Trappable by HCR_EL2.TIDCP)
1448 return MISCREG_IMPDEF_UNIMPL;
1449 }
1450 break;
1451 case 2:
1452 switch (crn) {
1453 case 0:
1454 switch (op1) {
1455 case 0:
1456 switch (crm) {
1457 case 0:
1458 switch (op2) {
1459 case 2:
1460 return MISCREG_OSDTRRX_EL1;
1461 case 4:
1462 return MISCREG_DBGBVR0_EL1;
1463 case 5:
1464 return MISCREG_DBGBCR0_EL1;
1465 case 6:
1466 return MISCREG_DBGWVR0_EL1;
1467 case 7:
1468 return MISCREG_DBGWCR0_EL1;
1469 }
1470 break;
1471 case 1:
1472 switch (op2) {
1473 case 4:
1474 return MISCREG_DBGBVR1_EL1;
1475 case 5:
1476 return MISCREG_DBGBCR1_EL1;
1477 case 6:
1478 return MISCREG_DBGWVR1_EL1;
1479 case 7:
1480 return MISCREG_DBGWCR1_EL1;
1481 }
1482 break;
1483 case 2:
1484 switch (op2) {
1485 case 0:
1486 return MISCREG_MDCCINT_EL1;
1487 case 2:
1488 return MISCREG_MDSCR_EL1;
1489 case 4:
1490 return MISCREG_DBGBVR2_EL1;
1491 case 5:
1492 return MISCREG_DBGBCR2_EL1;
1493 case 6:
1494 return MISCREG_DBGWVR2_EL1;
1495 case 7:
1496 return MISCREG_DBGWCR2_EL1;
1497 }
1498 break;
1499 case 3:
1500 switch (op2) {
1501 case 2:
1502 return MISCREG_OSDTRTX_EL1;
1503 case 4:
1504 return MISCREG_DBGBVR3_EL1;
1505 case 5:
1506 return MISCREG_DBGBCR3_EL1;
1507 case 6:
1508 return MISCREG_DBGWVR3_EL1;
1509 case 7:
1510 return MISCREG_DBGWCR3_EL1;
1511 }
1512 break;
1513 case 4:
1514 switch (op2) {
1515 case 4:
1516 return MISCREG_DBGBVR4_EL1;
1517 case 5:
1518 return MISCREG_DBGBCR4_EL1;
1519 }
1520 break;
1521 case 5:
1522 switch (op2) {
1523 case 4:
1524 return MISCREG_DBGBVR5_EL1;
1525 case 5:
1526 return MISCREG_DBGBCR5_EL1;
1527 }
1528 break;
1529 case 6:
1530 switch (op2) {
1531 case 2:
1532 return MISCREG_OSECCR_EL1;
1533 }
1534 break;
1535 }
1536 break;
1537 case 2:
1538 switch (crm) {
1539 case 0:
1540 switch (op2) {
1541 case 0:
1542 return MISCREG_TEECR32_EL1;
1543 }
1544 break;
1545 }
1546 break;
1547 case 3:
1548 switch (crm) {
1549 case 1:
1550 switch (op2) {
1551 case 0:
1552 return MISCREG_MDCCSR_EL0;
1553 }
1554 break;
1555 case 4:
1556 switch (op2) {
1557 case 0:
1558 return MISCREG_MDDTR_EL0;
1559 }
1560 break;
1561 case 5:
1562 switch (op2) {
1563 case 0:
1564 return MISCREG_MDDTRRX_EL0;
1565 }
1566 break;
1567 }
1568 break;
1569 case 4:
1570 switch (crm) {
1571 case 7:
1572 switch (op2) {
1573 case 0:
1574 return MISCREG_DBGVCR32_EL2;
1575 }
1576 break;
1577 }
1578 break;
1579 }
1580 break;
1581 case 1:
1582 switch (op1) {
1583 case 0:
1584 switch (crm) {
1585 case 0:
1586 switch (op2) {
1587 case 0:
1588 return MISCREG_MDRAR_EL1;
1589 case 4:
1590 return MISCREG_OSLAR_EL1;
1591 }
1592 break;
1593 case 1:
1594 switch (op2) {
1595 case 4:
1596 return MISCREG_OSLSR_EL1;
1597 }
1598 break;
1599 case 3:
1600 switch (op2) {
1601 case 4:
1602 return MISCREG_OSDLR_EL1;
1603 }
1604 break;
1605 case 4:
1606 switch (op2) {
1607 case 4:
1608 return MISCREG_DBGPRCR_EL1;
1609 }
1610 break;
1611 }
1612 break;
1613 case 2:
1614 switch (crm) {
1615 case 0:
1616 switch (op2) {
1617 case 0:
1618 return MISCREG_TEEHBR32_EL1;
1619 }
1620 break;
1621 }
1622 break;
1623 }
1624 break;
1625 case 7:
1626 switch (op1) {
1627 case 0:
1628 switch (crm) {
1629 case 8:
1630 switch (op2) {
1631 case 6:
1632 return MISCREG_DBGCLAIMSET_EL1;
1633 }
1634 break;
1635 case 9:
1636 switch (op2) {
1637 case 6:
1638 return MISCREG_DBGCLAIMCLR_EL1;
1639 }
1640 break;
1641 case 14:
1642 switch (op2) {
1643 case 6:
1644 return MISCREG_DBGAUTHSTATUS_EL1;
1645 }
1646 break;
1647 }
1648 break;
1649 }
1650 break;
1651 }
1652 break;
1653 case 3:
1654 switch (crn) {
1655 case 0:
1656 switch (op1) {
1657 case 0:
1658 switch (crm) {
1659 case 0:
1660 switch (op2) {
1661 case 0:
1662 return MISCREG_MIDR_EL1;
1663 case 5:
1664 return MISCREG_MPIDR_EL1;
1665 case 6:
1666 return MISCREG_REVIDR_EL1;
1667 }
1668 break;
1669 case 1:
1670 switch (op2) {
1671 case 0:
1672 return MISCREG_ID_PFR0_EL1;
1673 case 1:
1674 return MISCREG_ID_PFR1_EL1;
1675 case 2:
1676 return MISCREG_ID_DFR0_EL1;
1677 case 3:
1678 return MISCREG_ID_AFR0_EL1;
1679 case 4:
1680 return MISCREG_ID_MMFR0_EL1;
1681 case 5:
1682 return MISCREG_ID_MMFR1_EL1;
1683 case 6:
1684 return MISCREG_ID_MMFR2_EL1;
1685 case 7:
1686 return MISCREG_ID_MMFR3_EL1;
1687 }
1688 break;
1689 case 2:
1690 switch (op2) {
1691 case 0:
1692 return MISCREG_ID_ISAR0_EL1;
1693 case 1:
1694 return MISCREG_ID_ISAR1_EL1;
1695 case 2:
1696 return MISCREG_ID_ISAR2_EL1;
1697 case 3:
1698 return MISCREG_ID_ISAR3_EL1;
1699 case 4:
1700 return MISCREG_ID_ISAR4_EL1;
1701 case 5:
1702 return MISCREG_ID_ISAR5_EL1;
1703 }
1704 break;
1705 case 3:
1706 switch (op2) {
1707 case 0:
1708 return MISCREG_MVFR0_EL1;
1709 case 1:
1710 return MISCREG_MVFR1_EL1;
1711 case 2:
1712 return MISCREG_MVFR2_EL1;
1713 case 3 ... 7:
1714 return MISCREG_RAZ;
1715 }
1716 break;
1717 case 4:
1718 switch (op2) {
1719 case 0:
1720 return MISCREG_ID_AA64PFR0_EL1;
1721 case 1:
1722 return MISCREG_ID_AA64PFR1_EL1;
1723 case 2 ... 3:
1724 return MISCREG_RAZ;
1725 case 4:
1726 return MISCREG_ID_AA64ZFR0_EL1;
1727 case 5 ... 7:
1728 return MISCREG_RAZ;
1729 }
1730 break;
1731 case 5:
1732 switch (op2) {
1733 case 0:
1734 return MISCREG_ID_AA64DFR0_EL1;
1735 case 1:
1736 return MISCREG_ID_AA64DFR1_EL1;
1737 case 4:
1738 return MISCREG_ID_AA64AFR0_EL1;
1739 case 5:
1740 return MISCREG_ID_AA64AFR1_EL1;
1741 case 2:
1742 case 3:
1743 case 6:
1744 case 7:
1745 return MISCREG_RAZ;
1746 }
1747 break;
1748 case 6:
1749 switch (op2) {
1750 case 0:
1751 return MISCREG_ID_AA64ISAR0_EL1;
1752 case 1:
1753 return MISCREG_ID_AA64ISAR1_EL1;
1754 case 2 ... 7:
1755 return MISCREG_RAZ;
1756 }
1757 break;
1758 case 7:
1759 switch (op2) {
1760 case 0:
1761 return MISCREG_ID_AA64MMFR0_EL1;
1762 case 1:
1763 return MISCREG_ID_AA64MMFR1_EL1;
1764 case 2:
1765 return MISCREG_ID_AA64MMFR2_EL1;
1766 case 3 ... 7:
1767 return MISCREG_RAZ;
1768 }
1769 break;
1770 }
1771 break;
1772 case 1:
1773 switch (crm) {
1774 case 0:
1775 switch (op2) {
1776 case 0:
1777 return MISCREG_CCSIDR_EL1;
1778 case 1:
1779 return MISCREG_CLIDR_EL1;
1780 case 7:
1781 return MISCREG_AIDR_EL1;
1782 }
1783 break;
1784 }
1785 break;
1786 case 2:
1787 switch (crm) {
1788 case 0:
1789 switch (op2) {
1790 case 0:
1791 return MISCREG_CSSELR_EL1;
1792 }
1793 break;
1794 }
1795 break;
1796 case 3:
1797 switch (crm) {
1798 case 0:
1799 switch (op2) {
1800 case 1:
1801 return MISCREG_CTR_EL0;
1802 case 7:
1803 return MISCREG_DCZID_EL0;
1804 }
1805 break;
1806 }
1807 break;
1808 case 4:
1809 switch (crm) {
1810 case 0:
1811 switch (op2) {
1812 case 0:
1813 return MISCREG_VPIDR_EL2;
1814 case 5:
1815 return MISCREG_VMPIDR_EL2;
1816 }
1817 break;
1818 }
1819 break;
1820 }
1821 break;
1822 case 1:
1823 switch (op1) {
1824 case 0:
1825 switch (crm) {
1826 case 0:
1827 switch (op2) {
1828 case 0:
1829 return MISCREG_SCTLR_EL1;
1830 case 1:
1831 return MISCREG_ACTLR_EL1;
1832 case 2:
1833 return MISCREG_CPACR_EL1;
1834 }
1835 break;
1836 case 2:
1837 switch (op2) {
1838 case 0:
1839 return MISCREG_ZCR_EL1;
1840 }
1841 break;
1842 }
1843 break;
1844 case 4:
1845 switch (crm) {
1846 case 0:
1847 switch (op2) {
1848 case 0:
1849 return MISCREG_SCTLR_EL2;
1850 case 1:
1851 return MISCREG_ACTLR_EL2;
1852 }
1853 break;
1854 case 1:
1855 switch (op2) {
1856 case 0:
1857 return MISCREG_HCR_EL2;
1858 case 1:
1859 return MISCREG_MDCR_EL2;
1860 case 2:
1861 return MISCREG_CPTR_EL2;
1862 case 3:
1863 return MISCREG_HSTR_EL2;
1864 case 7:
1865 return MISCREG_HACR_EL2;
1866 }
1867 break;
1868 case 2:
1869 switch (op2) {
1870 case 0:
1871 return MISCREG_ZCR_EL2;
1872 }
1873 break;
1874 }
1875 break;
1876 case 5:
1877 switch (crm) {
1878 case 2:
1879 switch (op2) {
1880 case 0:
1881 return MISCREG_ZCR_EL12;
1882 }
1883 break;
1884 }
1885 break;
1886 case 6:
1887 switch (crm) {
1888 case 0:
1889 switch (op2) {
1890 case 0:
1891 return MISCREG_SCTLR_EL3;
1892 case 1:
1893 return MISCREG_ACTLR_EL3;
1894 }
1895 break;
1896 case 1:
1897 switch (op2) {
1898 case 0:
1899 return MISCREG_SCR_EL3;
1900 case 1:
1901 return MISCREG_SDER32_EL3;
1902 case 2:
1903 return MISCREG_CPTR_EL3;
1904 }
1905 break;
1906 case 2:
1907 switch (op2) {
1908 case 0:
1909 return MISCREG_ZCR_EL3;
1910 }
1911 break;
1912 case 3:
1913 switch (op2) {
1914 case 1:
1915 return MISCREG_MDCR_EL3;
1916 }
1917 break;
1918 }
1919 break;
1920 }
1921 break;
1922 case 2:
1923 switch (op1) {
1924 case 0:
1925 switch (crm) {
1926 case 0:
1927 switch (op2) {
1928 case 0:
1929 return MISCREG_TTBR0_EL1;
1930 case 1:
1931 return MISCREG_TTBR1_EL1;
1932 case 2:
1933 return MISCREG_TCR_EL1;
1934 }
1935 break;
1936 case 0x1:
1937 switch (op2) {
1938 case 0x0:
1939 return MISCREG_APIAKeyLo_EL1;
1940 case 0x1:
1941 return MISCREG_APIAKeyHi_EL1;
1942 case 0x2:
1943 return MISCREG_APIBKeyLo_EL1;
1944 case 0x3:
1945 return MISCREG_APIBKeyHi_EL1;
1946 }
1947 break;
1948 case 0x2:
1949 switch (op2) {
1950 case 0x0:
1951 return MISCREG_APDAKeyLo_EL1;
1952 case 0x1:
1953 return MISCREG_APDAKeyHi_EL1;
1954 case 0x2:
1955 return MISCREG_APDBKeyLo_EL1;
1956 case 0x3:
1957 return MISCREG_APDBKeyHi_EL1;
1958 }
1959 break;
1960
1961 case 0x3:
1962 switch (op2) {
1963 case 0x0:
1964 return MISCREG_APGAKeyLo_EL1;
1965 case 0x1:
1966 return MISCREG_APGAKeyHi_EL1;
1967 }
1968 break;
1969 }
1970 break;
1971 case 4:
1972 switch (crm) {
1973 case 0:
1974 switch (op2) {
1975 case 0:
1976 return MISCREG_TTBR0_EL2;
1977 case 1:
1978 return MISCREG_TTBR1_EL2;
1979 case 2:
1980 return MISCREG_TCR_EL2;
1981 }
1982 break;
1983 case 1:
1984 switch (op2) {
1985 case 0:
1986 return MISCREG_VTTBR_EL2;
1987 case 2:
1988 return MISCREG_VTCR_EL2;
1989 }
1990 break;
1991 }
1992 break;
1993 case 6:
1994 switch (crm) {
1995 case 0:
1996 switch (op2) {
1997 case 0:
1998 return MISCREG_TTBR0_EL3;
1999 case 2:
2000 return MISCREG_TCR_EL3;
2001 }
2002 break;
2003 }
2004 break;
2005 }
2006 break;
2007 case 3:
2008 switch (op1) {
2009 case 4:
2010 switch (crm) {
2011 case 0:
2012 switch (op2) {
2013 case 0:
2014 return MISCREG_DACR32_EL2;
2015 }
2016 break;
2017 }
2018 break;
2019 }
2020 break;
2021 case 4:
2022 switch (op1) {
2023 case 0:
2024 switch (crm) {
2025 case 0:
2026 switch (op2) {
2027 case 0:
2028 return MISCREG_SPSR_EL1;
2029 case 1:
2030 return MISCREG_ELR_EL1;
2031 }
2032 break;
2033 case 1:
2034 switch (op2) {
2035 case 0:
2036 return MISCREG_SP_EL0;
2037 }
2038 break;
2039 case 2:
2040 switch (op2) {
2041 case 0:
2042 return MISCREG_SPSEL;
2043 case 2:
2044 return MISCREG_CURRENTEL;
2045 case 3:
2046 return MISCREG_PAN;
2047 }
2048 break;
2049 case 6:
2050 switch (op2) {
2051 case 0:
2052 return MISCREG_ICC_PMR_EL1;
2053 }
2054 break;
2055 }
2056 break;
2057 case 3:
2058 switch (crm) {
2059 case 2:
2060 switch (op2) {
2061 case 0:
2062 return MISCREG_NZCV;
2063 case 1:
2064 return MISCREG_DAIF;
2065 }
2066 break;
2067 case 4:
2068 switch (op2) {
2069 case 0:
2070 return MISCREG_FPCR;
2071 case 1:
2072 return MISCREG_FPSR;
2073 }
2074 break;
2075 case 5:
2076 switch (op2) {
2077 case 0:
2078 return MISCREG_DSPSR_EL0;
2079 case 1:
2080 return MISCREG_DLR_EL0;
2081 }
2082 break;
2083 }
2084 break;
2085 case 4:
2086 switch (crm) {
2087 case 0:
2088 switch (op2) {
2089 case 0:
2090 return MISCREG_SPSR_EL2;
2091 case 1:
2092 return MISCREG_ELR_EL2;
2093 }
2094 break;
2095 case 1:
2096 switch (op2) {
2097 case 0:
2098 return MISCREG_SP_EL1;
2099 }
2100 break;
2101 case 3:
2102 switch (op2) {
2103 case 0:
2104 return MISCREG_SPSR_IRQ_AA64;
2105 case 1:
2106 return MISCREG_SPSR_ABT_AA64;
2107 case 2:
2108 return MISCREG_SPSR_UND_AA64;
2109 case 3:
2110 return MISCREG_SPSR_FIQ_AA64;
2111 }
2112 break;
2113 }
2114 break;
2115 case 6:
2116 switch (crm) {
2117 case 0:
2118 switch (op2) {
2119 case 0:
2120 return MISCREG_SPSR_EL3;
2121 case 1:
2122 return MISCREG_ELR_EL3;
2123 }
2124 break;
2125 case 1:
2126 switch (op2) {
2127 case 0:
2128 return MISCREG_SP_EL2;
2129 }
2130 break;
2131 }
2132 break;
2133 }
2134 break;
2135 case 5:
2136 switch (op1) {
2137 case 0:
2138 switch (crm) {
2139 case 1:
2140 switch (op2) {
2141 case 0:
2142 return MISCREG_AFSR0_EL1;
2143 case 1:
2144 return MISCREG_AFSR1_EL1;
2145 }
2146 break;
2147 case 2:
2148 switch (op2) {
2149 case 0:
2150 return MISCREG_ESR_EL1;
2151 }
2152 break;
2153 case 3:
2154 switch (op2) {
2155 case 0:
2156 return MISCREG_ERRIDR_EL1;
2157 case 1:
2158 return MISCREG_ERRSELR_EL1;
2159 }
2160 break;
2161 case 4:
2162 switch (op2) {
2163 case 0:
2164 return MISCREG_ERXFR_EL1;
2165 case 1:
2166 return MISCREG_ERXCTLR_EL1;
2167 case 2:
2168 return MISCREG_ERXSTATUS_EL1;
2169 case 3:
2170 return MISCREG_ERXADDR_EL1;
2171 }
2172 break;
2173 case 5:
2174 switch (op2) {
2175 case 0:
2176 return MISCREG_ERXMISC0_EL1;
2177 case 1:
2178 return MISCREG_ERXMISC1_EL1;
2179 }
2180 break;
2181 }
2182 break;
2183 case 4:
2184 switch (crm) {
2185 case 0:
2186 switch (op2) {
2187 case 1:
2188 return MISCREG_IFSR32_EL2;
2189 }
2190 break;
2191 case 1:
2192 switch (op2) {
2193 case 0:
2194 return MISCREG_AFSR0_EL2;
2195 case 1:
2196 return MISCREG_AFSR1_EL2;
2197 }
2198 break;
2199 case 2:
2200 switch (op2) {
2201 case 0:
2202 return MISCREG_ESR_EL2;
2203 case 3:
2204 return MISCREG_VSESR_EL2;
2205 }
2206 break;
2207 case 3:
2208 switch (op2) {
2209 case 0:
2210 return MISCREG_FPEXC32_EL2;
2211 }
2212 break;
2213 }
2214 break;
2215 case 6:
2216 switch (crm) {
2217 case 1:
2218 switch (op2) {
2219 case 0:
2220 return MISCREG_AFSR0_EL3;
2221 case 1:
2222 return MISCREG_AFSR1_EL3;
2223 }
2224 break;
2225 case 2:
2226 switch (op2) {
2227 case 0:
2228 return MISCREG_ESR_EL3;
2229 }
2230 break;
2231 }
2232 break;
2233 }
2234 break;
2235 case 6:
2236 switch (op1) {
2237 case 0:
2238 switch (crm) {
2239 case 0:
2240 switch (op2) {
2241 case 0:
2242 return MISCREG_FAR_EL1;
2243 }
2244 break;
2245 }
2246 break;
2247 case 4:
2248 switch (crm) {
2249 case 0:
2250 switch (op2) {
2251 case 0:
2252 return MISCREG_FAR_EL2;
2253 case 4:
2254 return MISCREG_HPFAR_EL2;
2255 }
2256 break;
2257 }
2258 break;
2259 case 6:
2260 switch (crm) {
2261 case 0:
2262 switch (op2) {
2263 case 0:
2264 return MISCREG_FAR_EL3;
2265 }
2266 break;
2267 }
2268 break;
2269 }
2270 break;
2271 case 7:
2272 switch (op1) {
2273 case 0:
2274 switch (crm) {
2275 case 4:
2276 switch (op2) {
2277 case 0:
2278 return MISCREG_PAR_EL1;
2279 }
2280 break;
2281 }
2282 break;
2283 }
2284 break;
2285 case 9:
2286 switch (op1) {
2287 case 0:
2288 switch (crm) {
2289 case 14:
2290 switch (op2) {
2291 case 1:
2292 return MISCREG_PMINTENSET_EL1;
2293 case 2:
2294 return MISCREG_PMINTENCLR_EL1;
2295 }
2296 break;
2297 }
2298 break;
2299 case 3:
2300 switch (crm) {
2301 case 12:
2302 switch (op2) {
2303 case 0:
2304 return MISCREG_PMCR_EL0;
2305 case 1:
2306 return MISCREG_PMCNTENSET_EL0;
2307 case 2:
2308 return MISCREG_PMCNTENCLR_EL0;
2309 case 3:
2310 return MISCREG_PMOVSCLR_EL0;
2311 case 4:
2312 return MISCREG_PMSWINC_EL0;
2313 case 5:
2314 return MISCREG_PMSELR_EL0;
2315 case 6:
2316 return MISCREG_PMCEID0_EL0;
2317 case 7:
2318 return MISCREG_PMCEID1_EL0;
2319 }
2320 break;
2321 case 13:
2322 switch (op2) {
2323 case 0:
2324 return MISCREG_PMCCNTR_EL0;
2325 case 1:
2326 return MISCREG_PMXEVTYPER_EL0;
2327 case 2:
2328 return MISCREG_PMXEVCNTR_EL0;
2329 }
2330 break;
2331 case 14:
2332 switch (op2) {
2333 case 0:
2334 return MISCREG_PMUSERENR_EL0;
2335 case 3:
2336 return MISCREG_PMOVSSET_EL0;
2337 }
2338 break;
2339 }
2340 break;
2341 }
2342 break;
2343 case 10:
2344 switch (op1) {
2345 case 0:
2346 switch (crm) {
2347 case 2:
2348 switch (op2) {
2349 case 0:
2350 return MISCREG_MAIR_EL1;
2351 }
2352 break;
2353 case 3:
2354 switch (op2) {
2355 case 0:
2356 return MISCREG_AMAIR_EL1;
2357 }
2358 break;
2359 }
2360 break;
2361 case 4:
2362 switch (crm) {
2363 case 2:
2364 switch (op2) {
2365 case 0:
2366 return MISCREG_MAIR_EL2;
2367 }
2368 break;
2369 case 3:
2370 switch (op2) {
2371 case 0:
2372 return MISCREG_AMAIR_EL2;
2373 }
2374 break;
2375 }
2376 break;
2377 case 6:
2378 switch (crm) {
2379 case 2:
2380 switch (op2) {
2381 case 0:
2382 return MISCREG_MAIR_EL3;
2383 }
2384 break;
2385 case 3:
2386 switch (op2) {
2387 case 0:
2388 return MISCREG_AMAIR_EL3;
2389 }
2390 break;
2391 }
2392 break;
2393 }
2394 break;
2395 case 11:
2396 switch (op1) {
2397 case 1:
2398 switch (crm) {
2399 case 0:
2400 switch (op2) {
2401 case 2:
2402 return MISCREG_L2CTLR_EL1;
2403 case 3:
2404 return MISCREG_L2ECTLR_EL1;
2405 }
2406 break;
2407 }
2408 M5_FALLTHROUGH;
2409 default:
2410 // S3_<op1>_11_<Cm>_<op2>
2411 return MISCREG_IMPDEF_UNIMPL;
2412 }
2413 M5_UNREACHABLE;
2414 case 12:
2415 switch (op1) {
2416 case 0:
2417 switch (crm) {
2418 case 0:
2419 switch (op2) {
2420 case 0:
2421 return MISCREG_VBAR_EL1;
2422 case 1:
2423 return MISCREG_RVBAR_EL1;
2424 }
2425 break;
2426 case 1:
2427 switch (op2) {
2428 case 0:
2429 return MISCREG_ISR_EL1;
2430 case 1:
2431 return MISCREG_DISR_EL1;
2432 }
2433 break;
2434 case 8:
2435 switch (op2) {
2436 case 0:
2437 return MISCREG_ICC_IAR0_EL1;
2438 case 1:
2439 return MISCREG_ICC_EOIR0_EL1;
2440 case 2:
2441 return MISCREG_ICC_HPPIR0_EL1;
2442 case 3:
2443 return MISCREG_ICC_BPR0_EL1;
2444 case 4:
2445 return MISCREG_ICC_AP0R0_EL1;
2446 case 5:
2447 return MISCREG_ICC_AP0R1_EL1;
2448 case 6:
2449 return MISCREG_ICC_AP0R2_EL1;
2450 case 7:
2451 return MISCREG_ICC_AP0R3_EL1;
2452 }
2453 break;
2454 case 9:
2455 switch (op2) {
2456 case 0:
2457 return MISCREG_ICC_AP1R0_EL1;
2458 case 1:
2459 return MISCREG_ICC_AP1R1_EL1;
2460 case 2:
2461 return MISCREG_ICC_AP1R2_EL1;
2462 case 3:
2463 return MISCREG_ICC_AP1R3_EL1;
2464 }
2465 break;
2466 case 11:
2467 switch (op2) {
2468 case 1:
2469 return MISCREG_ICC_DIR_EL1;
2470 case 3:
2471 return MISCREG_ICC_RPR_EL1;
2472 case 5:
2473 return MISCREG_ICC_SGI1R_EL1;
2474 case 6:
2475 return MISCREG_ICC_ASGI1R_EL1;
2476 case 7:
2477 return MISCREG_ICC_SGI0R_EL1;
2478 }
2479 break;
2480 case 12:
2481 switch (op2) {
2482 case 0:
2483 return MISCREG_ICC_IAR1_EL1;
2484 case 1:
2485 return MISCREG_ICC_EOIR1_EL1;
2486 case 2:
2487 return MISCREG_ICC_HPPIR1_EL1;
2488 case 3:
2489 return MISCREG_ICC_BPR1_EL1;
2490 case 4:
2491 return MISCREG_ICC_CTLR_EL1;
2492 case 5:
2493 return MISCREG_ICC_SRE_EL1;
2494 case 6:
2495 return MISCREG_ICC_IGRPEN0_EL1;
2496 case 7:
2497 return MISCREG_ICC_IGRPEN1_EL1;
2498 }
2499 break;
2500 }
2501 break;
2502 case 4:
2503 switch (crm) {
2504 case 0:
2505 switch (op2) {
2506 case 0:
2507 return MISCREG_VBAR_EL2;
2508 case 1:
2509 return MISCREG_RVBAR_EL2;
2510 }
2511 break;
2512 case 1:
2513 switch (op2) {
2514 case 1:
2515 return MISCREG_VDISR_EL2;
2516 }
2517 break;
2518 case 8:
2519 switch (op2) {
2520 case 0:
2521 return MISCREG_ICH_AP0R0_EL2;
2522 case 1:
2523 return MISCREG_ICH_AP0R1_EL2;
2524 case 2:
2525 return MISCREG_ICH_AP0R2_EL2;
2526 case 3:
2527 return MISCREG_ICH_AP0R3_EL2;
2528 }
2529 break;
2530 case 9:
2531 switch (op2) {
2532 case 0:
2533 return MISCREG_ICH_AP1R0_EL2;
2534 case 1:
2535 return MISCREG_ICH_AP1R1_EL2;
2536 case 2:
2537 return MISCREG_ICH_AP1R2_EL2;
2538 case 3:
2539 return MISCREG_ICH_AP1R3_EL2;
2540 case 5:
2541 return MISCREG_ICC_SRE_EL2;
2542 }
2543 break;
2544 case 11:
2545 switch (op2) {
2546 case 0:
2547 return MISCREG_ICH_HCR_EL2;
2548 case 1:
2549 return MISCREG_ICH_VTR_EL2;
2550 case 2:
2551 return MISCREG_ICH_MISR_EL2;
2552 case 3:
2553 return MISCREG_ICH_EISR_EL2;
2554 case 5:
2555 return MISCREG_ICH_ELRSR_EL2;
2556 case 7:
2557 return MISCREG_ICH_VMCR_EL2;
2558 }
2559 break;
2560 case 12:
2561 switch (op2) {
2562 case 0:
2563 return MISCREG_ICH_LR0_EL2;
2564 case 1:
2565 return MISCREG_ICH_LR1_EL2;
2566 case 2:
2567 return MISCREG_ICH_LR2_EL2;
2568 case 3:
2569 return MISCREG_ICH_LR3_EL2;
2570 case 4:
2571 return MISCREG_ICH_LR4_EL2;
2572 case 5:
2573 return MISCREG_ICH_LR5_EL2;
2574 case 6:
2575 return MISCREG_ICH_LR6_EL2;
2576 case 7:
2577 return MISCREG_ICH_LR7_EL2;
2578 }
2579 break;
2580 case 13:
2581 switch (op2) {
2582 case 0:
2583 return MISCREG_ICH_LR8_EL2;
2584 case 1:
2585 return MISCREG_ICH_LR9_EL2;
2586 case 2:
2587 return MISCREG_ICH_LR10_EL2;
2588 case 3:
2589 return MISCREG_ICH_LR11_EL2;
2590 case 4:
2591 return MISCREG_ICH_LR12_EL2;
2592 case 5:
2593 return MISCREG_ICH_LR13_EL2;
2594 case 6:
2595 return MISCREG_ICH_LR14_EL2;
2596 case 7:
2597 return MISCREG_ICH_LR15_EL2;
2598 }
2599 break;
2600 }
2601 break;
2602 case 6:
2603 switch (crm) {
2604 case 0:
2605 switch (op2) {
2606 case 0:
2607 return MISCREG_VBAR_EL3;
2608 case 1:
2609 return MISCREG_RVBAR_EL3;
2610 case 2:
2611 return MISCREG_RMR_EL3;
2612 }
2613 break;
2614 case 12:
2615 switch (op2) {
2616 case 4:
2617 return MISCREG_ICC_CTLR_EL3;
2618 case 5:
2619 return MISCREG_ICC_SRE_EL3;
2620 case 7:
2621 return MISCREG_ICC_IGRPEN1_EL3;
2622 }
2623 break;
2624 }
2625 break;
2626 }
2627 break;
2628 case 13:
2629 switch (op1) {
2630 case 0:
2631 switch (crm) {
2632 case 0:
2633 switch (op2) {
2634 case 1:
2635 return MISCREG_CONTEXTIDR_EL1;
2636 case 4:
2637 return MISCREG_TPIDR_EL1;
2638 }
2639 break;
2640 }
2641 break;
2642 case 3:
2643 switch (crm) {
2644 case 0:
2645 switch (op2) {
2646 case 2:
2647 return MISCREG_TPIDR_EL0;
2648 case 3:
2649 return MISCREG_TPIDRRO_EL0;
2650 }
2651 break;
2652 }
2653 break;
2654 case 4:
2655 switch (crm) {
2656 case 0:
2657 switch (op2) {
2658 case 1:
2659 return MISCREG_CONTEXTIDR_EL2;
2660 case 2:
2661 return MISCREG_TPIDR_EL2;
2662 }
2663 break;
2664 }
2665 break;
2666 case 6:
2667 switch (crm) {
2668 case 0:
2669 switch (op2) {
2670 case 2:
2671 return MISCREG_TPIDR_EL3;
2672 }
2673 break;
2674 }
2675 break;
2676 }
2677 break;
2678 case 14:
2679 switch (op1) {
2680 case 0:
2681 switch (crm) {
2682 case 1:
2683 switch (op2) {
2684 case 0:
2685 return MISCREG_CNTKCTL_EL1;
2686 }
2687 break;
2688 }
2689 break;
2690 case 3:
2691 switch (crm) {
2692 case 0:
2693 switch (op2) {
2694 case 0:
2695 return MISCREG_CNTFRQ_EL0;
2696 case 1:
2697 return MISCREG_CNTPCT_EL0;
2698 case 2:
2699 return MISCREG_CNTVCT_EL0;
2700 }
2701 break;
2702 case 2:
2703 switch (op2) {
2704 case 0:
2705 return MISCREG_CNTP_TVAL_EL0;
2706 case 1:
2707 return MISCREG_CNTP_CTL_EL0;
2708 case 2:
2709 return MISCREG_CNTP_CVAL_EL0;
2710 }
2711 break;
2712 case 3:
2713 switch (op2) {
2714 case 0:
2715 return MISCREG_CNTV_TVAL_EL0;
2716 case 1:
2717 return MISCREG_CNTV_CTL_EL0;
2718 case 2:
2719 return MISCREG_CNTV_CVAL_EL0;
2720 }
2721 break;
2722 case 8:
2723 switch (op2) {
2724 case 0:
2725 return MISCREG_PMEVCNTR0_EL0;
2726 case 1:
2727 return MISCREG_PMEVCNTR1_EL0;
2728 case 2:
2729 return MISCREG_PMEVCNTR2_EL0;
2730 case 3:
2731 return MISCREG_PMEVCNTR3_EL0;
2732 case 4:
2733 return MISCREG_PMEVCNTR4_EL0;
2734 case 5:
2735 return MISCREG_PMEVCNTR5_EL0;
2736 }
2737 break;
2738 case 12:
2739 switch (op2) {
2740 case 0:
2741 return MISCREG_PMEVTYPER0_EL0;
2742 case 1:
2743 return MISCREG_PMEVTYPER1_EL0;
2744 case 2:
2745 return MISCREG_PMEVTYPER2_EL0;
2746 case 3:
2747 return MISCREG_PMEVTYPER3_EL0;
2748 case 4:
2749 return MISCREG_PMEVTYPER4_EL0;
2750 case 5:
2751 return MISCREG_PMEVTYPER5_EL0;
2752 }
2753 break;
2754 case 15:
2755 switch (op2) {
2756 case 7:
2757 return MISCREG_PMCCFILTR_EL0;
2758 }
2759 }
2760 break;
2761 case 4:
2762 switch (crm) {
2763 case 0:
2764 switch (op2) {
2765 case 3:
2766 return MISCREG_CNTVOFF_EL2;
2767 }
2768 break;
2769 case 1:
2770 switch (op2) {
2771 case 0:
2772 return MISCREG_CNTHCTL_EL2;
2773 }
2774 break;
2775 case 2:
2776 switch (op2) {
2777 case 0:
2778 return MISCREG_CNTHP_TVAL_EL2;
2779 case 1:
2780 return MISCREG_CNTHP_CTL_EL2;
2781 case 2:
2782 return MISCREG_CNTHP_CVAL_EL2;
2783 }
2784 break;
2785 case 3:
2786 switch (op2) {
2787 case 0:
2788 return MISCREG_CNTHV_TVAL_EL2;
2789 case 1:
2790 return MISCREG_CNTHV_CTL_EL2;
2791 case 2:
2792 return MISCREG_CNTHV_CVAL_EL2;
2793 }
2794 break;
2795 }
2796 break;
2797 case 7:
2798 switch (crm) {
2799 case 2:
2800 switch (op2) {
2801 case 0:
2802 return MISCREG_CNTPS_TVAL_EL1;
2803 case 1:
2804 return MISCREG_CNTPS_CTL_EL1;
2805 case 2:
2806 return MISCREG_CNTPS_CVAL_EL1;
2807 }
2808 break;
2809 }
2810 break;
2811 }
2812 break;
2813 case 15:
2814 switch (op1) {
2815 case 0:
2816 switch (crm) {
2817 case 0:
2818 switch (op2) {
2819 case 0:
2820 return MISCREG_IL1DATA0_EL1;
2821 case 1:
2822 return MISCREG_IL1DATA1_EL1;
2823 case 2:
2824 return MISCREG_IL1DATA2_EL1;
2825 case 3:
2826 return MISCREG_IL1DATA3_EL1;
2827 }
2828 break;
2829 case 1:
2830 switch (op2) {
2831 case 0:
2832 return MISCREG_DL1DATA0_EL1;
2833 case 1:
2834 return MISCREG_DL1DATA1_EL1;
2835 case 2:
2836 return MISCREG_DL1DATA2_EL1;
2837 case 3:
2838 return MISCREG_DL1DATA3_EL1;
2839 case 4:
2840 return MISCREG_DL1DATA4_EL1;
2841 }
2842 break;
2843 }
2844 break;
2845 case 1:
2846 switch (crm) {
2847 case 0:
2848 switch (op2) {
2849 case 0:
2850 return MISCREG_L2ACTLR_EL1;
2851 }
2852 break;
2853 case 2:
2854 switch (op2) {
2855 case 0:
2856 return MISCREG_CPUACTLR_EL1;
2857 case 1:
2858 return MISCREG_CPUECTLR_EL1;
2859 case 2:
2860 return MISCREG_CPUMERRSR_EL1;
2861 case 3:
2862 return MISCREG_L2MERRSR_EL1;
2863 }
2864 break;
2865 case 3:
2866 switch (op2) {
2867 case 0:
2868 return MISCREG_CBAR_EL1;
2869
2870 }
2871 break;
2872 }
2873 break;
2874 }
2875 // S3_<op1>_15_<Cm>_<op2>
2876 return MISCREG_IMPDEF_UNIMPL;
2877 }
2878 break;
2879 }
2880
2881 return MISCREG_UNKNOWN;
2882 }
2883
2884 bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below
2885
2886 void
2887 ISA::initializeMiscRegMetadata()
2888 {
2889 // the MiscReg metadata tables are shared across all instances of the
2890 // ISA object, so there's no need to initialize them multiple times.
2891 static bool completed = false;
2892 if (completed)
2893 return;
2894
2895 // This boolean variable specifies if the system is running in aarch32 at
2896 // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
2897 // is running in aarch64 (aarch32EL3 = false)
2898 bool aarch32EL3 = haveSecurity && !highestELIs64;
2899
2900 // Set Privileged Access Never on taking an exception to EL1 (Arm 8.1+),
2901 // unsupported
2902 bool SPAN = false;
2903
2904 // Implicit error synchronization event enable (Arm 8.2+), unsupported
2905 bool IESB = false;
2906
2907 // Load Multiple and Store Multiple Atomicity and Ordering (Arm 8.2+),
2908 // unsupported
2909 bool LSMAOE = false;
2910
2911 // No Trap Load Multiple and Store Multiple (Arm 8.2+), unsupported
2912 bool nTLSMD = false;
2913
2914 // Pointer authentication (Arm 8.3+), unsupported
2915 bool EnDA = true; // using APDAKey_EL1 key of instr addrs in ELs 0,1
2916 bool EnDB = true; // using APDBKey_EL1 key of instr addrs in ELs 0,1
2917 bool EnIA = true; // using APIAKey_EL1 key of instr addrs in ELs 0,1
2918 bool EnIB = true; // using APIBKey_EL1 key of instr addrs in ELs 0,1
2919
2920 /**
2921 * Some registers alias with others, and therefore need to be translated.
2922 * When two mapping registers are given, they are the 32b lower and
2923 * upper halves, respectively, of the 64b register being mapped.
2924 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
2925 *
2926 * NAM = "not architecturally mandated",
2927 * from ARM DDI 0487A.i, template text
2928 * "AArch64 System register ___ can be mapped to
2929 * AArch32 System register ___, but this is not
2930 * architecturally mandated."
2931 */
2932
2933 InitReg(MISCREG_CPSR)
2934 .allPrivileges();
2935 InitReg(MISCREG_SPSR)
2936 .allPrivileges();
2937 InitReg(MISCREG_SPSR_FIQ)
2938 .allPrivileges();
2939 InitReg(MISCREG_SPSR_IRQ)
2940 .allPrivileges();
2941 InitReg(MISCREG_SPSR_SVC)
2942 .allPrivileges();
2943 InitReg(MISCREG_SPSR_MON)
2944 .allPrivileges();
2945 InitReg(MISCREG_SPSR_ABT)
2946 .allPrivileges();
2947 InitReg(MISCREG_SPSR_HYP)
2948 .allPrivileges();
2949 InitReg(MISCREG_SPSR_UND)
2950 .allPrivileges();
2951 InitReg(MISCREG_ELR_HYP)
2952 .allPrivileges();
2953 InitReg(MISCREG_FPSID)
2954 .allPrivileges();
2955 InitReg(MISCREG_FPSCR)
2956 .allPrivileges();
2957 InitReg(MISCREG_MVFR1)
2958 .allPrivileges();
2959 InitReg(MISCREG_MVFR0)
2960 .allPrivileges();
2961 InitReg(MISCREG_FPEXC)
2962 .allPrivileges();
2963
2964 // Helper registers
2965 InitReg(MISCREG_CPSR_MODE)
2966 .allPrivileges();
2967 InitReg(MISCREG_CPSR_Q)
2968 .allPrivileges();
2969 InitReg(MISCREG_FPSCR_EXC)
2970 .allPrivileges();
2971 InitReg(MISCREG_FPSCR_QC)
2972 .allPrivileges();
2973 InitReg(MISCREG_LOCKADDR)
2974 .allPrivileges();
2975 InitReg(MISCREG_LOCKFLAG)
2976 .allPrivileges();
2977 InitReg(MISCREG_PRRR_MAIR0)
2978 .mutex()
2979 .banked();
2980 InitReg(MISCREG_PRRR_MAIR0_NS)
2981 .mutex()
2982 .privSecure(!aarch32EL3)
2983 .bankedChild();
2984 InitReg(MISCREG_PRRR_MAIR0_S)
2985 .mutex()
2986 .bankedChild();
2987 InitReg(MISCREG_NMRR_MAIR1)
2988 .mutex()
2989 .banked();
2990 InitReg(MISCREG_NMRR_MAIR1_NS)
2991 .mutex()
2992 .privSecure(!aarch32EL3)
2993 .bankedChild();
2994 InitReg(MISCREG_NMRR_MAIR1_S)
2995 .mutex()
2996 .bankedChild();
2997 InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
2998 .mutex();
2999 InitReg(MISCREG_SCTLR_RST)
3000 .allPrivileges();
3001 InitReg(MISCREG_SEV_MAILBOX)
3002 .allPrivileges();
3003
3004 // AArch32 CP14 registers
3005 InitReg(MISCREG_DBGDIDR)
3006 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3007 InitReg(MISCREG_DBGDSCRint)
3008 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3009 InitReg(MISCREG_DBGDCCINT)
3010 .unimplemented()
3011 .allPrivileges();
3012 InitReg(MISCREG_DBGDTRTXint)
3013 .unimplemented()
3014 .allPrivileges();
3015 InitReg(MISCREG_DBGDTRRXint)
3016 .unimplemented()
3017 .allPrivileges();
3018 InitReg(MISCREG_DBGWFAR)
3019 .unimplemented()
3020 .allPrivileges();
3021 InitReg(MISCREG_DBGVCR)
3022 .unimplemented()
3023 .allPrivileges();
3024 InitReg(MISCREG_DBGDTRRXext)
3025 .unimplemented()
3026 .allPrivileges();
3027 InitReg(MISCREG_DBGDSCRext)
3028 .unimplemented()
3029 .warnNotFail()
3030 .allPrivileges();
3031 InitReg(MISCREG_DBGDTRTXext)
3032 .unimplemented()
3033 .allPrivileges();
3034 InitReg(MISCREG_DBGOSECCR)
3035 .unimplemented()
3036 .allPrivileges();
3037 InitReg(MISCREG_DBGBVR0)
3038 .unimplemented()
3039 .allPrivileges();
3040 InitReg(MISCREG_DBGBVR1)
3041 .unimplemented()
3042 .allPrivileges();
3043 InitReg(MISCREG_DBGBVR2)
3044 .unimplemented()
3045 .allPrivileges();
3046 InitReg(MISCREG_DBGBVR3)
3047 .unimplemented()
3048 .allPrivileges();
3049 InitReg(MISCREG_DBGBVR4)
3050 .unimplemented()
3051 .allPrivileges();
3052 InitReg(MISCREG_DBGBVR5)
3053 .unimplemented()
3054 .allPrivileges();
3055 InitReg(MISCREG_DBGBCR0)
3056 .unimplemented()
3057 .allPrivileges();
3058 InitReg(MISCREG_DBGBCR1)
3059 .unimplemented()
3060 .allPrivileges();
3061 InitReg(MISCREG_DBGBCR2)
3062 .unimplemented()
3063 .allPrivileges();
3064 InitReg(MISCREG_DBGBCR3)
3065 .unimplemented()
3066 .allPrivileges();
3067 InitReg(MISCREG_DBGBCR4)
3068 .unimplemented()
3069 .allPrivileges();
3070 InitReg(MISCREG_DBGBCR5)
3071 .unimplemented()
3072 .allPrivileges();
3073 InitReg(MISCREG_DBGWVR0)
3074 .unimplemented()
3075 .allPrivileges();
3076 InitReg(MISCREG_DBGWVR1)
3077 .unimplemented()
3078 .allPrivileges();
3079 InitReg(MISCREG_DBGWVR2)
3080 .unimplemented()
3081 .allPrivileges();
3082 InitReg(MISCREG_DBGWVR3)
3083 .unimplemented()
3084 .allPrivileges();
3085 InitReg(MISCREG_DBGWCR0)
3086 .unimplemented()
3087 .allPrivileges();
3088 InitReg(MISCREG_DBGWCR1)
3089 .unimplemented()
3090 .allPrivileges();
3091 InitReg(MISCREG_DBGWCR2)
3092 .unimplemented()
3093 .allPrivileges();
3094 InitReg(MISCREG_DBGWCR3)
3095 .unimplemented()
3096 .allPrivileges();
3097 InitReg(MISCREG_DBGDRAR)
3098 .unimplemented()
3099 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3100 InitReg(MISCREG_DBGBXVR4)
3101 .unimplemented()
3102 .allPrivileges();
3103 InitReg(MISCREG_DBGBXVR5)
3104 .unimplemented()
3105 .allPrivileges();
3106 InitReg(MISCREG_DBGOSLAR)
3107 .unimplemented()
3108 .allPrivileges().monSecureRead(0).monNonSecureRead(0);
3109 InitReg(MISCREG_DBGOSLSR)
3110 .unimplemented()
3111 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3112 InitReg(MISCREG_DBGOSDLR)
3113 .unimplemented()
3114 .allPrivileges();
3115 InitReg(MISCREG_DBGPRCR)
3116 .unimplemented()
3117 .allPrivileges();
3118 InitReg(MISCREG_DBGDSAR)
3119 .unimplemented()
3120 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3121 InitReg(MISCREG_DBGCLAIMSET)
3122 .unimplemented()
3123 .allPrivileges();
3124 InitReg(MISCREG_DBGCLAIMCLR)
3125 .unimplemented()
3126 .allPrivileges();
3127 InitReg(MISCREG_DBGAUTHSTATUS)
3128 .unimplemented()
3129 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3130 InitReg(MISCREG_DBGDEVID2)
3131 .unimplemented()
3132 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3133 InitReg(MISCREG_DBGDEVID1)
3134 .unimplemented()
3135 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3136 InitReg(MISCREG_DBGDEVID0)
3137 .unimplemented()
3138 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3139 InitReg(MISCREG_TEECR)
3140 .unimplemented()
3141 .allPrivileges();
3142 InitReg(MISCREG_JIDR)
3143 .allPrivileges();
3144 InitReg(MISCREG_TEEHBR)
3145 .allPrivileges();
3146 InitReg(MISCREG_JOSCR)
3147 .allPrivileges();
3148 InitReg(MISCREG_JMCR)
3149 .allPrivileges();
3150
3151 // AArch32 CP15 registers
3152 InitReg(MISCREG_MIDR)
3153 .allPrivileges().exceptUserMode().writes(0);
3154 InitReg(MISCREG_CTR)
3155 .allPrivileges().exceptUserMode().writes(0);
3156 InitReg(MISCREG_TCMTR)
3157 .allPrivileges().exceptUserMode().writes(0);
3158 InitReg(MISCREG_TLBTR)
3159 .allPrivileges().exceptUserMode().writes(0);
3160 InitReg(MISCREG_MPIDR)
3161 .allPrivileges().exceptUserMode().writes(0);
3162 InitReg(MISCREG_REVIDR)
3163 .unimplemented()
3164 .warnNotFail()
3165 .allPrivileges().exceptUserMode().writes(0);
3166 InitReg(MISCREG_ID_PFR0)
3167 .allPrivileges().exceptUserMode().writes(0);
3168 InitReg(MISCREG_ID_PFR1)
3169 .allPrivileges().exceptUserMode().writes(0);
3170 InitReg(MISCREG_ID_DFR0)
3171 .allPrivileges().exceptUserMode().writes(0);
3172 InitReg(MISCREG_ID_AFR0)
3173 .allPrivileges().exceptUserMode().writes(0);
3174 InitReg(MISCREG_ID_MMFR0)
3175 .allPrivileges().exceptUserMode().writes(0);
3176 InitReg(MISCREG_ID_MMFR1)
3177 .allPrivileges().exceptUserMode().writes(0);
3178 InitReg(MISCREG_ID_MMFR2)
3179 .allPrivileges().exceptUserMode().writes(0);
3180 InitReg(MISCREG_ID_MMFR3)
3181 .allPrivileges().exceptUserMode().writes(0);
3182 InitReg(MISCREG_ID_ISAR0)
3183 .allPrivileges().exceptUserMode().writes(0);
3184 InitReg(MISCREG_ID_ISAR1)
3185 .allPrivileges().exceptUserMode().writes(0);
3186 InitReg(MISCREG_ID_ISAR2)
3187 .allPrivileges().exceptUserMode().writes(0);
3188 InitReg(MISCREG_ID_ISAR3)
3189 .allPrivileges().exceptUserMode().writes(0);
3190 InitReg(MISCREG_ID_ISAR4)
3191 .allPrivileges().exceptUserMode().writes(0);
3192 InitReg(MISCREG_ID_ISAR5)
3193 .allPrivileges().exceptUserMode().writes(0);
3194 InitReg(MISCREG_CCSIDR)
3195 .allPrivileges().exceptUserMode().writes(0);
3196 InitReg(MISCREG_CLIDR)
3197 .allPrivileges().exceptUserMode().writes(0);
3198 InitReg(MISCREG_AIDR)
3199 .allPrivileges().exceptUserMode().writes(0);
3200 InitReg(MISCREG_CSSELR)
3201 .banked();
3202 InitReg(MISCREG_CSSELR_NS)
3203 .bankedChild()
3204 .privSecure(!aarch32EL3)
3205 .nonSecure().exceptUserMode();
3206 InitReg(MISCREG_CSSELR_S)
3207 .bankedChild()
3208 .secure().exceptUserMode();
3209 InitReg(MISCREG_VPIDR)
3210 .hyp().monNonSecure();
3211 InitReg(MISCREG_VMPIDR)
3212 .hyp().monNonSecure();
3213 InitReg(MISCREG_SCTLR)
3214 .banked()
3215 // readMiscRegNoEffect() uses this metadata
3216 // despite using children (below) as backing store
3217 .res0(0x8d22c600)
3218 .res1(0x00400800 | (SPAN ? 0 : 0x800000)
3219 | (LSMAOE ? 0 : 0x10)
3220 | (nTLSMD ? 0 : 0x8));
3221 InitReg(MISCREG_SCTLR_NS)
3222 .bankedChild()
3223 .privSecure(!aarch32EL3)
3224 .nonSecure().exceptUserMode();
3225 InitReg(MISCREG_SCTLR_S)
3226 .bankedChild()
3227 .secure().exceptUserMode();
3228 InitReg(MISCREG_ACTLR)
3229 .banked();
3230 InitReg(MISCREG_ACTLR_NS)
3231 .bankedChild()
3232 .privSecure(!aarch32EL3)
3233 .nonSecure().exceptUserMode();
3234 InitReg(MISCREG_ACTLR_S)
3235 .bankedChild()
3236 .secure().exceptUserMode();
3237 InitReg(MISCREG_CPACR)
3238 .allPrivileges().exceptUserMode();
3239 InitReg(MISCREG_SCR)
3240 .mon().secure().exceptUserMode()
3241 .res0(0xff40) // [31:16], [6]
3242 .res1(0x0030); // [5:4]
3243 InitReg(MISCREG_SDER)
3244 .mon();
3245 InitReg(MISCREG_NSACR)
3246 .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
3247 InitReg(MISCREG_HSCTLR)
3248 .hyp().monNonSecure()
3249 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
3250 | (IESB ? 0 : 0x200000)
3251 | (EnDA ? 0 : 0x8000000)
3252 | (EnIB ? 0 : 0x40000000)
3253 | (EnIA ? 0 : 0x80000000))
3254 .res1(0x30c50830);
3255 InitReg(MISCREG_HACTLR)
3256 .hyp().monNonSecure();
3257 InitReg(MISCREG_HCR)
3258 .hyp().monNonSecure()
3259 .res0(0x90000000);
3260 InitReg(MISCREG_HCR2)
3261 .hyp().monNonSecure()
3262 .res0(0xffa9ff8c);
3263 InitReg(MISCREG_HDCR)
3264 .hyp().monNonSecure();
3265 InitReg(MISCREG_HCPTR)
3266 .hyp().monNonSecure();
3267 InitReg(MISCREG_HSTR)
3268 .hyp().monNonSecure();
3269 InitReg(MISCREG_HACR)
3270 .unimplemented()
3271 .warnNotFail()
3272 .hyp().monNonSecure();
3273 InitReg(MISCREG_TTBR0)
3274 .banked();
3275 InitReg(MISCREG_TTBR0_NS)
3276 .bankedChild()
3277 .privSecure(!aarch32EL3)
3278 .nonSecure().exceptUserMode();
3279 InitReg(MISCREG_TTBR0_S)
3280 .bankedChild()
3281 .secure().exceptUserMode();
3282 InitReg(MISCREG_TTBR1)
3283 .banked();
3284 InitReg(MISCREG_TTBR1_NS)
3285 .bankedChild()
3286 .privSecure(!aarch32EL3)
3287 .nonSecure().exceptUserMode();
3288 InitReg(MISCREG_TTBR1_S)
3289 .bankedChild()
3290 .secure().exceptUserMode();
3291 InitReg(MISCREG_TTBCR)
3292 .banked();
3293 InitReg(MISCREG_TTBCR_NS)
3294 .bankedChild()
3295 .privSecure(!aarch32EL3)
3296 .nonSecure().exceptUserMode();
3297 InitReg(MISCREG_TTBCR_S)
3298 .bankedChild()
3299 .secure().exceptUserMode();
3300 InitReg(MISCREG_HTCR)
3301 .hyp().monNonSecure();
3302 InitReg(MISCREG_VTCR)
3303 .hyp().monNonSecure();
3304 InitReg(MISCREG_DACR)
3305 .banked();
3306 InitReg(MISCREG_DACR_NS)
3307 .bankedChild()
3308 .privSecure(!aarch32EL3)
3309 .nonSecure().exceptUserMode();
3310 InitReg(MISCREG_DACR_S)
3311 .bankedChild()
3312 .secure().exceptUserMode();
3313 InitReg(MISCREG_DFSR)
3314 .banked();
3315 InitReg(MISCREG_DFSR_NS)
3316 .bankedChild()
3317 .privSecure(!aarch32EL3)
3318 .nonSecure().exceptUserMode();
3319 InitReg(MISCREG_DFSR_S)
3320 .bankedChild()
3321 .secure().exceptUserMode();
3322 InitReg(MISCREG_IFSR)
3323 .banked();
3324 InitReg(MISCREG_IFSR_NS)
3325 .bankedChild()
3326 .privSecure(!aarch32EL3)
3327 .nonSecure().exceptUserMode();
3328 InitReg(MISCREG_IFSR_S)
3329 .bankedChild()
3330 .secure().exceptUserMode();
3331 InitReg(MISCREG_ADFSR)
3332 .unimplemented()
3333 .warnNotFail()
3334 .banked();
3335 InitReg(MISCREG_ADFSR_NS)
3336 .unimplemented()
3337 .warnNotFail()
3338 .bankedChild()
3339 .privSecure(!aarch32EL3)
3340 .nonSecure().exceptUserMode();
3341 InitReg(MISCREG_ADFSR_S)
3342 .unimplemented()
3343 .warnNotFail()
3344 .bankedChild()
3345 .secure().exceptUserMode();
3346 InitReg(MISCREG_AIFSR)
3347 .unimplemented()
3348 .warnNotFail()
3349 .banked();
3350 InitReg(MISCREG_AIFSR_NS)
3351 .unimplemented()
3352 .warnNotFail()
3353 .bankedChild()
3354 .privSecure(!aarch32EL3)
3355 .nonSecure().exceptUserMode();
3356 InitReg(MISCREG_AIFSR_S)
3357 .unimplemented()
3358 .warnNotFail()
3359 .bankedChild()
3360 .secure().exceptUserMode();
3361 InitReg(MISCREG_HADFSR)
3362 .hyp().monNonSecure();
3363 InitReg(MISCREG_HAIFSR)
3364 .hyp().monNonSecure();
3365 InitReg(MISCREG_HSR)
3366 .hyp().monNonSecure();
3367 InitReg(MISCREG_DFAR)
3368 .banked();
3369 InitReg(MISCREG_DFAR_NS)
3370 .bankedChild()
3371 .privSecure(!aarch32EL3)
3372 .nonSecure().exceptUserMode();
3373 InitReg(MISCREG_DFAR_S)
3374 .bankedChild()
3375 .secure().exceptUserMode();
3376 InitReg(MISCREG_IFAR)
3377 .banked();
3378 InitReg(MISCREG_IFAR_NS)
3379 .bankedChild()
3380 .privSecure(!aarch32EL3)
3381 .nonSecure().exceptUserMode();
3382 InitReg(MISCREG_IFAR_S)
3383 .bankedChild()
3384 .secure().exceptUserMode();
3385 InitReg(MISCREG_HDFAR)
3386 .hyp().monNonSecure();
3387 InitReg(MISCREG_HIFAR)
3388 .hyp().monNonSecure();
3389 InitReg(MISCREG_HPFAR)
3390 .hyp().monNonSecure();
3391 InitReg(MISCREG_ICIALLUIS)
3392 .unimplemented()
3393 .warnNotFail()
3394 .writes(1).exceptUserMode();
3395 InitReg(MISCREG_BPIALLIS)
3396 .unimplemented()
3397 .warnNotFail()
3398 .writes(1).exceptUserMode();
3399 InitReg(MISCREG_PAR)
3400 .banked();
3401 InitReg(MISCREG_PAR_NS)
3402 .bankedChild()
3403 .privSecure(!aarch32EL3)
3404 .nonSecure().exceptUserMode();
3405 InitReg(MISCREG_PAR_S)
3406 .bankedChild()
3407 .secure().exceptUserMode();
3408 InitReg(MISCREG_ICIALLU)
3409 .writes(1).exceptUserMode();
3410 InitReg(MISCREG_ICIMVAU)
3411 .unimplemented()
3412 .warnNotFail()
3413 .writes(1).exceptUserMode();
3414 InitReg(MISCREG_CP15ISB)
3415 .writes(1);
3416 InitReg(MISCREG_BPIALL)
3417 .unimplemented()
3418 .warnNotFail()
3419 .writes(1).exceptUserMode();
3420 InitReg(MISCREG_BPIMVA)
3421 .unimplemented()
3422 .warnNotFail()
3423 .writes(1).exceptUserMode();
3424 InitReg(MISCREG_DCIMVAC)
3425 .unimplemented()
3426 .warnNotFail()
3427 .writes(1).exceptUserMode();
3428 InitReg(MISCREG_DCISW)
3429 .unimplemented()
3430 .warnNotFail()
3431 .writes(1).exceptUserMode();
3432 InitReg(MISCREG_ATS1CPR)
3433 .writes(1).exceptUserMode();
3434 InitReg(MISCREG_ATS1CPW)
3435 .writes(1).exceptUserMode();
3436 InitReg(MISCREG_ATS1CUR)
3437 .writes(1).exceptUserMode();
3438 InitReg(MISCREG_ATS1CUW)
3439 .writes(1).exceptUserMode();
3440 InitReg(MISCREG_ATS12NSOPR)
3441 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3442 InitReg(MISCREG_ATS12NSOPW)
3443 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3444 InitReg(MISCREG_ATS12NSOUR)
3445 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3446 InitReg(MISCREG_ATS12NSOUW)
3447 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3448 InitReg(MISCREG_DCCMVAC)
3449 .writes(1).exceptUserMode();
3450 InitReg(MISCREG_DCCSW)
3451 .unimplemented()
3452 .warnNotFail()
3453 .writes(1).exceptUserMode();
3454 InitReg(MISCREG_CP15DSB)
3455 .writes(1);
3456 InitReg(MISCREG_CP15DMB)
3457 .writes(1);
3458 InitReg(MISCREG_DCCMVAU)
3459 .unimplemented()
3460 .warnNotFail()
3461 .writes(1).exceptUserMode();
3462 InitReg(MISCREG_DCCIMVAC)
3463 .unimplemented()
3464 .warnNotFail()
3465 .writes(1).exceptUserMode();
3466 InitReg(MISCREG_DCCISW)
3467 .unimplemented()
3468 .warnNotFail()
3469 .writes(1).exceptUserMode();
3470 InitReg(MISCREG_ATS1HR)
3471 .monNonSecureWrite().hypWrite();
3472 InitReg(MISCREG_ATS1HW)
3473 .monNonSecureWrite().hypWrite();
3474 InitReg(MISCREG_TLBIALLIS)
3475 .writes(1).exceptUserMode();
3476 InitReg(MISCREG_TLBIMVAIS)
3477 .writes(1).exceptUserMode();
3478 InitReg(MISCREG_TLBIASIDIS)
3479 .writes(1).exceptUserMode();
3480 InitReg(MISCREG_TLBIMVAAIS)
3481 .writes(1).exceptUserMode();
3482 InitReg(MISCREG_TLBIMVALIS)
3483 .writes(1).exceptUserMode();
3484 InitReg(MISCREG_TLBIMVAALIS)
3485 .writes(1).exceptUserMode();
3486 InitReg(MISCREG_ITLBIALL)
3487 .writes(1).exceptUserMode();
3488 InitReg(MISCREG_ITLBIMVA)
3489 .writes(1).exceptUserMode();
3490 InitReg(MISCREG_ITLBIASID)
3491 .writes(1).exceptUserMode();
3492 InitReg(MISCREG_DTLBIALL)
3493 .writes(1).exceptUserMode();
3494 InitReg(MISCREG_DTLBIMVA)
3495 .writes(1).exceptUserMode();
3496 InitReg(MISCREG_DTLBIASID)
3497 .writes(1).exceptUserMode();
3498 InitReg(MISCREG_TLBIALL)
3499 .writes(1).exceptUserMode();
3500 InitReg(MISCREG_TLBIMVA)
3501 .writes(1).exceptUserMode();
3502 InitReg(MISCREG_TLBIASID)
3503 .writes(1).exceptUserMode();
3504 InitReg(MISCREG_TLBIMVAA)
3505 .writes(1).exceptUserMode();
3506 InitReg(MISCREG_TLBIMVAL)
3507 .writes(1).exceptUserMode();
3508 InitReg(MISCREG_TLBIMVAAL)
3509 .writes(1).exceptUserMode();
3510 InitReg(MISCREG_TLBIIPAS2IS)
3511 .monNonSecureWrite().hypWrite();
3512 InitReg(MISCREG_TLBIIPAS2LIS)
3513 .monNonSecureWrite().hypWrite();
3514 InitReg(MISCREG_TLBIALLHIS)
3515 .monNonSecureWrite().hypWrite();
3516 InitReg(MISCREG_TLBIMVAHIS)
3517 .monNonSecureWrite().hypWrite();
3518 InitReg(MISCREG_TLBIALLNSNHIS)
3519 .monNonSecureWrite().hypWrite();
3520 InitReg(MISCREG_TLBIMVALHIS)
3521 .monNonSecureWrite().hypWrite();
3522 InitReg(MISCREG_TLBIIPAS2)
3523 .monNonSecureWrite().hypWrite();
3524 InitReg(MISCREG_TLBIIPAS2L)
3525 .monNonSecureWrite().hypWrite();
3526 InitReg(MISCREG_TLBIALLH)
3527 .monNonSecureWrite().hypWrite();
3528 InitReg(MISCREG_TLBIMVAH)
3529 .monNonSecureWrite().hypWrite();
3530 InitReg(MISCREG_TLBIALLNSNH)
3531 .monNonSecureWrite().hypWrite();
3532 InitReg(MISCREG_TLBIMVALH)
3533 .monNonSecureWrite().hypWrite();
3534 InitReg(MISCREG_PMCR)
3535 .allPrivileges();
3536 InitReg(MISCREG_PMCNTENSET)
3537 .allPrivileges();
3538 InitReg(MISCREG_PMCNTENCLR)
3539 .allPrivileges();
3540 InitReg(MISCREG_PMOVSR)
3541 .allPrivileges();
3542 InitReg(MISCREG_PMSWINC)
3543 .allPrivileges();
3544 InitReg(MISCREG_PMSELR)
3545 .allPrivileges();
3546 InitReg(MISCREG_PMCEID0)
3547 .allPrivileges();
3548 InitReg(MISCREG_PMCEID1)
3549 .allPrivileges();
3550 InitReg(MISCREG_PMCCNTR)
3551 .allPrivileges();
3552 InitReg(MISCREG_PMXEVTYPER)
3553 .allPrivileges();
3554 InitReg(MISCREG_PMCCFILTR)
3555 .allPrivileges();
3556 InitReg(MISCREG_PMXEVCNTR)
3557 .allPrivileges();
3558 InitReg(MISCREG_PMUSERENR)
3559 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
3560 InitReg(MISCREG_PMINTENSET)
3561 .allPrivileges().exceptUserMode();
3562 InitReg(MISCREG_PMINTENCLR)
3563 .allPrivileges().exceptUserMode();
3564 InitReg(MISCREG_PMOVSSET)
3565 .unimplemented()
3566 .allPrivileges();
3567 InitReg(MISCREG_L2CTLR)
3568 .allPrivileges().exceptUserMode();
3569 InitReg(MISCREG_L2ECTLR)
3570 .unimplemented()
3571 .allPrivileges().exceptUserMode();
3572 InitReg(MISCREG_PRRR)
3573 .banked();
3574 InitReg(MISCREG_PRRR_NS)
3575 .bankedChild()
3576 .privSecure(!aarch32EL3)
3577 .nonSecure().exceptUserMode();
3578 InitReg(MISCREG_PRRR_S)
3579 .bankedChild()
3580 .secure().exceptUserMode();
3581 InitReg(MISCREG_MAIR0)
3582 .banked();
3583 InitReg(MISCREG_MAIR0_NS)
3584 .bankedChild()
3585 .privSecure(!aarch32EL3)
3586 .nonSecure().exceptUserMode();
3587 InitReg(MISCREG_MAIR0_S)
3588 .bankedChild()
3589 .secure().exceptUserMode();
3590 InitReg(MISCREG_NMRR)
3591 .banked();
3592 InitReg(MISCREG_NMRR_NS)
3593 .bankedChild()
3594 .privSecure(!aarch32EL3)
3595 .nonSecure().exceptUserMode();
3596 InitReg(MISCREG_NMRR_S)
3597 .bankedChild()
3598 .secure().exceptUserMode();
3599 InitReg(MISCREG_MAIR1)
3600 .banked();
3601 InitReg(MISCREG_MAIR1_NS)
3602 .bankedChild()
3603 .privSecure(!aarch32EL3)
3604 .nonSecure().exceptUserMode();
3605 InitReg(MISCREG_MAIR1_S)
3606 .bankedChild()
3607 .secure().exceptUserMode();
3608 InitReg(MISCREG_AMAIR0)
3609 .banked();
3610 InitReg(MISCREG_AMAIR0_NS)
3611 .bankedChild()
3612 .privSecure(!aarch32EL3)
3613 .nonSecure().exceptUserMode();
3614 InitReg(MISCREG_AMAIR0_S)
3615 .bankedChild()
3616 .secure().exceptUserMode();
3617 InitReg(MISCREG_AMAIR1)
3618 .banked();
3619 InitReg(MISCREG_AMAIR1_NS)
3620 .bankedChild()
3621 .privSecure(!aarch32EL3)
3622 .nonSecure().exceptUserMode();
3623 InitReg(MISCREG_AMAIR1_S)
3624 .bankedChild()
3625 .secure().exceptUserMode();
3626 InitReg(MISCREG_HMAIR0)
3627 .hyp().monNonSecure();
3628 InitReg(MISCREG_HMAIR1)
3629 .hyp().monNonSecure();
3630 InitReg(MISCREG_HAMAIR0)
3631 .unimplemented()
3632 .warnNotFail()
3633 .hyp().monNonSecure();
3634 InitReg(MISCREG_HAMAIR1)
3635 .unimplemented()
3636 .warnNotFail()
3637 .hyp().monNonSecure();
3638 InitReg(MISCREG_VBAR)
3639 .banked();
3640 InitReg(MISCREG_VBAR_NS)
3641 .bankedChild()
3642 .privSecure(!aarch32EL3)
3643 .nonSecure().exceptUserMode();
3644 InitReg(MISCREG_VBAR_S)
3645 .bankedChild()
3646 .secure().exceptUserMode();
3647 InitReg(MISCREG_MVBAR)
3648 .mon().secure()
3649 .hypRead(FullSystem && system->highestEL() == EL2)
3650 .privRead(FullSystem && system->highestEL() == EL1)
3651 .exceptUserMode();
3652 InitReg(MISCREG_RMR)
3653 .unimplemented()
3654 .mon().secure().exceptUserMode();
3655 InitReg(MISCREG_ISR)
3656 .allPrivileges().exceptUserMode().writes(0);
3657 InitReg(MISCREG_HVBAR)
3658 .hyp().monNonSecure()
3659 .res0(0x1f);
3660 InitReg(MISCREG_FCSEIDR)
3661 .unimplemented()
3662 .warnNotFail()
3663 .allPrivileges().exceptUserMode();
3664 InitReg(MISCREG_CONTEXTIDR)
3665 .banked();
3666 InitReg(MISCREG_CONTEXTIDR_NS)
3667 .bankedChild()
3668 .privSecure(!aarch32EL3)
3669 .nonSecure().exceptUserMode();
3670 InitReg(MISCREG_CONTEXTIDR_S)
3671 .bankedChild()
3672 .secure().exceptUserMode();
3673 InitReg(MISCREG_TPIDRURW)
3674 .banked();
3675 InitReg(MISCREG_TPIDRURW_NS)
3676 .bankedChild()
3677 .allPrivileges()
3678 .privSecure(!aarch32EL3)
3679 .monSecure(0);
3680 InitReg(MISCREG_TPIDRURW_S)
3681 .bankedChild()
3682 .secure();
3683 InitReg(MISCREG_TPIDRURO)
3684 .banked();
3685 InitReg(MISCREG_TPIDRURO_NS)
3686 .bankedChild()
3687 .allPrivileges()
3688 .userNonSecureWrite(0).userSecureRead(1)
3689 .privSecure(!aarch32EL3)
3690 .monSecure(0);
3691 InitReg(MISCREG_TPIDRURO_S)
3692 .bankedChild()
3693 .secure().userSecureWrite(0);
3694 InitReg(MISCREG_TPIDRPRW)
3695 .banked();
3696 InitReg(MISCREG_TPIDRPRW_NS)
3697 .bankedChild()
3698 .nonSecure().exceptUserMode()
3699 .privSecure(!aarch32EL3);
3700 InitReg(MISCREG_TPIDRPRW_S)
3701 .bankedChild()
3702 .secure().exceptUserMode();
3703 InitReg(MISCREG_HTPIDR)
3704 .hyp().monNonSecure();
3705 InitReg(MISCREG_CNTFRQ)
3706 .reads(1)
3707 .highest(system)
3708 .privSecureWrite(aarch32EL3);
3709 InitReg(MISCREG_CNTKCTL)
3710 .allPrivileges().exceptUserMode();
3711 InitReg(MISCREG_CNTP_TVAL)
3712 .banked();
3713 InitReg(MISCREG_CNTP_TVAL_NS)
3714 .bankedChild()
3715 .allPrivileges()
3716 .privSecure(!aarch32EL3)
3717 .monSecure(0);
3718 InitReg(MISCREG_CNTP_TVAL_S)
3719 .bankedChild()
3720 .secure().user(1);
3721 InitReg(MISCREG_CNTP_CTL)
3722 .banked();
3723 InitReg(MISCREG_CNTP_CTL_NS)
3724 .bankedChild()
3725 .allPrivileges()
3726 .privSecure(!aarch32EL3)
3727 .monSecure(0);
3728 InitReg(MISCREG_CNTP_CTL_S)
3729 .bankedChild()
3730 .secure().user(1);
3731 InitReg(MISCREG_CNTV_TVAL)
3732 .allPrivileges();
3733 InitReg(MISCREG_CNTV_CTL)
3734 .allPrivileges();
3735 InitReg(MISCREG_CNTHCTL)
3736 .hypWrite().monNonSecureRead();
3737 InitReg(MISCREG_CNTHP_TVAL)
3738 .hypWrite().monNonSecureRead();
3739 InitReg(MISCREG_CNTHP_CTL)
3740 .hypWrite().monNonSecureRead();
3741 InitReg(MISCREG_IL1DATA0)
3742 .unimplemented()
3743 .allPrivileges().exceptUserMode();
3744 InitReg(MISCREG_IL1DATA1)
3745 .unimplemented()
3746 .allPrivileges().exceptUserMode();
3747 InitReg(MISCREG_IL1DATA2)
3748 .unimplemented()
3749 .allPrivileges().exceptUserMode();
3750 InitReg(MISCREG_IL1DATA3)
3751 .unimplemented()
3752 .allPrivileges().exceptUserMode();
3753 InitReg(MISCREG_DL1DATA0)
3754 .unimplemented()
3755 .allPrivileges().exceptUserMode();
3756 InitReg(MISCREG_DL1DATA1)
3757 .unimplemented()
3758 .allPrivileges().exceptUserMode();
3759 InitReg(MISCREG_DL1DATA2)
3760 .unimplemented()
3761 .allPrivileges().exceptUserMode();
3762 InitReg(MISCREG_DL1DATA3)
3763 .unimplemented()
3764 .allPrivileges().exceptUserMode();
3765 InitReg(MISCREG_DL1DATA4)
3766 .unimplemented()
3767 .allPrivileges().exceptUserMode();
3768 InitReg(MISCREG_RAMINDEX)
3769 .unimplemented()
3770 .writes(1).exceptUserMode();
3771 InitReg(MISCREG_L2ACTLR)
3772 .unimplemented()
3773 .allPrivileges().exceptUserMode();
3774 InitReg(MISCREG_CBAR)
3775 .unimplemented()
3776 .allPrivileges().exceptUserMode().writes(0);
3777 InitReg(MISCREG_HTTBR)
3778 .hyp().monNonSecure();
3779 InitReg(MISCREG_VTTBR)
3780 .hyp().monNonSecure();
3781 InitReg(MISCREG_CNTPCT)
3782 .reads(1);
3783 InitReg(MISCREG_CNTVCT)
3784 .unverifiable()
3785 .reads(1);
3786 InitReg(MISCREG_CNTP_CVAL)
3787 .banked();
3788 InitReg(MISCREG_CNTP_CVAL_NS)
3789 .bankedChild()
3790 .allPrivileges()
3791 .privSecure(!aarch32EL3)
3792 .monSecure(0);
3793 InitReg(MISCREG_CNTP_CVAL_S)
3794 .bankedChild()
3795 .secure().user(1);
3796 InitReg(MISCREG_CNTV_CVAL)
3797 .allPrivileges();
3798 InitReg(MISCREG_CNTVOFF)
3799 .hyp().monNonSecure();
3800 InitReg(MISCREG_CNTHP_CVAL)
3801 .hypWrite().monNonSecureRead();
3802 InitReg(MISCREG_CPUMERRSR)
3803 .unimplemented()
3804 .allPrivileges().exceptUserMode();
3805 InitReg(MISCREG_L2MERRSR)
3806 .unimplemented()
3807 .warnNotFail()
3808 .allPrivileges().exceptUserMode();
3809
3810 // AArch64 registers (Op0=2);
3811 InitReg(MISCREG_MDCCINT_EL1)
3812 .allPrivileges();
3813 InitReg(MISCREG_OSDTRRX_EL1)
3814 .allPrivileges()
3815 .mapsTo(MISCREG_DBGDTRRXext);
3816 InitReg(MISCREG_MDSCR_EL1)
3817 .allPrivileges()
3818 .mapsTo(MISCREG_DBGDSCRext);
3819 InitReg(MISCREG_OSDTRTX_EL1)
3820 .allPrivileges()
3821 .mapsTo(MISCREG_DBGDTRTXext);
3822 InitReg(MISCREG_OSECCR_EL1)
3823 .allPrivileges()
3824 .mapsTo(MISCREG_DBGOSECCR);
3825 InitReg(MISCREG_DBGBVR0_EL1)
3826 .allPrivileges()
3827 .mapsTo(MISCREG_DBGBVR0 /*, MISCREG_DBGBXVR0 */);
3828 InitReg(MISCREG_DBGBVR1_EL1)
3829 .allPrivileges()
3830 .mapsTo(MISCREG_DBGBVR1 /*, MISCREG_DBGBXVR1 */);
3831 InitReg(MISCREG_DBGBVR2_EL1)
3832 .allPrivileges()
3833 .mapsTo(MISCREG_DBGBVR2 /*, MISCREG_DBGBXVR2 */);
3834 InitReg(MISCREG_DBGBVR3_EL1)
3835 .allPrivileges()
3836 .mapsTo(MISCREG_DBGBVR3 /*, MISCREG_DBGBXVR3 */);
3837 InitReg(MISCREG_DBGBVR4_EL1)
3838 .allPrivileges()
3839 .mapsTo(MISCREG_DBGBVR4 /*, MISCREG_DBGBXVR4 */);
3840 InitReg(MISCREG_DBGBVR5_EL1)
3841 .allPrivileges()
3842 .mapsTo(MISCREG_DBGBVR5 /*, MISCREG_DBGBXVR5 */);
3843 InitReg(MISCREG_DBGBCR0_EL1)
3844 .allPrivileges()
3845 .mapsTo(MISCREG_DBGBCR0);
3846 InitReg(MISCREG_DBGBCR1_EL1)
3847 .allPrivileges()
3848 .mapsTo(MISCREG_DBGBCR1);
3849 InitReg(MISCREG_DBGBCR2_EL1)
3850 .allPrivileges()
3851 .mapsTo(MISCREG_DBGBCR2);
3852 InitReg(MISCREG_DBGBCR3_EL1)
3853 .allPrivileges()
3854 .mapsTo(MISCREG_DBGBCR3);
3855 InitReg(MISCREG_DBGBCR4_EL1)
3856 .allPrivileges()
3857 .mapsTo(MISCREG_DBGBCR4);
3858 InitReg(MISCREG_DBGBCR5_EL1)
3859 .allPrivileges()
3860 .mapsTo(MISCREG_DBGBCR5);
3861 InitReg(MISCREG_DBGWVR0_EL1)
3862 .allPrivileges()
3863 .mapsTo(MISCREG_DBGWVR0);
3864 InitReg(MISCREG_DBGWVR1_EL1)
3865 .allPrivileges()
3866 .mapsTo(MISCREG_DBGWVR1);
3867 InitReg(MISCREG_DBGWVR2_EL1)
3868 .allPrivileges()
3869 .mapsTo(MISCREG_DBGWVR2);
3870 InitReg(MISCREG_DBGWVR3_EL1)
3871 .allPrivileges()
3872 .mapsTo(MISCREG_DBGWVR3);
3873 InitReg(MISCREG_DBGWCR0_EL1)
3874 .allPrivileges()
3875 .mapsTo(MISCREG_DBGWCR0);
3876 InitReg(MISCREG_DBGWCR1_EL1)
3877 .allPrivileges()
3878 .mapsTo(MISCREG_DBGWCR1);
3879 InitReg(MISCREG_DBGWCR2_EL1)
3880 .allPrivileges()
3881 .mapsTo(MISCREG_DBGWCR2);
3882 InitReg(MISCREG_DBGWCR3_EL1)
3883 .allPrivileges()
3884 .mapsTo(MISCREG_DBGWCR3);
3885 InitReg(MISCREG_MDCCSR_EL0)
3886 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3887 .mapsTo(MISCREG_DBGDSCRint);
3888 InitReg(MISCREG_MDDTR_EL0)
3889 .allPrivileges();
3890 InitReg(MISCREG_MDDTRTX_EL0)
3891 .allPrivileges();
3892 InitReg(MISCREG_MDDTRRX_EL0)
3893 .allPrivileges();
3894 InitReg(MISCREG_DBGVCR32_EL2)
3895 .allPrivileges()
3896 .mapsTo(MISCREG_DBGVCR);
3897 InitReg(MISCREG_MDRAR_EL1)
3898 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3899 .mapsTo(MISCREG_DBGDRAR);
3900 InitReg(MISCREG_OSLAR_EL1)
3901 .allPrivileges().monSecureRead(0).monNonSecureRead(0)
3902 .mapsTo(MISCREG_DBGOSLAR);
3903 InitReg(MISCREG_OSLSR_EL1)
3904 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3905 .mapsTo(MISCREG_DBGOSLSR);
3906 InitReg(MISCREG_OSDLR_EL1)
3907 .allPrivileges()
3908 .mapsTo(MISCREG_DBGOSDLR);
3909 InitReg(MISCREG_DBGPRCR_EL1)
3910 .allPrivileges()
3911 .mapsTo(MISCREG_DBGPRCR);
3912 InitReg(MISCREG_DBGCLAIMSET_EL1)
3913 .allPrivileges()
3914 .mapsTo(MISCREG_DBGCLAIMSET);
3915 InitReg(MISCREG_DBGCLAIMCLR_EL1)
3916 .allPrivileges()
3917 .mapsTo(MISCREG_DBGCLAIMCLR);
3918 InitReg(MISCREG_DBGAUTHSTATUS_EL1)
3919 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3920 .mapsTo(MISCREG_DBGAUTHSTATUS);
3921 InitReg(MISCREG_TEECR32_EL1);
3922 InitReg(MISCREG_TEEHBR32_EL1);
3923
3924 // AArch64 registers (Op0=1,3);
3925 InitReg(MISCREG_MIDR_EL1)
3926 .allPrivileges().exceptUserMode().writes(0);
3927 InitReg(MISCREG_MPIDR_EL1)
3928 .allPrivileges().exceptUserMode().writes(0);
3929 InitReg(MISCREG_REVIDR_EL1)
3930 .allPrivileges().exceptUserMode().writes(0);
3931 InitReg(MISCREG_ID_PFR0_EL1)
3932 .allPrivileges().exceptUserMode().writes(0)
3933 .mapsTo(MISCREG_ID_PFR0);
3934 InitReg(MISCREG_ID_PFR1_EL1)
3935 .allPrivileges().exceptUserMode().writes(0)
3936 .mapsTo(MISCREG_ID_PFR1);
3937 InitReg(MISCREG_ID_DFR0_EL1)
3938 .allPrivileges().exceptUserMode().writes(0)
3939 .mapsTo(MISCREG_ID_DFR0);
3940 InitReg(MISCREG_ID_AFR0_EL1)
3941 .allPrivileges().exceptUserMode().writes(0)
3942 .mapsTo(MISCREG_ID_AFR0);
3943 InitReg(MISCREG_ID_MMFR0_EL1)
3944 .allPrivileges().exceptUserMode().writes(0)
3945 .mapsTo(MISCREG_ID_MMFR0);
3946 InitReg(MISCREG_ID_MMFR1_EL1)
3947 .allPrivileges().exceptUserMode().writes(0)
3948 .mapsTo(MISCREG_ID_MMFR1);
3949 InitReg(MISCREG_ID_MMFR2_EL1)
3950 .allPrivileges().exceptUserMode().writes(0)
3951 .mapsTo(MISCREG_ID_MMFR2);
3952 InitReg(MISCREG_ID_MMFR3_EL1)
3953 .allPrivileges().exceptUserMode().writes(0)
3954 .mapsTo(MISCREG_ID_MMFR3);
3955 InitReg(MISCREG_ID_ISAR0_EL1)
3956 .allPrivileges().exceptUserMode().writes(0)
3957 .mapsTo(MISCREG_ID_ISAR0);
3958 InitReg(MISCREG_ID_ISAR1_EL1)
3959 .allPrivileges().exceptUserMode().writes(0)
3960 .mapsTo(MISCREG_ID_ISAR1);
3961 InitReg(MISCREG_ID_ISAR2_EL1)
3962 .allPrivileges().exceptUserMode().writes(0)
3963 .mapsTo(MISCREG_ID_ISAR2);
3964 InitReg(MISCREG_ID_ISAR3_EL1)
3965 .allPrivileges().exceptUserMode().writes(0)
3966 .mapsTo(MISCREG_ID_ISAR3);
3967 InitReg(MISCREG_ID_ISAR4_EL1)
3968 .allPrivileges().exceptUserMode().writes(0)
3969 .mapsTo(MISCREG_ID_ISAR4);
3970 InitReg(MISCREG_ID_ISAR5_EL1)
3971 .allPrivileges().exceptUserMode().writes(0)
3972 .mapsTo(MISCREG_ID_ISAR5);
3973 InitReg(MISCREG_MVFR0_EL1)
3974 .allPrivileges().exceptUserMode().writes(0);
3975 InitReg(MISCREG_MVFR1_EL1)
3976 .allPrivileges().exceptUserMode().writes(0);
3977 InitReg(MISCREG_MVFR2_EL1)
3978 .allPrivileges().exceptUserMode().writes(0);
3979 InitReg(MISCREG_ID_AA64PFR0_EL1)
3980 .allPrivileges().exceptUserMode().writes(0);
3981 InitReg(MISCREG_ID_AA64PFR1_EL1)
3982 .allPrivileges().exceptUserMode().writes(0);
3983 InitReg(MISCREG_ID_AA64DFR0_EL1)
3984 .allPrivileges().exceptUserMode().writes(0);
3985 InitReg(MISCREG_ID_AA64DFR1_EL1)
3986 .allPrivileges().exceptUserMode().writes(0);
3987 InitReg(MISCREG_ID_AA64AFR0_EL1)
3988 .allPrivileges().exceptUserMode().writes(0);
3989 InitReg(MISCREG_ID_AA64AFR1_EL1)
3990 .allPrivileges().exceptUserMode().writes(0);
3991 InitReg(MISCREG_ID_AA64ISAR0_EL1)
3992 .allPrivileges().exceptUserMode().writes(0);
3993 InitReg(MISCREG_ID_AA64ISAR1_EL1)
3994 .allPrivileges().exceptUserMode().writes(0);
3995 InitReg(MISCREG_ID_AA64MMFR0_EL1)
3996 .allPrivileges().exceptUserMode().writes(0);
3997 InitReg(MISCREG_ID_AA64MMFR1_EL1)
3998 .allPrivileges().exceptUserMode().writes(0);
3999 InitReg(MISCREG_ID_AA64MMFR2_EL1)
4000 .allPrivileges().exceptUserMode().writes(0);
4001
4002 InitReg(MISCREG_APDAKeyHi_EL1)
4003 .allPrivileges().exceptUserMode();
4004 InitReg(MISCREG_APDAKeyLo_EL1)
4005 .allPrivileges().exceptUserMode();
4006 InitReg(MISCREG_APDBKeyHi_EL1)
4007 .allPrivileges().exceptUserMode();
4008 InitReg(MISCREG_APDBKeyLo_EL1)
4009 .allPrivileges().exceptUserMode();
4010 InitReg(MISCREG_APGAKeyHi_EL1)
4011 .allPrivileges().exceptUserMode();
4012 InitReg(MISCREG_APGAKeyLo_EL1)
4013 .allPrivileges().exceptUserMode();
4014 InitReg(MISCREG_APIAKeyHi_EL1)
4015 .allPrivileges().exceptUserMode();
4016 InitReg(MISCREG_APIAKeyLo_EL1)
4017 .allPrivileges().exceptUserMode();
4018 InitReg(MISCREG_APIBKeyHi_EL1)
4019 .allPrivileges().exceptUserMode();
4020 InitReg(MISCREG_APIBKeyLo_EL1)
4021 .allPrivileges().exceptUserMode();
4022
4023 InitReg(MISCREG_CCSIDR_EL1)
4024 .allPrivileges().exceptUserMode().writes(0);
4025 InitReg(MISCREG_CLIDR_EL1)
4026 .allPrivileges().exceptUserMode().writes(0);
4027 InitReg(MISCREG_AIDR_EL1)
4028 .allPrivileges().exceptUserMode().writes(0);
4029 InitReg(MISCREG_CSSELR_EL1)
4030 .allPrivileges().exceptUserMode()
4031 .mapsTo(MISCREG_CSSELR_NS);
4032 InitReg(MISCREG_CTR_EL0)
4033 .reads(1);
4034 InitReg(MISCREG_DCZID_EL0)
4035 .reads(1);
4036 InitReg(MISCREG_VPIDR_EL2)
4037 .hyp().mon()
4038 .mapsTo(MISCREG_VPIDR);
4039 InitReg(MISCREG_VMPIDR_EL2)
4040 .hyp().mon()
4041 .mapsTo(MISCREG_VMPIDR);
4042 InitReg(MISCREG_SCTLR_EL1)
4043 .allPrivileges().exceptUserMode()
4044 .res0( 0x20440 | (EnDB ? 0 : 0x2000)
4045 | (IESB ? 0 : 0x200000)
4046 | (EnDA ? 0 : 0x8000000)
4047 | (EnIB ? 0 : 0x40000000)
4048 | (EnIA ? 0 : 0x80000000))
4049 .res1(0x500800 | (SPAN ? 0 : 0x800000)
4050 | (nTLSMD ? 0 : 0x8000000)
4051 | (LSMAOE ? 0 : 0x10000000))
4052 .mapsTo(MISCREG_SCTLR_NS);
4053 InitReg(MISCREG_ACTLR_EL1)
4054 .allPrivileges().exceptUserMode()
4055 .mapsTo(MISCREG_ACTLR_NS);
4056 InitReg(MISCREG_CPACR_EL1)
4057 .allPrivileges().exceptUserMode()
4058 .mapsTo(MISCREG_CPACR);
4059 InitReg(MISCREG_SCTLR_EL2)
4060 .hyp().mon()
4061 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
4062 | (IESB ? 0 : 0x200000)
4063 | (EnDA ? 0 : 0x8000000)
4064 | (EnIB ? 0 : 0x40000000)
4065 | (EnIA ? 0 : 0x80000000))
4066 .res1(0x30c50830)
4067 .mapsTo(MISCREG_HSCTLR);
4068 InitReg(MISCREG_ACTLR_EL2)
4069 .hyp().mon()
4070 .mapsTo(MISCREG_HACTLR);
4071 InitReg(MISCREG_HCR_EL2)
4072 .hyp().mon()
4073 .mapsTo(MISCREG_HCR, MISCREG_HCR2);
4074 InitReg(MISCREG_MDCR_EL2)
4075 .hyp().mon()
4076 .mapsTo(MISCREG_HDCR);
4077 InitReg(MISCREG_CPTR_EL2)
4078 .hyp().mon()
4079 .mapsTo(MISCREG_HCPTR);
4080 InitReg(MISCREG_HSTR_EL2)
4081 .hyp().mon()
4082 .mapsTo(MISCREG_HSTR);
4083 InitReg(MISCREG_HACR_EL2)
4084 .hyp().mon()
4085 .mapsTo(MISCREG_HACR);
4086 InitReg(MISCREG_SCTLR_EL3)
4087 .mon()
4088 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
4089 | (IESB ? 0 : 0x200000)
4090 | (EnDA ? 0 : 0x8000000)
4091 | (EnIB ? 0 : 0x40000000)
4092 | (EnIA ? 0 : 0x80000000))
4093 .res1(0x30c50830);
4094 InitReg(MISCREG_ACTLR_EL3)
4095 .mon();
4096 InitReg(MISCREG_SCR_EL3)
4097 .mon()
4098 .mapsTo(MISCREG_SCR); // NAM D7-2005
4099 InitReg(MISCREG_SDER32_EL3)
4100 .mon()
4101 .mapsTo(MISCREG_SDER);
4102 InitReg(MISCREG_CPTR_EL3)
4103 .mon();
4104 InitReg(MISCREG_MDCR_EL3)
4105 .mon();
4106 InitReg(MISCREG_TTBR0_EL1)
4107 .allPrivileges().exceptUserMode()
4108 .mapsTo(MISCREG_TTBR0_NS);
4109 InitReg(MISCREG_TTBR1_EL1)
4110 .allPrivileges().exceptUserMode()
4111 .mapsTo(MISCREG_TTBR1_NS);
4112 InitReg(MISCREG_TCR_EL1)
4113 .allPrivileges().exceptUserMode()
4114 .mapsTo(MISCREG_TTBCR_NS);
4115 InitReg(MISCREG_TTBR0_EL2)
4116 .hyp().mon()
4117 .mapsTo(MISCREG_HTTBR);
4118 InitReg(MISCREG_TTBR1_EL2)
4119 .hyp().mon();
4120 InitReg(MISCREG_TCR_EL2)
4121 .hyp().mon()
4122 .mapsTo(MISCREG_HTCR);
4123 InitReg(MISCREG_VTTBR_EL2)
4124 .hyp().mon()
4125 .mapsTo(MISCREG_VTTBR);
4126 InitReg(MISCREG_VTCR_EL2)
4127 .hyp().mon()
4128 .mapsTo(MISCREG_VTCR);
4129 InitReg(MISCREG_TTBR0_EL3)
4130 .mon();
4131 InitReg(MISCREG_TCR_EL3)
4132 .mon();
4133 InitReg(MISCREG_DACR32_EL2)
4134 .hyp().mon()
4135 .mapsTo(MISCREG_DACR_NS);
4136 InitReg(MISCREG_SPSR_EL1)
4137 .allPrivileges().exceptUserMode()
4138 .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
4139 InitReg(MISCREG_ELR_EL1)
4140 .allPrivileges().exceptUserMode();
4141 InitReg(MISCREG_SP_EL0)
4142 .allPrivileges().exceptUserMode();
4143 InitReg(MISCREG_SPSEL)
4144 .allPrivileges().exceptUserMode();
4145 InitReg(MISCREG_CURRENTEL)
4146 .allPrivileges().exceptUserMode().writes(0);
4147 InitReg(MISCREG_PAN)
4148 .allPrivileges().exceptUserMode()
4149 .implemented(havePAN);
4150 InitReg(MISCREG_NZCV)
4151 .allPrivileges();
4152 InitReg(MISCREG_DAIF)
4153 .allPrivileges();
4154 InitReg(MISCREG_FPCR)
4155 .allPrivileges();
4156 InitReg(MISCREG_FPSR)
4157 .allPrivileges();
4158 InitReg(MISCREG_DSPSR_EL0)
4159 .allPrivileges();
4160 InitReg(MISCREG_DLR_EL0)
4161 .allPrivileges();
4162 InitReg(MISCREG_SPSR_EL2)
4163 .hyp().mon()
4164 .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2
4165 InitReg(MISCREG_ELR_EL2)
4166 .hyp().mon();
4167 InitReg(MISCREG_SP_EL1)
4168 .hyp().mon();
4169 InitReg(MISCREG_SPSR_IRQ_AA64)
4170 .hyp().mon();
4171 InitReg(MISCREG_SPSR_ABT_AA64)
4172 .hyp().mon();
4173 InitReg(MISCREG_SPSR_UND_AA64)
4174 .hyp().mon();
4175 InitReg(MISCREG_SPSR_FIQ_AA64)
4176 .hyp().mon();
4177 InitReg(MISCREG_SPSR_EL3)
4178 .mon()
4179 .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3
4180 InitReg(MISCREG_ELR_EL3)
4181 .mon();
4182 InitReg(MISCREG_SP_EL2)
4183 .mon();
4184 InitReg(MISCREG_AFSR0_EL1)
4185 .allPrivileges().exceptUserMode()
4186 .mapsTo(MISCREG_ADFSR_NS);
4187 InitReg(MISCREG_AFSR1_EL1)
4188 .allPrivileges().exceptUserMode()
4189 .mapsTo(MISCREG_AIFSR_NS);
4190 InitReg(MISCREG_ESR_EL1)
4191 .allPrivileges().exceptUserMode();
4192 InitReg(MISCREG_IFSR32_EL2)
4193 .hyp().mon()
4194 .mapsTo(MISCREG_IFSR_NS);
4195 InitReg(MISCREG_AFSR0_EL2)
4196 .hyp().mon()
4197 .mapsTo(MISCREG_HADFSR);
4198 InitReg(MISCREG_AFSR1_EL2)
4199 .hyp().mon()
4200 .mapsTo(MISCREG_HAIFSR);
4201 InitReg(MISCREG_ESR_EL2)
4202 .hyp().mon()
4203 .mapsTo(MISCREG_HSR);
4204 InitReg(MISCREG_FPEXC32_EL2)
4205 .hyp().mon().mapsTo(MISCREG_FPEXC);
4206 InitReg(MISCREG_AFSR0_EL3)
4207 .mon();
4208 InitReg(MISCREG_AFSR1_EL3)
4209 .mon();
4210 InitReg(MISCREG_ESR_EL3)
4211 .mon();
4212 InitReg(MISCREG_FAR_EL1)
4213 .allPrivileges().exceptUserMode()
4214 .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
4215 InitReg(MISCREG_FAR_EL2)
4216 .hyp().mon()
4217 .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR);
4218 InitReg(MISCREG_HPFAR_EL2)
4219 .hyp().mon()
4220 .mapsTo(MISCREG_HPFAR);
4221 InitReg(MISCREG_FAR_EL3)
4222 .mon();
4223 InitReg(MISCREG_IC_IALLUIS)
4224 .warnNotFail()
4225 .writes(1).exceptUserMode();
4226 InitReg(MISCREG_PAR_EL1)
4227 .allPrivileges().exceptUserMode()
4228 .mapsTo(MISCREG_PAR_NS);
4229 InitReg(MISCREG_IC_IALLU)
4230 .warnNotFail()
4231 .writes(1).exceptUserMode();
4232 InitReg(MISCREG_DC_IVAC_Xt)
4233 .warnNotFail()
4234 .writes(1).exceptUserMode();
4235 InitReg(MISCREG_DC_ISW_Xt)
4236 .warnNotFail()
4237 .writes(1).exceptUserMode();
4238 InitReg(MISCREG_AT_S1E1R_Xt)
4239 .writes(1).exceptUserMode();
4240 InitReg(MISCREG_AT_S1E1W_Xt)
4241 .writes(1).exceptUserMode();
4242 InitReg(MISCREG_AT_S1E0R_Xt)
4243 .writes(1).exceptUserMode();
4244 InitReg(MISCREG_AT_S1E0W_Xt)
4245 .writes(1).exceptUserMode();
4246 InitReg(MISCREG_DC_CSW_Xt)
4247 .warnNotFail()
4248 .writes(1).exceptUserMode();
4249 InitReg(MISCREG_DC_CISW_Xt)
4250 .warnNotFail()
4251 .writes(1).exceptUserMode();
4252 InitReg(MISCREG_DC_ZVA_Xt)
4253 .warnNotFail()
4254 .writes(1).userSecureWrite(0);
4255 InitReg(MISCREG_IC_IVAU_Xt)
4256 .writes(1);
4257 InitReg(MISCREG_DC_CVAC_Xt)
4258 .warnNotFail()
4259 .writes(1);
4260 InitReg(MISCREG_DC_CVAU_Xt)
4261 .warnNotFail()
4262 .writes(1);
4263 InitReg(MISCREG_DC_CIVAC_Xt)
4264 .warnNotFail()
4265 .writes(1);
4266 InitReg(MISCREG_AT_S1E2R_Xt)
4267 .monNonSecureWrite().hypWrite();
4268 InitReg(MISCREG_AT_S1E2W_Xt)
4269 .monNonSecureWrite().hypWrite();
4270 InitReg(MISCREG_AT_S12E1R_Xt)
4271 .hypWrite().monSecureWrite().monNonSecureWrite();
4272 InitReg(MISCREG_AT_S12E1W_Xt)
4273 .hypWrite().monSecureWrite().monNonSecureWrite();
4274 InitReg(MISCREG_AT_S12E0R_Xt)
4275 .hypWrite().monSecureWrite().monNonSecureWrite();
4276 InitReg(MISCREG_AT_S12E0W_Xt)
4277 .hypWrite().monSecureWrite().monNonSecureWrite();
4278 InitReg(MISCREG_AT_S1E3R_Xt)
4279 .monSecureWrite().monNonSecureWrite();
4280 InitReg(MISCREG_AT_S1E3W_Xt)
4281 .monSecureWrite().monNonSecureWrite();
4282 InitReg(MISCREG_TLBI_VMALLE1IS)
4283 .writes(1).exceptUserMode();
4284 InitReg(MISCREG_TLBI_VAE1IS_Xt)
4285 .writes(1).exceptUserMode();
4286 InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
4287 .writes(1).exceptUserMode();
4288 InitReg(MISCREG_TLBI_VAAE1IS_Xt)
4289 .writes(1).exceptUserMode();
4290 InitReg(MISCREG_TLBI_VALE1IS_Xt)
4291 .writes(1).exceptUserMode();
4292 InitReg(MISCREG_TLBI_VAALE1IS_Xt)
4293 .writes(1).exceptUserMode();
4294 InitReg(MISCREG_TLBI_VMALLE1)
4295 .writes(1).exceptUserMode();
4296 InitReg(MISCREG_TLBI_VAE1_Xt)
4297 .writes(1).exceptUserMode();
4298 InitReg(MISCREG_TLBI_ASIDE1_Xt)
4299 .writes(1).exceptUserMode();
4300 InitReg(MISCREG_TLBI_VAAE1_Xt)
4301 .writes(1).exceptUserMode();
4302 InitReg(MISCREG_TLBI_VALE1_Xt)
4303 .writes(1).exceptUserMode();
4304 InitReg(MISCREG_TLBI_VAALE1_Xt)
4305 .writes(1).exceptUserMode();
4306 InitReg(MISCREG_TLBI_IPAS2E1IS_Xt)
4307 .hypWrite().monSecureWrite().monNonSecureWrite();
4308 InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt)
4309 .hypWrite().monSecureWrite().monNonSecureWrite();
4310 InitReg(MISCREG_TLBI_ALLE2IS)
4311 .monNonSecureWrite().hypWrite();
4312 InitReg(MISCREG_TLBI_VAE2IS_Xt)
4313 .monNonSecureWrite().hypWrite();
4314 InitReg(MISCREG_TLBI_ALLE1IS)
4315 .hypWrite().monSecureWrite().monNonSecureWrite();
4316 InitReg(MISCREG_TLBI_VALE2IS_Xt)
4317 .monNonSecureWrite().hypWrite();
4318 InitReg(MISCREG_TLBI_VMALLS12E1IS)
4319 .hypWrite().monSecureWrite().monNonSecureWrite();
4320 InitReg(MISCREG_TLBI_IPAS2E1_Xt)
4321 .hypWrite().monSecureWrite().monNonSecureWrite();
4322 InitReg(MISCREG_TLBI_IPAS2LE1_Xt)
4323 .hypWrite().monSecureWrite().monNonSecureWrite();
4324 InitReg(MISCREG_TLBI_ALLE2)
4325 .monNonSecureWrite().hypWrite();
4326 InitReg(MISCREG_TLBI_VAE2_Xt)
4327 .monNonSecureWrite().hypWrite();
4328 InitReg(MISCREG_TLBI_ALLE1)
4329 .hypWrite().monSecureWrite().monNonSecureWrite();
4330 InitReg(MISCREG_TLBI_VALE2_Xt)
4331 .monNonSecureWrite().hypWrite();
4332 InitReg(MISCREG_TLBI_VMALLS12E1)
4333 .hypWrite().monSecureWrite().monNonSecureWrite();
4334 InitReg(MISCREG_TLBI_ALLE3IS)
4335 .monSecureWrite().monNonSecureWrite();
4336 InitReg(MISCREG_TLBI_VAE3IS_Xt)
4337 .monSecureWrite().monNonSecureWrite();
4338 InitReg(MISCREG_TLBI_VALE3IS_Xt)
4339 .monSecureWrite().monNonSecureWrite();
4340 InitReg(MISCREG_TLBI_ALLE3)
4341 .monSecureWrite().monNonSecureWrite();
4342 InitReg(MISCREG_TLBI_VAE3_Xt)
4343 .monSecureWrite().monNonSecureWrite();
4344 InitReg(MISCREG_TLBI_VALE3_Xt)
4345 .monSecureWrite().monNonSecureWrite();
4346 InitReg(MISCREG_PMINTENSET_EL1)
4347 .allPrivileges().exceptUserMode()
4348 .mapsTo(MISCREG_PMINTENSET);
4349 InitReg(MISCREG_PMINTENCLR_EL1)
4350 .allPrivileges().exceptUserMode()
4351 .mapsTo(MISCREG_PMINTENCLR);
4352 InitReg(MISCREG_PMCR_EL0)
4353 .allPrivileges()
4354 .mapsTo(MISCREG_PMCR);
4355 InitReg(MISCREG_PMCNTENSET_EL0)
4356 .allPrivileges()
4357 .mapsTo(MISCREG_PMCNTENSET);
4358 InitReg(MISCREG_PMCNTENCLR_EL0)
4359 .allPrivileges()
4360 .mapsTo(MISCREG_PMCNTENCLR);
4361 InitReg(MISCREG_PMOVSCLR_EL0)
4362 .allPrivileges();
4363 // .mapsTo(MISCREG_PMOVSCLR);
4364 InitReg(MISCREG_PMSWINC_EL0)
4365 .writes(1).user()
4366 .mapsTo(MISCREG_PMSWINC);
4367 InitReg(MISCREG_PMSELR_EL0)
4368 .allPrivileges()
4369 .mapsTo(MISCREG_PMSELR);
4370 InitReg(MISCREG_PMCEID0_EL0)
4371 .reads(1).user()
4372 .mapsTo(MISCREG_PMCEID0);
4373 InitReg(MISCREG_PMCEID1_EL0)
4374 .reads(1).user()
4375 .mapsTo(MISCREG_PMCEID1);
4376 InitReg(MISCREG_PMCCNTR_EL0)
4377 .allPrivileges()
4378 .mapsTo(MISCREG_PMCCNTR);
4379 InitReg(MISCREG_PMXEVTYPER_EL0)
4380 .allPrivileges()
4381 .mapsTo(MISCREG_PMXEVTYPER);
4382 InitReg(MISCREG_PMCCFILTR_EL0)
4383 .allPrivileges();
4384 InitReg(MISCREG_PMXEVCNTR_EL0)
4385 .allPrivileges()
4386 .mapsTo(MISCREG_PMXEVCNTR);
4387 InitReg(MISCREG_PMUSERENR_EL0)
4388 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
4389 .mapsTo(MISCREG_PMUSERENR);
4390 InitReg(MISCREG_PMOVSSET_EL0)
4391 .allPrivileges()
4392 .mapsTo(MISCREG_PMOVSSET);
4393 InitReg(MISCREG_MAIR_EL1)
4394 .allPrivileges().exceptUserMode()
4395 .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
4396 InitReg(MISCREG_AMAIR_EL1)
4397 .allPrivileges().exceptUserMode()
4398 .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
4399 InitReg(MISCREG_MAIR_EL2)
4400 .hyp().mon()
4401 .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1);
4402 InitReg(MISCREG_AMAIR_EL2)
4403 .hyp().mon()
4404 .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1);
4405 InitReg(MISCREG_MAIR_EL3)
4406 .mon();
4407 InitReg(MISCREG_AMAIR_EL3)
4408 .mon();
4409 InitReg(MISCREG_L2CTLR_EL1)
4410 .allPrivileges().exceptUserMode();
4411 InitReg(MISCREG_L2ECTLR_EL1)
4412 .allPrivileges().exceptUserMode();
4413 InitReg(MISCREG_VBAR_EL1)
4414 .allPrivileges().exceptUserMode()
4415 .mapsTo(MISCREG_VBAR_NS);
4416 InitReg(MISCREG_RVBAR_EL1)
4417 .allPrivileges().exceptUserMode().writes(0);
4418 InitReg(MISCREG_ISR_EL1)
4419 .allPrivileges().exceptUserMode().writes(0);
4420 InitReg(MISCREG_VBAR_EL2)
4421 .hyp().mon()
4422 .res0(0x7ff)
4423 .mapsTo(MISCREG_HVBAR);
4424 InitReg(MISCREG_RVBAR_EL2)
4425 .mon().hyp().writes(0);
4426 InitReg(MISCREG_VBAR_EL3)
4427 .mon();
4428 InitReg(MISCREG_RVBAR_EL3)
4429 .mon().writes(0);
4430 InitReg(MISCREG_RMR_EL3)
4431 .mon();
4432 InitReg(MISCREG_CONTEXTIDR_EL1)
4433 .allPrivileges().exceptUserMode()
4434 .mapsTo(MISCREG_CONTEXTIDR_NS);
4435 InitReg(MISCREG_TPIDR_EL1)
4436 .allPrivileges().exceptUserMode()
4437 .mapsTo(MISCREG_TPIDRPRW_NS);
4438 InitReg(MISCREG_TPIDR_EL0)
4439 .allPrivileges()
4440 .mapsTo(MISCREG_TPIDRURW_NS);
4441 InitReg(MISCREG_TPIDRRO_EL0)
4442 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
4443 .mapsTo(MISCREG_TPIDRURO_NS);
4444 InitReg(MISCREG_TPIDR_EL2)
4445 .hyp().mon()
4446 .mapsTo(MISCREG_HTPIDR);
4447 InitReg(MISCREG_TPIDR_EL3)
4448 .mon();
4449 InitReg(MISCREG_CNTKCTL_EL1)
4450 .allPrivileges().exceptUserMode()
4451 .mapsTo(MISCREG_CNTKCTL);
4452 InitReg(MISCREG_CNTFRQ_EL0)
4453 .reads(1)
4454 .highest(system)
4455 .privSecureWrite(aarch32EL3)
4456 .mapsTo(MISCREG_CNTFRQ);
4457 InitReg(MISCREG_CNTPCT_EL0)
4458 .reads(1)
4459 .mapsTo(MISCREG_CNTPCT); /* 64b */
4460 InitReg(MISCREG_CNTVCT_EL0)
4461 .unverifiable()
4462 .reads(1)
4463 .mapsTo(MISCREG_CNTVCT); /* 64b */
4464 InitReg(MISCREG_CNTP_TVAL_EL0)
4465 .allPrivileges()
4466 .mapsTo(MISCREG_CNTP_TVAL_NS);
4467 InitReg(MISCREG_CNTP_CTL_EL0)
4468 .allPrivileges()
4469 .mapsTo(MISCREG_CNTP_CTL_NS);
4470 InitReg(MISCREG_CNTP_CVAL_EL0)
4471 .allPrivileges()
4472 .mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b */
4473 InitReg(MISCREG_CNTV_TVAL_EL0)
4474 .allPrivileges()
4475 .mapsTo(MISCREG_CNTV_TVAL);
4476 InitReg(MISCREG_CNTV_CTL_EL0)
4477 .allPrivileges()
4478 .mapsTo(MISCREG_CNTV_CTL);
4479 InitReg(MISCREG_CNTV_CVAL_EL0)
4480 .allPrivileges()
4481 .mapsTo(MISCREG_CNTV_CVAL); /* 64b */
4482 InitReg(MISCREG_PMEVCNTR0_EL0)
4483 .allPrivileges();
4484 // .mapsTo(MISCREG_PMEVCNTR0);
4485 InitReg(MISCREG_PMEVCNTR1_EL0)
4486 .allPrivileges();
4487 // .mapsTo(MISCREG_PMEVCNTR1);
4488 InitReg(MISCREG_PMEVCNTR2_EL0)
4489 .allPrivileges();
4490 // .mapsTo(MISCREG_PMEVCNTR2);
4491 InitReg(MISCREG_PMEVCNTR3_EL0)
4492 .allPrivileges();
4493 // .mapsTo(MISCREG_PMEVCNTR3);
4494 InitReg(MISCREG_PMEVCNTR4_EL0)
4495 .allPrivileges();
4496 // .mapsTo(MISCREG_PMEVCNTR4);
4497 InitReg(MISCREG_PMEVCNTR5_EL0)
4498 .allPrivileges();
4499 // .mapsTo(MISCREG_PMEVCNTR5);
4500 InitReg(MISCREG_PMEVTYPER0_EL0)
4501 .allPrivileges();
4502 // .mapsTo(MISCREG_PMEVTYPER0);
4503 InitReg(MISCREG_PMEVTYPER1_EL0)
4504 .allPrivileges();
4505 // .mapsTo(MISCREG_PMEVTYPER1);
4506 InitReg(MISCREG_PMEVTYPER2_EL0)
4507 .allPrivileges();
4508 // .mapsTo(MISCREG_PMEVTYPER2);
4509 InitReg(MISCREG_PMEVTYPER3_EL0)
4510 .allPrivileges();
4511 // .mapsTo(MISCREG_PMEVTYPER3);
4512 InitReg(MISCREG_PMEVTYPER4_EL0)
4513 .allPrivileges();
4514 // .mapsTo(MISCREG_PMEVTYPER4);
4515 InitReg(MISCREG_PMEVTYPER5_EL0)
4516 .allPrivileges();
4517 // .mapsTo(MISCREG_PMEVTYPER5);
4518 InitReg(MISCREG_CNTVOFF_EL2)
4519 .hyp().mon()
4520 .mapsTo(MISCREG_CNTVOFF); /* 64b */
4521 InitReg(MISCREG_CNTHCTL_EL2)
4522 .mon().hyp()
4523 .mapsTo(MISCREG_CNTHCTL);
4524 InitReg(MISCREG_CNTHP_TVAL_EL2)
4525 .mon().hyp()
4526 .mapsTo(MISCREG_CNTHP_TVAL);
4527 InitReg(MISCREG_CNTHP_CTL_EL2)
4528 .mon().hyp()
4529 .mapsTo(MISCREG_CNTHP_CTL);
4530 InitReg(MISCREG_CNTHP_CVAL_EL2)
4531 .mon().hyp()
4532 .mapsTo(MISCREG_CNTHP_CVAL); /* 64b */
4533 InitReg(MISCREG_CNTPS_TVAL_EL1)
4534 .mon().privSecure();
4535 InitReg(MISCREG_CNTPS_CTL_EL1)
4536 .mon().privSecure();
4537 InitReg(MISCREG_CNTPS_CVAL_EL1)
4538 .mon().privSecure();
4539 InitReg(MISCREG_IL1DATA0_EL1)
4540 .allPrivileges().exceptUserMode();
4541 InitReg(MISCREG_IL1DATA1_EL1)
4542 .allPrivileges().exceptUserMode();
4543 InitReg(MISCREG_IL1DATA2_EL1)
4544 .allPrivileges().exceptUserMode();
4545 InitReg(MISCREG_IL1DATA3_EL1)
4546 .allPrivileges().exceptUserMode();
4547 InitReg(MISCREG_DL1DATA0_EL1)
4548 .allPrivileges().exceptUserMode();
4549 InitReg(MISCREG_DL1DATA1_EL1)
4550 .allPrivileges().exceptUserMode();
4551 InitReg(MISCREG_DL1DATA2_EL1)
4552 .allPrivileges().exceptUserMode();
4553 InitReg(MISCREG_DL1DATA3_EL1)
4554 .allPrivileges().exceptUserMode();
4555 InitReg(MISCREG_DL1DATA4_EL1)
4556 .allPrivileges().exceptUserMode();
4557 InitReg(MISCREG_L2ACTLR_EL1)
4558 .allPrivileges().exceptUserMode();
4559 InitReg(MISCREG_CPUACTLR_EL1)
4560 .allPrivileges().exceptUserMode();
4561 InitReg(MISCREG_CPUECTLR_EL1)
4562 .allPrivileges().exceptUserMode();
4563 InitReg(MISCREG_CPUMERRSR_EL1)
4564 .allPrivileges().exceptUserMode();
4565 InitReg(MISCREG_L2MERRSR_EL1)
4566 .unimplemented()
4567 .warnNotFail()
4568 .allPrivileges().exceptUserMode();
4569 InitReg(MISCREG_CBAR_EL1)
4570 .allPrivileges().exceptUserMode().writes(0);
4571 InitReg(MISCREG_CONTEXTIDR_EL2)
4572 .mon().hyp();
4573
4574 // GICv3 AArch64
4575 InitReg(MISCREG_ICC_PMR_EL1)
4576 .res0(0xffffff00) // [31:8]
4577 .allPrivileges().exceptUserMode()
4578 .mapsTo(MISCREG_ICC_PMR);
4579 InitReg(MISCREG_ICC_IAR0_EL1)
4580 .allPrivileges().exceptUserMode().writes(0)
4581 .mapsTo(MISCREG_ICC_IAR0);
4582 InitReg(MISCREG_ICC_EOIR0_EL1)
4583 .allPrivileges().exceptUserMode().reads(0)
4584 .mapsTo(MISCREG_ICC_EOIR0);
4585 InitReg(MISCREG_ICC_HPPIR0_EL1)
4586 .allPrivileges().exceptUserMode().writes(0)
4587 .mapsTo(MISCREG_ICC_HPPIR0);
4588 InitReg(MISCREG_ICC_BPR0_EL1)
4589 .res0(0xfffffff8) // [31:3]
4590 .allPrivileges().exceptUserMode()
4591 .mapsTo(MISCREG_ICC_BPR0);
4592 InitReg(MISCREG_ICC_AP0R0_EL1)
4593 .allPrivileges().exceptUserMode()
4594 .mapsTo(MISCREG_ICC_AP0R0);
4595 InitReg(MISCREG_ICC_AP0R1_EL1)
4596 .allPrivileges().exceptUserMode()
4597 .mapsTo(MISCREG_ICC_AP0R1);
4598 InitReg(MISCREG_ICC_AP0R2_EL1)
4599 .allPrivileges().exceptUserMode()
4600 .mapsTo(MISCREG_ICC_AP0R2);
4601 InitReg(MISCREG_ICC_AP0R3_EL1)
4602 .allPrivileges().exceptUserMode()
4603 .mapsTo(MISCREG_ICC_AP0R3);
4604 InitReg(MISCREG_ICC_AP1R0_EL1)
4605 .banked64()
4606 .mapsTo(MISCREG_ICC_AP1R0);
4607 InitReg(MISCREG_ICC_AP1R0_EL1_NS)
4608 .bankedChild()
4609 .allPrivileges().exceptUserMode()
4610 .mapsTo(MISCREG_ICC_AP1R0_NS);
4611 InitReg(MISCREG_ICC_AP1R0_EL1_S)
4612 .bankedChild()
4613 .allPrivileges().exceptUserMode()
4614 .mapsTo(MISCREG_ICC_AP1R0_S);
4615 InitReg(MISCREG_ICC_AP1R1_EL1)
4616 .banked64()
4617 .mapsTo(MISCREG_ICC_AP1R1);
4618 InitReg(MISCREG_ICC_AP1R1_EL1_NS)
4619 .bankedChild()
4620 .allPrivileges().exceptUserMode()
4621 .mapsTo(MISCREG_ICC_AP1R1_NS);
4622 InitReg(MISCREG_ICC_AP1R1_EL1_S)
4623 .bankedChild()
4624 .allPrivileges().exceptUserMode()
4625 .mapsTo(MISCREG_ICC_AP1R1_S);
4626 InitReg(MISCREG_ICC_AP1R2_EL1)
4627 .banked64()
4628 .mapsTo(MISCREG_ICC_AP1R2);
4629 InitReg(MISCREG_ICC_AP1R2_EL1_NS)
4630 .bankedChild()
4631 .allPrivileges().exceptUserMode()
4632 .mapsTo(MISCREG_ICC_AP1R2_NS);
4633 InitReg(MISCREG_ICC_AP1R2_EL1_S)
4634 .bankedChild()
4635 .allPrivileges().exceptUserMode()
4636 .mapsTo(MISCREG_ICC_AP1R2_S);
4637 InitReg(MISCREG_ICC_AP1R3_EL1)
4638 .banked64()
4639 .mapsTo(MISCREG_ICC_AP1R3);
4640 InitReg(MISCREG_ICC_AP1R3_EL1_NS)
4641 .bankedChild()
4642 .allPrivileges().exceptUserMode()
4643 .mapsTo(MISCREG_ICC_AP1R3_NS);
4644 InitReg(MISCREG_ICC_AP1R3_EL1_S)
4645 .bankedChild()
4646 .allPrivileges().exceptUserMode()
4647 .mapsTo(MISCREG_ICC_AP1R3_S);
4648 InitReg(MISCREG_ICC_DIR_EL1)
4649 .res0(0xFF000000) // [31:24]
4650 .allPrivileges().exceptUserMode().reads(0)
4651 .mapsTo(MISCREG_ICC_DIR);
4652 InitReg(MISCREG_ICC_RPR_EL1)
4653 .allPrivileges().exceptUserMode().writes(0)
4654 .mapsTo(MISCREG_ICC_RPR);
4655 InitReg(MISCREG_ICC_SGI1R_EL1)
4656 .allPrivileges().exceptUserMode().reads(0)
4657 .mapsTo(MISCREG_ICC_SGI1R);
4658 InitReg(MISCREG_ICC_ASGI1R_EL1)
4659 .allPrivileges().exceptUserMode().reads(0)
4660 .mapsTo(MISCREG_ICC_ASGI1R);
4661 InitReg(MISCREG_ICC_SGI0R_EL1)
4662 .allPrivileges().exceptUserMode().reads(0)
4663 .mapsTo(MISCREG_ICC_SGI0R);
4664 InitReg(MISCREG_ICC_IAR1_EL1)
4665 .allPrivileges().exceptUserMode().writes(0)
4666 .mapsTo(MISCREG_ICC_IAR1);
4667 InitReg(MISCREG_ICC_EOIR1_EL1)
4668 .res0(0xFF000000) // [31:24]
4669 .allPrivileges().exceptUserMode().reads(0)
4670 .mapsTo(MISCREG_ICC_EOIR1);
4671 InitReg(MISCREG_ICC_HPPIR1_EL1)
4672 .allPrivileges().exceptUserMode().writes(0)
4673 .mapsTo(MISCREG_ICC_HPPIR1);
4674 InitReg(MISCREG_ICC_BPR1_EL1)
4675 .banked64()
4676 .mapsTo(MISCREG_ICC_BPR1);
4677 InitReg(MISCREG_ICC_BPR1_EL1_NS)
4678 .bankedChild()
4679 .res0(0xfffffff8) // [31:3]
4680 .allPrivileges().exceptUserMode()
4681 .mapsTo(MISCREG_ICC_BPR1_NS);
4682 InitReg(MISCREG_ICC_BPR1_EL1_S)
4683 .bankedChild()
4684 .res0(0xfffffff8) // [31:3]
4685 .secure().exceptUserMode()
4686 .mapsTo(MISCREG_ICC_BPR1_S);
4687 InitReg(MISCREG_ICC_CTLR_EL1)
4688 .banked64()
4689 .mapsTo(MISCREG_ICC_CTLR);
4690 InitReg(MISCREG_ICC_CTLR_EL1_NS)
4691 .bankedChild()
4692 .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
4693 .allPrivileges().exceptUserMode()
4694 .mapsTo(MISCREG_ICC_CTLR_NS);
4695 InitReg(MISCREG_ICC_CTLR_EL1_S)
4696 .bankedChild()
4697 .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
4698 .secure().exceptUserMode()
4699 .mapsTo(MISCREG_ICC_CTLR_S);
4700 InitReg(MISCREG_ICC_SRE_EL1)
4701 .banked()
4702 .mapsTo(MISCREG_ICC_SRE);
4703 InitReg(MISCREG_ICC_SRE_EL1_NS)
4704 .bankedChild()
4705 .res0(0xFFFFFFF8) // [31:3]
4706 .allPrivileges().exceptUserMode()
4707 .mapsTo(MISCREG_ICC_SRE_NS);
4708 InitReg(MISCREG_ICC_SRE_EL1_S)
4709 .bankedChild()
4710 .res0(0xFFFFFFF8) // [31:3]
4711 .secure().exceptUserMode()
4712 .mapsTo(MISCREG_ICC_SRE_S);
4713 InitReg(MISCREG_ICC_IGRPEN0_EL1)
4714 .res0(0xFFFFFFFE) // [31:1]
4715 .allPrivileges().exceptUserMode()
4716 .mapsTo(MISCREG_ICC_IGRPEN0);
4717 InitReg(MISCREG_ICC_IGRPEN1_EL1)
4718 .banked64()
4719 .mapsTo(MISCREG_ICC_IGRPEN1);
4720 InitReg(MISCREG_ICC_IGRPEN1_EL1_NS)
4721 .bankedChild()
4722 .res0(0xFFFFFFFE) // [31:1]
4723 .allPrivileges().exceptUserMode()
4724 .mapsTo(MISCREG_ICC_IGRPEN1_NS);
4725 InitReg(MISCREG_ICC_IGRPEN1_EL1_S)
4726 .bankedChild()
4727 .res0(0xFFFFFFFE) // [31:1]
4728 .secure().exceptUserMode()
4729 .mapsTo(MISCREG_ICC_IGRPEN1_S);
4730 InitReg(MISCREG_ICC_SRE_EL2)
4731 .hyp().mon()
4732 .mapsTo(MISCREG_ICC_HSRE);
4733 InitReg(MISCREG_ICC_CTLR_EL3)
4734 .allPrivileges().exceptUserMode()
4735 .mapsTo(MISCREG_ICC_MCTLR);
4736 InitReg(MISCREG_ICC_SRE_EL3)
4737 .allPrivileges().exceptUserMode()
4738 .mapsTo(MISCREG_ICC_MSRE);
4739 InitReg(MISCREG_ICC_IGRPEN1_EL3)
4740 .allPrivileges().exceptUserMode()
4741 .mapsTo(MISCREG_ICC_MGRPEN1);
4742
4743 InitReg(MISCREG_ICH_AP0R0_EL2)
4744 .hyp().mon()
4745 .mapsTo(MISCREG_ICH_AP0R0);
4746 InitReg(MISCREG_ICH_AP0R1_EL2)
4747 .hyp().mon()
4748 .unimplemented()
4749 .mapsTo(MISCREG_ICH_AP0R1);
4750 InitReg(MISCREG_ICH_AP0R2_EL2)
4751 .hyp().mon()
4752 .unimplemented()
4753 .mapsTo(MISCREG_ICH_AP0R2);
4754 InitReg(MISCREG_ICH_AP0R3_EL2)
4755 .hyp().mon()
4756 .unimplemented()
4757 .mapsTo(MISCREG_ICH_AP0R3);
4758 InitReg(MISCREG_ICH_AP1R0_EL2)
4759 .hyp().mon()
4760 .mapsTo(MISCREG_ICH_AP1R0);
4761 InitReg(MISCREG_ICH_AP1R1_EL2)
4762 .hyp().mon()
4763 .unimplemented()
4764 .mapsTo(MISCREG_ICH_AP1R1);
4765 InitReg(MISCREG_ICH_AP1R2_EL2)
4766 .hyp().mon()
4767 .unimplemented()
4768 .mapsTo(MISCREG_ICH_AP1R2);
4769 InitReg(MISCREG_ICH_AP1R3_EL2)
4770 .hyp().mon()
4771 .unimplemented()
4772 .mapsTo(MISCREG_ICH_AP1R3);
4773 InitReg(MISCREG_ICH_HCR_EL2)
4774 .hyp().mon()
4775 .mapsTo(MISCREG_ICH_HCR);
4776 InitReg(MISCREG_ICH_VTR_EL2)
4777 .hyp().mon().writes(0)
4778 .mapsTo(MISCREG_ICH_VTR);
4779 InitReg(MISCREG_ICH_MISR_EL2)
4780 .hyp().mon().writes(0)
4781 .mapsTo(MISCREG_ICH_MISR);
4782 InitReg(MISCREG_ICH_EISR_EL2)
4783 .hyp().mon().writes(0)
4784 .mapsTo(MISCREG_ICH_EISR);
4785 InitReg(MISCREG_ICH_ELRSR_EL2)
4786 .hyp().mon().writes(0)
4787 .mapsTo(MISCREG_ICH_ELRSR);
4788 InitReg(MISCREG_ICH_VMCR_EL2)
4789 .hyp().mon()
4790 .mapsTo(MISCREG_ICH_VMCR);
4791 InitReg(MISCREG_ICH_LR0_EL2)
4792 .hyp().mon()
4793 .allPrivileges().exceptUserMode();
4794 InitReg(MISCREG_ICH_LR1_EL2)
4795 .hyp().mon()
4796 .allPrivileges().exceptUserMode();
4797 InitReg(MISCREG_ICH_LR2_EL2)
4798 .hyp().mon()
4799 .allPrivileges().exceptUserMode();
4800 InitReg(MISCREG_ICH_LR3_EL2)
4801 .hyp().mon()
4802 .allPrivileges().exceptUserMode();
4803 InitReg(MISCREG_ICH_LR4_EL2)
4804 .hyp().mon()
4805 .allPrivileges().exceptUserMode();
4806 InitReg(MISCREG_ICH_LR5_EL2)
4807 .hyp().mon()
4808 .allPrivileges().exceptUserMode();
4809 InitReg(MISCREG_ICH_LR6_EL2)
4810 .hyp().mon()
4811 .allPrivileges().exceptUserMode();
4812 InitReg(MISCREG_ICH_LR7_EL2)
4813 .hyp().mon()
4814 .allPrivileges().exceptUserMode();
4815 InitReg(MISCREG_ICH_LR8_EL2)
4816 .hyp().mon()
4817 .allPrivileges().exceptUserMode();
4818 InitReg(MISCREG_ICH_LR9_EL2)
4819 .hyp().mon()
4820 .allPrivileges().exceptUserMode();
4821 InitReg(MISCREG_ICH_LR10_EL2)
4822 .hyp().mon()
4823 .allPrivileges().exceptUserMode();
4824 InitReg(MISCREG_ICH_LR11_EL2)
4825 .hyp().mon()
4826 .allPrivileges().exceptUserMode();
4827 InitReg(MISCREG_ICH_LR12_EL2)
4828 .hyp().mon()
4829 .allPrivileges().exceptUserMode();
4830 InitReg(MISCREG_ICH_LR13_EL2)
4831 .hyp().mon()
4832 .allPrivileges().exceptUserMode();
4833 InitReg(MISCREG_ICH_LR14_EL2)
4834 .hyp().mon()
4835 .allPrivileges().exceptUserMode();
4836 InitReg(MISCREG_ICH_LR15_EL2)
4837 .hyp().mon()
4838 .allPrivileges().exceptUserMode();
4839
4840 // GICv3 AArch32
4841 InitReg(MISCREG_ICC_AP0R0)
4842 .allPrivileges().exceptUserMode();
4843 InitReg(MISCREG_ICC_AP0R1)
4844 .allPrivileges().exceptUserMode();
4845 InitReg(MISCREG_ICC_AP0R2)
4846 .allPrivileges().exceptUserMode();
4847 InitReg(MISCREG_ICC_AP0R3)
4848 .allPrivileges().exceptUserMode();
4849 InitReg(MISCREG_ICC_AP1R0)
4850 .allPrivileges().exceptUserMode();
4851 InitReg(MISCREG_ICC_AP1R0_NS)
4852 .allPrivileges().exceptUserMode();
4853 InitReg(MISCREG_ICC_AP1R0_S)
4854 .allPrivileges().exceptUserMode();
4855 InitReg(MISCREG_ICC_AP1R1)
4856 .allPrivileges().exceptUserMode();
4857 InitReg(MISCREG_ICC_AP1R1_NS)
4858 .allPrivileges().exceptUserMode();
4859 InitReg(MISCREG_ICC_AP1R1_S)
4860 .allPrivileges().exceptUserMode();
4861 InitReg(MISCREG_ICC_AP1R2)
4862 .allPrivileges().exceptUserMode();
4863 InitReg(MISCREG_ICC_AP1R2_NS)
4864 .allPrivileges().exceptUserMode();
4865 InitReg(MISCREG_ICC_AP1R2_S)
4866 .allPrivileges().exceptUserMode();
4867 InitReg(MISCREG_ICC_AP1R3)
4868 .allPrivileges().exceptUserMode();
4869 InitReg(MISCREG_ICC_AP1R3_NS)
4870 .allPrivileges().exceptUserMode();
4871 InitReg(MISCREG_ICC_AP1R3_S)
4872 .allPrivileges().exceptUserMode();
4873 InitReg(MISCREG_ICC_ASGI1R)
4874 .allPrivileges().exceptUserMode().reads(0);
4875 InitReg(MISCREG_ICC_BPR0)
4876 .allPrivileges().exceptUserMode();
4877 InitReg(MISCREG_ICC_BPR1)
4878 .allPrivileges().exceptUserMode();
4879 InitReg(MISCREG_ICC_BPR1_NS)
4880 .allPrivileges().exceptUserMode();
4881 InitReg(MISCREG_ICC_BPR1_S)
4882 .allPrivileges().exceptUserMode();
4883 InitReg(MISCREG_ICC_CTLR)
4884 .allPrivileges().exceptUserMode();
4885 InitReg(MISCREG_ICC_CTLR_NS)
4886 .allPrivileges().exceptUserMode();
4887 InitReg(MISCREG_ICC_CTLR_S)
4888 .allPrivileges().exceptUserMode();
4889 InitReg(MISCREG_ICC_DIR)
4890 .allPrivileges().exceptUserMode().reads(0);
4891 InitReg(MISCREG_ICC_EOIR0)
4892 .allPrivileges().exceptUserMode().reads(0);
4893 InitReg(MISCREG_ICC_EOIR1)
4894 .allPrivileges().exceptUserMode().reads(0);
4895 InitReg(MISCREG_ICC_HPPIR0)
4896 .allPrivileges().exceptUserMode().writes(0);
4897 InitReg(MISCREG_ICC_HPPIR1)
4898 .allPrivileges().exceptUserMode().writes(0);
4899 InitReg(MISCREG_ICC_HSRE)
4900 .allPrivileges().exceptUserMode();
4901 InitReg(MISCREG_ICC_IAR0)
4902 .allPrivileges().exceptUserMode().writes(0);
4903 InitReg(MISCREG_ICC_IAR1)
4904 .allPrivileges().exceptUserMode().writes(0);
4905 InitReg(MISCREG_ICC_IGRPEN0)
4906 .allPrivileges().exceptUserMode();
4907 InitReg(MISCREG_ICC_IGRPEN1)
4908 .allPrivileges().exceptUserMode();
4909 InitReg(MISCREG_ICC_IGRPEN1_NS)
4910 .allPrivileges().exceptUserMode();
4911 InitReg(MISCREG_ICC_IGRPEN1_S)
4912 .allPrivileges().exceptUserMode();
4913 InitReg(MISCREG_ICC_MCTLR)
4914 .allPrivileges().exceptUserMode();
4915 InitReg(MISCREG_ICC_MGRPEN1)
4916 .allPrivileges().exceptUserMode();
4917 InitReg(MISCREG_ICC_MSRE)
4918 .allPrivileges().exceptUserMode();
4919 InitReg(MISCREG_ICC_PMR)
4920 .allPrivileges().exceptUserMode();
4921 InitReg(MISCREG_ICC_RPR)
4922 .allPrivileges().exceptUserMode().writes(0);
4923 InitReg(MISCREG_ICC_SGI0R)
4924 .allPrivileges().exceptUserMode().reads(0);
4925 InitReg(MISCREG_ICC_SGI1R)
4926 .allPrivileges().exceptUserMode().reads(0);
4927 InitReg(MISCREG_ICC_SRE)
4928 .allPrivileges().exceptUserMode();
4929 InitReg(MISCREG_ICC_SRE_NS)
4930 .allPrivileges().exceptUserMode();
4931 InitReg(MISCREG_ICC_SRE_S)
4932 .allPrivileges().exceptUserMode();
4933
4934 InitReg(MISCREG_ICH_AP0R0)
4935 .hyp().mon();
4936 InitReg(MISCREG_ICH_AP0R1)
4937 .hyp().mon();
4938 InitReg(MISCREG_ICH_AP0R2)
4939 .hyp().mon();
4940 InitReg(MISCREG_ICH_AP0R3)
4941 .hyp().mon();
4942 InitReg(MISCREG_ICH_AP1R0)
4943 .hyp().mon();
4944 InitReg(MISCREG_ICH_AP1R1)
4945 .hyp().mon();
4946 InitReg(MISCREG_ICH_AP1R2)
4947 .hyp().mon();
4948 InitReg(MISCREG_ICH_AP1R3)
4949 .hyp().mon();
4950 InitReg(MISCREG_ICH_HCR)
4951 .hyp().mon();
4952 InitReg(MISCREG_ICH_VTR)
4953 .hyp().mon().writes(0);
4954 InitReg(MISCREG_ICH_MISR)
4955 .hyp().mon().writes(0);
4956 InitReg(MISCREG_ICH_EISR)
4957 .hyp().mon().writes(0);
4958 InitReg(MISCREG_ICH_ELRSR)
4959 .hyp().mon().writes(0);
4960 InitReg(MISCREG_ICH_VMCR)
4961 .hyp().mon();
4962 InitReg(MISCREG_ICH_LR0)
4963 .hyp().mon();
4964 InitReg(MISCREG_ICH_LR1)
4965 .hyp().mon();
4966 InitReg(MISCREG_ICH_LR2)
4967 .hyp().mon();
4968 InitReg(MISCREG_ICH_LR3)
4969 .hyp().mon();
4970 InitReg(MISCREG_ICH_LR4)
4971 .hyp().mon();
4972 InitReg(MISCREG_ICH_LR5)
4973 .hyp().mon();
4974 InitReg(MISCREG_ICH_LR6)
4975 .hyp().mon();
4976 InitReg(MISCREG_ICH_LR7)
4977 .hyp().mon();
4978 InitReg(MISCREG_ICH_LR8)
4979 .hyp().mon();
4980 InitReg(MISCREG_ICH_LR9)
4981 .hyp().mon();
4982 InitReg(MISCREG_ICH_LR10)
4983 .hyp().mon();
4984 InitReg(MISCREG_ICH_LR11)
4985 .hyp().mon();
4986 InitReg(MISCREG_ICH_LR12)
4987 .hyp().mon();
4988 InitReg(MISCREG_ICH_LR13)
4989 .hyp().mon();
4990 InitReg(MISCREG_ICH_LR14)
4991 .hyp().mon();
4992 InitReg(MISCREG_ICH_LR15)
4993 .hyp().mon();
4994 InitReg(MISCREG_ICH_LRC0)
4995 .mapsTo(MISCREG_ICH_LR0)
4996 .hyp().mon();
4997 InitReg(MISCREG_ICH_LRC1)
4998 .mapsTo(MISCREG_ICH_LR1)
4999 .hyp().mon();
5000 InitReg(MISCREG_ICH_LRC2)
5001 .mapsTo(MISCREG_ICH_LR2)
5002 .hyp().mon();
5003 InitReg(MISCREG_ICH_LRC3)
5004 .mapsTo(MISCREG_ICH_LR3)
5005 .hyp().mon();
5006 InitReg(MISCREG_ICH_LRC4)
5007 .mapsTo(MISCREG_ICH_LR4)
5008 .hyp().mon();
5009 InitReg(MISCREG_ICH_LRC5)
5010 .mapsTo(MISCREG_ICH_LR5)
5011 .hyp().mon();
5012 InitReg(MISCREG_ICH_LRC6)
5013 .mapsTo(MISCREG_ICH_LR6)
5014 .hyp().mon();
5015 InitReg(MISCREG_ICH_LRC7)
5016 .mapsTo(MISCREG_ICH_LR7)
5017 .hyp().mon();
5018 InitReg(MISCREG_ICH_LRC8)
5019 .mapsTo(MISCREG_ICH_LR8)
5020 .hyp().mon();
5021 InitReg(MISCREG_ICH_LRC9)
5022 .mapsTo(MISCREG_ICH_LR9)
5023 .hyp().mon();
5024 InitReg(MISCREG_ICH_LRC10)
5025 .mapsTo(MISCREG_ICH_LR10)
5026 .hyp().mon();
5027 InitReg(MISCREG_ICH_LRC11)
5028 .mapsTo(MISCREG_ICH_LR11)
5029 .hyp().mon();
5030 InitReg(MISCREG_ICH_LRC12)
5031 .mapsTo(MISCREG_ICH_LR12)
5032 .hyp().mon();
5033 InitReg(MISCREG_ICH_LRC13)
5034 .mapsTo(MISCREG_ICH_LR13)
5035 .hyp().mon();
5036 InitReg(MISCREG_ICH_LRC14)
5037 .mapsTo(MISCREG_ICH_LR14)
5038 .hyp().mon();
5039 InitReg(MISCREG_ICH_LRC15)
5040 .mapsTo(MISCREG_ICH_LR15)
5041 .hyp().mon();
5042
5043 InitReg(MISCREG_CNTHV_CTL_EL2)
5044 .mon().hyp();
5045 InitReg(MISCREG_CNTHV_CVAL_EL2)
5046 .mon().hyp();
5047 InitReg(MISCREG_CNTHV_TVAL_EL2)
5048 .mon().hyp();
5049
5050 // SVE
5051 InitReg(MISCREG_ID_AA64ZFR0_EL1)
5052 .allPrivileges().exceptUserMode().writes(0);
5053 InitReg(MISCREG_ZCR_EL3)
5054 .mon();
5055 InitReg(MISCREG_ZCR_EL2)
5056 .hyp().mon();
5057 InitReg(MISCREG_ZCR_EL12)
5058 .unimplemented().warnNotFail();
5059 InitReg(MISCREG_ZCR_EL1)
5060 .allPrivileges().exceptUserMode();
5061
5062 // Dummy registers
5063 InitReg(MISCREG_NOP)
5064 .allPrivileges();
5065 InitReg(MISCREG_RAZ)
5066 .allPrivileges().exceptUserMode().writes(0);
5067 InitReg(MISCREG_CP14_UNIMPL)
5068 .unimplemented()
5069 .warnNotFail();
5070 InitReg(MISCREG_CP15_UNIMPL)
5071 .unimplemented()
5072 .warnNotFail();
5073 InitReg(MISCREG_UNKNOWN);
5074 InitReg(MISCREG_IMPDEF_UNIMPL)
5075 .unimplemented()
5076 .warnNotFail(impdefAsNop);
5077
5078 // RAS extension (unimplemented)
5079 InitReg(MISCREG_ERRIDR_EL1)
5080 .unimplemented()
5081 .warnNotFail();
5082 InitReg(MISCREG_ERRSELR_EL1)
5083 .unimplemented()
5084 .warnNotFail();
5085 InitReg(MISCREG_ERXFR_EL1)
5086 .unimplemented()
5087 .warnNotFail();
5088 InitReg(MISCREG_ERXCTLR_EL1)
5089 .unimplemented()
5090 .warnNotFail();
5091 InitReg(MISCREG_ERXSTATUS_EL1)
5092 .unimplemented()
5093 .warnNotFail();
5094 InitReg(MISCREG_ERXADDR_EL1)
5095 .unimplemented()
5096 .warnNotFail();
5097 InitReg(MISCREG_ERXMISC0_EL1)
5098 .unimplemented()
5099 .warnNotFail();
5100 InitReg(MISCREG_ERXMISC1_EL1)
5101 .unimplemented()
5102 .warnNotFail();
5103 InitReg(MISCREG_DISR_EL1)
5104 .unimplemented()
5105 .warnNotFail();
5106 InitReg(MISCREG_VSESR_EL2)
5107 .unimplemented()
5108 .warnNotFail();
5109 InitReg(MISCREG_VDISR_EL2)
5110 .unimplemented()
5111 .warnNotFail();
5112
5113 // Register mappings for some unimplemented registers:
5114 // ESR_EL1 -> DFSR
5115 // RMR_EL1 -> RMR
5116 // RMR_EL2 -> HRMR
5117 // DBGDTR_EL0 -> DBGDTR{R or T}Xint
5118 // DBGDTRRX_EL0 -> DBGDTRRXint
5119 // DBGDTRTX_EL0 -> DBGDTRRXint
5120 // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
5121
5122 completed = true;
5123 }
5124
5125 } // namespace ArmISA