2 * Copyright (c) 2010 ARM Limited
5 * The license below extends only to copyright in the software and shall
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41 #include "arch/arm/isa.hh"
42 #include "arch/arm/miscregs.hh"
43 #include "base/misc.hh"
49 decodeCP15Reg(unsigned crn
, unsigned opc1
, unsigned crm
, unsigned opc2
)
73 return MISCREG_ID_PFR0
;
75 return MISCREG_ID_PFR1
;
77 return MISCREG_ID_DFR0
;
79 return MISCREG_ID_AFR0
;
81 return MISCREG_ID_MMFR0
;
83 return MISCREG_ID_MMFR1
;
85 return MISCREG_ID_MMFR2
;
87 return MISCREG_ID_MMFR3
;
93 return MISCREG_ID_ISAR0
;
95 return MISCREG_ID_ISAR1
;
97 return MISCREG_ID_ISAR2
;
99 return MISCREG_ID_ISAR3
;
101 return MISCREG_ID_ISAR4
;
103 return MISCREG_ID_ISAR5
;
106 return MISCREG_RAZ
; // read as zero
110 return MISCREG_RAZ
; // read as zero
117 return MISCREG_CCSIDR
;
119 return MISCREG_CLIDR
;
126 if (crm
== 0 && opc2
== 0) {
127 return MISCREG_CSSELR
;
137 return MISCREG_SCTLR
;
139 return MISCREG_ACTLR
;
141 return MISCREG_CPACR
;
143 } else if (crm
== 1) {
150 return MISCREG_NSACR
;
156 if (opc1
== 0 && crm
== 0) {
159 return MISCREG_TTBR0
;
161 return MISCREG_TTBR1
;
163 return MISCREG_TTBCR
;
168 if (opc1
== 0 && crm
== 0 && opc2
== 0) {
177 } else if (opc2
== 1) {
180 } else if (crm
== 1) {
182 return MISCREG_ADFSR
;
183 } else if (opc2
== 1) {
184 return MISCREG_AIFSR
;
190 if (opc1
== 0 && crm
== 0) {
210 return MISCREG_ICIALLUIS
;
212 return MISCREG_BPIALLIS
;
223 return MISCREG_ICIALLU
;
225 return MISCREG_ICIMVAU
;
227 return MISCREG_CP15ISB
;
229 return MISCREG_BPIALL
;
231 return MISCREG_BPIMVA
;
236 return MISCREG_DCIMVAC
;
237 } else if (opc2
== 2) {
238 return MISCREG_DCISW
;
244 return MISCREG_V2PCWPR
;
246 return MISCREG_V2PCWPW
;
248 return MISCREG_V2PCWUR
;
250 return MISCREG_V2PCWUW
;
252 return MISCREG_V2POWPR
;
254 return MISCREG_V2POWPW
;
256 return MISCREG_V2POWUR
;
258 return MISCREG_V2POWUW
;
264 return MISCREG_DCCMVAC
;
266 return MISCREG_MCCSW
;
268 return MISCREG_CP15DSB
;
270 return MISCREG_CP15DMB
;
275 return MISCREG_DCCMVAU
;
285 return MISCREG_DCCIMVAC
;
286 } else if (opc2
== 2) {
287 return MISCREG_DCCISW
;
299 return MISCREG_TLBIALLIS
;
301 return MISCREG_TLBIMVAIS
;
303 return MISCREG_TLBIASIDIS
;
305 return MISCREG_TLBIMVAAIS
;
311 return MISCREG_ITLBIALL
;
313 return MISCREG_ITLBIMVA
;
315 return MISCREG_ITLBIASID
;
321 return MISCREG_DTLBIALL
;
323 return MISCREG_DTLBIMVA
;
325 return MISCREG_DTLBIASID
;
331 return MISCREG_TLBIALL
;
333 return MISCREG_TLBIMVA
;
335 return MISCREG_TLBIASID
;
337 return MISCREG_TLBIMVAA
;
351 return MISCREG_PMCNTENSET
;
353 return MISCREG_PMCNTENCLR
;
355 return MISCREG_PMOVSR
;
357 return MISCREG_PMSWINC
;
359 return MISCREG_PMSELR
;
361 return MISCREG_PMCEID0
;
363 return MISCREG_PMCEID1
;
368 return MISCREG_PMCCNTR
;
370 return MISCREG_PMC_OTHER
;
372 return MISCREG_PMXEVCNTR
;
377 return MISCREG_PMUSERENR
;
379 return MISCREG_PMINTENSET
;
381 return MISCREG_PMINTENCLR
;
385 //Reserved for Branch Predictor, Cache and TCM operations
389 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
390 if (crm
== 2) { // TEX Remap Registers
393 } else if (opc2
== 1) {
400 if (opc1
>= 0 && opc1
<=7) {
412 // Reserved for DMA operations for TCM access
422 } else if (opc2
== 1) {
423 return MISCREG_MVBAR
;
425 } else if (crm
== 1) {
437 return MISCREG_FCEIDR
;
439 return MISCREG_CONTEXTIDR
;
441 return MISCREG_TPIDRURW
;
443 return MISCREG_TPIDRURO
;
445 return MISCREG_TPIDRPRW
;
451 // Implementation defined
454 warn("Unknown miscreg: CRn: %d Opc1: %d CRm: %d opc2: %d\n",
455 crn
, opc1
, crm
, opc2
);
456 // Unrecognized register