2 * Copyright (c) 2010-2013, 2015-2019 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include "arch/arm/miscregs.hh"
46 #include "arch/arm/isa.hh"
47 #include "base/logging.hh"
48 #include "cpu/thread_context.hh"
49 #include "sim/full_system.hh"
55 decodeCP14Reg(unsigned crn
, unsigned opc1
, unsigned crm
, unsigned opc2
)
65 return MISCREG_DBGDIDR
;
67 return MISCREG_DBGDSCRint
;
91 return MISCREG_TEEHBR
;
101 return MISCREG_JOSCR
;
123 // If we get here then it must be a register that we haven't implemented
124 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
125 crn
, opc1
, crm
, opc2
);
126 return MISCREG_CP14_UNIMPL
;
132 decodeCP15Reg(unsigned crn
, unsigned opc1
, unsigned crm
, unsigned opc2
)
144 return MISCREG_TCMTR
;
146 return MISCREG_TLBTR
;
148 return MISCREG_MPIDR
;
150 return MISCREG_REVIDR
;
158 return MISCREG_ID_PFR0
;
160 return MISCREG_ID_PFR1
;
162 return MISCREG_ID_DFR0
;
164 return MISCREG_ID_AFR0
;
166 return MISCREG_ID_MMFR0
;
168 return MISCREG_ID_MMFR1
;
170 return MISCREG_ID_MMFR2
;
172 return MISCREG_ID_MMFR3
;
178 return MISCREG_ID_ISAR0
;
180 return MISCREG_ID_ISAR1
;
182 return MISCREG_ID_ISAR2
;
184 return MISCREG_ID_ISAR3
;
186 return MISCREG_ID_ISAR4
;
188 return MISCREG_ID_ISAR5
;
191 return MISCREG_RAZ
; // read as zero
195 return MISCREG_RAZ
; // read as zero
202 return MISCREG_CCSIDR
;
204 return MISCREG_CLIDR
;
211 if (crm
== 0 && opc2
== 0) {
212 return MISCREG_CSSELR
;
218 return MISCREG_VPIDR
;
220 return MISCREG_VMPIDR
;
230 return MISCREG_SCTLR
;
232 return MISCREG_ACTLR
;
234 return MISCREG_CPACR
;
236 } else if (crm
== 1) {
243 return MISCREG_NSACR
;
246 } else if (opc1
== 4) {
249 return MISCREG_HSCTLR
;
251 return MISCREG_HACTLR
;
252 } else if (crm
== 1) {
259 return MISCREG_HCPTR
;
269 if (opc1
== 0 && crm
== 0) {
272 return MISCREG_TTBR0
;
274 return MISCREG_TTBR1
;
276 return MISCREG_TTBCR
;
278 } else if (opc1
== 4) {
279 if (crm
== 0 && opc2
== 2)
281 else if (crm
== 1 && opc2
== 2)
286 if (opc1
== 0 && crm
== 0 && opc2
== 0) {
291 if (opc1
== 0 && crm
== 6 && opc2
== 0) {
292 return MISCREG_ICC_PMR
;
300 } else if (opc2
== 1) {
303 } else if (crm
== 1) {
305 return MISCREG_ADFSR
;
306 } else if (opc2
== 1) {
307 return MISCREG_AIFSR
;
310 } else if (opc1
== 4) {
313 return MISCREG_HADFSR
;
315 return MISCREG_HAIFSR
;
316 } else if (crm
== 2 && opc2
== 0) {
322 if (opc1
== 0 && crm
== 0) {
329 } else if (opc1
== 4 && crm
== 0) {
332 return MISCREG_HDFAR
;
334 return MISCREG_HIFAR
;
336 return MISCREG_HPFAR
;
351 return MISCREG_ICIALLUIS
;
353 return MISCREG_BPIALLIS
;
364 return MISCREG_ICIALLU
;
366 return MISCREG_ICIMVAU
;
368 return MISCREG_CP15ISB
;
370 return MISCREG_BPIALL
;
372 return MISCREG_BPIMVA
;
377 return MISCREG_DCIMVAC
;
378 } else if (opc2
== 2) {
379 return MISCREG_DCISW
;
385 return MISCREG_ATS1CPR
;
387 return MISCREG_ATS1CPW
;
389 return MISCREG_ATS1CUR
;
391 return MISCREG_ATS1CUW
;
393 return MISCREG_ATS12NSOPR
;
395 return MISCREG_ATS12NSOPW
;
397 return MISCREG_ATS12NSOUR
;
399 return MISCREG_ATS12NSOUW
;
405 return MISCREG_DCCMVAC
;
407 return MISCREG_DCCSW
;
409 return MISCREG_CP15DSB
;
411 return MISCREG_CP15DMB
;
416 return MISCREG_DCCMVAU
;
426 return MISCREG_DCCIMVAC
;
427 } else if (opc2
== 2) {
428 return MISCREG_DCCISW
;
432 } else if (opc1
== 4 && crm
== 8) {
434 return MISCREG_ATS1HR
;
436 return MISCREG_ATS1HW
;
445 return MISCREG_TLBIALLIS
;
447 return MISCREG_TLBIMVAIS
;
449 return MISCREG_TLBIASIDIS
;
451 return MISCREG_TLBIMVAAIS
;
453 return MISCREG_TLBIMVALIS
;
455 return MISCREG_TLBIMVAALIS
;
461 return MISCREG_ITLBIALL
;
463 return MISCREG_ITLBIMVA
;
465 return MISCREG_ITLBIASID
;
471 return MISCREG_DTLBIALL
;
473 return MISCREG_DTLBIMVA
;
475 return MISCREG_DTLBIASID
;
481 return MISCREG_TLBIALL
;
483 return MISCREG_TLBIMVA
;
485 return MISCREG_TLBIASID
;
487 return MISCREG_TLBIMVAA
;
489 return MISCREG_TLBIMVAL
;
491 return MISCREG_TLBIMVAAL
;
495 } else if (opc1
== 4) {
499 return MISCREG_TLBIIPAS2IS
;
501 return MISCREG_TLBIIPAS2LIS
;
503 } else if (crm
== 3) {
506 return MISCREG_TLBIALLHIS
;
508 return MISCREG_TLBIMVAHIS
;
510 return MISCREG_TLBIALLNSNHIS
;
512 return MISCREG_TLBIMVALHIS
;
514 } else if (crm
== 4) {
517 return MISCREG_TLBIIPAS2
;
519 return MISCREG_TLBIIPAS2L
;
521 } else if (crm
== 7) {
524 return MISCREG_TLBIALLH
;
526 return MISCREG_TLBIMVAH
;
528 return MISCREG_TLBIALLNSNH
;
530 return MISCREG_TLBIMVALH
;
536 // Every cop register with CRn = 9 and CRm in
537 // {0-2}, {5-8} is implementation defined regardless
547 return MISCREG_IMPDEF_UNIMPL
;
556 return MISCREG_PMCNTENSET
;
558 return MISCREG_PMCNTENCLR
;
560 return MISCREG_PMOVSR
;
562 return MISCREG_PMSWINC
;
564 return MISCREG_PMSELR
;
566 return MISCREG_PMCEID0
;
568 return MISCREG_PMCEID1
;
574 return MISCREG_PMCCNTR
;
576 // Selector is PMSELR.SEL
577 return MISCREG_PMXEVTYPER_PMCCFILTR
;
579 return MISCREG_PMXEVCNTR
;
585 return MISCREG_PMUSERENR
;
587 return MISCREG_PMINTENSET
;
589 return MISCREG_PMINTENCLR
;
591 return MISCREG_PMOVSSET
;
595 } else if (opc1
== 1) {
599 case 2: // L2CTLR, L2 Control Register
600 return MISCREG_L2CTLR
;
602 return MISCREG_L2ECTLR
;
611 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
613 return MISCREG_IMPDEF_UNIMPL
;
614 } else if (crm
== 2) { // TEX Remap Registers
616 // Selector is TTBCR.EAE
617 return MISCREG_PRRR_MAIR0
;
618 } else if (opc2
== 1) {
619 // Selector is TTBCR.EAE
620 return MISCREG_NMRR_MAIR1
;
622 } else if (crm
== 3) {
624 return MISCREG_AMAIR0
;
625 } else if (opc2
== 1) {
626 return MISCREG_AMAIR1
;
629 } else if (opc1
== 4) {
630 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
633 return MISCREG_HMAIR0
;
635 return MISCREG_HMAIR1
;
636 } else if (crm
== 3) {
638 return MISCREG_HAMAIR0
;
640 return MISCREG_HAMAIR1
;
657 // Reserved for DMA operations for TCM access
658 return MISCREG_IMPDEF_UNIMPL
;
669 } else if (opc2
== 1) {
670 return MISCREG_MVBAR
;
672 } else if (crm
== 1) {
676 } else if (crm
== 8) {
679 return MISCREG_ICC_IAR0
;
681 return MISCREG_ICC_EOIR0
;
683 return MISCREG_ICC_HPPIR0
;
685 return MISCREG_ICC_BPR0
;
687 return MISCREG_ICC_AP0R0
;
689 return MISCREG_ICC_AP0R1
;
691 return MISCREG_ICC_AP0R2
;
693 return MISCREG_ICC_AP0R3
;
695 } else if (crm
== 9) {
698 return MISCREG_ICC_AP1R0
;
700 return MISCREG_ICC_AP1R1
;
702 return MISCREG_ICC_AP1R2
;
704 return MISCREG_ICC_AP1R3
;
706 } else if (crm
== 11) {
709 return MISCREG_ICC_DIR
;
711 return MISCREG_ICC_RPR
;
713 } else if (crm
== 12) {
716 return MISCREG_ICC_IAR1
;
718 return MISCREG_ICC_EOIR1
;
720 return MISCREG_ICC_HPPIR1
;
722 return MISCREG_ICC_BPR1
;
724 return MISCREG_ICC_CTLR
;
726 return MISCREG_ICC_SRE
;
728 return MISCREG_ICC_IGRPEN0
;
730 return MISCREG_ICC_IGRPEN1
;
733 } else if (opc1
== 4) {
734 if (crm
== 0 && opc2
== 0) {
735 return MISCREG_HVBAR
;
736 } else if (crm
== 8) {
739 return MISCREG_ICH_AP0R0
;
741 return MISCREG_ICH_AP0R1
;
743 return MISCREG_ICH_AP0R2
;
745 return MISCREG_ICH_AP0R3
;
747 } else if (crm
== 9) {
750 return MISCREG_ICH_AP1R0
;
752 return MISCREG_ICH_AP1R1
;
754 return MISCREG_ICH_AP1R2
;
756 return MISCREG_ICH_AP1R3
;
758 return MISCREG_ICC_HSRE
;
760 } else if (crm
== 11) {
763 return MISCREG_ICH_HCR
;
765 return MISCREG_ICH_VTR
;
767 return MISCREG_ICH_MISR
;
769 return MISCREG_ICH_EISR
;
771 return MISCREG_ICH_ELRSR
;
773 return MISCREG_ICH_VMCR
;
775 } else if (crm
== 12) {
778 return MISCREG_ICH_LR0
;
780 return MISCREG_ICH_LR1
;
782 return MISCREG_ICH_LR2
;
784 return MISCREG_ICH_LR3
;
786 return MISCREG_ICH_LR4
;
788 return MISCREG_ICH_LR5
;
790 return MISCREG_ICH_LR6
;
792 return MISCREG_ICH_LR7
;
794 } else if (crm
== 13) {
797 return MISCREG_ICH_LR8
;
799 return MISCREG_ICH_LR9
;
801 return MISCREG_ICH_LR10
;
803 return MISCREG_ICH_LR11
;
805 return MISCREG_ICH_LR12
;
807 return MISCREG_ICH_LR13
;
809 return MISCREG_ICH_LR14
;
811 return MISCREG_ICH_LR15
;
813 } else if (crm
== 14) {
816 return MISCREG_ICH_LRC0
;
818 return MISCREG_ICH_LRC1
;
820 return MISCREG_ICH_LRC2
;
822 return MISCREG_ICH_LRC3
;
824 return MISCREG_ICH_LRC4
;
826 return MISCREG_ICH_LRC5
;
828 return MISCREG_ICH_LRC6
;
830 return MISCREG_ICH_LRC7
;
832 } else if (crm
== 15) {
835 return MISCREG_ICH_LRC8
;
837 return MISCREG_ICH_LRC9
;
839 return MISCREG_ICH_LRC10
;
841 return MISCREG_ICH_LRC11
;
843 return MISCREG_ICH_LRC12
;
845 return MISCREG_ICH_LRC13
;
847 return MISCREG_ICH_LRC14
;
849 return MISCREG_ICH_LRC15
;
852 } else if (opc1
== 6) {
856 return MISCREG_ICC_MCTLR
;
858 return MISCREG_ICC_MSRE
;
860 return MISCREG_ICC_MGRPEN1
;
870 return MISCREG_FCSEIDR
;
872 return MISCREG_CONTEXTIDR
;
874 return MISCREG_TPIDRURW
;
876 return MISCREG_TPIDRURO
;
878 return MISCREG_TPIDRPRW
;
881 } else if (opc1
== 4) {
882 if (crm
== 0 && opc2
== 2)
883 return MISCREG_HTPIDR
;
891 return MISCREG_CNTFRQ
;
895 return MISCREG_CNTKCTL
;
899 return MISCREG_CNTP_TVAL
;
901 return MISCREG_CNTP_CTL
;
905 return MISCREG_CNTV_TVAL
;
907 return MISCREG_CNTV_CTL
;
910 } else if (opc1
== 4) {
911 if (crm
== 1 && opc2
== 0) {
912 return MISCREG_CNTHCTL
;
913 } else if (crm
== 2) {
915 return MISCREG_CNTHP_TVAL
;
917 return MISCREG_CNTHP_CTL
;
922 // Implementation defined
923 return MISCREG_IMPDEF_UNIMPL
;
925 // Unrecognized register
926 return MISCREG_CP15_UNIMPL
;
930 decodeCP15Reg64(unsigned crm
, unsigned opc1
)
936 return MISCREG_TTBR0
;
938 return MISCREG_TTBR1
;
940 return MISCREG_HTTBR
;
942 return MISCREG_VTTBR
;
952 return MISCREG_CNTPCT
;
954 return MISCREG_CNTVCT
;
956 return MISCREG_CNTP_CVAL
;
958 return MISCREG_CNTV_CVAL
;
960 return MISCREG_CNTVOFF
;
962 return MISCREG_CNTHP_CVAL
;
968 return MISCREG_ICC_SGI1R
;
970 return MISCREG_ICC_ASGI1R
;
972 return MISCREG_ICC_SGI0R
;
979 return MISCREG_CPUMERRSR
;
981 return MISCREG_L2MERRSR
;
984 // Unrecognized register
985 return MISCREG_CP15_UNIMPL
;
988 std::tuple
<bool, bool>
989 canReadCoprocReg(MiscRegIndex reg
, SCR scr
, CPSR cpsr
)
991 bool secure
= !scr
.ns
;
992 bool canRead
= false;
993 bool undefined
= false;
997 canRead
= secure
? miscRegInfo
[reg
][MISCREG_USR_S_RD
] :
998 miscRegInfo
[reg
][MISCREG_USR_NS_RD
];
1004 case MODE_UNDEFINED
:
1006 canRead
= secure
? miscRegInfo
[reg
][MISCREG_PRI_S_RD
] :
1007 miscRegInfo
[reg
][MISCREG_PRI_NS_RD
];
1010 canRead
= secure
? miscRegInfo
[reg
][MISCREG_MON_NS0_RD
] :
1011 miscRegInfo
[reg
][MISCREG_MON_NS1_RD
];
1014 canRead
= miscRegInfo
[reg
][MISCREG_HYP_RD
];
1019 // can't do permissions checkes on the root of a banked pair of regs
1020 assert(!miscRegInfo
[reg
][MISCREG_BANKED
]);
1021 return std::make_tuple(canRead
, undefined
);
1024 std::tuple
<bool, bool>
1025 canWriteCoprocReg(MiscRegIndex reg
, SCR scr
, CPSR cpsr
)
1027 bool secure
= !scr
.ns
;
1028 bool canWrite
= false;
1029 bool undefined
= false;
1031 switch (cpsr
.mode
) {
1033 canWrite
= secure
? miscRegInfo
[reg
][MISCREG_USR_S_WR
] :
1034 miscRegInfo
[reg
][MISCREG_USR_NS_WR
];
1040 case MODE_UNDEFINED
:
1042 canWrite
= secure
? miscRegInfo
[reg
][MISCREG_PRI_S_WR
] :
1043 miscRegInfo
[reg
][MISCREG_PRI_NS_WR
];
1046 canWrite
= secure
? miscRegInfo
[reg
][MISCREG_MON_NS0_WR
] :
1047 miscRegInfo
[reg
][MISCREG_MON_NS1_WR
];
1050 canWrite
= miscRegInfo
[reg
][MISCREG_HYP_WR
];
1055 // can't do permissions checkes on the root of a banked pair of regs
1056 assert(!miscRegInfo
[reg
][MISCREG_BANKED
]);
1057 return std::make_tuple(canWrite
, undefined
);
1061 snsBankedIndex(MiscRegIndex reg
, ThreadContext
*tc
)
1063 SCR scr
= tc
->readMiscReg(MISCREG_SCR
);
1064 return snsBankedIndex(reg
, tc
, scr
.ns
);
1068 snsBankedIndex(MiscRegIndex reg
, ThreadContext
*tc
, bool ns
)
1070 int reg_as_int
= static_cast<int>(reg
);
1071 if (miscRegInfo
[reg
][MISCREG_BANKED
]) {
1072 reg_as_int
+= (ArmSystem::haveSecurity(tc
) &&
1073 !ArmSystem::highestELIs64(tc
) && !ns
) ? 2 : 1;
1079 snsBankedIndex64(MiscRegIndex reg
, ThreadContext
*tc
)
1081 SCR scr
= tc
->readMiscReg(MISCREG_SCR
);
1082 return tc
->getIsaPtr()->snsBankedIndex64(reg
, scr
.ns
);
1086 * If the reg is a child reg of a banked set, then the parent is the last
1087 * banked one in the list. This is messy, and the wish is to eventually have
1088 * the bitmap replaced with a better data structure. the preUnflatten function
1089 * initializes a lookup table to speed up the search for these banked
1093 int unflattenResultMiscReg
[NUM_MISCREGS
];
1096 preUnflattenMiscReg()
1099 for (int i
= 0 ; i
< NUM_MISCREGS
; i
++){
1100 if (miscRegInfo
[i
][MISCREG_BANKED
])
1102 if (miscRegInfo
[i
][MISCREG_BANKED_CHILD
])
1103 unflattenResultMiscReg
[i
] = reg
;
1105 unflattenResultMiscReg
[i
] = i
;
1106 // if this assert fails, no parent was found, and something is broken
1107 assert(unflattenResultMiscReg
[i
] > -1);
1112 unflattenMiscReg(int reg
)
1114 return unflattenResultMiscReg
[reg
];
1118 canReadAArch64SysReg(MiscRegIndex reg
, SCR scr
, CPSR cpsr
, ThreadContext
*tc
)
1120 // Check for SP_EL0 access while SPSEL == 0
1121 if ((reg
== MISCREG_SP_EL0
) && (tc
->readMiscReg(MISCREG_SPSEL
) == 0))
1124 // Check for RVBAR access
1125 if (reg
== MISCREG_RVBAR_EL1
) {
1126 ExceptionLevel highest_el
= ArmSystem::highestEL(tc
);
1127 if (highest_el
== EL2
|| highest_el
== EL3
)
1130 if (reg
== MISCREG_RVBAR_EL2
) {
1131 ExceptionLevel highest_el
= ArmSystem::highestEL(tc
);
1132 if (highest_el
== EL3
)
1136 bool secure
= ArmSystem::haveSecurity(tc
) && !scr
.ns
;
1138 switch (currEL(cpsr
)) {
1140 return secure
? miscRegInfo
[reg
][MISCREG_USR_S_RD
] :
1141 miscRegInfo
[reg
][MISCREG_USR_NS_RD
];
1143 return secure
? miscRegInfo
[reg
][MISCREG_PRI_S_RD
] :
1144 miscRegInfo
[reg
][MISCREG_PRI_NS_RD
];
1146 return miscRegInfo
[reg
][MISCREG_HYP_RD
];
1148 return secure
? miscRegInfo
[reg
][MISCREG_MON_NS0_RD
] :
1149 miscRegInfo
[reg
][MISCREG_MON_NS1_RD
];
1151 panic("Invalid exception level");
1156 canWriteAArch64SysReg(MiscRegIndex reg
, SCR scr
, CPSR cpsr
, ThreadContext
*tc
)
1158 // Check for SP_EL0 access while SPSEL == 0
1159 if ((reg
== MISCREG_SP_EL0
) && (tc
->readMiscReg(MISCREG_SPSEL
) == 0))
1161 ExceptionLevel el
= currEL(cpsr
);
1162 if (reg
== MISCREG_DAIF
) {
1163 SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR_EL1
);
1164 if (el
== EL0
&& !sctlr
.uma
)
1167 if (FullSystem
&& reg
== MISCREG_DC_ZVA_Xt
) {
1168 // In syscall-emulation mode, this test is skipped and DCZVA is always
1170 SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR_EL1
);
1171 if (el
== EL0
&& !sctlr
.dze
)
1174 if (reg
== MISCREG_DC_CVAC_Xt
|| reg
== MISCREG_DC_CIVAC_Xt
) {
1175 SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR_EL1
);
1176 if (el
== EL0
&& !sctlr
.uci
)
1180 bool secure
= ArmSystem::haveSecurity(tc
) && !scr
.ns
;
1184 return secure
? miscRegInfo
[reg
][MISCREG_USR_S_WR
] :
1185 miscRegInfo
[reg
][MISCREG_USR_NS_WR
];
1187 return secure
? miscRegInfo
[reg
][MISCREG_PRI_S_WR
] :
1188 miscRegInfo
[reg
][MISCREG_PRI_NS_WR
];
1190 return miscRegInfo
[reg
][MISCREG_HYP_WR
];
1192 return secure
? miscRegInfo
[reg
][MISCREG_MON_NS0_WR
] :
1193 miscRegInfo
[reg
][MISCREG_MON_NS1_WR
];
1195 panic("Invalid exception level");
1200 decodeAArch64SysReg(unsigned op0
, unsigned op1
,
1201 unsigned crn
, unsigned crm
,
1214 return MISCREG_IC_IALLUIS
;
1220 return MISCREG_IC_IALLU
;
1226 return MISCREG_DC_IVAC_Xt
;
1228 return MISCREG_DC_ISW_Xt
;
1234 return MISCREG_AT_S1E1R_Xt
;
1236 return MISCREG_AT_S1E1W_Xt
;
1238 return MISCREG_AT_S1E0R_Xt
;
1240 return MISCREG_AT_S1E0W_Xt
;
1246 return MISCREG_DC_CSW_Xt
;
1252 return MISCREG_DC_CISW_Xt
;
1262 return MISCREG_DC_ZVA_Xt
;
1268 return MISCREG_IC_IVAU_Xt
;
1274 return MISCREG_DC_CVAC_Xt
;
1280 return MISCREG_DC_CVAU_Xt
;
1286 return MISCREG_DC_CIVAC_Xt
;
1296 return MISCREG_AT_S1E2R_Xt
;
1298 return MISCREG_AT_S1E2W_Xt
;
1300 return MISCREG_AT_S12E1R_Xt
;
1302 return MISCREG_AT_S12E1W_Xt
;
1304 return MISCREG_AT_S12E0R_Xt
;
1306 return MISCREG_AT_S12E0W_Xt
;
1316 return MISCREG_AT_S1E3R_Xt
;
1318 return MISCREG_AT_S1E3W_Xt
;
1332 return MISCREG_TLBI_VMALLE1IS
;
1334 return MISCREG_TLBI_VAE1IS_Xt
;
1336 return MISCREG_TLBI_ASIDE1IS_Xt
;
1338 return MISCREG_TLBI_VAAE1IS_Xt
;
1340 return MISCREG_TLBI_VALE1IS_Xt
;
1342 return MISCREG_TLBI_VAALE1IS_Xt
;
1348 return MISCREG_TLBI_VMALLE1
;
1350 return MISCREG_TLBI_VAE1_Xt
;
1352 return MISCREG_TLBI_ASIDE1_Xt
;
1354 return MISCREG_TLBI_VAAE1_Xt
;
1356 return MISCREG_TLBI_VALE1_Xt
;
1358 return MISCREG_TLBI_VAALE1_Xt
;
1368 return MISCREG_TLBI_IPAS2E1IS_Xt
;
1370 return MISCREG_TLBI_IPAS2LE1IS_Xt
;
1376 return MISCREG_TLBI_ALLE2IS
;
1378 return MISCREG_TLBI_VAE2IS_Xt
;
1380 return MISCREG_TLBI_ALLE1IS
;
1382 return MISCREG_TLBI_VALE2IS_Xt
;
1384 return MISCREG_TLBI_VMALLS12E1IS
;
1390 return MISCREG_TLBI_IPAS2E1_Xt
;
1392 return MISCREG_TLBI_IPAS2LE1_Xt
;
1398 return MISCREG_TLBI_ALLE2
;
1400 return MISCREG_TLBI_VAE2_Xt
;
1402 return MISCREG_TLBI_ALLE1
;
1404 return MISCREG_TLBI_VALE2_Xt
;
1406 return MISCREG_TLBI_VMALLS12E1
;
1416 return MISCREG_TLBI_ALLE3IS
;
1418 return MISCREG_TLBI_VAE3IS_Xt
;
1420 return MISCREG_TLBI_VALE3IS_Xt
;
1426 return MISCREG_TLBI_ALLE3
;
1428 return MISCREG_TLBI_VAE3_Xt
;
1430 return MISCREG_TLBI_VALE3_Xt
;
1439 // SYS Instruction with CRn = { 11, 15 }
1440 // (Trappable by HCR_EL2.TIDCP)
1441 return MISCREG_IMPDEF_UNIMPL
;
1453 return MISCREG_OSDTRRX_EL1
;
1455 return MISCREG_DBGBVR0_EL1
;
1457 return MISCREG_DBGBCR0_EL1
;
1459 return MISCREG_DBGWVR0_EL1
;
1461 return MISCREG_DBGWCR0_EL1
;
1467 return MISCREG_DBGBVR1_EL1
;
1469 return MISCREG_DBGBCR1_EL1
;
1471 return MISCREG_DBGWVR1_EL1
;
1473 return MISCREG_DBGWCR1_EL1
;
1479 return MISCREG_MDCCINT_EL1
;
1481 return MISCREG_MDSCR_EL1
;
1483 return MISCREG_DBGBVR2_EL1
;
1485 return MISCREG_DBGBCR2_EL1
;
1487 return MISCREG_DBGWVR2_EL1
;
1489 return MISCREG_DBGWCR2_EL1
;
1495 return MISCREG_OSDTRTX_EL1
;
1497 return MISCREG_DBGBVR3_EL1
;
1499 return MISCREG_DBGBCR3_EL1
;
1501 return MISCREG_DBGWVR3_EL1
;
1503 return MISCREG_DBGWCR3_EL1
;
1509 return MISCREG_DBGBVR4_EL1
;
1511 return MISCREG_DBGBCR4_EL1
;
1517 return MISCREG_DBGBVR5_EL1
;
1519 return MISCREG_DBGBCR5_EL1
;
1525 return MISCREG_OSECCR_EL1
;
1535 return MISCREG_TEECR32_EL1
;
1545 return MISCREG_MDCCSR_EL0
;
1551 return MISCREG_MDDTR_EL0
;
1557 return MISCREG_MDDTRRX_EL0
;
1567 return MISCREG_DBGVCR32_EL2
;
1581 return MISCREG_MDRAR_EL1
;
1583 return MISCREG_OSLAR_EL1
;
1589 return MISCREG_OSLSR_EL1
;
1595 return MISCREG_OSDLR_EL1
;
1601 return MISCREG_DBGPRCR_EL1
;
1611 return MISCREG_TEEHBR32_EL1
;
1625 return MISCREG_DBGCLAIMSET_EL1
;
1631 return MISCREG_DBGCLAIMCLR_EL1
;
1637 return MISCREG_DBGAUTHSTATUS_EL1
;
1655 return MISCREG_MIDR_EL1
;
1657 return MISCREG_MPIDR_EL1
;
1659 return MISCREG_REVIDR_EL1
;
1665 return MISCREG_ID_PFR0_EL1
;
1667 return MISCREG_ID_PFR1_EL1
;
1669 return MISCREG_ID_DFR0_EL1
;
1671 return MISCREG_ID_AFR0_EL1
;
1673 return MISCREG_ID_MMFR0_EL1
;
1675 return MISCREG_ID_MMFR1_EL1
;
1677 return MISCREG_ID_MMFR2_EL1
;
1679 return MISCREG_ID_MMFR3_EL1
;
1685 return MISCREG_ID_ISAR0_EL1
;
1687 return MISCREG_ID_ISAR1_EL1
;
1689 return MISCREG_ID_ISAR2_EL1
;
1691 return MISCREG_ID_ISAR3_EL1
;
1693 return MISCREG_ID_ISAR4_EL1
;
1695 return MISCREG_ID_ISAR5_EL1
;
1701 return MISCREG_MVFR0_EL1
;
1703 return MISCREG_MVFR1_EL1
;
1705 return MISCREG_MVFR2_EL1
;
1713 return MISCREG_ID_AA64PFR0_EL1
;
1715 return MISCREG_ID_AA64PFR1_EL1
;
1719 return MISCREG_ID_AA64ZFR0_EL1
;
1727 return MISCREG_ID_AA64DFR0_EL1
;
1729 return MISCREG_ID_AA64DFR1_EL1
;
1731 return MISCREG_ID_AA64AFR0_EL1
;
1733 return MISCREG_ID_AA64AFR1_EL1
;
1744 return MISCREG_ID_AA64ISAR0_EL1
;
1746 return MISCREG_ID_AA64ISAR1_EL1
;
1754 return MISCREG_ID_AA64MMFR0_EL1
;
1756 return MISCREG_ID_AA64MMFR1_EL1
;
1758 return MISCREG_ID_AA64MMFR2_EL1
;
1770 return MISCREG_CCSIDR_EL1
;
1772 return MISCREG_CLIDR_EL1
;
1774 return MISCREG_AIDR_EL1
;
1784 return MISCREG_CSSELR_EL1
;
1794 return MISCREG_CTR_EL0
;
1796 return MISCREG_DCZID_EL0
;
1806 return MISCREG_VPIDR_EL2
;
1808 return MISCREG_VMPIDR_EL2
;
1822 return MISCREG_SCTLR_EL1
;
1824 return MISCREG_ACTLR_EL1
;
1826 return MISCREG_CPACR_EL1
;
1832 return MISCREG_ZCR_EL1
;
1842 return MISCREG_SCTLR_EL2
;
1844 return MISCREG_ACTLR_EL2
;
1850 return MISCREG_HCR_EL2
;
1852 return MISCREG_MDCR_EL2
;
1854 return MISCREG_CPTR_EL2
;
1856 return MISCREG_HSTR_EL2
;
1858 return MISCREG_HACR_EL2
;
1864 return MISCREG_ZCR_EL2
;
1874 return MISCREG_ZCR_EL12
;
1884 return MISCREG_SCTLR_EL3
;
1886 return MISCREG_ACTLR_EL3
;
1892 return MISCREG_SCR_EL3
;
1894 return MISCREG_SDER32_EL3
;
1896 return MISCREG_CPTR_EL3
;
1902 return MISCREG_ZCR_EL3
;
1908 return MISCREG_MDCR_EL3
;
1922 return MISCREG_TTBR0_EL1
;
1924 return MISCREG_TTBR1_EL1
;
1926 return MISCREG_TCR_EL1
;
1936 return MISCREG_TTBR0_EL2
;
1938 return MISCREG_TTBR1_EL2
;
1940 return MISCREG_TCR_EL2
;
1946 return MISCREG_VTTBR_EL2
;
1948 return MISCREG_VTCR_EL2
;
1958 return MISCREG_TTBR0_EL3
;
1960 return MISCREG_TCR_EL3
;
1974 return MISCREG_DACR32_EL2
;
1988 return MISCREG_SPSR_EL1
;
1990 return MISCREG_ELR_EL1
;
1996 return MISCREG_SP_EL0
;
2002 return MISCREG_SPSEL
;
2004 return MISCREG_CURRENTEL
;
2012 return MISCREG_ICC_PMR_EL1
;
2022 return MISCREG_NZCV
;
2024 return MISCREG_DAIF
;
2030 return MISCREG_FPCR
;
2032 return MISCREG_FPSR
;
2038 return MISCREG_DSPSR_EL0
;
2040 return MISCREG_DLR_EL0
;
2050 return MISCREG_SPSR_EL2
;
2052 return MISCREG_ELR_EL2
;
2058 return MISCREG_SP_EL1
;
2064 return MISCREG_SPSR_IRQ_AA64
;
2066 return MISCREG_SPSR_ABT_AA64
;
2068 return MISCREG_SPSR_UND_AA64
;
2070 return MISCREG_SPSR_FIQ_AA64
;
2080 return MISCREG_SPSR_EL3
;
2082 return MISCREG_ELR_EL3
;
2088 return MISCREG_SP_EL2
;
2102 return MISCREG_AFSR0_EL1
;
2104 return MISCREG_AFSR1_EL1
;
2110 return MISCREG_ESR_EL1
;
2116 return MISCREG_ERRIDR_EL1
;
2118 return MISCREG_ERRSELR_EL1
;
2124 return MISCREG_ERXFR_EL1
;
2126 return MISCREG_ERXCTLR_EL1
;
2128 return MISCREG_ERXSTATUS_EL1
;
2130 return MISCREG_ERXADDR_EL1
;
2136 return MISCREG_ERXMISC0_EL1
;
2138 return MISCREG_ERXMISC1_EL1
;
2148 return MISCREG_IFSR32_EL2
;
2154 return MISCREG_AFSR0_EL2
;
2156 return MISCREG_AFSR1_EL2
;
2162 return MISCREG_ESR_EL2
;
2164 return MISCREG_VSESR_EL2
;
2170 return MISCREG_FPEXC32_EL2
;
2180 return MISCREG_AFSR0_EL3
;
2182 return MISCREG_AFSR1_EL3
;
2188 return MISCREG_ESR_EL3
;
2202 return MISCREG_FAR_EL1
;
2212 return MISCREG_FAR_EL2
;
2214 return MISCREG_HPFAR_EL2
;
2224 return MISCREG_FAR_EL3
;
2238 return MISCREG_PAR_EL1
;
2252 return MISCREG_PMINTENSET_EL1
;
2254 return MISCREG_PMINTENCLR_EL1
;
2264 return MISCREG_PMCR_EL0
;
2266 return MISCREG_PMCNTENSET_EL0
;
2268 return MISCREG_PMCNTENCLR_EL0
;
2270 return MISCREG_PMOVSCLR_EL0
;
2272 return MISCREG_PMSWINC_EL0
;
2274 return MISCREG_PMSELR_EL0
;
2276 return MISCREG_PMCEID0_EL0
;
2278 return MISCREG_PMCEID1_EL0
;
2284 return MISCREG_PMCCNTR_EL0
;
2286 return MISCREG_PMXEVTYPER_EL0
;
2288 return MISCREG_PMXEVCNTR_EL0
;
2294 return MISCREG_PMUSERENR_EL0
;
2296 return MISCREG_PMOVSSET_EL0
;
2310 return MISCREG_MAIR_EL1
;
2316 return MISCREG_AMAIR_EL1
;
2326 return MISCREG_MAIR_EL2
;
2332 return MISCREG_AMAIR_EL2
;
2342 return MISCREG_MAIR_EL3
;
2348 return MISCREG_AMAIR_EL3
;
2362 return MISCREG_L2CTLR_EL1
;
2364 return MISCREG_L2ECTLR_EL1
;
2370 // S3_<op1>_11_<Cm>_<op2>
2371 return MISCREG_IMPDEF_UNIMPL
;
2381 return MISCREG_VBAR_EL1
;
2383 return MISCREG_RVBAR_EL1
;
2389 return MISCREG_ISR_EL1
;
2391 return MISCREG_DISR_EL1
;
2397 return MISCREG_ICC_IAR0_EL1
;
2399 return MISCREG_ICC_EOIR0_EL1
;
2401 return MISCREG_ICC_HPPIR0_EL1
;
2403 return MISCREG_ICC_BPR0_EL1
;
2405 return MISCREG_ICC_AP0R0_EL1
;
2407 return MISCREG_ICC_AP0R1_EL1
;
2409 return MISCREG_ICC_AP0R2_EL1
;
2411 return MISCREG_ICC_AP0R3_EL1
;
2417 return MISCREG_ICC_AP1R0_EL1
;
2419 return MISCREG_ICC_AP1R1_EL1
;
2421 return MISCREG_ICC_AP1R2_EL1
;
2423 return MISCREG_ICC_AP1R3_EL1
;
2429 return MISCREG_ICC_DIR_EL1
;
2431 return MISCREG_ICC_RPR_EL1
;
2433 return MISCREG_ICC_SGI1R_EL1
;
2435 return MISCREG_ICC_ASGI1R_EL1
;
2437 return MISCREG_ICC_SGI0R_EL1
;
2443 return MISCREG_ICC_IAR1_EL1
;
2445 return MISCREG_ICC_EOIR1_EL1
;
2447 return MISCREG_ICC_HPPIR1_EL1
;
2449 return MISCREG_ICC_BPR1_EL1
;
2451 return MISCREG_ICC_CTLR_EL1
;
2453 return MISCREG_ICC_SRE_EL1
;
2455 return MISCREG_ICC_IGRPEN0_EL1
;
2457 return MISCREG_ICC_IGRPEN1_EL1
;
2467 return MISCREG_VBAR_EL2
;
2469 return MISCREG_RVBAR_EL2
;
2475 return MISCREG_VDISR_EL2
;
2481 return MISCREG_ICH_AP0R0_EL2
;
2483 return MISCREG_ICH_AP0R1_EL2
;
2485 return MISCREG_ICH_AP0R2_EL2
;
2487 return MISCREG_ICH_AP0R3_EL2
;
2493 return MISCREG_ICH_AP1R0_EL2
;
2495 return MISCREG_ICH_AP1R1_EL2
;
2497 return MISCREG_ICH_AP1R2_EL2
;
2499 return MISCREG_ICH_AP1R3_EL2
;
2501 return MISCREG_ICC_SRE_EL2
;
2507 return MISCREG_ICH_HCR_EL2
;
2509 return MISCREG_ICH_VTR_EL2
;
2511 return MISCREG_ICH_MISR_EL2
;
2513 return MISCREG_ICH_EISR_EL2
;
2515 return MISCREG_ICH_ELRSR_EL2
;
2517 return MISCREG_ICH_VMCR_EL2
;
2523 return MISCREG_ICH_LR0_EL2
;
2525 return MISCREG_ICH_LR1_EL2
;
2527 return MISCREG_ICH_LR2_EL2
;
2529 return MISCREG_ICH_LR3_EL2
;
2531 return MISCREG_ICH_LR4_EL2
;
2533 return MISCREG_ICH_LR5_EL2
;
2535 return MISCREG_ICH_LR6_EL2
;
2537 return MISCREG_ICH_LR7_EL2
;
2543 return MISCREG_ICH_LR8_EL2
;
2545 return MISCREG_ICH_LR9_EL2
;
2547 return MISCREG_ICH_LR10_EL2
;
2549 return MISCREG_ICH_LR11_EL2
;
2551 return MISCREG_ICH_LR12_EL2
;
2553 return MISCREG_ICH_LR13_EL2
;
2555 return MISCREG_ICH_LR14_EL2
;
2557 return MISCREG_ICH_LR15_EL2
;
2567 return MISCREG_VBAR_EL3
;
2569 return MISCREG_RVBAR_EL3
;
2571 return MISCREG_RMR_EL3
;
2577 return MISCREG_ICC_CTLR_EL3
;
2579 return MISCREG_ICC_SRE_EL3
;
2581 return MISCREG_ICC_IGRPEN1_EL3
;
2595 return MISCREG_CONTEXTIDR_EL1
;
2597 return MISCREG_TPIDR_EL1
;
2607 return MISCREG_TPIDR_EL0
;
2609 return MISCREG_TPIDRRO_EL0
;
2619 return MISCREG_CONTEXTIDR_EL2
;
2621 return MISCREG_TPIDR_EL2
;
2631 return MISCREG_TPIDR_EL3
;
2645 return MISCREG_CNTKCTL_EL1
;
2655 return MISCREG_CNTFRQ_EL0
;
2657 return MISCREG_CNTPCT_EL0
;
2659 return MISCREG_CNTVCT_EL0
;
2665 return MISCREG_CNTP_TVAL_EL0
;
2667 return MISCREG_CNTP_CTL_EL0
;
2669 return MISCREG_CNTP_CVAL_EL0
;
2675 return MISCREG_CNTV_TVAL_EL0
;
2677 return MISCREG_CNTV_CTL_EL0
;
2679 return MISCREG_CNTV_CVAL_EL0
;
2685 return MISCREG_PMEVCNTR0_EL0
;
2687 return MISCREG_PMEVCNTR1_EL0
;
2689 return MISCREG_PMEVCNTR2_EL0
;
2691 return MISCREG_PMEVCNTR3_EL0
;
2693 return MISCREG_PMEVCNTR4_EL0
;
2695 return MISCREG_PMEVCNTR5_EL0
;
2701 return MISCREG_PMEVTYPER0_EL0
;
2703 return MISCREG_PMEVTYPER1_EL0
;
2705 return MISCREG_PMEVTYPER2_EL0
;
2707 return MISCREG_PMEVTYPER3_EL0
;
2709 return MISCREG_PMEVTYPER4_EL0
;
2711 return MISCREG_PMEVTYPER5_EL0
;
2717 return MISCREG_PMCCFILTR_EL0
;
2726 return MISCREG_CNTVOFF_EL2
;
2732 return MISCREG_CNTHCTL_EL2
;
2738 return MISCREG_CNTHP_TVAL_EL2
;
2740 return MISCREG_CNTHP_CTL_EL2
;
2742 return MISCREG_CNTHP_CVAL_EL2
;
2748 return MISCREG_CNTHV_TVAL_EL2
;
2750 return MISCREG_CNTHV_CTL_EL2
;
2752 return MISCREG_CNTHV_CVAL_EL2
;
2762 return MISCREG_CNTPS_TVAL_EL1
;
2764 return MISCREG_CNTPS_CTL_EL1
;
2766 return MISCREG_CNTPS_CVAL_EL1
;
2780 return MISCREG_IL1DATA0_EL1
;
2782 return MISCREG_IL1DATA1_EL1
;
2784 return MISCREG_IL1DATA2_EL1
;
2786 return MISCREG_IL1DATA3_EL1
;
2792 return MISCREG_DL1DATA0_EL1
;
2794 return MISCREG_DL1DATA1_EL1
;
2796 return MISCREG_DL1DATA2_EL1
;
2798 return MISCREG_DL1DATA3_EL1
;
2800 return MISCREG_DL1DATA4_EL1
;
2810 return MISCREG_L2ACTLR_EL1
;
2816 return MISCREG_CPUACTLR_EL1
;
2818 return MISCREG_CPUECTLR_EL1
;
2820 return MISCREG_CPUMERRSR_EL1
;
2822 return MISCREG_L2MERRSR_EL1
;
2828 return MISCREG_CBAR_EL1
;
2835 // S3_<op1>_15_<Cm>_<op2>
2836 return MISCREG_IMPDEF_UNIMPL
;
2841 return MISCREG_UNKNOWN
;
2844 bitset
<NUM_MISCREG_INFOS
> miscRegInfo
[NUM_MISCREGS
]; // initialized below
2847 ISA::initializeMiscRegMetadata()
2849 // the MiscReg metadata tables are shared across all instances of the
2850 // ISA object, so there's no need to initialize them multiple times.
2851 static bool completed
= false;
2855 // This boolean variable specifies if the system is running in aarch32 at
2856 // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
2857 // is running in aarch64 (aarch32EL3 = false)
2858 bool aarch32EL3
= haveSecurity
&& !highestELIs64
;
2860 // Set Privileged Access Never on taking an exception to EL1 (Arm 8.1+),
2864 // Implicit error synchronization event enable (Arm 8.2+), unsupported
2867 // Load Multiple and Store Multiple Atomicity and Ordering (Arm 8.2+),
2869 bool LSMAOE
= false;
2871 // No Trap Load Multiple and Store Multiple (Arm 8.2+), unsupported
2872 bool nTLSMD
= false;
2874 // Pointer authentication (Arm 8.3+), unsupported
2875 bool EnDA
= false; // using APDAKey_EL1 key of instr addrs in ELs 0,1
2876 bool EnDB
= false; // using APDBKey_EL1 key of instr addrs in ELs 0,1
2877 bool EnIA
= false; // using APIAKey_EL1 key of instr addrs in ELs 0,1
2878 bool EnIB
= false; // using APIBKey_EL1 key of instr addrs in ELs 0,1
2881 * Some registers alias with others, and therefore need to be translated.
2882 * When two mapping registers are given, they are the 32b lower and
2883 * upper halves, respectively, of the 64b register being mapped.
2884 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
2886 * NAM = "not architecturally mandated",
2887 * from ARM DDI 0487A.i, template text
2888 * "AArch64 System register ___ can be mapped to
2889 * AArch32 System register ___, but this is not
2890 * architecturally mandated."
2893 InitReg(MISCREG_CPSR
)
2895 InitReg(MISCREG_SPSR
)
2897 InitReg(MISCREG_SPSR_FIQ
)
2899 InitReg(MISCREG_SPSR_IRQ
)
2901 InitReg(MISCREG_SPSR_SVC
)
2903 InitReg(MISCREG_SPSR_MON
)
2905 InitReg(MISCREG_SPSR_ABT
)
2907 InitReg(MISCREG_SPSR_HYP
)
2909 InitReg(MISCREG_SPSR_UND
)
2911 InitReg(MISCREG_ELR_HYP
)
2913 InitReg(MISCREG_FPSID
)
2915 InitReg(MISCREG_FPSCR
)
2917 InitReg(MISCREG_MVFR1
)
2919 InitReg(MISCREG_MVFR0
)
2921 InitReg(MISCREG_FPEXC
)
2925 InitReg(MISCREG_CPSR_MODE
)
2927 InitReg(MISCREG_CPSR_Q
)
2929 InitReg(MISCREG_FPSCR_EXC
)
2931 InitReg(MISCREG_FPSCR_QC
)
2933 InitReg(MISCREG_LOCKADDR
)
2935 InitReg(MISCREG_LOCKFLAG
)
2937 InitReg(MISCREG_PRRR_MAIR0
)
2940 InitReg(MISCREG_PRRR_MAIR0_NS
)
2942 .privSecure(!aarch32EL3
)
2944 InitReg(MISCREG_PRRR_MAIR0_S
)
2947 InitReg(MISCREG_NMRR_MAIR1
)
2950 InitReg(MISCREG_NMRR_MAIR1_NS
)
2952 .privSecure(!aarch32EL3
)
2954 InitReg(MISCREG_NMRR_MAIR1_S
)
2957 InitReg(MISCREG_PMXEVTYPER_PMCCFILTR
)
2959 InitReg(MISCREG_SCTLR_RST
)
2961 InitReg(MISCREG_SEV_MAILBOX
)
2964 // AArch32 CP14 registers
2965 InitReg(MISCREG_DBGDIDR
)
2966 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2967 InitReg(MISCREG_DBGDSCRint
)
2968 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2969 InitReg(MISCREG_DBGDCCINT
)
2972 InitReg(MISCREG_DBGDTRTXint
)
2975 InitReg(MISCREG_DBGDTRRXint
)
2978 InitReg(MISCREG_DBGWFAR
)
2981 InitReg(MISCREG_DBGVCR
)
2984 InitReg(MISCREG_DBGDTRRXext
)
2987 InitReg(MISCREG_DBGDSCRext
)
2991 InitReg(MISCREG_DBGDTRTXext
)
2994 InitReg(MISCREG_DBGOSECCR
)
2997 InitReg(MISCREG_DBGBVR0
)
3000 InitReg(MISCREG_DBGBVR1
)
3003 InitReg(MISCREG_DBGBVR2
)
3006 InitReg(MISCREG_DBGBVR3
)
3009 InitReg(MISCREG_DBGBVR4
)
3012 InitReg(MISCREG_DBGBVR5
)
3015 InitReg(MISCREG_DBGBCR0
)
3018 InitReg(MISCREG_DBGBCR1
)
3021 InitReg(MISCREG_DBGBCR2
)
3024 InitReg(MISCREG_DBGBCR3
)
3027 InitReg(MISCREG_DBGBCR4
)
3030 InitReg(MISCREG_DBGBCR5
)
3033 InitReg(MISCREG_DBGWVR0
)
3036 InitReg(MISCREG_DBGWVR1
)
3039 InitReg(MISCREG_DBGWVR2
)
3042 InitReg(MISCREG_DBGWVR3
)
3045 InitReg(MISCREG_DBGWCR0
)
3048 InitReg(MISCREG_DBGWCR1
)
3051 InitReg(MISCREG_DBGWCR2
)
3054 InitReg(MISCREG_DBGWCR3
)
3057 InitReg(MISCREG_DBGDRAR
)
3059 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3060 InitReg(MISCREG_DBGBXVR4
)
3063 InitReg(MISCREG_DBGBXVR5
)
3066 InitReg(MISCREG_DBGOSLAR
)
3068 .allPrivileges().monSecureRead(0).monNonSecureRead(0);
3069 InitReg(MISCREG_DBGOSLSR
)
3071 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3072 InitReg(MISCREG_DBGOSDLR
)
3075 InitReg(MISCREG_DBGPRCR
)
3078 InitReg(MISCREG_DBGDSAR
)
3080 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3081 InitReg(MISCREG_DBGCLAIMSET
)
3084 InitReg(MISCREG_DBGCLAIMCLR
)
3087 InitReg(MISCREG_DBGAUTHSTATUS
)
3089 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3090 InitReg(MISCREG_DBGDEVID2
)
3092 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3093 InitReg(MISCREG_DBGDEVID1
)
3095 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3096 InitReg(MISCREG_DBGDEVID0
)
3098 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3099 InitReg(MISCREG_TEECR
)
3102 InitReg(MISCREG_JIDR
)
3104 InitReg(MISCREG_TEEHBR
)
3106 InitReg(MISCREG_JOSCR
)
3108 InitReg(MISCREG_JMCR
)
3111 // AArch32 CP15 registers
3112 InitReg(MISCREG_MIDR
)
3113 .allPrivileges().exceptUserMode().writes(0);
3114 InitReg(MISCREG_CTR
)
3115 .allPrivileges().exceptUserMode().writes(0);
3116 InitReg(MISCREG_TCMTR
)
3117 .allPrivileges().exceptUserMode().writes(0);
3118 InitReg(MISCREG_TLBTR
)
3119 .allPrivileges().exceptUserMode().writes(0);
3120 InitReg(MISCREG_MPIDR
)
3121 .allPrivileges().exceptUserMode().writes(0);
3122 InitReg(MISCREG_REVIDR
)
3125 .allPrivileges().exceptUserMode().writes(0);
3126 InitReg(MISCREG_ID_PFR0
)
3127 .allPrivileges().exceptUserMode().writes(0);
3128 InitReg(MISCREG_ID_PFR1
)
3129 .allPrivileges().exceptUserMode().writes(0);
3130 InitReg(MISCREG_ID_DFR0
)
3131 .allPrivileges().exceptUserMode().writes(0);
3132 InitReg(MISCREG_ID_AFR0
)
3133 .allPrivileges().exceptUserMode().writes(0);
3134 InitReg(MISCREG_ID_MMFR0
)
3135 .allPrivileges().exceptUserMode().writes(0);
3136 InitReg(MISCREG_ID_MMFR1
)
3137 .allPrivileges().exceptUserMode().writes(0);
3138 InitReg(MISCREG_ID_MMFR2
)
3139 .allPrivileges().exceptUserMode().writes(0);
3140 InitReg(MISCREG_ID_MMFR3
)
3141 .allPrivileges().exceptUserMode().writes(0);
3142 InitReg(MISCREG_ID_ISAR0
)
3143 .allPrivileges().exceptUserMode().writes(0);
3144 InitReg(MISCREG_ID_ISAR1
)
3145 .allPrivileges().exceptUserMode().writes(0);
3146 InitReg(MISCREG_ID_ISAR2
)
3147 .allPrivileges().exceptUserMode().writes(0);
3148 InitReg(MISCREG_ID_ISAR3
)
3149 .allPrivileges().exceptUserMode().writes(0);
3150 InitReg(MISCREG_ID_ISAR4
)
3151 .allPrivileges().exceptUserMode().writes(0);
3152 InitReg(MISCREG_ID_ISAR5
)
3153 .allPrivileges().exceptUserMode().writes(0);
3154 InitReg(MISCREG_CCSIDR
)
3155 .allPrivileges().exceptUserMode().writes(0);
3156 InitReg(MISCREG_CLIDR
)
3157 .allPrivileges().exceptUserMode().writes(0);
3158 InitReg(MISCREG_AIDR
)
3159 .allPrivileges().exceptUserMode().writes(0);
3160 InitReg(MISCREG_CSSELR
)
3162 InitReg(MISCREG_CSSELR_NS
)
3164 .privSecure(!aarch32EL3
)
3165 .nonSecure().exceptUserMode();
3166 InitReg(MISCREG_CSSELR_S
)
3168 .secure().exceptUserMode();
3169 InitReg(MISCREG_VPIDR
)
3170 .hyp().monNonSecure();
3171 InitReg(MISCREG_VMPIDR
)
3172 .hyp().monNonSecure();
3173 InitReg(MISCREG_SCTLR
)
3175 // readMiscRegNoEffect() uses this metadata
3176 // despite using children (below) as backing store
3178 .res1(0x00400800 | (SPAN
? 0 : 0x800000)
3179 | (LSMAOE
? 0 : 0x10)
3180 | (nTLSMD
? 0 : 0x8));
3181 InitReg(MISCREG_SCTLR_NS
)
3183 .privSecure(!aarch32EL3
)
3184 .nonSecure().exceptUserMode();
3185 InitReg(MISCREG_SCTLR_S
)
3187 .secure().exceptUserMode();
3188 InitReg(MISCREG_ACTLR
)
3190 InitReg(MISCREG_ACTLR_NS
)
3192 .privSecure(!aarch32EL3
)
3193 .nonSecure().exceptUserMode();
3194 InitReg(MISCREG_ACTLR_S
)
3196 .secure().exceptUserMode();
3197 InitReg(MISCREG_CPACR
)
3198 .allPrivileges().exceptUserMode();
3199 InitReg(MISCREG_SCR
)
3200 .mon().secure().exceptUserMode()
3201 .res0(0xff40) // [31:16], [6]
3202 .res1(0x0030); // [5:4]
3203 InitReg(MISCREG_SDER
)
3205 InitReg(MISCREG_NSACR
)
3206 .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
3207 InitReg(MISCREG_HSCTLR
)
3208 .hyp().monNonSecure()
3209 .res0(0x0512c7c0 | (EnDB
? 0 : 0x2000)
3210 | (IESB
? 0 : 0x200000)
3211 | (EnDA
? 0 : 0x8000000)
3212 | (EnIB
? 0 : 0x40000000)
3213 | (EnIA
? 0 : 0x80000000))
3215 InitReg(MISCREG_HACTLR
)
3216 .hyp().monNonSecure();
3217 InitReg(MISCREG_HCR
)
3218 .hyp().monNonSecure();
3219 InitReg(MISCREG_HDCR
)
3220 .hyp().monNonSecure();
3221 InitReg(MISCREG_HCPTR
)
3222 .hyp().monNonSecure();
3223 InitReg(MISCREG_HSTR
)
3224 .hyp().monNonSecure();
3225 InitReg(MISCREG_HACR
)
3228 .hyp().monNonSecure();
3229 InitReg(MISCREG_TTBR0
)
3231 InitReg(MISCREG_TTBR0_NS
)
3233 .privSecure(!aarch32EL3
)
3234 .nonSecure().exceptUserMode();
3235 InitReg(MISCREG_TTBR0_S
)
3237 .secure().exceptUserMode();
3238 InitReg(MISCREG_TTBR1
)
3240 InitReg(MISCREG_TTBR1_NS
)
3242 .privSecure(!aarch32EL3
)
3243 .nonSecure().exceptUserMode();
3244 InitReg(MISCREG_TTBR1_S
)
3246 .secure().exceptUserMode();
3247 InitReg(MISCREG_TTBCR
)
3249 InitReg(MISCREG_TTBCR_NS
)
3251 .privSecure(!aarch32EL3
)
3252 .nonSecure().exceptUserMode();
3253 InitReg(MISCREG_TTBCR_S
)
3255 .secure().exceptUserMode();
3256 InitReg(MISCREG_HTCR
)
3257 .hyp().monNonSecure();
3258 InitReg(MISCREG_VTCR
)
3259 .hyp().monNonSecure();
3260 InitReg(MISCREG_DACR
)
3262 InitReg(MISCREG_DACR_NS
)
3264 .privSecure(!aarch32EL3
)
3265 .nonSecure().exceptUserMode();
3266 InitReg(MISCREG_DACR_S
)
3268 .secure().exceptUserMode();
3269 InitReg(MISCREG_DFSR
)
3271 InitReg(MISCREG_DFSR_NS
)
3273 .privSecure(!aarch32EL3
)
3274 .nonSecure().exceptUserMode();
3275 InitReg(MISCREG_DFSR_S
)
3277 .secure().exceptUserMode();
3278 InitReg(MISCREG_IFSR
)
3280 InitReg(MISCREG_IFSR_NS
)
3282 .privSecure(!aarch32EL3
)
3283 .nonSecure().exceptUserMode();
3284 InitReg(MISCREG_IFSR_S
)
3286 .secure().exceptUserMode();
3287 InitReg(MISCREG_ADFSR
)
3291 InitReg(MISCREG_ADFSR_NS
)
3295 .privSecure(!aarch32EL3
)
3296 .nonSecure().exceptUserMode();
3297 InitReg(MISCREG_ADFSR_S
)
3301 .secure().exceptUserMode();
3302 InitReg(MISCREG_AIFSR
)
3306 InitReg(MISCREG_AIFSR_NS
)
3310 .privSecure(!aarch32EL3
)
3311 .nonSecure().exceptUserMode();
3312 InitReg(MISCREG_AIFSR_S
)
3316 .secure().exceptUserMode();
3317 InitReg(MISCREG_HADFSR
)
3318 .hyp().monNonSecure();
3319 InitReg(MISCREG_HAIFSR
)
3320 .hyp().monNonSecure();
3321 InitReg(MISCREG_HSR
)
3322 .hyp().monNonSecure();
3323 InitReg(MISCREG_DFAR
)
3325 InitReg(MISCREG_DFAR_NS
)
3327 .privSecure(!aarch32EL3
)
3328 .nonSecure().exceptUserMode();
3329 InitReg(MISCREG_DFAR_S
)
3331 .secure().exceptUserMode();
3332 InitReg(MISCREG_IFAR
)
3334 InitReg(MISCREG_IFAR_NS
)
3336 .privSecure(!aarch32EL3
)
3337 .nonSecure().exceptUserMode();
3338 InitReg(MISCREG_IFAR_S
)
3340 .secure().exceptUserMode();
3341 InitReg(MISCREG_HDFAR
)
3342 .hyp().monNonSecure();
3343 InitReg(MISCREG_HIFAR
)
3344 .hyp().monNonSecure();
3345 InitReg(MISCREG_HPFAR
)
3346 .hyp().monNonSecure();
3347 InitReg(MISCREG_ICIALLUIS
)
3350 .writes(1).exceptUserMode();
3351 InitReg(MISCREG_BPIALLIS
)
3354 .writes(1).exceptUserMode();
3355 InitReg(MISCREG_PAR
)
3357 InitReg(MISCREG_PAR_NS
)
3359 .privSecure(!aarch32EL3
)
3360 .nonSecure().exceptUserMode();
3361 InitReg(MISCREG_PAR_S
)
3363 .secure().exceptUserMode();
3364 InitReg(MISCREG_ICIALLU
)
3365 .writes(1).exceptUserMode();
3366 InitReg(MISCREG_ICIMVAU
)
3369 .writes(1).exceptUserMode();
3370 InitReg(MISCREG_CP15ISB
)
3372 InitReg(MISCREG_BPIALL
)
3375 .writes(1).exceptUserMode();
3376 InitReg(MISCREG_BPIMVA
)
3379 .writes(1).exceptUserMode();
3380 InitReg(MISCREG_DCIMVAC
)
3383 .writes(1).exceptUserMode();
3384 InitReg(MISCREG_DCISW
)
3387 .writes(1).exceptUserMode();
3388 InitReg(MISCREG_ATS1CPR
)
3389 .writes(1).exceptUserMode();
3390 InitReg(MISCREG_ATS1CPW
)
3391 .writes(1).exceptUserMode();
3392 InitReg(MISCREG_ATS1CUR
)
3393 .writes(1).exceptUserMode();
3394 InitReg(MISCREG_ATS1CUW
)
3395 .writes(1).exceptUserMode();
3396 InitReg(MISCREG_ATS12NSOPR
)
3397 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3398 InitReg(MISCREG_ATS12NSOPW
)
3399 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3400 InitReg(MISCREG_ATS12NSOUR
)
3401 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3402 InitReg(MISCREG_ATS12NSOUW
)
3403 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3404 InitReg(MISCREG_DCCMVAC
)
3405 .writes(1).exceptUserMode();
3406 InitReg(MISCREG_DCCSW
)
3409 .writes(1).exceptUserMode();
3410 InitReg(MISCREG_CP15DSB
)
3412 InitReg(MISCREG_CP15DMB
)
3414 InitReg(MISCREG_DCCMVAU
)
3417 .writes(1).exceptUserMode();
3418 InitReg(MISCREG_DCCIMVAC
)
3421 .writes(1).exceptUserMode();
3422 InitReg(MISCREG_DCCISW
)
3425 .writes(1).exceptUserMode();
3426 InitReg(MISCREG_ATS1HR
)
3427 .monNonSecureWrite().hypWrite();
3428 InitReg(MISCREG_ATS1HW
)
3429 .monNonSecureWrite().hypWrite();
3430 InitReg(MISCREG_TLBIALLIS
)
3431 .writes(1).exceptUserMode();
3432 InitReg(MISCREG_TLBIMVAIS
)
3433 .writes(1).exceptUserMode();
3434 InitReg(MISCREG_TLBIASIDIS
)
3435 .writes(1).exceptUserMode();
3436 InitReg(MISCREG_TLBIMVAAIS
)
3437 .writes(1).exceptUserMode();
3438 InitReg(MISCREG_TLBIMVALIS
)
3439 .writes(1).exceptUserMode();
3440 InitReg(MISCREG_TLBIMVAALIS
)
3441 .writes(1).exceptUserMode();
3442 InitReg(MISCREG_ITLBIALL
)
3443 .writes(1).exceptUserMode();
3444 InitReg(MISCREG_ITLBIMVA
)
3445 .writes(1).exceptUserMode();
3446 InitReg(MISCREG_ITLBIASID
)
3447 .writes(1).exceptUserMode();
3448 InitReg(MISCREG_DTLBIALL
)
3449 .writes(1).exceptUserMode();
3450 InitReg(MISCREG_DTLBIMVA
)
3451 .writes(1).exceptUserMode();
3452 InitReg(MISCREG_DTLBIASID
)
3453 .writes(1).exceptUserMode();
3454 InitReg(MISCREG_TLBIALL
)
3455 .writes(1).exceptUserMode();
3456 InitReg(MISCREG_TLBIMVA
)
3457 .writes(1).exceptUserMode();
3458 InitReg(MISCREG_TLBIASID
)
3459 .writes(1).exceptUserMode();
3460 InitReg(MISCREG_TLBIMVAA
)
3461 .writes(1).exceptUserMode();
3462 InitReg(MISCREG_TLBIMVAL
)
3463 .writes(1).exceptUserMode();
3464 InitReg(MISCREG_TLBIMVAAL
)
3465 .writes(1).exceptUserMode();
3466 InitReg(MISCREG_TLBIIPAS2IS
)
3467 .monNonSecureWrite().hypWrite();
3468 InitReg(MISCREG_TLBIIPAS2LIS
)
3469 .monNonSecureWrite().hypWrite();
3470 InitReg(MISCREG_TLBIALLHIS
)
3471 .monNonSecureWrite().hypWrite();
3472 InitReg(MISCREG_TLBIMVAHIS
)
3473 .monNonSecureWrite().hypWrite();
3474 InitReg(MISCREG_TLBIALLNSNHIS
)
3475 .monNonSecureWrite().hypWrite();
3476 InitReg(MISCREG_TLBIMVALHIS
)
3477 .monNonSecureWrite().hypWrite();
3478 InitReg(MISCREG_TLBIIPAS2
)
3479 .monNonSecureWrite().hypWrite();
3480 InitReg(MISCREG_TLBIIPAS2L
)
3481 .monNonSecureWrite().hypWrite();
3482 InitReg(MISCREG_TLBIALLH
)
3483 .monNonSecureWrite().hypWrite();
3484 InitReg(MISCREG_TLBIMVAH
)
3485 .monNonSecureWrite().hypWrite();
3486 InitReg(MISCREG_TLBIALLNSNH
)
3487 .monNonSecureWrite().hypWrite();
3488 InitReg(MISCREG_TLBIMVALH
)
3489 .monNonSecureWrite().hypWrite();
3490 InitReg(MISCREG_PMCR
)
3492 InitReg(MISCREG_PMCNTENSET
)
3494 InitReg(MISCREG_PMCNTENCLR
)
3496 InitReg(MISCREG_PMOVSR
)
3498 InitReg(MISCREG_PMSWINC
)
3500 InitReg(MISCREG_PMSELR
)
3502 InitReg(MISCREG_PMCEID0
)
3504 InitReg(MISCREG_PMCEID1
)
3506 InitReg(MISCREG_PMCCNTR
)
3508 InitReg(MISCREG_PMXEVTYPER
)
3510 InitReg(MISCREG_PMCCFILTR
)
3512 InitReg(MISCREG_PMXEVCNTR
)
3514 InitReg(MISCREG_PMUSERENR
)
3515 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
3516 InitReg(MISCREG_PMINTENSET
)
3517 .allPrivileges().exceptUserMode();
3518 InitReg(MISCREG_PMINTENCLR
)
3519 .allPrivileges().exceptUserMode();
3520 InitReg(MISCREG_PMOVSSET
)
3523 InitReg(MISCREG_L2CTLR
)
3524 .allPrivileges().exceptUserMode();
3525 InitReg(MISCREG_L2ECTLR
)
3527 .allPrivileges().exceptUserMode();
3528 InitReg(MISCREG_PRRR
)
3530 InitReg(MISCREG_PRRR_NS
)
3532 .privSecure(!aarch32EL3
)
3533 .nonSecure().exceptUserMode();
3534 InitReg(MISCREG_PRRR_S
)
3536 .secure().exceptUserMode();
3537 InitReg(MISCREG_MAIR0
)
3539 InitReg(MISCREG_MAIR0_NS
)
3541 .privSecure(!aarch32EL3
)
3542 .nonSecure().exceptUserMode();
3543 InitReg(MISCREG_MAIR0_S
)
3545 .secure().exceptUserMode();
3546 InitReg(MISCREG_NMRR
)
3548 InitReg(MISCREG_NMRR_NS
)
3550 .privSecure(!aarch32EL3
)
3551 .nonSecure().exceptUserMode();
3552 InitReg(MISCREG_NMRR_S
)
3554 .secure().exceptUserMode();
3555 InitReg(MISCREG_MAIR1
)
3557 InitReg(MISCREG_MAIR1_NS
)
3559 .privSecure(!aarch32EL3
)
3560 .nonSecure().exceptUserMode();
3561 InitReg(MISCREG_MAIR1_S
)
3563 .secure().exceptUserMode();
3564 InitReg(MISCREG_AMAIR0
)
3566 InitReg(MISCREG_AMAIR0_NS
)
3568 .privSecure(!aarch32EL3
)
3569 .nonSecure().exceptUserMode();
3570 InitReg(MISCREG_AMAIR0_S
)
3572 .secure().exceptUserMode();
3573 InitReg(MISCREG_AMAIR1
)
3575 InitReg(MISCREG_AMAIR1_NS
)
3577 .privSecure(!aarch32EL3
)
3578 .nonSecure().exceptUserMode();
3579 InitReg(MISCREG_AMAIR1_S
)
3581 .secure().exceptUserMode();
3582 InitReg(MISCREG_HMAIR0
)
3583 .hyp().monNonSecure();
3584 InitReg(MISCREG_HMAIR1
)
3585 .hyp().monNonSecure();
3586 InitReg(MISCREG_HAMAIR0
)
3589 .hyp().monNonSecure();
3590 InitReg(MISCREG_HAMAIR1
)
3593 .hyp().monNonSecure();
3594 InitReg(MISCREG_VBAR
)
3596 InitReg(MISCREG_VBAR_NS
)
3598 .privSecure(!aarch32EL3
)
3599 .nonSecure().exceptUserMode();
3600 InitReg(MISCREG_VBAR_S
)
3602 .secure().exceptUserMode();
3603 InitReg(MISCREG_MVBAR
)
3605 .hypRead(FullSystem
&& system
->highestEL() == EL2
)
3606 .privRead(FullSystem
&& system
->highestEL() == EL1
)
3608 InitReg(MISCREG_RMR
)
3610 .mon().secure().exceptUserMode();
3611 InitReg(MISCREG_ISR
)
3612 .allPrivileges().exceptUserMode().writes(0);
3613 InitReg(MISCREG_HVBAR
)
3614 .hyp().monNonSecure()
3616 InitReg(MISCREG_FCSEIDR
)
3619 .allPrivileges().exceptUserMode();
3620 InitReg(MISCREG_CONTEXTIDR
)
3622 InitReg(MISCREG_CONTEXTIDR_NS
)
3624 .privSecure(!aarch32EL3
)
3625 .nonSecure().exceptUserMode();
3626 InitReg(MISCREG_CONTEXTIDR_S
)
3628 .secure().exceptUserMode();
3629 InitReg(MISCREG_TPIDRURW
)
3631 InitReg(MISCREG_TPIDRURW_NS
)
3634 .privSecure(!aarch32EL3
)
3636 InitReg(MISCREG_TPIDRURW_S
)
3639 InitReg(MISCREG_TPIDRURO
)
3641 InitReg(MISCREG_TPIDRURO_NS
)
3644 .userNonSecureWrite(0).userSecureRead(1)
3645 .privSecure(!aarch32EL3
)
3647 InitReg(MISCREG_TPIDRURO_S
)
3649 .secure().userSecureWrite(0);
3650 InitReg(MISCREG_TPIDRPRW
)
3652 InitReg(MISCREG_TPIDRPRW_NS
)
3654 .nonSecure().exceptUserMode()
3655 .privSecure(!aarch32EL3
);
3656 InitReg(MISCREG_TPIDRPRW_S
)
3658 .secure().exceptUserMode();
3659 InitReg(MISCREG_HTPIDR
)
3660 .hyp().monNonSecure();
3661 InitReg(MISCREG_CNTFRQ
)
3664 InitReg(MISCREG_CNTKCTL
)
3665 .allPrivileges().exceptUserMode();
3666 InitReg(MISCREG_CNTP_TVAL
)
3668 InitReg(MISCREG_CNTP_TVAL_NS
)
3671 .privSecure(!aarch32EL3
)
3673 InitReg(MISCREG_CNTP_TVAL_S
)
3676 InitReg(MISCREG_CNTP_CTL
)
3678 InitReg(MISCREG_CNTP_CTL_NS
)
3681 .privSecure(!aarch32EL3
)
3683 InitReg(MISCREG_CNTP_CTL_S
)
3686 InitReg(MISCREG_CNTV_TVAL
)
3688 InitReg(MISCREG_CNTV_CTL
)
3690 InitReg(MISCREG_CNTHCTL
)
3691 .hypWrite().monNonSecureRead();
3692 InitReg(MISCREG_CNTHP_TVAL
)
3693 .hypWrite().monNonSecureRead();
3694 InitReg(MISCREG_CNTHP_CTL
)
3695 .hypWrite().monNonSecureRead();
3696 InitReg(MISCREG_IL1DATA0
)
3698 .allPrivileges().exceptUserMode();
3699 InitReg(MISCREG_IL1DATA1
)
3701 .allPrivileges().exceptUserMode();
3702 InitReg(MISCREG_IL1DATA2
)
3704 .allPrivileges().exceptUserMode();
3705 InitReg(MISCREG_IL1DATA3
)
3707 .allPrivileges().exceptUserMode();
3708 InitReg(MISCREG_DL1DATA0
)
3710 .allPrivileges().exceptUserMode();
3711 InitReg(MISCREG_DL1DATA1
)
3713 .allPrivileges().exceptUserMode();
3714 InitReg(MISCREG_DL1DATA2
)
3716 .allPrivileges().exceptUserMode();
3717 InitReg(MISCREG_DL1DATA3
)
3719 .allPrivileges().exceptUserMode();
3720 InitReg(MISCREG_DL1DATA4
)
3722 .allPrivileges().exceptUserMode();
3723 InitReg(MISCREG_RAMINDEX
)
3725 .writes(1).exceptUserMode();
3726 InitReg(MISCREG_L2ACTLR
)
3728 .allPrivileges().exceptUserMode();
3729 InitReg(MISCREG_CBAR
)
3731 .allPrivileges().exceptUserMode().writes(0);
3732 InitReg(MISCREG_HTTBR
)
3733 .hyp().monNonSecure();
3734 InitReg(MISCREG_VTTBR
)
3735 .hyp().monNonSecure();
3736 InitReg(MISCREG_CNTPCT
)
3738 InitReg(MISCREG_CNTVCT
)
3741 InitReg(MISCREG_CNTP_CVAL
)
3743 InitReg(MISCREG_CNTP_CVAL_NS
)
3746 .privSecure(!aarch32EL3
)
3748 InitReg(MISCREG_CNTP_CVAL_S
)
3751 InitReg(MISCREG_CNTV_CVAL
)
3753 InitReg(MISCREG_CNTVOFF
)
3754 .hyp().monNonSecure();
3755 InitReg(MISCREG_CNTHP_CVAL
)
3756 .hypWrite().monNonSecureRead();
3757 InitReg(MISCREG_CPUMERRSR
)
3759 .allPrivileges().exceptUserMode();
3760 InitReg(MISCREG_L2MERRSR
)
3763 .allPrivileges().exceptUserMode();
3765 // AArch64 registers (Op0=2);
3766 InitReg(MISCREG_MDCCINT_EL1
)
3768 InitReg(MISCREG_OSDTRRX_EL1
)
3770 .mapsTo(MISCREG_DBGDTRRXext
);
3771 InitReg(MISCREG_MDSCR_EL1
)
3773 .mapsTo(MISCREG_DBGDSCRext
);
3774 InitReg(MISCREG_OSDTRTX_EL1
)
3776 .mapsTo(MISCREG_DBGDTRTXext
);
3777 InitReg(MISCREG_OSECCR_EL1
)
3779 .mapsTo(MISCREG_DBGOSECCR
);
3780 InitReg(MISCREG_DBGBVR0_EL1
)
3782 .mapsTo(MISCREG_DBGBVR0
/*, MISCREG_DBGBXVR0 */);
3783 InitReg(MISCREG_DBGBVR1_EL1
)
3785 .mapsTo(MISCREG_DBGBVR1
/*, MISCREG_DBGBXVR1 */);
3786 InitReg(MISCREG_DBGBVR2_EL1
)
3788 .mapsTo(MISCREG_DBGBVR2
/*, MISCREG_DBGBXVR2 */);
3789 InitReg(MISCREG_DBGBVR3_EL1
)
3791 .mapsTo(MISCREG_DBGBVR3
/*, MISCREG_DBGBXVR3 */);
3792 InitReg(MISCREG_DBGBVR4_EL1
)
3794 .mapsTo(MISCREG_DBGBVR4
/*, MISCREG_DBGBXVR4 */);
3795 InitReg(MISCREG_DBGBVR5_EL1
)
3797 .mapsTo(MISCREG_DBGBVR5
/*, MISCREG_DBGBXVR5 */);
3798 InitReg(MISCREG_DBGBCR0_EL1
)
3800 .mapsTo(MISCREG_DBGBCR0
);
3801 InitReg(MISCREG_DBGBCR1_EL1
)
3803 .mapsTo(MISCREG_DBGBCR1
);
3804 InitReg(MISCREG_DBGBCR2_EL1
)
3806 .mapsTo(MISCREG_DBGBCR2
);
3807 InitReg(MISCREG_DBGBCR3_EL1
)
3809 .mapsTo(MISCREG_DBGBCR3
);
3810 InitReg(MISCREG_DBGBCR4_EL1
)
3812 .mapsTo(MISCREG_DBGBCR4
);
3813 InitReg(MISCREG_DBGBCR5_EL1
)
3815 .mapsTo(MISCREG_DBGBCR5
);
3816 InitReg(MISCREG_DBGWVR0_EL1
)
3818 .mapsTo(MISCREG_DBGWVR0
);
3819 InitReg(MISCREG_DBGWVR1_EL1
)
3821 .mapsTo(MISCREG_DBGWVR1
);
3822 InitReg(MISCREG_DBGWVR2_EL1
)
3824 .mapsTo(MISCREG_DBGWVR2
);
3825 InitReg(MISCREG_DBGWVR3_EL1
)
3827 .mapsTo(MISCREG_DBGWVR3
);
3828 InitReg(MISCREG_DBGWCR0_EL1
)
3830 .mapsTo(MISCREG_DBGWCR0
);
3831 InitReg(MISCREG_DBGWCR1_EL1
)
3833 .mapsTo(MISCREG_DBGWCR1
);
3834 InitReg(MISCREG_DBGWCR2_EL1
)
3836 .mapsTo(MISCREG_DBGWCR2
);
3837 InitReg(MISCREG_DBGWCR3_EL1
)
3839 .mapsTo(MISCREG_DBGWCR3
);
3840 InitReg(MISCREG_MDCCSR_EL0
)
3841 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3842 .mapsTo(MISCREG_DBGDSCRint
);
3843 InitReg(MISCREG_MDDTR_EL0
)
3845 InitReg(MISCREG_MDDTRTX_EL0
)
3847 InitReg(MISCREG_MDDTRRX_EL0
)
3849 InitReg(MISCREG_DBGVCR32_EL2
)
3851 .mapsTo(MISCREG_DBGVCR
);
3852 InitReg(MISCREG_MDRAR_EL1
)
3853 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3854 .mapsTo(MISCREG_DBGDRAR
);
3855 InitReg(MISCREG_OSLAR_EL1
)
3856 .allPrivileges().monSecureRead(0).monNonSecureRead(0)
3857 .mapsTo(MISCREG_DBGOSLAR
);
3858 InitReg(MISCREG_OSLSR_EL1
)
3859 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3860 .mapsTo(MISCREG_DBGOSLSR
);
3861 InitReg(MISCREG_OSDLR_EL1
)
3863 .mapsTo(MISCREG_DBGOSDLR
);
3864 InitReg(MISCREG_DBGPRCR_EL1
)
3866 .mapsTo(MISCREG_DBGPRCR
);
3867 InitReg(MISCREG_DBGCLAIMSET_EL1
)
3869 .mapsTo(MISCREG_DBGCLAIMSET
);
3870 InitReg(MISCREG_DBGCLAIMCLR_EL1
)
3872 .mapsTo(MISCREG_DBGCLAIMCLR
);
3873 InitReg(MISCREG_DBGAUTHSTATUS_EL1
)
3874 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3875 .mapsTo(MISCREG_DBGAUTHSTATUS
);
3876 InitReg(MISCREG_TEECR32_EL1
);
3877 InitReg(MISCREG_TEEHBR32_EL1
);
3879 // AArch64 registers (Op0=1,3);
3880 InitReg(MISCREG_MIDR_EL1
)
3881 .allPrivileges().exceptUserMode().writes(0);
3882 InitReg(MISCREG_MPIDR_EL1
)
3883 .allPrivileges().exceptUserMode().writes(0);
3884 InitReg(MISCREG_REVIDR_EL1
)
3885 .allPrivileges().exceptUserMode().writes(0);
3886 InitReg(MISCREG_ID_PFR0_EL1
)
3887 .allPrivileges().exceptUserMode().writes(0)
3888 .mapsTo(MISCREG_ID_PFR0
);
3889 InitReg(MISCREG_ID_PFR1_EL1
)
3890 .allPrivileges().exceptUserMode().writes(0)
3891 .mapsTo(MISCREG_ID_PFR1
);
3892 InitReg(MISCREG_ID_DFR0_EL1
)
3893 .allPrivileges().exceptUserMode().writes(0)
3894 .mapsTo(MISCREG_ID_DFR0
);
3895 InitReg(MISCREG_ID_AFR0_EL1
)
3896 .allPrivileges().exceptUserMode().writes(0)
3897 .mapsTo(MISCREG_ID_AFR0
);
3898 InitReg(MISCREG_ID_MMFR0_EL1
)
3899 .allPrivileges().exceptUserMode().writes(0)
3900 .mapsTo(MISCREG_ID_MMFR0
);
3901 InitReg(MISCREG_ID_MMFR1_EL1
)
3902 .allPrivileges().exceptUserMode().writes(0)
3903 .mapsTo(MISCREG_ID_MMFR1
);
3904 InitReg(MISCREG_ID_MMFR2_EL1
)
3905 .allPrivileges().exceptUserMode().writes(0)
3906 .mapsTo(MISCREG_ID_MMFR2
);
3907 InitReg(MISCREG_ID_MMFR3_EL1
)
3908 .allPrivileges().exceptUserMode().writes(0)
3909 .mapsTo(MISCREG_ID_MMFR3
);
3910 InitReg(MISCREG_ID_ISAR0_EL1
)
3911 .allPrivileges().exceptUserMode().writes(0)
3912 .mapsTo(MISCREG_ID_ISAR0
);
3913 InitReg(MISCREG_ID_ISAR1_EL1
)
3914 .allPrivileges().exceptUserMode().writes(0)
3915 .mapsTo(MISCREG_ID_ISAR1
);
3916 InitReg(MISCREG_ID_ISAR2_EL1
)
3917 .allPrivileges().exceptUserMode().writes(0)
3918 .mapsTo(MISCREG_ID_ISAR2
);
3919 InitReg(MISCREG_ID_ISAR3_EL1
)
3920 .allPrivileges().exceptUserMode().writes(0)
3921 .mapsTo(MISCREG_ID_ISAR3
);
3922 InitReg(MISCREG_ID_ISAR4_EL1
)
3923 .allPrivileges().exceptUserMode().writes(0)
3924 .mapsTo(MISCREG_ID_ISAR4
);
3925 InitReg(MISCREG_ID_ISAR5_EL1
)
3926 .allPrivileges().exceptUserMode().writes(0)
3927 .mapsTo(MISCREG_ID_ISAR5
);
3928 InitReg(MISCREG_MVFR0_EL1
)
3929 .allPrivileges().exceptUserMode().writes(0);
3930 InitReg(MISCREG_MVFR1_EL1
)
3931 .allPrivileges().exceptUserMode().writes(0);
3932 InitReg(MISCREG_MVFR2_EL1
)
3933 .allPrivileges().exceptUserMode().writes(0);
3934 InitReg(MISCREG_ID_AA64PFR0_EL1
)
3935 .allPrivileges().exceptUserMode().writes(0);
3936 InitReg(MISCREG_ID_AA64PFR1_EL1
)
3937 .allPrivileges().exceptUserMode().writes(0);
3938 InitReg(MISCREG_ID_AA64DFR0_EL1
)
3939 .allPrivileges().exceptUserMode().writes(0);
3940 InitReg(MISCREG_ID_AA64DFR1_EL1
)
3941 .allPrivileges().exceptUserMode().writes(0);
3942 InitReg(MISCREG_ID_AA64AFR0_EL1
)
3943 .allPrivileges().exceptUserMode().writes(0);
3944 InitReg(MISCREG_ID_AA64AFR1_EL1
)
3945 .allPrivileges().exceptUserMode().writes(0);
3946 InitReg(MISCREG_ID_AA64ISAR0_EL1
)
3947 .allPrivileges().exceptUserMode().writes(0);
3948 InitReg(MISCREG_ID_AA64ISAR1_EL1
)
3949 .allPrivileges().exceptUserMode().writes(0);
3950 InitReg(MISCREG_ID_AA64MMFR0_EL1
)
3951 .allPrivileges().exceptUserMode().writes(0);
3952 InitReg(MISCREG_ID_AA64MMFR1_EL1
)
3953 .allPrivileges().exceptUserMode().writes(0);
3954 InitReg(MISCREG_ID_AA64MMFR2_EL1
)
3955 .allPrivileges().exceptUserMode().writes(0);
3956 InitReg(MISCREG_CCSIDR_EL1
)
3957 .allPrivileges().exceptUserMode().writes(0);
3958 InitReg(MISCREG_CLIDR_EL1
)
3959 .allPrivileges().exceptUserMode().writes(0);
3960 InitReg(MISCREG_AIDR_EL1
)
3961 .allPrivileges().exceptUserMode().writes(0);
3962 InitReg(MISCREG_CSSELR_EL1
)
3963 .allPrivileges().exceptUserMode()
3964 .mapsTo(MISCREG_CSSELR_NS
);
3965 InitReg(MISCREG_CTR_EL0
)
3967 InitReg(MISCREG_DCZID_EL0
)
3969 InitReg(MISCREG_VPIDR_EL2
)
3971 .mapsTo(MISCREG_VPIDR
);
3972 InitReg(MISCREG_VMPIDR_EL2
)
3974 .mapsTo(MISCREG_VMPIDR
);
3975 InitReg(MISCREG_SCTLR_EL1
)
3976 .allPrivileges().exceptUserMode()
3977 .res0( 0x20440 | (EnDB
? 0 : 0x2000)
3978 | (IESB
? 0 : 0x200000)
3979 | (EnDA
? 0 : 0x8000000)
3980 | (EnIB
? 0 : 0x40000000)
3981 | (EnIA
? 0 : 0x80000000))
3982 .res1(0x500800 | (SPAN
? 0 : 0x800000)
3983 | (nTLSMD
? 0 : 0x8000000)
3984 | (LSMAOE
? 0 : 0x10000000))
3985 .mapsTo(MISCREG_SCTLR_NS
);
3986 InitReg(MISCREG_ACTLR_EL1
)
3987 .allPrivileges().exceptUserMode()
3988 .mapsTo(MISCREG_ACTLR_NS
);
3989 InitReg(MISCREG_CPACR_EL1
)
3990 .allPrivileges().exceptUserMode()
3991 .mapsTo(MISCREG_CPACR
);
3992 InitReg(MISCREG_SCTLR_EL2
)
3994 .res0(0x0512c7c0 | (EnDB
? 0 : 0x2000)
3995 | (IESB
? 0 : 0x200000)
3996 | (EnDA
? 0 : 0x8000000)
3997 | (EnIB
? 0 : 0x40000000)
3998 | (EnIA
? 0 : 0x80000000))
4000 .mapsTo(MISCREG_HSCTLR
);
4001 InitReg(MISCREG_ACTLR_EL2
)
4003 .mapsTo(MISCREG_HACTLR
);
4004 InitReg(MISCREG_HCR_EL2
)
4006 .mapsTo(MISCREG_HCR
/*, MISCREG_HCR2*/);
4007 InitReg(MISCREG_MDCR_EL2
)
4009 .mapsTo(MISCREG_HDCR
);
4010 InitReg(MISCREG_CPTR_EL2
)
4012 .mapsTo(MISCREG_HCPTR
);
4013 InitReg(MISCREG_HSTR_EL2
)
4015 .mapsTo(MISCREG_HSTR
);
4016 InitReg(MISCREG_HACR_EL2
)
4018 .mapsTo(MISCREG_HACR
);
4019 InitReg(MISCREG_SCTLR_EL3
)
4021 .res0(0x0512c7c0 | (EnDB
? 0 : 0x2000)
4022 | (IESB
? 0 : 0x200000)
4023 | (EnDA
? 0 : 0x8000000)
4024 | (EnIB
? 0 : 0x40000000)
4025 | (EnIA
? 0 : 0x80000000))
4027 InitReg(MISCREG_ACTLR_EL3
)
4029 InitReg(MISCREG_SCR_EL3
)
4031 .mapsTo(MISCREG_SCR
); // NAM D7-2005
4032 InitReg(MISCREG_SDER32_EL3
)
4034 .mapsTo(MISCREG_SDER
);
4035 InitReg(MISCREG_CPTR_EL3
)
4037 InitReg(MISCREG_MDCR_EL3
)
4039 InitReg(MISCREG_TTBR0_EL1
)
4040 .allPrivileges().exceptUserMode()
4041 .mapsTo(MISCREG_TTBR0_NS
);
4042 InitReg(MISCREG_TTBR1_EL1
)
4043 .allPrivileges().exceptUserMode()
4044 .mapsTo(MISCREG_TTBR1_NS
);
4045 InitReg(MISCREG_TCR_EL1
)
4046 .allPrivileges().exceptUserMode()
4047 .mapsTo(MISCREG_TTBCR_NS
);
4048 InitReg(MISCREG_TTBR0_EL2
)
4050 .mapsTo(MISCREG_HTTBR
);
4051 InitReg(MISCREG_TTBR1_EL2
)
4053 InitReg(MISCREG_TCR_EL2
)
4055 .mapsTo(MISCREG_HTCR
);
4056 InitReg(MISCREG_VTTBR_EL2
)
4058 .mapsTo(MISCREG_VTTBR
);
4059 InitReg(MISCREG_VTCR_EL2
)
4061 .mapsTo(MISCREG_VTCR
);
4062 InitReg(MISCREG_TTBR0_EL3
)
4064 InitReg(MISCREG_TCR_EL3
)
4066 InitReg(MISCREG_DACR32_EL2
)
4068 .mapsTo(MISCREG_DACR_NS
);
4069 InitReg(MISCREG_SPSR_EL1
)
4070 .allPrivileges().exceptUserMode()
4071 .mapsTo(MISCREG_SPSR_SVC
); // NAM C5.2.17 SPSR_EL1
4072 InitReg(MISCREG_ELR_EL1
)
4073 .allPrivileges().exceptUserMode();
4074 InitReg(MISCREG_SP_EL0
)
4075 .allPrivileges().exceptUserMode();
4076 InitReg(MISCREG_SPSEL
)
4077 .allPrivileges().exceptUserMode();
4078 InitReg(MISCREG_CURRENTEL
)
4079 .allPrivileges().exceptUserMode().writes(0);
4080 InitReg(MISCREG_PAN
)
4081 .allPrivileges().exceptUserMode()
4082 .implemented(havePAN
);
4083 InitReg(MISCREG_NZCV
)
4085 InitReg(MISCREG_DAIF
)
4087 InitReg(MISCREG_FPCR
)
4089 InitReg(MISCREG_FPSR
)
4091 InitReg(MISCREG_DSPSR_EL0
)
4093 InitReg(MISCREG_DLR_EL0
)
4095 InitReg(MISCREG_SPSR_EL2
)
4097 .mapsTo(MISCREG_SPSR_HYP
); // NAM C5.2.18 SPSR_EL2
4098 InitReg(MISCREG_ELR_EL2
)
4100 InitReg(MISCREG_SP_EL1
)
4102 InitReg(MISCREG_SPSR_IRQ_AA64
)
4104 InitReg(MISCREG_SPSR_ABT_AA64
)
4106 InitReg(MISCREG_SPSR_UND_AA64
)
4108 InitReg(MISCREG_SPSR_FIQ_AA64
)
4110 InitReg(MISCREG_SPSR_EL3
)
4112 .mapsTo(MISCREG_SPSR_MON
); // NAM C5.2.19 SPSR_EL3
4113 InitReg(MISCREG_ELR_EL3
)
4115 InitReg(MISCREG_SP_EL2
)
4117 InitReg(MISCREG_AFSR0_EL1
)
4118 .allPrivileges().exceptUserMode()
4119 .mapsTo(MISCREG_ADFSR_NS
);
4120 InitReg(MISCREG_AFSR1_EL1
)
4121 .allPrivileges().exceptUserMode()
4122 .mapsTo(MISCREG_AIFSR_NS
);
4123 InitReg(MISCREG_ESR_EL1
)
4124 .allPrivileges().exceptUserMode();
4125 InitReg(MISCREG_IFSR32_EL2
)
4127 .mapsTo(MISCREG_IFSR_NS
);
4128 InitReg(MISCREG_AFSR0_EL2
)
4130 .mapsTo(MISCREG_HADFSR
);
4131 InitReg(MISCREG_AFSR1_EL2
)
4133 .mapsTo(MISCREG_HAIFSR
);
4134 InitReg(MISCREG_ESR_EL2
)
4136 .mapsTo(MISCREG_HSR
);
4137 InitReg(MISCREG_FPEXC32_EL2
)
4138 .hyp().mon().mapsTo(MISCREG_FPEXC
);
4139 InitReg(MISCREG_AFSR0_EL3
)
4141 InitReg(MISCREG_AFSR1_EL3
)
4143 InitReg(MISCREG_ESR_EL3
)
4145 InitReg(MISCREG_FAR_EL1
)
4146 .allPrivileges().exceptUserMode()
4147 .mapsTo(MISCREG_DFAR_NS
, MISCREG_IFAR_NS
);
4148 InitReg(MISCREG_FAR_EL2
)
4150 .mapsTo(MISCREG_HDFAR
, MISCREG_HIFAR
);
4151 InitReg(MISCREG_HPFAR_EL2
)
4153 .mapsTo(MISCREG_HPFAR
);
4154 InitReg(MISCREG_FAR_EL3
)
4156 InitReg(MISCREG_IC_IALLUIS
)
4158 .writes(1).exceptUserMode();
4159 InitReg(MISCREG_PAR_EL1
)
4160 .allPrivileges().exceptUserMode()
4161 .mapsTo(MISCREG_PAR_NS
);
4162 InitReg(MISCREG_IC_IALLU
)
4164 .writes(1).exceptUserMode();
4165 InitReg(MISCREG_DC_IVAC_Xt
)
4167 .writes(1).exceptUserMode();
4168 InitReg(MISCREG_DC_ISW_Xt
)
4170 .writes(1).exceptUserMode();
4171 InitReg(MISCREG_AT_S1E1R_Xt
)
4172 .writes(1).exceptUserMode();
4173 InitReg(MISCREG_AT_S1E1W_Xt
)
4174 .writes(1).exceptUserMode();
4175 InitReg(MISCREG_AT_S1E0R_Xt
)
4176 .writes(1).exceptUserMode();
4177 InitReg(MISCREG_AT_S1E0W_Xt
)
4178 .writes(1).exceptUserMode();
4179 InitReg(MISCREG_DC_CSW_Xt
)
4181 .writes(1).exceptUserMode();
4182 InitReg(MISCREG_DC_CISW_Xt
)
4184 .writes(1).exceptUserMode();
4185 InitReg(MISCREG_DC_ZVA_Xt
)
4187 .writes(1).userSecureWrite(0);
4188 InitReg(MISCREG_IC_IVAU_Xt
)
4190 InitReg(MISCREG_DC_CVAC_Xt
)
4193 InitReg(MISCREG_DC_CVAU_Xt
)
4196 InitReg(MISCREG_DC_CIVAC_Xt
)
4199 InitReg(MISCREG_AT_S1E2R_Xt
)
4200 .monNonSecureWrite().hypWrite();
4201 InitReg(MISCREG_AT_S1E2W_Xt
)
4202 .monNonSecureWrite().hypWrite();
4203 InitReg(MISCREG_AT_S12E1R_Xt
)
4204 .hypWrite().monSecureWrite().monNonSecureWrite();
4205 InitReg(MISCREG_AT_S12E1W_Xt
)
4206 .hypWrite().monSecureWrite().monNonSecureWrite();
4207 InitReg(MISCREG_AT_S12E0R_Xt
)
4208 .hypWrite().monSecureWrite().monNonSecureWrite();
4209 InitReg(MISCREG_AT_S12E0W_Xt
)
4210 .hypWrite().monSecureWrite().monNonSecureWrite();
4211 InitReg(MISCREG_AT_S1E3R_Xt
)
4212 .monSecureWrite().monNonSecureWrite();
4213 InitReg(MISCREG_AT_S1E3W_Xt
)
4214 .monSecureWrite().monNonSecureWrite();
4215 InitReg(MISCREG_TLBI_VMALLE1IS
)
4216 .writes(1).exceptUserMode();
4217 InitReg(MISCREG_TLBI_VAE1IS_Xt
)
4218 .writes(1).exceptUserMode();
4219 InitReg(MISCREG_TLBI_ASIDE1IS_Xt
)
4220 .writes(1).exceptUserMode();
4221 InitReg(MISCREG_TLBI_VAAE1IS_Xt
)
4222 .writes(1).exceptUserMode();
4223 InitReg(MISCREG_TLBI_VALE1IS_Xt
)
4224 .writes(1).exceptUserMode();
4225 InitReg(MISCREG_TLBI_VAALE1IS_Xt
)
4226 .writes(1).exceptUserMode();
4227 InitReg(MISCREG_TLBI_VMALLE1
)
4228 .writes(1).exceptUserMode();
4229 InitReg(MISCREG_TLBI_VAE1_Xt
)
4230 .writes(1).exceptUserMode();
4231 InitReg(MISCREG_TLBI_ASIDE1_Xt
)
4232 .writes(1).exceptUserMode();
4233 InitReg(MISCREG_TLBI_VAAE1_Xt
)
4234 .writes(1).exceptUserMode();
4235 InitReg(MISCREG_TLBI_VALE1_Xt
)
4236 .writes(1).exceptUserMode();
4237 InitReg(MISCREG_TLBI_VAALE1_Xt
)
4238 .writes(1).exceptUserMode();
4239 InitReg(MISCREG_TLBI_IPAS2E1IS_Xt
)
4240 .hypWrite().monSecureWrite().monNonSecureWrite();
4241 InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt
)
4242 .hypWrite().monSecureWrite().monNonSecureWrite();
4243 InitReg(MISCREG_TLBI_ALLE2IS
)
4244 .monNonSecureWrite().hypWrite();
4245 InitReg(MISCREG_TLBI_VAE2IS_Xt
)
4246 .monNonSecureWrite().hypWrite();
4247 InitReg(MISCREG_TLBI_ALLE1IS
)
4248 .hypWrite().monSecureWrite().monNonSecureWrite();
4249 InitReg(MISCREG_TLBI_VALE2IS_Xt
)
4250 .monNonSecureWrite().hypWrite();
4251 InitReg(MISCREG_TLBI_VMALLS12E1IS
)
4252 .hypWrite().monSecureWrite().monNonSecureWrite();
4253 InitReg(MISCREG_TLBI_IPAS2E1_Xt
)
4254 .hypWrite().monSecureWrite().monNonSecureWrite();
4255 InitReg(MISCREG_TLBI_IPAS2LE1_Xt
)
4256 .hypWrite().monSecureWrite().monNonSecureWrite();
4257 InitReg(MISCREG_TLBI_ALLE2
)
4258 .monNonSecureWrite().hypWrite();
4259 InitReg(MISCREG_TLBI_VAE2_Xt
)
4260 .monNonSecureWrite().hypWrite();
4261 InitReg(MISCREG_TLBI_ALLE1
)
4262 .hypWrite().monSecureWrite().monNonSecureWrite();
4263 InitReg(MISCREG_TLBI_VALE2_Xt
)
4264 .monNonSecureWrite().hypWrite();
4265 InitReg(MISCREG_TLBI_VMALLS12E1
)
4266 .hypWrite().monSecureWrite().monNonSecureWrite();
4267 InitReg(MISCREG_TLBI_ALLE3IS
)
4268 .monSecureWrite().monNonSecureWrite();
4269 InitReg(MISCREG_TLBI_VAE3IS_Xt
)
4270 .monSecureWrite().monNonSecureWrite();
4271 InitReg(MISCREG_TLBI_VALE3IS_Xt
)
4272 .monSecureWrite().monNonSecureWrite();
4273 InitReg(MISCREG_TLBI_ALLE3
)
4274 .monSecureWrite().monNonSecureWrite();
4275 InitReg(MISCREG_TLBI_VAE3_Xt
)
4276 .monSecureWrite().monNonSecureWrite();
4277 InitReg(MISCREG_TLBI_VALE3_Xt
)
4278 .monSecureWrite().monNonSecureWrite();
4279 InitReg(MISCREG_PMINTENSET_EL1
)
4280 .allPrivileges().exceptUserMode()
4281 .mapsTo(MISCREG_PMINTENSET
);
4282 InitReg(MISCREG_PMINTENCLR_EL1
)
4283 .allPrivileges().exceptUserMode()
4284 .mapsTo(MISCREG_PMINTENCLR
);
4285 InitReg(MISCREG_PMCR_EL0
)
4287 .mapsTo(MISCREG_PMCR
);
4288 InitReg(MISCREG_PMCNTENSET_EL0
)
4290 .mapsTo(MISCREG_PMCNTENSET
);
4291 InitReg(MISCREG_PMCNTENCLR_EL0
)
4293 .mapsTo(MISCREG_PMCNTENCLR
);
4294 InitReg(MISCREG_PMOVSCLR_EL0
)
4296 // .mapsTo(MISCREG_PMOVSCLR);
4297 InitReg(MISCREG_PMSWINC_EL0
)
4299 .mapsTo(MISCREG_PMSWINC
);
4300 InitReg(MISCREG_PMSELR_EL0
)
4302 .mapsTo(MISCREG_PMSELR
);
4303 InitReg(MISCREG_PMCEID0_EL0
)
4305 .mapsTo(MISCREG_PMCEID0
);
4306 InitReg(MISCREG_PMCEID1_EL0
)
4308 .mapsTo(MISCREG_PMCEID1
);
4309 InitReg(MISCREG_PMCCNTR_EL0
)
4311 .mapsTo(MISCREG_PMCCNTR
);
4312 InitReg(MISCREG_PMXEVTYPER_EL0
)
4314 .mapsTo(MISCREG_PMXEVTYPER
);
4315 InitReg(MISCREG_PMCCFILTR_EL0
)
4317 InitReg(MISCREG_PMXEVCNTR_EL0
)
4319 .mapsTo(MISCREG_PMXEVCNTR
);
4320 InitReg(MISCREG_PMUSERENR_EL0
)
4321 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
4322 .mapsTo(MISCREG_PMUSERENR
);
4323 InitReg(MISCREG_PMOVSSET_EL0
)
4325 .mapsTo(MISCREG_PMOVSSET
);
4326 InitReg(MISCREG_MAIR_EL1
)
4327 .allPrivileges().exceptUserMode()
4328 .mapsTo(MISCREG_PRRR_NS
, MISCREG_NMRR_NS
);
4329 InitReg(MISCREG_AMAIR_EL1
)
4330 .allPrivileges().exceptUserMode()
4331 .mapsTo(MISCREG_AMAIR0_NS
, MISCREG_AMAIR1_NS
);
4332 InitReg(MISCREG_MAIR_EL2
)
4334 .mapsTo(MISCREG_HMAIR0
, MISCREG_HMAIR1
);
4335 InitReg(MISCREG_AMAIR_EL2
)
4337 .mapsTo(MISCREG_HAMAIR0
, MISCREG_HAMAIR1
);
4338 InitReg(MISCREG_MAIR_EL3
)
4340 InitReg(MISCREG_AMAIR_EL3
)
4342 InitReg(MISCREG_L2CTLR_EL1
)
4343 .allPrivileges().exceptUserMode();
4344 InitReg(MISCREG_L2ECTLR_EL1
)
4345 .allPrivileges().exceptUserMode();
4346 InitReg(MISCREG_VBAR_EL1
)
4347 .allPrivileges().exceptUserMode()
4348 .mapsTo(MISCREG_VBAR_NS
);
4349 InitReg(MISCREG_RVBAR_EL1
)
4350 .allPrivileges().exceptUserMode().writes(0);
4351 InitReg(MISCREG_ISR_EL1
)
4352 .allPrivileges().exceptUserMode().writes(0);
4353 InitReg(MISCREG_VBAR_EL2
)
4356 .mapsTo(MISCREG_HVBAR
);
4357 InitReg(MISCREG_RVBAR_EL2
)
4358 .mon().hyp().writes(0);
4359 InitReg(MISCREG_VBAR_EL3
)
4361 InitReg(MISCREG_RVBAR_EL3
)
4363 InitReg(MISCREG_RMR_EL3
)
4365 InitReg(MISCREG_CONTEXTIDR_EL1
)
4366 .allPrivileges().exceptUserMode()
4367 .mapsTo(MISCREG_CONTEXTIDR_NS
);
4368 InitReg(MISCREG_TPIDR_EL1
)
4369 .allPrivileges().exceptUserMode()
4370 .mapsTo(MISCREG_TPIDRPRW_NS
);
4371 InitReg(MISCREG_TPIDR_EL0
)
4373 .mapsTo(MISCREG_TPIDRURW_NS
);
4374 InitReg(MISCREG_TPIDRRO_EL0
)
4375 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
4376 .mapsTo(MISCREG_TPIDRURO_NS
);
4377 InitReg(MISCREG_TPIDR_EL2
)
4379 .mapsTo(MISCREG_HTPIDR
);
4380 InitReg(MISCREG_TPIDR_EL3
)
4382 InitReg(MISCREG_CNTKCTL_EL1
)
4383 .allPrivileges().exceptUserMode()
4384 .mapsTo(MISCREG_CNTKCTL
);
4385 InitReg(MISCREG_CNTFRQ_EL0
)
4387 .mapsTo(MISCREG_CNTFRQ
);
4388 InitReg(MISCREG_CNTPCT_EL0
)
4390 .mapsTo(MISCREG_CNTPCT
); /* 64b */
4391 InitReg(MISCREG_CNTVCT_EL0
)
4394 .mapsTo(MISCREG_CNTVCT
); /* 64b */
4395 InitReg(MISCREG_CNTP_TVAL_EL0
)
4397 .mapsTo(MISCREG_CNTP_TVAL_NS
);
4398 InitReg(MISCREG_CNTP_CTL_EL0
)
4400 .mapsTo(MISCREG_CNTP_CTL_NS
);
4401 InitReg(MISCREG_CNTP_CVAL_EL0
)
4403 .mapsTo(MISCREG_CNTP_CVAL_NS
); /* 64b */
4404 InitReg(MISCREG_CNTV_TVAL_EL0
)
4406 .mapsTo(MISCREG_CNTV_TVAL
);
4407 InitReg(MISCREG_CNTV_CTL_EL0
)
4409 .mapsTo(MISCREG_CNTV_CTL
);
4410 InitReg(MISCREG_CNTV_CVAL_EL0
)
4412 .mapsTo(MISCREG_CNTV_CVAL
); /* 64b */
4413 InitReg(MISCREG_PMEVCNTR0_EL0
)
4415 // .mapsTo(MISCREG_PMEVCNTR0);
4416 InitReg(MISCREG_PMEVCNTR1_EL0
)
4418 // .mapsTo(MISCREG_PMEVCNTR1);
4419 InitReg(MISCREG_PMEVCNTR2_EL0
)
4421 // .mapsTo(MISCREG_PMEVCNTR2);
4422 InitReg(MISCREG_PMEVCNTR3_EL0
)
4424 // .mapsTo(MISCREG_PMEVCNTR3);
4425 InitReg(MISCREG_PMEVCNTR4_EL0
)
4427 // .mapsTo(MISCREG_PMEVCNTR4);
4428 InitReg(MISCREG_PMEVCNTR5_EL0
)
4430 // .mapsTo(MISCREG_PMEVCNTR5);
4431 InitReg(MISCREG_PMEVTYPER0_EL0
)
4433 // .mapsTo(MISCREG_PMEVTYPER0);
4434 InitReg(MISCREG_PMEVTYPER1_EL0
)
4436 // .mapsTo(MISCREG_PMEVTYPER1);
4437 InitReg(MISCREG_PMEVTYPER2_EL0
)
4439 // .mapsTo(MISCREG_PMEVTYPER2);
4440 InitReg(MISCREG_PMEVTYPER3_EL0
)
4442 // .mapsTo(MISCREG_PMEVTYPER3);
4443 InitReg(MISCREG_PMEVTYPER4_EL0
)
4445 // .mapsTo(MISCREG_PMEVTYPER4);
4446 InitReg(MISCREG_PMEVTYPER5_EL0
)
4448 // .mapsTo(MISCREG_PMEVTYPER5);
4449 InitReg(MISCREG_CNTVOFF_EL2
)
4451 .mapsTo(MISCREG_CNTVOFF
); /* 64b */
4452 InitReg(MISCREG_CNTHCTL_EL2
)
4454 .mapsTo(MISCREG_CNTHCTL
);
4455 InitReg(MISCREG_CNTHP_TVAL_EL2
)
4457 .mapsTo(MISCREG_CNTHP_TVAL
);
4458 InitReg(MISCREG_CNTHP_CTL_EL2
)
4460 .mapsTo(MISCREG_CNTHP_CTL
);
4461 InitReg(MISCREG_CNTHP_CVAL_EL2
)
4463 .mapsTo(MISCREG_CNTHP_CVAL
); /* 64b */
4464 InitReg(MISCREG_CNTPS_TVAL_EL1
)
4465 .mon().privSecure();
4466 InitReg(MISCREG_CNTPS_CTL_EL1
)
4467 .mon().privSecure();
4468 InitReg(MISCREG_CNTPS_CVAL_EL1
)
4469 .mon().privSecure();
4470 InitReg(MISCREG_IL1DATA0_EL1
)
4471 .allPrivileges().exceptUserMode();
4472 InitReg(MISCREG_IL1DATA1_EL1
)
4473 .allPrivileges().exceptUserMode();
4474 InitReg(MISCREG_IL1DATA2_EL1
)
4475 .allPrivileges().exceptUserMode();
4476 InitReg(MISCREG_IL1DATA3_EL1
)
4477 .allPrivileges().exceptUserMode();
4478 InitReg(MISCREG_DL1DATA0_EL1
)
4479 .allPrivileges().exceptUserMode();
4480 InitReg(MISCREG_DL1DATA1_EL1
)
4481 .allPrivileges().exceptUserMode();
4482 InitReg(MISCREG_DL1DATA2_EL1
)
4483 .allPrivileges().exceptUserMode();
4484 InitReg(MISCREG_DL1DATA3_EL1
)
4485 .allPrivileges().exceptUserMode();
4486 InitReg(MISCREG_DL1DATA4_EL1
)
4487 .allPrivileges().exceptUserMode();
4488 InitReg(MISCREG_L2ACTLR_EL1
)
4489 .allPrivileges().exceptUserMode();
4490 InitReg(MISCREG_CPUACTLR_EL1
)
4491 .allPrivileges().exceptUserMode();
4492 InitReg(MISCREG_CPUECTLR_EL1
)
4493 .allPrivileges().exceptUserMode();
4494 InitReg(MISCREG_CPUMERRSR_EL1
)
4495 .allPrivileges().exceptUserMode();
4496 InitReg(MISCREG_L2MERRSR_EL1
)
4499 .allPrivileges().exceptUserMode();
4500 InitReg(MISCREG_CBAR_EL1
)
4501 .allPrivileges().exceptUserMode().writes(0);
4502 InitReg(MISCREG_CONTEXTIDR_EL2
)
4506 InitReg(MISCREG_ICC_PMR_EL1
)
4507 .res0(0xffffff00) // [31:8]
4508 .allPrivileges().exceptUserMode()
4509 .mapsTo(MISCREG_ICC_PMR
);
4510 InitReg(MISCREG_ICC_IAR0_EL1
)
4511 .allPrivileges().exceptUserMode().writes(0)
4512 .mapsTo(MISCREG_ICC_IAR0
);
4513 InitReg(MISCREG_ICC_EOIR0_EL1
)
4514 .allPrivileges().exceptUserMode().reads(0)
4515 .mapsTo(MISCREG_ICC_EOIR0
);
4516 InitReg(MISCREG_ICC_HPPIR0_EL1
)
4517 .allPrivileges().exceptUserMode().writes(0)
4518 .mapsTo(MISCREG_ICC_HPPIR0
);
4519 InitReg(MISCREG_ICC_BPR0_EL1
)
4520 .res0(0xfffffff8) // [31:3]
4521 .allPrivileges().exceptUserMode()
4522 .mapsTo(MISCREG_ICC_BPR0
);
4523 InitReg(MISCREG_ICC_AP0R0_EL1
)
4524 .allPrivileges().exceptUserMode()
4525 .mapsTo(MISCREG_ICC_AP0R0
);
4526 InitReg(MISCREG_ICC_AP0R1_EL1
)
4527 .allPrivileges().exceptUserMode()
4528 .mapsTo(MISCREG_ICC_AP0R1
);
4529 InitReg(MISCREG_ICC_AP0R2_EL1
)
4530 .allPrivileges().exceptUserMode()
4531 .mapsTo(MISCREG_ICC_AP0R2
);
4532 InitReg(MISCREG_ICC_AP0R3_EL1
)
4533 .allPrivileges().exceptUserMode()
4534 .mapsTo(MISCREG_ICC_AP0R3
);
4535 InitReg(MISCREG_ICC_AP1R0_EL1
)
4537 .mapsTo(MISCREG_ICC_AP1R0
);
4538 InitReg(MISCREG_ICC_AP1R0_EL1_NS
)
4540 .allPrivileges().exceptUserMode()
4541 .mapsTo(MISCREG_ICC_AP1R0_NS
);
4542 InitReg(MISCREG_ICC_AP1R0_EL1_S
)
4544 .allPrivileges().exceptUserMode()
4545 .mapsTo(MISCREG_ICC_AP1R0_S
);
4546 InitReg(MISCREG_ICC_AP1R1_EL1
)
4548 .mapsTo(MISCREG_ICC_AP1R1
);
4549 InitReg(MISCREG_ICC_AP1R1_EL1_NS
)
4551 .allPrivileges().exceptUserMode()
4552 .mapsTo(MISCREG_ICC_AP1R1_NS
);
4553 InitReg(MISCREG_ICC_AP1R1_EL1_S
)
4555 .allPrivileges().exceptUserMode()
4556 .mapsTo(MISCREG_ICC_AP1R1_S
);
4557 InitReg(MISCREG_ICC_AP1R2_EL1
)
4559 .mapsTo(MISCREG_ICC_AP1R2
);
4560 InitReg(MISCREG_ICC_AP1R2_EL1_NS
)
4562 .allPrivileges().exceptUserMode()
4563 .mapsTo(MISCREG_ICC_AP1R2_NS
);
4564 InitReg(MISCREG_ICC_AP1R2_EL1_S
)
4566 .allPrivileges().exceptUserMode()
4567 .mapsTo(MISCREG_ICC_AP1R2_S
);
4568 InitReg(MISCREG_ICC_AP1R3_EL1
)
4570 .mapsTo(MISCREG_ICC_AP1R3
);
4571 InitReg(MISCREG_ICC_AP1R3_EL1_NS
)
4573 .allPrivileges().exceptUserMode()
4574 .mapsTo(MISCREG_ICC_AP1R3_NS
);
4575 InitReg(MISCREG_ICC_AP1R3_EL1_S
)
4577 .allPrivileges().exceptUserMode()
4578 .mapsTo(MISCREG_ICC_AP1R3_S
);
4579 InitReg(MISCREG_ICC_DIR_EL1
)
4580 .res0(0xFF000000) // [31:24]
4581 .allPrivileges().exceptUserMode().reads(0)
4582 .mapsTo(MISCREG_ICC_DIR
);
4583 InitReg(MISCREG_ICC_RPR_EL1
)
4584 .allPrivileges().exceptUserMode().writes(0)
4585 .mapsTo(MISCREG_ICC_RPR
);
4586 InitReg(MISCREG_ICC_SGI1R_EL1
)
4587 .allPrivileges().exceptUserMode().reads(0)
4588 .mapsTo(MISCREG_ICC_SGI1R
);
4589 InitReg(MISCREG_ICC_ASGI1R_EL1
)
4590 .allPrivileges().exceptUserMode().reads(0)
4591 .mapsTo(MISCREG_ICC_ASGI1R
);
4592 InitReg(MISCREG_ICC_SGI0R_EL1
)
4593 .allPrivileges().exceptUserMode().reads(0)
4594 .mapsTo(MISCREG_ICC_SGI0R
);
4595 InitReg(MISCREG_ICC_IAR1_EL1
)
4596 .allPrivileges().exceptUserMode().writes(0)
4597 .mapsTo(MISCREG_ICC_IAR1
);
4598 InitReg(MISCREG_ICC_EOIR1_EL1
)
4599 .res0(0xFF000000) // [31:24]
4600 .allPrivileges().exceptUserMode().reads(0)
4601 .mapsTo(MISCREG_ICC_EOIR1
);
4602 InitReg(MISCREG_ICC_HPPIR1_EL1
)
4603 .allPrivileges().exceptUserMode().writes(0)
4604 .mapsTo(MISCREG_ICC_HPPIR1
);
4605 InitReg(MISCREG_ICC_BPR1_EL1
)
4607 .mapsTo(MISCREG_ICC_BPR1
);
4608 InitReg(MISCREG_ICC_BPR1_EL1_NS
)
4610 .res0(0xfffffff8) // [31:3]
4611 .allPrivileges().exceptUserMode()
4612 .mapsTo(MISCREG_ICC_BPR1_NS
);
4613 InitReg(MISCREG_ICC_BPR1_EL1_S
)
4615 .res0(0xfffffff8) // [31:3]
4616 .secure().exceptUserMode()
4617 .mapsTo(MISCREG_ICC_BPR1_S
);
4618 InitReg(MISCREG_ICC_CTLR_EL1
)
4620 .mapsTo(MISCREG_ICC_CTLR
);
4621 InitReg(MISCREG_ICC_CTLR_EL1_NS
)
4623 .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
4624 .allPrivileges().exceptUserMode()
4625 .mapsTo(MISCREG_ICC_CTLR_NS
);
4626 InitReg(MISCREG_ICC_CTLR_EL1_S
)
4628 .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
4629 .secure().exceptUserMode()
4630 .mapsTo(MISCREG_ICC_CTLR_S
);
4631 InitReg(MISCREG_ICC_SRE_EL1
)
4633 .mapsTo(MISCREG_ICC_SRE
);
4634 InitReg(MISCREG_ICC_SRE_EL1_NS
)
4636 .res0(0xFFFFFFF8) // [31:3]
4637 .allPrivileges().exceptUserMode()
4638 .mapsTo(MISCREG_ICC_SRE_NS
);
4639 InitReg(MISCREG_ICC_SRE_EL1_S
)
4641 .res0(0xFFFFFFF8) // [31:3]
4642 .secure().exceptUserMode()
4643 .mapsTo(MISCREG_ICC_SRE_S
);
4644 InitReg(MISCREG_ICC_IGRPEN0_EL1
)
4645 .res0(0xFFFFFFFE) // [31:1]
4646 .allPrivileges().exceptUserMode()
4647 .mapsTo(MISCREG_ICC_IGRPEN0
);
4648 InitReg(MISCREG_ICC_IGRPEN1_EL1
)
4650 .mapsTo(MISCREG_ICC_IGRPEN1
);
4651 InitReg(MISCREG_ICC_IGRPEN1_EL1_NS
)
4653 .res0(0xFFFFFFFE) // [31:1]
4654 .allPrivileges().exceptUserMode()
4655 .mapsTo(MISCREG_ICC_IGRPEN1_NS
);
4656 InitReg(MISCREG_ICC_IGRPEN1_EL1_S
)
4658 .res0(0xFFFFFFFE) // [31:1]
4659 .secure().exceptUserMode()
4660 .mapsTo(MISCREG_ICC_IGRPEN1_S
);
4661 InitReg(MISCREG_ICC_SRE_EL2
)
4663 .mapsTo(MISCREG_ICC_HSRE
);
4664 InitReg(MISCREG_ICC_CTLR_EL3
)
4665 .allPrivileges().exceptUserMode()
4666 .mapsTo(MISCREG_ICC_MCTLR
);
4667 InitReg(MISCREG_ICC_SRE_EL3
)
4668 .allPrivileges().exceptUserMode()
4669 .mapsTo(MISCREG_ICC_MSRE
);
4670 InitReg(MISCREG_ICC_IGRPEN1_EL3
)
4671 .allPrivileges().exceptUserMode()
4672 .mapsTo(MISCREG_ICC_MGRPEN1
);
4674 InitReg(MISCREG_ICH_AP0R0_EL2
)
4676 .mapsTo(MISCREG_ICH_AP0R0
);
4677 InitReg(MISCREG_ICH_AP0R1_EL2
)
4680 .mapsTo(MISCREG_ICH_AP0R1
);
4681 InitReg(MISCREG_ICH_AP0R2_EL2
)
4684 .mapsTo(MISCREG_ICH_AP0R2
);
4685 InitReg(MISCREG_ICH_AP0R3_EL2
)
4688 .mapsTo(MISCREG_ICH_AP0R3
);
4689 InitReg(MISCREG_ICH_AP1R0_EL2
)
4691 .mapsTo(MISCREG_ICH_AP1R0
);
4692 InitReg(MISCREG_ICH_AP1R1_EL2
)
4695 .mapsTo(MISCREG_ICH_AP1R1
);
4696 InitReg(MISCREG_ICH_AP1R2_EL2
)
4699 .mapsTo(MISCREG_ICH_AP1R2
);
4700 InitReg(MISCREG_ICH_AP1R3_EL2
)
4703 .mapsTo(MISCREG_ICH_AP1R3
);
4704 InitReg(MISCREG_ICH_HCR_EL2
)
4706 .mapsTo(MISCREG_ICH_HCR
);
4707 InitReg(MISCREG_ICH_VTR_EL2
)
4708 .hyp().mon().writes(0)
4709 .mapsTo(MISCREG_ICH_VTR
);
4710 InitReg(MISCREG_ICH_MISR_EL2
)
4711 .hyp().mon().writes(0)
4712 .mapsTo(MISCREG_ICH_MISR
);
4713 InitReg(MISCREG_ICH_EISR_EL2
)
4714 .hyp().mon().writes(0)
4715 .mapsTo(MISCREG_ICH_EISR
);
4716 InitReg(MISCREG_ICH_ELRSR_EL2
)
4717 .hyp().mon().writes(0)
4718 .mapsTo(MISCREG_ICH_ELRSR
);
4719 InitReg(MISCREG_ICH_VMCR_EL2
)
4721 .mapsTo(MISCREG_ICH_VMCR
);
4722 InitReg(MISCREG_ICH_LR0_EL2
)
4724 .allPrivileges().exceptUserMode();
4725 InitReg(MISCREG_ICH_LR1_EL2
)
4727 .allPrivileges().exceptUserMode();
4728 InitReg(MISCREG_ICH_LR2_EL2
)
4730 .allPrivileges().exceptUserMode();
4731 InitReg(MISCREG_ICH_LR3_EL2
)
4733 .allPrivileges().exceptUserMode();
4734 InitReg(MISCREG_ICH_LR4_EL2
)
4736 .allPrivileges().exceptUserMode();
4737 InitReg(MISCREG_ICH_LR5_EL2
)
4739 .allPrivileges().exceptUserMode();
4740 InitReg(MISCREG_ICH_LR6_EL2
)
4742 .allPrivileges().exceptUserMode();
4743 InitReg(MISCREG_ICH_LR7_EL2
)
4745 .allPrivileges().exceptUserMode();
4746 InitReg(MISCREG_ICH_LR8_EL2
)
4748 .allPrivileges().exceptUserMode();
4749 InitReg(MISCREG_ICH_LR9_EL2
)
4751 .allPrivileges().exceptUserMode();
4752 InitReg(MISCREG_ICH_LR10_EL2
)
4754 .allPrivileges().exceptUserMode();
4755 InitReg(MISCREG_ICH_LR11_EL2
)
4757 .allPrivileges().exceptUserMode();
4758 InitReg(MISCREG_ICH_LR12_EL2
)
4760 .allPrivileges().exceptUserMode();
4761 InitReg(MISCREG_ICH_LR13_EL2
)
4763 .allPrivileges().exceptUserMode();
4764 InitReg(MISCREG_ICH_LR14_EL2
)
4766 .allPrivileges().exceptUserMode();
4767 InitReg(MISCREG_ICH_LR15_EL2
)
4769 .allPrivileges().exceptUserMode();
4772 InitReg(MISCREG_ICC_AP0R0
)
4773 .allPrivileges().exceptUserMode();
4774 InitReg(MISCREG_ICC_AP0R1
)
4775 .allPrivileges().exceptUserMode();
4776 InitReg(MISCREG_ICC_AP0R2
)
4777 .allPrivileges().exceptUserMode();
4778 InitReg(MISCREG_ICC_AP0R3
)
4779 .allPrivileges().exceptUserMode();
4780 InitReg(MISCREG_ICC_AP1R0
)
4781 .allPrivileges().exceptUserMode();
4782 InitReg(MISCREG_ICC_AP1R0_NS
)
4783 .allPrivileges().exceptUserMode();
4784 InitReg(MISCREG_ICC_AP1R0_S
)
4785 .allPrivileges().exceptUserMode();
4786 InitReg(MISCREG_ICC_AP1R1
)
4787 .allPrivileges().exceptUserMode();
4788 InitReg(MISCREG_ICC_AP1R1_NS
)
4789 .allPrivileges().exceptUserMode();
4790 InitReg(MISCREG_ICC_AP1R1_S
)
4791 .allPrivileges().exceptUserMode();
4792 InitReg(MISCREG_ICC_AP1R2
)
4793 .allPrivileges().exceptUserMode();
4794 InitReg(MISCREG_ICC_AP1R2_NS
)
4795 .allPrivileges().exceptUserMode();
4796 InitReg(MISCREG_ICC_AP1R2_S
)
4797 .allPrivileges().exceptUserMode();
4798 InitReg(MISCREG_ICC_AP1R3
)
4799 .allPrivileges().exceptUserMode();
4800 InitReg(MISCREG_ICC_AP1R3_NS
)
4801 .allPrivileges().exceptUserMode();
4802 InitReg(MISCREG_ICC_AP1R3_S
)
4803 .allPrivileges().exceptUserMode();
4804 InitReg(MISCREG_ICC_ASGI1R
)
4805 .allPrivileges().exceptUserMode().reads(0);
4806 InitReg(MISCREG_ICC_BPR0
)
4807 .allPrivileges().exceptUserMode();
4808 InitReg(MISCREG_ICC_BPR1
)
4809 .allPrivileges().exceptUserMode();
4810 InitReg(MISCREG_ICC_BPR1_NS
)
4811 .allPrivileges().exceptUserMode();
4812 InitReg(MISCREG_ICC_BPR1_S
)
4813 .allPrivileges().exceptUserMode();
4814 InitReg(MISCREG_ICC_CTLR
)
4815 .allPrivileges().exceptUserMode();
4816 InitReg(MISCREG_ICC_CTLR_NS
)
4817 .allPrivileges().exceptUserMode();
4818 InitReg(MISCREG_ICC_CTLR_S
)
4819 .allPrivileges().exceptUserMode();
4820 InitReg(MISCREG_ICC_DIR
)
4821 .allPrivileges().exceptUserMode().reads(0);
4822 InitReg(MISCREG_ICC_EOIR0
)
4823 .allPrivileges().exceptUserMode().reads(0);
4824 InitReg(MISCREG_ICC_EOIR1
)
4825 .allPrivileges().exceptUserMode().reads(0);
4826 InitReg(MISCREG_ICC_HPPIR0
)
4827 .allPrivileges().exceptUserMode().writes(0);
4828 InitReg(MISCREG_ICC_HPPIR1
)
4829 .allPrivileges().exceptUserMode().writes(0);
4830 InitReg(MISCREG_ICC_HSRE
)
4831 .allPrivileges().exceptUserMode();
4832 InitReg(MISCREG_ICC_IAR0
)
4833 .allPrivileges().exceptUserMode().writes(0);
4834 InitReg(MISCREG_ICC_IAR1
)
4835 .allPrivileges().exceptUserMode().writes(0);
4836 InitReg(MISCREG_ICC_IGRPEN0
)
4837 .allPrivileges().exceptUserMode();
4838 InitReg(MISCREG_ICC_IGRPEN1
)
4839 .allPrivileges().exceptUserMode();
4840 InitReg(MISCREG_ICC_IGRPEN1_NS
)
4841 .allPrivileges().exceptUserMode();
4842 InitReg(MISCREG_ICC_IGRPEN1_S
)
4843 .allPrivileges().exceptUserMode();
4844 InitReg(MISCREG_ICC_MCTLR
)
4845 .allPrivileges().exceptUserMode();
4846 InitReg(MISCREG_ICC_MGRPEN1
)
4847 .allPrivileges().exceptUserMode();
4848 InitReg(MISCREG_ICC_MSRE
)
4849 .allPrivileges().exceptUserMode();
4850 InitReg(MISCREG_ICC_PMR
)
4851 .allPrivileges().exceptUserMode();
4852 InitReg(MISCREG_ICC_RPR
)
4853 .allPrivileges().exceptUserMode().writes(0);
4854 InitReg(MISCREG_ICC_SGI0R
)
4855 .allPrivileges().exceptUserMode().reads(0);
4856 InitReg(MISCREG_ICC_SGI1R
)
4857 .allPrivileges().exceptUserMode().reads(0);
4858 InitReg(MISCREG_ICC_SRE
)
4859 .allPrivileges().exceptUserMode();
4860 InitReg(MISCREG_ICC_SRE_NS
)
4861 .allPrivileges().exceptUserMode();
4862 InitReg(MISCREG_ICC_SRE_S
)
4863 .allPrivileges().exceptUserMode();
4865 InitReg(MISCREG_ICH_AP0R0
)
4867 InitReg(MISCREG_ICH_AP0R1
)
4869 InitReg(MISCREG_ICH_AP0R2
)
4871 InitReg(MISCREG_ICH_AP0R3
)
4873 InitReg(MISCREG_ICH_AP1R0
)
4875 InitReg(MISCREG_ICH_AP1R1
)
4877 InitReg(MISCREG_ICH_AP1R2
)
4879 InitReg(MISCREG_ICH_AP1R3
)
4881 InitReg(MISCREG_ICH_HCR
)
4883 InitReg(MISCREG_ICH_VTR
)
4884 .hyp().mon().writes(0);
4885 InitReg(MISCREG_ICH_MISR
)
4886 .hyp().mon().writes(0);
4887 InitReg(MISCREG_ICH_EISR
)
4888 .hyp().mon().writes(0);
4889 InitReg(MISCREG_ICH_ELRSR
)
4890 .hyp().mon().writes(0);
4891 InitReg(MISCREG_ICH_VMCR
)
4893 InitReg(MISCREG_ICH_LR0
)
4895 InitReg(MISCREG_ICH_LR1
)
4897 InitReg(MISCREG_ICH_LR2
)
4899 InitReg(MISCREG_ICH_LR3
)
4901 InitReg(MISCREG_ICH_LR4
)
4903 InitReg(MISCREG_ICH_LR5
)
4905 InitReg(MISCREG_ICH_LR6
)
4907 InitReg(MISCREG_ICH_LR7
)
4909 InitReg(MISCREG_ICH_LR8
)
4911 InitReg(MISCREG_ICH_LR9
)
4913 InitReg(MISCREG_ICH_LR10
)
4915 InitReg(MISCREG_ICH_LR11
)
4917 InitReg(MISCREG_ICH_LR12
)
4919 InitReg(MISCREG_ICH_LR13
)
4921 InitReg(MISCREG_ICH_LR14
)
4923 InitReg(MISCREG_ICH_LR15
)
4925 InitReg(MISCREG_ICH_LRC0
)
4926 .mapsTo(MISCREG_ICH_LR0
)
4928 InitReg(MISCREG_ICH_LRC1
)
4929 .mapsTo(MISCREG_ICH_LR1
)
4931 InitReg(MISCREG_ICH_LRC2
)
4932 .mapsTo(MISCREG_ICH_LR2
)
4934 InitReg(MISCREG_ICH_LRC3
)
4935 .mapsTo(MISCREG_ICH_LR3
)
4937 InitReg(MISCREG_ICH_LRC4
)
4938 .mapsTo(MISCREG_ICH_LR4
)
4940 InitReg(MISCREG_ICH_LRC5
)
4941 .mapsTo(MISCREG_ICH_LR5
)
4943 InitReg(MISCREG_ICH_LRC6
)
4944 .mapsTo(MISCREG_ICH_LR6
)
4946 InitReg(MISCREG_ICH_LRC7
)
4947 .mapsTo(MISCREG_ICH_LR7
)
4949 InitReg(MISCREG_ICH_LRC8
)
4950 .mapsTo(MISCREG_ICH_LR8
)
4952 InitReg(MISCREG_ICH_LRC9
)
4953 .mapsTo(MISCREG_ICH_LR9
)
4955 InitReg(MISCREG_ICH_LRC10
)
4956 .mapsTo(MISCREG_ICH_LR10
)
4958 InitReg(MISCREG_ICH_LRC11
)
4959 .mapsTo(MISCREG_ICH_LR11
)
4961 InitReg(MISCREG_ICH_LRC12
)
4962 .mapsTo(MISCREG_ICH_LR12
)
4964 InitReg(MISCREG_ICH_LRC13
)
4965 .mapsTo(MISCREG_ICH_LR13
)
4967 InitReg(MISCREG_ICH_LRC14
)
4968 .mapsTo(MISCREG_ICH_LR14
)
4970 InitReg(MISCREG_ICH_LRC15
)
4971 .mapsTo(MISCREG_ICH_LR15
)
4974 InitReg(MISCREG_CNTHV_CTL_EL2
)
4976 InitReg(MISCREG_CNTHV_CVAL_EL2
)
4978 InitReg(MISCREG_CNTHV_TVAL_EL2
)
4982 InitReg(MISCREG_ID_AA64ZFR0_EL1
)
4983 .allPrivileges().exceptUserMode().writes(0);
4984 InitReg(MISCREG_ZCR_EL3
)
4986 InitReg(MISCREG_ZCR_EL2
)
4988 InitReg(MISCREG_ZCR_EL12
)
4989 .unimplemented().warnNotFail();
4990 InitReg(MISCREG_ZCR_EL1
)
4991 .allPrivileges().exceptUserMode();
4994 InitReg(MISCREG_NOP
)
4996 InitReg(MISCREG_RAZ
)
4997 .allPrivileges().exceptUserMode().writes(0);
4998 InitReg(MISCREG_CP14_UNIMPL
)
5001 InitReg(MISCREG_CP15_UNIMPL
)
5004 InitReg(MISCREG_UNKNOWN
);
5005 InitReg(MISCREG_IMPDEF_UNIMPL
)
5007 .warnNotFail(impdefAsNop
);
5009 // RAS extension (unimplemented)
5010 InitReg(MISCREG_ERRIDR_EL1
)
5013 InitReg(MISCREG_ERRSELR_EL1
)
5016 InitReg(MISCREG_ERXFR_EL1
)
5019 InitReg(MISCREG_ERXCTLR_EL1
)
5022 InitReg(MISCREG_ERXSTATUS_EL1
)
5025 InitReg(MISCREG_ERXADDR_EL1
)
5028 InitReg(MISCREG_ERXMISC0_EL1
)
5031 InitReg(MISCREG_ERXMISC1_EL1
)
5034 InitReg(MISCREG_DISR_EL1
)
5037 InitReg(MISCREG_VSESR_EL2
)
5040 InitReg(MISCREG_VDISR_EL2
)
5044 // Register mappings for some unimplemented registers:
5048 // DBGDTR_EL0 -> DBGDTR{R or T}Xint
5049 // DBGDTRRX_EL0 -> DBGDTRRXint
5050 // DBGDTRTX_EL0 -> DBGDTRRXint
5051 // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
5056 } // namespace ArmISA