2 * Copyright (c) 2010-2013, 2015-2018 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include "arch/arm/miscregs.hh"
46 #include "arch/arm/isa.hh"
47 #include "base/logging.hh"
48 #include "cpu/thread_context.hh"
49 #include "sim/full_system.hh"
55 decodeCP14Reg(unsigned crn
, unsigned opc1
, unsigned crm
, unsigned opc2
)
65 return MISCREG_DBGDIDR
;
67 return MISCREG_DBGDSCRint
;
91 return MISCREG_TEEHBR
;
101 return MISCREG_JOSCR
;
123 // If we get here then it must be a register that we haven't implemented
124 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
125 crn
, opc1
, crm
, opc2
);
126 return MISCREG_CP14_UNIMPL
;
132 decodeCP15Reg(unsigned crn
, unsigned opc1
, unsigned crm
, unsigned opc2
)
144 return MISCREG_TCMTR
;
146 return MISCREG_TLBTR
;
148 return MISCREG_MPIDR
;
150 return MISCREG_REVIDR
;
158 return MISCREG_ID_PFR0
;
160 return MISCREG_ID_PFR1
;
162 return MISCREG_ID_DFR0
;
164 return MISCREG_ID_AFR0
;
166 return MISCREG_ID_MMFR0
;
168 return MISCREG_ID_MMFR1
;
170 return MISCREG_ID_MMFR2
;
172 return MISCREG_ID_MMFR3
;
178 return MISCREG_ID_ISAR0
;
180 return MISCREG_ID_ISAR1
;
182 return MISCREG_ID_ISAR2
;
184 return MISCREG_ID_ISAR3
;
186 return MISCREG_ID_ISAR4
;
188 return MISCREG_ID_ISAR5
;
191 return MISCREG_RAZ
; // read as zero
195 return MISCREG_RAZ
; // read as zero
202 return MISCREG_CCSIDR
;
204 return MISCREG_CLIDR
;
211 if (crm
== 0 && opc2
== 0) {
212 return MISCREG_CSSELR
;
218 return MISCREG_VPIDR
;
220 return MISCREG_VMPIDR
;
230 return MISCREG_SCTLR
;
232 return MISCREG_ACTLR
;
234 return MISCREG_CPACR
;
236 } else if (crm
== 1) {
243 return MISCREG_NSACR
;
246 } else if (opc1
== 4) {
249 return MISCREG_HSCTLR
;
251 return MISCREG_HACTLR
;
252 } else if (crm
== 1) {
259 return MISCREG_HCPTR
;
269 if (opc1
== 0 && crm
== 0) {
272 return MISCREG_TTBR0
;
274 return MISCREG_TTBR1
;
276 return MISCREG_TTBCR
;
278 } else if (opc1
== 4) {
279 if (crm
== 0 && opc2
== 2)
281 else if (crm
== 1 && opc2
== 2)
286 if (opc1
== 0 && crm
== 0 && opc2
== 0) {
295 } else if (opc2
== 1) {
298 } else if (crm
== 1) {
300 return MISCREG_ADFSR
;
301 } else if (opc2
== 1) {
302 return MISCREG_AIFSR
;
305 } else if (opc1
== 4) {
308 return MISCREG_HADFSR
;
310 return MISCREG_HAIFSR
;
311 } else if (crm
== 2 && opc2
== 0) {
317 if (opc1
== 0 && crm
== 0) {
324 } else if (opc1
== 4 && crm
== 0) {
327 return MISCREG_HDFAR
;
329 return MISCREG_HIFAR
;
331 return MISCREG_HPFAR
;
346 return MISCREG_ICIALLUIS
;
348 return MISCREG_BPIALLIS
;
359 return MISCREG_ICIALLU
;
361 return MISCREG_ICIMVAU
;
363 return MISCREG_CP15ISB
;
365 return MISCREG_BPIALL
;
367 return MISCREG_BPIMVA
;
372 return MISCREG_DCIMVAC
;
373 } else if (opc2
== 2) {
374 return MISCREG_DCISW
;
380 return MISCREG_ATS1CPR
;
382 return MISCREG_ATS1CPW
;
384 return MISCREG_ATS1CUR
;
386 return MISCREG_ATS1CUW
;
388 return MISCREG_ATS12NSOPR
;
390 return MISCREG_ATS12NSOPW
;
392 return MISCREG_ATS12NSOUR
;
394 return MISCREG_ATS12NSOUW
;
400 return MISCREG_DCCMVAC
;
402 return MISCREG_DCCSW
;
404 return MISCREG_CP15DSB
;
406 return MISCREG_CP15DMB
;
411 return MISCREG_DCCMVAU
;
421 return MISCREG_DCCIMVAC
;
422 } else if (opc2
== 2) {
423 return MISCREG_DCCISW
;
427 } else if (opc1
== 4 && crm
== 8) {
429 return MISCREG_ATS1HR
;
431 return MISCREG_ATS1HW
;
440 return MISCREG_TLBIALLIS
;
442 return MISCREG_TLBIMVAIS
;
444 return MISCREG_TLBIASIDIS
;
446 return MISCREG_TLBIMVAAIS
;
448 return MISCREG_TLBIMVALIS
;
450 return MISCREG_TLBIMVAALIS
;
456 return MISCREG_ITLBIALL
;
458 return MISCREG_ITLBIMVA
;
460 return MISCREG_ITLBIASID
;
466 return MISCREG_DTLBIALL
;
468 return MISCREG_DTLBIMVA
;
470 return MISCREG_DTLBIASID
;
476 return MISCREG_TLBIALL
;
478 return MISCREG_TLBIMVA
;
480 return MISCREG_TLBIASID
;
482 return MISCREG_TLBIMVAA
;
484 return MISCREG_TLBIMVAL
;
486 return MISCREG_TLBIMVAAL
;
490 } else if (opc1
== 4) {
494 return MISCREG_TLBIIPAS2IS
;
496 return MISCREG_TLBIIPAS2LIS
;
498 } else if (crm
== 3) {
501 return MISCREG_TLBIALLHIS
;
503 return MISCREG_TLBIMVAHIS
;
505 return MISCREG_TLBIALLNSNHIS
;
507 return MISCREG_TLBIMVALHIS
;
509 } else if (crm
== 4) {
512 return MISCREG_TLBIIPAS2
;
514 return MISCREG_TLBIIPAS2L
;
516 } else if (crm
== 7) {
519 return MISCREG_TLBIALLH
;
521 return MISCREG_TLBIMVAH
;
523 return MISCREG_TLBIALLNSNH
;
525 return MISCREG_TLBIMVALH
;
531 // Every cop register with CRn = 9 and CRm in
532 // {0-2}, {5-8} is implementation defined regardless
542 return MISCREG_IMPDEF_UNIMPL
;
551 return MISCREG_PMCNTENSET
;
553 return MISCREG_PMCNTENCLR
;
555 return MISCREG_PMOVSR
;
557 return MISCREG_PMSWINC
;
559 return MISCREG_PMSELR
;
561 return MISCREG_PMCEID0
;
563 return MISCREG_PMCEID1
;
569 return MISCREG_PMCCNTR
;
571 // Selector is PMSELR.SEL
572 return MISCREG_PMXEVTYPER_PMCCFILTR
;
574 return MISCREG_PMXEVCNTR
;
580 return MISCREG_PMUSERENR
;
582 return MISCREG_PMINTENSET
;
584 return MISCREG_PMINTENCLR
;
586 return MISCREG_PMOVSSET
;
590 } else if (opc1
== 1) {
594 case 2: // L2CTLR, L2 Control Register
595 return MISCREG_L2CTLR
;
597 return MISCREG_L2ECTLR
;
606 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
608 return MISCREG_IMPDEF_UNIMPL
;
609 } else if (crm
== 2) { // TEX Remap Registers
611 // Selector is TTBCR.EAE
612 return MISCREG_PRRR_MAIR0
;
613 } else if (opc2
== 1) {
614 // Selector is TTBCR.EAE
615 return MISCREG_NMRR_MAIR1
;
617 } else if (crm
== 3) {
619 return MISCREG_AMAIR0
;
620 } else if (opc2
== 1) {
621 return MISCREG_AMAIR1
;
624 } else if (opc1
== 4) {
625 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
628 return MISCREG_HMAIR0
;
630 return MISCREG_HMAIR1
;
631 } else if (crm
== 3) {
633 return MISCREG_HAMAIR0
;
635 return MISCREG_HAMAIR1
;
652 // Reserved for DMA operations for TCM access
653 return MISCREG_IMPDEF_UNIMPL
;
664 } else if (opc2
== 1) {
665 return MISCREG_MVBAR
;
667 } else if (crm
== 1) {
672 } else if (opc1
== 4) {
673 if (crm
== 0 && opc2
== 0)
674 return MISCREG_HVBAR
;
682 return MISCREG_FCSEIDR
;
684 return MISCREG_CONTEXTIDR
;
686 return MISCREG_TPIDRURW
;
688 return MISCREG_TPIDRURO
;
690 return MISCREG_TPIDRPRW
;
693 } else if (opc1
== 4) {
694 if (crm
== 0 && opc2
== 2)
695 return MISCREG_HTPIDR
;
703 return MISCREG_CNTFRQ
;
707 return MISCREG_CNTKCTL
;
711 return MISCREG_CNTP_TVAL
;
713 return MISCREG_CNTP_CTL
;
717 return MISCREG_CNTV_TVAL
;
719 return MISCREG_CNTV_CTL
;
722 } else if (opc1
== 4) {
723 if (crm
== 1 && opc2
== 0) {
724 return MISCREG_CNTHCTL
;
725 } else if (crm
== 2) {
727 return MISCREG_CNTHP_TVAL
;
729 return MISCREG_CNTHP_CTL
;
734 // Implementation defined
735 return MISCREG_IMPDEF_UNIMPL
;
737 // Unrecognized register
738 return MISCREG_CP15_UNIMPL
;
742 decodeCP15Reg64(unsigned crm
, unsigned opc1
)
748 return MISCREG_TTBR0
;
750 return MISCREG_TTBR1
;
752 return MISCREG_HTTBR
;
754 return MISCREG_VTTBR
;
764 return MISCREG_CNTPCT
;
766 return MISCREG_CNTVCT
;
768 return MISCREG_CNTP_CVAL
;
770 return MISCREG_CNTV_CVAL
;
772 return MISCREG_CNTVOFF
;
774 return MISCREG_CNTHP_CVAL
;
779 return MISCREG_CPUMERRSR
;
781 return MISCREG_L2MERRSR
;
784 // Unrecognized register
785 return MISCREG_CP15_UNIMPL
;
788 std::tuple
<bool, bool>
789 canReadCoprocReg(MiscRegIndex reg
, SCR scr
, CPSR cpsr
)
791 bool secure
= !scr
.ns
;
792 bool canRead
= false;
793 bool undefined
= false;
797 canRead
= secure
? miscRegInfo
[reg
][MISCREG_USR_S_RD
] :
798 miscRegInfo
[reg
][MISCREG_USR_NS_RD
];
806 canRead
= secure
? miscRegInfo
[reg
][MISCREG_PRI_S_RD
] :
807 miscRegInfo
[reg
][MISCREG_PRI_NS_RD
];
810 canRead
= secure
? miscRegInfo
[reg
][MISCREG_MON_NS0_RD
] :
811 miscRegInfo
[reg
][MISCREG_MON_NS1_RD
];
814 canRead
= miscRegInfo
[reg
][MISCREG_HYP_RD
];
819 // can't do permissions checkes on the root of a banked pair of regs
820 assert(!miscRegInfo
[reg
][MISCREG_BANKED
]);
821 return std::make_tuple(canRead
, undefined
);
824 std::tuple
<bool, bool>
825 canWriteCoprocReg(MiscRegIndex reg
, SCR scr
, CPSR cpsr
)
827 bool secure
= !scr
.ns
;
828 bool canWrite
= false;
829 bool undefined
= false;
833 canWrite
= secure
? miscRegInfo
[reg
][MISCREG_USR_S_WR
] :
834 miscRegInfo
[reg
][MISCREG_USR_NS_WR
];
842 canWrite
= secure
? miscRegInfo
[reg
][MISCREG_PRI_S_WR
] :
843 miscRegInfo
[reg
][MISCREG_PRI_NS_WR
];
846 canWrite
= secure
? miscRegInfo
[reg
][MISCREG_MON_NS0_WR
] :
847 miscRegInfo
[reg
][MISCREG_MON_NS1_WR
];
850 canWrite
= miscRegInfo
[reg
][MISCREG_HYP_WR
];
855 // can't do permissions checkes on the root of a banked pair of regs
856 assert(!miscRegInfo
[reg
][MISCREG_BANKED
]);
857 return std::make_tuple(canWrite
, undefined
);
861 snsBankedIndex(MiscRegIndex reg
, ThreadContext
*tc
)
863 SCR scr
= tc
->readMiscReg(MISCREG_SCR
);
864 return snsBankedIndex(reg
, tc
, scr
.ns
);
868 snsBankedIndex(MiscRegIndex reg
, ThreadContext
*tc
, bool ns
)
870 int reg_as_int
= static_cast<int>(reg
);
871 if (miscRegInfo
[reg
][MISCREG_BANKED
]) {
872 reg_as_int
+= (ArmSystem::haveSecurity(tc
) &&
873 !ArmSystem::highestELIs64(tc
) && !ns
) ? 2 : 1;
880 * If the reg is a child reg of a banked set, then the parent is the last
881 * banked one in the list. This is messy, and the wish is to eventually have
882 * the bitmap replaced with a better data structure. the preUnflatten function
883 * initializes a lookup table to speed up the search for these banked
887 int unflattenResultMiscReg
[NUM_MISCREGS
];
890 preUnflattenMiscReg()
893 for (int i
= 0 ; i
< NUM_MISCREGS
; i
++){
894 if (miscRegInfo
[i
][MISCREG_BANKED
])
896 if (miscRegInfo
[i
][MISCREG_BANKED_CHILD
])
897 unflattenResultMiscReg
[i
] = reg
;
899 unflattenResultMiscReg
[i
] = i
;
900 // if this assert fails, no parent was found, and something is broken
901 assert(unflattenResultMiscReg
[i
] > -1);
906 unflattenMiscReg(int reg
)
908 return unflattenResultMiscReg
[reg
];
912 canReadAArch64SysReg(MiscRegIndex reg
, SCR scr
, CPSR cpsr
, ThreadContext
*tc
)
914 // Check for SP_EL0 access while SPSEL == 0
915 if ((reg
== MISCREG_SP_EL0
) && (tc
->readMiscReg(MISCREG_SPSEL
) == 0))
918 // Check for RVBAR access
919 if (reg
== MISCREG_RVBAR_EL1
) {
920 ExceptionLevel highest_el
= ArmSystem::highestEL(tc
);
921 if (highest_el
== EL2
|| highest_el
== EL3
)
924 if (reg
== MISCREG_RVBAR_EL2
) {
925 ExceptionLevel highest_el
= ArmSystem::highestEL(tc
);
926 if (highest_el
== EL3
)
930 bool secure
= ArmSystem::haveSecurity(tc
) && !scr
.ns
;
932 switch (opModeToEL((OperatingMode
) (uint8_t) cpsr
.mode
)) {
934 return secure
? miscRegInfo
[reg
][MISCREG_USR_S_RD
] :
935 miscRegInfo
[reg
][MISCREG_USR_NS_RD
];
937 return secure
? miscRegInfo
[reg
][MISCREG_PRI_S_RD
] :
938 miscRegInfo
[reg
][MISCREG_PRI_NS_RD
];
940 return miscRegInfo
[reg
][MISCREG_HYP_RD
];
942 return secure
? miscRegInfo
[reg
][MISCREG_MON_NS0_RD
] :
943 miscRegInfo
[reg
][MISCREG_MON_NS1_RD
];
945 panic("Invalid exception level");
950 canWriteAArch64SysReg(MiscRegIndex reg
, SCR scr
, CPSR cpsr
, ThreadContext
*tc
)
952 // Check for SP_EL0 access while SPSEL == 0
953 if ((reg
== MISCREG_SP_EL0
) && (tc
->readMiscReg(MISCREG_SPSEL
) == 0))
955 ExceptionLevel el
= opModeToEL((OperatingMode
) (uint8_t) cpsr
.mode
);
956 if (reg
== MISCREG_DAIF
) {
957 SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR_EL1
);
958 if (el
== EL0
&& !sctlr
.uma
)
961 if (FullSystem
&& reg
== MISCREG_DC_ZVA_Xt
) {
962 // In syscall-emulation mode, this test is skipped and DCZVA is always
964 SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR_EL1
);
965 if (el
== EL0
&& !sctlr
.dze
)
968 if (reg
== MISCREG_DC_CVAC_Xt
|| reg
== MISCREG_DC_CIVAC_Xt
) {
969 SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR_EL1
);
970 if (el
== EL0
&& !sctlr
.uci
)
974 bool secure
= ArmSystem::haveSecurity(tc
) && !scr
.ns
;
978 return secure
? miscRegInfo
[reg
][MISCREG_USR_S_WR
] :
979 miscRegInfo
[reg
][MISCREG_USR_NS_WR
];
981 return secure
? miscRegInfo
[reg
][MISCREG_PRI_S_WR
] :
982 miscRegInfo
[reg
][MISCREG_PRI_NS_WR
];
984 return miscRegInfo
[reg
][MISCREG_HYP_WR
];
986 return secure
? miscRegInfo
[reg
][MISCREG_MON_NS0_WR
] :
987 miscRegInfo
[reg
][MISCREG_MON_NS1_WR
];
989 panic("Invalid exception level");
994 decodeAArch64SysReg(unsigned op0
, unsigned op1
,
995 unsigned crn
, unsigned crm
,
1008 return MISCREG_IC_IALLUIS
;
1014 return MISCREG_IC_IALLU
;
1020 return MISCREG_DC_IVAC_Xt
;
1022 return MISCREG_DC_ISW_Xt
;
1028 return MISCREG_AT_S1E1R_Xt
;
1030 return MISCREG_AT_S1E1W_Xt
;
1032 return MISCREG_AT_S1E0R_Xt
;
1034 return MISCREG_AT_S1E0W_Xt
;
1040 return MISCREG_DC_CSW_Xt
;
1046 return MISCREG_DC_CISW_Xt
;
1056 return MISCREG_DC_ZVA_Xt
;
1062 return MISCREG_IC_IVAU_Xt
;
1068 return MISCREG_DC_CVAC_Xt
;
1074 return MISCREG_DC_CVAU_Xt
;
1080 return MISCREG_DC_CIVAC_Xt
;
1090 return MISCREG_AT_S1E2R_Xt
;
1092 return MISCREG_AT_S1E2W_Xt
;
1094 return MISCREG_AT_S12E1R_Xt
;
1096 return MISCREG_AT_S12E1W_Xt
;
1098 return MISCREG_AT_S12E0R_Xt
;
1100 return MISCREG_AT_S12E0W_Xt
;
1110 return MISCREG_AT_S1E3R_Xt
;
1112 return MISCREG_AT_S1E3W_Xt
;
1126 return MISCREG_TLBI_VMALLE1IS
;
1128 return MISCREG_TLBI_VAE1IS_Xt
;
1130 return MISCREG_TLBI_ASIDE1IS_Xt
;
1132 return MISCREG_TLBI_VAAE1IS_Xt
;
1134 return MISCREG_TLBI_VALE1IS_Xt
;
1136 return MISCREG_TLBI_VAALE1IS_Xt
;
1142 return MISCREG_TLBI_VMALLE1
;
1144 return MISCREG_TLBI_VAE1_Xt
;
1146 return MISCREG_TLBI_ASIDE1_Xt
;
1148 return MISCREG_TLBI_VAAE1_Xt
;
1150 return MISCREG_TLBI_VALE1_Xt
;
1152 return MISCREG_TLBI_VAALE1_Xt
;
1162 return MISCREG_TLBI_IPAS2E1IS_Xt
;
1164 return MISCREG_TLBI_IPAS2LE1IS_Xt
;
1170 return MISCREG_TLBI_ALLE2IS
;
1172 return MISCREG_TLBI_VAE2IS_Xt
;
1174 return MISCREG_TLBI_ALLE1IS
;
1176 return MISCREG_TLBI_VALE2IS_Xt
;
1178 return MISCREG_TLBI_VMALLS12E1IS
;
1184 return MISCREG_TLBI_IPAS2E1_Xt
;
1186 return MISCREG_TLBI_IPAS2LE1_Xt
;
1192 return MISCREG_TLBI_ALLE2
;
1194 return MISCREG_TLBI_VAE2_Xt
;
1196 return MISCREG_TLBI_ALLE1
;
1198 return MISCREG_TLBI_VALE2_Xt
;
1200 return MISCREG_TLBI_VMALLS12E1
;
1210 return MISCREG_TLBI_ALLE3IS
;
1212 return MISCREG_TLBI_VAE3IS_Xt
;
1214 return MISCREG_TLBI_VALE3IS_Xt
;
1220 return MISCREG_TLBI_ALLE3
;
1222 return MISCREG_TLBI_VAE3_Xt
;
1224 return MISCREG_TLBI_VALE3_Xt
;
1242 return MISCREG_OSDTRRX_EL1
;
1244 return MISCREG_DBGBVR0_EL1
;
1246 return MISCREG_DBGBCR0_EL1
;
1248 return MISCREG_DBGWVR0_EL1
;
1250 return MISCREG_DBGWCR0_EL1
;
1256 return MISCREG_DBGBVR1_EL1
;
1258 return MISCREG_DBGBCR1_EL1
;
1260 return MISCREG_DBGWVR1_EL1
;
1262 return MISCREG_DBGWCR1_EL1
;
1268 return MISCREG_MDCCINT_EL1
;
1270 return MISCREG_MDSCR_EL1
;
1272 return MISCREG_DBGBVR2_EL1
;
1274 return MISCREG_DBGBCR2_EL1
;
1276 return MISCREG_DBGWVR2_EL1
;
1278 return MISCREG_DBGWCR2_EL1
;
1284 return MISCREG_OSDTRTX_EL1
;
1286 return MISCREG_DBGBVR3_EL1
;
1288 return MISCREG_DBGBCR3_EL1
;
1290 return MISCREG_DBGWVR3_EL1
;
1292 return MISCREG_DBGWCR3_EL1
;
1298 return MISCREG_DBGBVR4_EL1
;
1300 return MISCREG_DBGBCR4_EL1
;
1306 return MISCREG_DBGBVR5_EL1
;
1308 return MISCREG_DBGBCR5_EL1
;
1314 return MISCREG_OSECCR_EL1
;
1324 return MISCREG_TEECR32_EL1
;
1334 return MISCREG_MDCCSR_EL0
;
1340 return MISCREG_MDDTR_EL0
;
1346 return MISCREG_MDDTRRX_EL0
;
1356 return MISCREG_DBGVCR32_EL2
;
1370 return MISCREG_MDRAR_EL1
;
1372 return MISCREG_OSLAR_EL1
;
1378 return MISCREG_OSLSR_EL1
;
1384 return MISCREG_OSDLR_EL1
;
1390 return MISCREG_DBGPRCR_EL1
;
1400 return MISCREG_TEEHBR32_EL1
;
1414 return MISCREG_DBGCLAIMSET_EL1
;
1420 return MISCREG_DBGCLAIMCLR_EL1
;
1426 return MISCREG_DBGAUTHSTATUS_EL1
;
1444 return MISCREG_MIDR_EL1
;
1446 return MISCREG_MPIDR_EL1
;
1448 return MISCREG_REVIDR_EL1
;
1454 return MISCREG_ID_PFR0_EL1
;
1456 return MISCREG_ID_PFR1_EL1
;
1458 return MISCREG_ID_DFR0_EL1
;
1460 return MISCREG_ID_AFR0_EL1
;
1462 return MISCREG_ID_MMFR0_EL1
;
1464 return MISCREG_ID_MMFR1_EL1
;
1466 return MISCREG_ID_MMFR2_EL1
;
1468 return MISCREG_ID_MMFR3_EL1
;
1474 return MISCREG_ID_ISAR0_EL1
;
1476 return MISCREG_ID_ISAR1_EL1
;
1478 return MISCREG_ID_ISAR2_EL1
;
1480 return MISCREG_ID_ISAR3_EL1
;
1482 return MISCREG_ID_ISAR4_EL1
;
1484 return MISCREG_ID_ISAR5_EL1
;
1490 return MISCREG_MVFR0_EL1
;
1492 return MISCREG_MVFR1_EL1
;
1494 return MISCREG_MVFR2_EL1
;
1502 return MISCREG_ID_AA64PFR0_EL1
;
1504 return MISCREG_ID_AA64PFR1_EL1
;
1512 return MISCREG_ID_AA64DFR0_EL1
;
1514 return MISCREG_ID_AA64DFR1_EL1
;
1516 return MISCREG_ID_AA64AFR0_EL1
;
1518 return MISCREG_ID_AA64AFR1_EL1
;
1529 return MISCREG_ID_AA64ISAR0_EL1
;
1531 return MISCREG_ID_AA64ISAR1_EL1
;
1539 return MISCREG_ID_AA64MMFR0_EL1
;
1541 return MISCREG_ID_AA64MMFR1_EL1
;
1553 return MISCREG_CCSIDR_EL1
;
1555 return MISCREG_CLIDR_EL1
;
1557 return MISCREG_AIDR_EL1
;
1567 return MISCREG_CSSELR_EL1
;
1577 return MISCREG_CTR_EL0
;
1579 return MISCREG_DCZID_EL0
;
1589 return MISCREG_VPIDR_EL2
;
1591 return MISCREG_VMPIDR_EL2
;
1605 return MISCREG_SCTLR_EL1
;
1607 return MISCREG_ACTLR_EL1
;
1609 return MISCREG_CPACR_EL1
;
1619 return MISCREG_SCTLR_EL2
;
1621 return MISCREG_ACTLR_EL2
;
1627 return MISCREG_HCR_EL2
;
1629 return MISCREG_MDCR_EL2
;
1631 return MISCREG_CPTR_EL2
;
1633 return MISCREG_HSTR_EL2
;
1635 return MISCREG_HACR_EL2
;
1645 return MISCREG_SCTLR_EL3
;
1647 return MISCREG_ACTLR_EL3
;
1653 return MISCREG_SCR_EL3
;
1655 return MISCREG_SDER32_EL3
;
1657 return MISCREG_CPTR_EL3
;
1663 return MISCREG_MDCR_EL3
;
1677 return MISCREG_TTBR0_EL1
;
1679 return MISCREG_TTBR1_EL1
;
1681 return MISCREG_TCR_EL1
;
1691 return MISCREG_TTBR0_EL2
;
1693 return MISCREG_TTBR1_EL2
;
1695 return MISCREG_TCR_EL2
;
1701 return MISCREG_VTTBR_EL2
;
1703 return MISCREG_VTCR_EL2
;
1713 return MISCREG_TTBR0_EL3
;
1715 return MISCREG_TCR_EL3
;
1729 return MISCREG_DACR32_EL2
;
1743 return MISCREG_SPSR_EL1
;
1745 return MISCREG_ELR_EL1
;
1751 return MISCREG_SP_EL0
;
1757 return MISCREG_SPSEL
;
1759 return MISCREG_CURRENTEL
;
1769 return MISCREG_NZCV
;
1771 return MISCREG_DAIF
;
1777 return MISCREG_FPCR
;
1779 return MISCREG_FPSR
;
1785 return MISCREG_DSPSR_EL0
;
1787 return MISCREG_DLR_EL0
;
1797 return MISCREG_SPSR_EL2
;
1799 return MISCREG_ELR_EL2
;
1805 return MISCREG_SP_EL1
;
1811 return MISCREG_SPSR_IRQ_AA64
;
1813 return MISCREG_SPSR_ABT_AA64
;
1815 return MISCREG_SPSR_UND_AA64
;
1817 return MISCREG_SPSR_FIQ_AA64
;
1827 return MISCREG_SPSR_EL3
;
1829 return MISCREG_ELR_EL3
;
1835 return MISCREG_SP_EL2
;
1849 return MISCREG_AFSR0_EL1
;
1851 return MISCREG_AFSR1_EL1
;
1857 return MISCREG_ESR_EL1
;
1867 return MISCREG_IFSR32_EL2
;
1873 return MISCREG_AFSR0_EL2
;
1875 return MISCREG_AFSR1_EL2
;
1881 return MISCREG_ESR_EL2
;
1887 return MISCREG_FPEXC32_EL2
;
1897 return MISCREG_AFSR0_EL3
;
1899 return MISCREG_AFSR1_EL3
;
1905 return MISCREG_ESR_EL3
;
1919 return MISCREG_FAR_EL1
;
1929 return MISCREG_FAR_EL2
;
1931 return MISCREG_HPFAR_EL2
;
1941 return MISCREG_FAR_EL3
;
1955 return MISCREG_PAR_EL1
;
1969 return MISCREG_PMINTENSET_EL1
;
1971 return MISCREG_PMINTENCLR_EL1
;
1981 return MISCREG_PMCR_EL0
;
1983 return MISCREG_PMCNTENSET_EL0
;
1985 return MISCREG_PMCNTENCLR_EL0
;
1987 return MISCREG_PMOVSCLR_EL0
;
1989 return MISCREG_PMSWINC_EL0
;
1991 return MISCREG_PMSELR_EL0
;
1993 return MISCREG_PMCEID0_EL0
;
1995 return MISCREG_PMCEID1_EL0
;
2001 return MISCREG_PMCCNTR_EL0
;
2003 return MISCREG_PMXEVTYPER_EL0
;
2005 return MISCREG_PMXEVCNTR_EL0
;
2011 return MISCREG_PMUSERENR_EL0
;
2013 return MISCREG_PMOVSSET_EL0
;
2027 return MISCREG_MAIR_EL1
;
2033 return MISCREG_AMAIR_EL1
;
2043 return MISCREG_MAIR_EL2
;
2049 return MISCREG_AMAIR_EL2
;
2059 return MISCREG_MAIR_EL3
;
2065 return MISCREG_AMAIR_EL3
;
2079 return MISCREG_L2CTLR_EL1
;
2081 return MISCREG_L2ECTLR_EL1
;
2095 return MISCREG_VBAR_EL1
;
2097 return MISCREG_RVBAR_EL1
;
2103 return MISCREG_ISR_EL1
;
2113 return MISCREG_VBAR_EL2
;
2115 return MISCREG_RVBAR_EL2
;
2125 return MISCREG_VBAR_EL3
;
2127 return MISCREG_RVBAR_EL3
;
2129 return MISCREG_RMR_EL3
;
2143 return MISCREG_CONTEXTIDR_EL1
;
2145 return MISCREG_TPIDR_EL1
;
2155 return MISCREG_TPIDR_EL0
;
2157 return MISCREG_TPIDRRO_EL0
;
2167 return MISCREG_CONTEXTIDR_EL2
;
2169 return MISCREG_TPIDR_EL2
;
2179 return MISCREG_TPIDR_EL3
;
2193 return MISCREG_CNTKCTL_EL1
;
2203 return MISCREG_CNTFRQ_EL0
;
2205 return MISCREG_CNTPCT_EL0
;
2207 return MISCREG_CNTVCT_EL0
;
2213 return MISCREG_CNTP_TVAL_EL0
;
2215 return MISCREG_CNTP_CTL_EL0
;
2217 return MISCREG_CNTP_CVAL_EL0
;
2223 return MISCREG_CNTV_TVAL_EL0
;
2225 return MISCREG_CNTV_CTL_EL0
;
2227 return MISCREG_CNTV_CVAL_EL0
;
2233 return MISCREG_PMEVCNTR0_EL0
;
2235 return MISCREG_PMEVCNTR1_EL0
;
2237 return MISCREG_PMEVCNTR2_EL0
;
2239 return MISCREG_PMEVCNTR3_EL0
;
2241 return MISCREG_PMEVCNTR4_EL0
;
2243 return MISCREG_PMEVCNTR5_EL0
;
2249 return MISCREG_PMEVTYPER0_EL0
;
2251 return MISCREG_PMEVTYPER1_EL0
;
2253 return MISCREG_PMEVTYPER2_EL0
;
2255 return MISCREG_PMEVTYPER3_EL0
;
2257 return MISCREG_PMEVTYPER4_EL0
;
2259 return MISCREG_PMEVTYPER5_EL0
;
2265 return MISCREG_PMCCFILTR_EL0
;
2274 return MISCREG_CNTVOFF_EL2
;
2280 return MISCREG_CNTHCTL_EL2
;
2286 return MISCREG_CNTHP_TVAL_EL2
;
2288 return MISCREG_CNTHP_CTL_EL2
;
2290 return MISCREG_CNTHP_CVAL_EL2
;
2300 return MISCREG_CNTPS_TVAL_EL1
;
2302 return MISCREG_CNTPS_CTL_EL1
;
2304 return MISCREG_CNTPS_CVAL_EL1
;
2318 return MISCREG_IL1DATA0_EL1
;
2320 return MISCREG_IL1DATA1_EL1
;
2322 return MISCREG_IL1DATA2_EL1
;
2324 return MISCREG_IL1DATA3_EL1
;
2330 return MISCREG_DL1DATA0_EL1
;
2332 return MISCREG_DL1DATA1_EL1
;
2334 return MISCREG_DL1DATA2_EL1
;
2336 return MISCREG_DL1DATA3_EL1
;
2338 return MISCREG_DL1DATA4_EL1
;
2348 return MISCREG_L2ACTLR_EL1
;
2354 return MISCREG_CPUACTLR_EL1
;
2356 return MISCREG_CPUECTLR_EL1
;
2358 return MISCREG_CPUMERRSR_EL1
;
2360 return MISCREG_L2MERRSR_EL1
;
2366 return MISCREG_CBAR_EL1
;
2378 return MISCREG_UNKNOWN
;
2381 bitset
<NUM_MISCREG_INFOS
> miscRegInfo
[NUM_MISCREGS
]; // initialized below
2384 ISA::initializeMiscRegMetadata()
2386 // the MiscReg metadata tables are shared across all instances of the
2387 // ISA object, so there's no need to initialize them multiple times.
2388 static bool completed
= false;
2392 // This boolean variable specifies if the system is running in aarch32 at
2393 // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
2394 // is running in aarch64 (aarch32EL3 = false)
2395 bool aarch32EL3
= haveSecurity
&& !highestELIs64
;
2398 * Some registers alias with others, and therefore need to be translated.
2399 * When two mapping registers are given, they are the 32b lower and
2400 * upper halves, respectively, of the 64b register being mapped.
2401 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
2403 * NAM = "not architecturally mandated",
2404 * from ARM DDI 0487A.i, template text
2405 * "AArch64 System register ___ can be mapped to
2406 * AArch32 System register ___, but this is not
2407 * architecturally mandated."
2410 InitReg(MISCREG_CPSR
)
2412 InitReg(MISCREG_SPSR
)
2414 InitReg(MISCREG_SPSR_FIQ
)
2416 InitReg(MISCREG_SPSR_IRQ
)
2418 InitReg(MISCREG_SPSR_SVC
)
2420 InitReg(MISCREG_SPSR_MON
)
2422 InitReg(MISCREG_SPSR_ABT
)
2424 InitReg(MISCREG_SPSR_HYP
)
2426 InitReg(MISCREG_SPSR_UND
)
2428 InitReg(MISCREG_ELR_HYP
)
2430 InitReg(MISCREG_FPSID
)
2432 InitReg(MISCREG_FPSCR
)
2434 InitReg(MISCREG_MVFR1
)
2436 InitReg(MISCREG_MVFR0
)
2438 InitReg(MISCREG_FPEXC
)
2442 InitReg(MISCREG_CPSR_MODE
)
2444 InitReg(MISCREG_CPSR_Q
)
2446 InitReg(MISCREG_FPSCR_EXC
)
2448 InitReg(MISCREG_FPSCR_QC
)
2450 InitReg(MISCREG_LOCKADDR
)
2452 InitReg(MISCREG_LOCKFLAG
)
2454 InitReg(MISCREG_PRRR_MAIR0
)
2457 InitReg(MISCREG_PRRR_MAIR0_NS
)
2459 .privSecure(!aarch32EL3
)
2461 InitReg(MISCREG_PRRR_MAIR0_S
)
2464 InitReg(MISCREG_NMRR_MAIR1
)
2467 InitReg(MISCREG_NMRR_MAIR1_NS
)
2469 .privSecure(!aarch32EL3
)
2471 InitReg(MISCREG_NMRR_MAIR1_S
)
2474 InitReg(MISCREG_PMXEVTYPER_PMCCFILTR
)
2476 InitReg(MISCREG_SCTLR_RST
)
2478 InitReg(MISCREG_SEV_MAILBOX
)
2481 // AArch32 CP14 registers
2482 InitReg(MISCREG_DBGDIDR
)
2483 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2484 InitReg(MISCREG_DBGDSCRint
)
2485 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2486 InitReg(MISCREG_DBGDCCINT
)
2489 InitReg(MISCREG_DBGDTRTXint
)
2492 InitReg(MISCREG_DBGDTRRXint
)
2495 InitReg(MISCREG_DBGWFAR
)
2498 InitReg(MISCREG_DBGVCR
)
2501 InitReg(MISCREG_DBGDTRRXext
)
2504 InitReg(MISCREG_DBGDSCRext
)
2508 InitReg(MISCREG_DBGDTRTXext
)
2511 InitReg(MISCREG_DBGOSECCR
)
2514 InitReg(MISCREG_DBGBVR0
)
2517 InitReg(MISCREG_DBGBVR1
)
2520 InitReg(MISCREG_DBGBVR2
)
2523 InitReg(MISCREG_DBGBVR3
)
2526 InitReg(MISCREG_DBGBVR4
)
2529 InitReg(MISCREG_DBGBVR5
)
2532 InitReg(MISCREG_DBGBCR0
)
2535 InitReg(MISCREG_DBGBCR1
)
2538 InitReg(MISCREG_DBGBCR2
)
2541 InitReg(MISCREG_DBGBCR3
)
2544 InitReg(MISCREG_DBGBCR4
)
2547 InitReg(MISCREG_DBGBCR5
)
2550 InitReg(MISCREG_DBGWVR0
)
2553 InitReg(MISCREG_DBGWVR1
)
2556 InitReg(MISCREG_DBGWVR2
)
2559 InitReg(MISCREG_DBGWVR3
)
2562 InitReg(MISCREG_DBGWCR0
)
2565 InitReg(MISCREG_DBGWCR1
)
2568 InitReg(MISCREG_DBGWCR2
)
2571 InitReg(MISCREG_DBGWCR3
)
2574 InitReg(MISCREG_DBGDRAR
)
2576 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2577 InitReg(MISCREG_DBGBXVR4
)
2580 InitReg(MISCREG_DBGBXVR5
)
2583 InitReg(MISCREG_DBGOSLAR
)
2585 .allPrivileges().monSecureRead(0).monNonSecureRead(0);
2586 InitReg(MISCREG_DBGOSLSR
)
2588 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2589 InitReg(MISCREG_DBGOSDLR
)
2592 InitReg(MISCREG_DBGPRCR
)
2595 InitReg(MISCREG_DBGDSAR
)
2597 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2598 InitReg(MISCREG_DBGCLAIMSET
)
2601 InitReg(MISCREG_DBGCLAIMCLR
)
2604 InitReg(MISCREG_DBGAUTHSTATUS
)
2606 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2607 InitReg(MISCREG_DBGDEVID2
)
2609 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2610 InitReg(MISCREG_DBGDEVID1
)
2612 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2613 InitReg(MISCREG_DBGDEVID0
)
2615 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2616 InitReg(MISCREG_TEECR
)
2619 InitReg(MISCREG_JIDR
)
2621 InitReg(MISCREG_TEEHBR
)
2623 InitReg(MISCREG_JOSCR
)
2625 InitReg(MISCREG_JMCR
)
2628 // AArch32 CP15 registers
2629 InitReg(MISCREG_MIDR
)
2630 .allPrivileges().exceptUserMode().writes(0);
2631 InitReg(MISCREG_CTR
)
2632 .allPrivileges().exceptUserMode().writes(0);
2633 InitReg(MISCREG_TCMTR
)
2634 .allPrivileges().exceptUserMode().writes(0);
2635 InitReg(MISCREG_TLBTR
)
2636 .allPrivileges().exceptUserMode().writes(0);
2637 InitReg(MISCREG_MPIDR
)
2638 .allPrivileges().exceptUserMode().writes(0);
2639 InitReg(MISCREG_REVIDR
)
2642 .allPrivileges().exceptUserMode().writes(0);
2643 InitReg(MISCREG_ID_PFR0
)
2644 .allPrivileges().exceptUserMode().writes(0);
2645 InitReg(MISCREG_ID_PFR1
)
2646 .allPrivileges().exceptUserMode().writes(0);
2647 InitReg(MISCREG_ID_DFR0
)
2648 .allPrivileges().exceptUserMode().writes(0);
2649 InitReg(MISCREG_ID_AFR0
)
2650 .allPrivileges().exceptUserMode().writes(0);
2651 InitReg(MISCREG_ID_MMFR0
)
2652 .allPrivileges().exceptUserMode().writes(0);
2653 InitReg(MISCREG_ID_MMFR1
)
2654 .allPrivileges().exceptUserMode().writes(0);
2655 InitReg(MISCREG_ID_MMFR2
)
2656 .allPrivileges().exceptUserMode().writes(0);
2657 InitReg(MISCREG_ID_MMFR3
)
2658 .allPrivileges().exceptUserMode().writes(0);
2659 InitReg(MISCREG_ID_ISAR0
)
2660 .allPrivileges().exceptUserMode().writes(0);
2661 InitReg(MISCREG_ID_ISAR1
)
2662 .allPrivileges().exceptUserMode().writes(0);
2663 InitReg(MISCREG_ID_ISAR2
)
2664 .allPrivileges().exceptUserMode().writes(0);
2665 InitReg(MISCREG_ID_ISAR3
)
2666 .allPrivileges().exceptUserMode().writes(0);
2667 InitReg(MISCREG_ID_ISAR4
)
2668 .allPrivileges().exceptUserMode().writes(0);
2669 InitReg(MISCREG_ID_ISAR5
)
2670 .allPrivileges().exceptUserMode().writes(0);
2671 InitReg(MISCREG_CCSIDR
)
2672 .allPrivileges().exceptUserMode().writes(0);
2673 InitReg(MISCREG_CLIDR
)
2674 .allPrivileges().exceptUserMode().writes(0);
2675 InitReg(MISCREG_AIDR
)
2676 .allPrivileges().exceptUserMode().writes(0);
2677 InitReg(MISCREG_CSSELR
)
2679 InitReg(MISCREG_CSSELR_NS
)
2681 .privSecure(!aarch32EL3
)
2682 .nonSecure().exceptUserMode();
2683 InitReg(MISCREG_CSSELR_S
)
2685 .secure().exceptUserMode();
2686 InitReg(MISCREG_VPIDR
)
2687 .hyp().monNonSecure();
2688 InitReg(MISCREG_VMPIDR
)
2689 .hyp().monNonSecure();
2690 InitReg(MISCREG_SCTLR
)
2692 InitReg(MISCREG_SCTLR_NS
)
2694 .privSecure(!aarch32EL3
)
2695 .nonSecure().exceptUserMode();
2696 InitReg(MISCREG_SCTLR_S
)
2698 .secure().exceptUserMode();
2699 InitReg(MISCREG_ACTLR
)
2701 InitReg(MISCREG_ACTLR_NS
)
2703 .privSecure(!aarch32EL3
)
2704 .nonSecure().exceptUserMode();
2705 InitReg(MISCREG_ACTLR_S
)
2707 .secure().exceptUserMode();
2708 InitReg(MISCREG_CPACR
)
2709 .allPrivileges().exceptUserMode();
2710 InitReg(MISCREG_SCR
)
2711 .mon().secure().exceptUserMode()
2712 .res0(0xff40) // [31:16], [6]
2713 .res1(0x0030); // [5:4]
2714 InitReg(MISCREG_SDER
)
2716 InitReg(MISCREG_NSACR
)
2717 .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
2718 InitReg(MISCREG_HSCTLR
)
2719 .hyp().monNonSecure();
2720 InitReg(MISCREG_HACTLR
)
2721 .hyp().monNonSecure();
2722 InitReg(MISCREG_HCR
)
2723 .hyp().monNonSecure();
2724 InitReg(MISCREG_HDCR
)
2725 .hyp().monNonSecure();
2726 InitReg(MISCREG_HCPTR
)
2727 .hyp().monNonSecure();
2728 InitReg(MISCREG_HSTR
)
2729 .hyp().monNonSecure();
2730 InitReg(MISCREG_HACR
)
2733 .hyp().monNonSecure();
2734 InitReg(MISCREG_TTBR0
)
2736 InitReg(MISCREG_TTBR0_NS
)
2738 .privSecure(!aarch32EL3
)
2739 .nonSecure().exceptUserMode();
2740 InitReg(MISCREG_TTBR0_S
)
2742 .secure().exceptUserMode();
2743 InitReg(MISCREG_TTBR1
)
2745 InitReg(MISCREG_TTBR1_NS
)
2747 .privSecure(!aarch32EL3
)
2748 .nonSecure().exceptUserMode();
2749 InitReg(MISCREG_TTBR1_S
)
2751 .secure().exceptUserMode();
2752 InitReg(MISCREG_TTBCR
)
2754 InitReg(MISCREG_TTBCR_NS
)
2756 .privSecure(!aarch32EL3
)
2757 .nonSecure().exceptUserMode();
2758 InitReg(MISCREG_TTBCR_S
)
2760 .secure().exceptUserMode();
2761 InitReg(MISCREG_HTCR
)
2762 .hyp().monNonSecure();
2763 InitReg(MISCREG_VTCR
)
2764 .hyp().monNonSecure();
2765 InitReg(MISCREG_DACR
)
2767 InitReg(MISCREG_DACR_NS
)
2769 .privSecure(!aarch32EL3
)
2770 .nonSecure().exceptUserMode();
2771 InitReg(MISCREG_DACR_S
)
2773 .secure().exceptUserMode();
2774 InitReg(MISCREG_DFSR
)
2776 InitReg(MISCREG_DFSR_NS
)
2778 .privSecure(!aarch32EL3
)
2779 .nonSecure().exceptUserMode();
2780 InitReg(MISCREG_DFSR_S
)
2782 .secure().exceptUserMode();
2783 InitReg(MISCREG_IFSR
)
2785 InitReg(MISCREG_IFSR_NS
)
2787 .privSecure(!aarch32EL3
)
2788 .nonSecure().exceptUserMode();
2789 InitReg(MISCREG_IFSR_S
)
2791 .secure().exceptUserMode();
2792 InitReg(MISCREG_ADFSR
)
2796 InitReg(MISCREG_ADFSR_NS
)
2800 .privSecure(!aarch32EL3
)
2801 .nonSecure().exceptUserMode();
2802 InitReg(MISCREG_ADFSR_S
)
2806 .secure().exceptUserMode();
2807 InitReg(MISCREG_AIFSR
)
2811 InitReg(MISCREG_AIFSR_NS
)
2815 .privSecure(!aarch32EL3
)
2816 .nonSecure().exceptUserMode();
2817 InitReg(MISCREG_AIFSR_S
)
2821 .secure().exceptUserMode();
2822 InitReg(MISCREG_HADFSR
)
2823 .hyp().monNonSecure();
2824 InitReg(MISCREG_HAIFSR
)
2825 .hyp().monNonSecure();
2826 InitReg(MISCREG_HSR
)
2827 .hyp().monNonSecure();
2828 InitReg(MISCREG_DFAR
)
2830 InitReg(MISCREG_DFAR_NS
)
2832 .privSecure(!aarch32EL3
)
2833 .nonSecure().exceptUserMode();
2834 InitReg(MISCREG_DFAR_S
)
2836 .secure().exceptUserMode();
2837 InitReg(MISCREG_IFAR
)
2839 InitReg(MISCREG_IFAR_NS
)
2841 .privSecure(!aarch32EL3
)
2842 .nonSecure().exceptUserMode();
2843 InitReg(MISCREG_IFAR_S
)
2845 .secure().exceptUserMode();
2846 InitReg(MISCREG_HDFAR
)
2847 .hyp().monNonSecure();
2848 InitReg(MISCREG_HIFAR
)
2849 .hyp().monNonSecure();
2850 InitReg(MISCREG_HPFAR
)
2851 .hyp().monNonSecure();
2852 InitReg(MISCREG_ICIALLUIS
)
2855 .writes(1).exceptUserMode();
2856 InitReg(MISCREG_BPIALLIS
)
2859 .writes(1).exceptUserMode();
2860 InitReg(MISCREG_PAR
)
2862 InitReg(MISCREG_PAR_NS
)
2864 .privSecure(!aarch32EL3
)
2865 .nonSecure().exceptUserMode();
2866 InitReg(MISCREG_PAR_S
)
2868 .secure().exceptUserMode();
2869 InitReg(MISCREG_ICIALLU
)
2870 .writes(1).exceptUserMode();
2871 InitReg(MISCREG_ICIMVAU
)
2874 .writes(1).exceptUserMode();
2875 InitReg(MISCREG_CP15ISB
)
2877 InitReg(MISCREG_BPIALL
)
2880 .writes(1).exceptUserMode();
2881 InitReg(MISCREG_BPIMVA
)
2884 .writes(1).exceptUserMode();
2885 InitReg(MISCREG_DCIMVAC
)
2888 .writes(1).exceptUserMode();
2889 InitReg(MISCREG_DCISW
)
2892 .writes(1).exceptUserMode();
2893 InitReg(MISCREG_ATS1CPR
)
2894 .writes(1).exceptUserMode();
2895 InitReg(MISCREG_ATS1CPW
)
2896 .writes(1).exceptUserMode();
2897 InitReg(MISCREG_ATS1CUR
)
2898 .writes(1).exceptUserMode();
2899 InitReg(MISCREG_ATS1CUW
)
2900 .writes(1).exceptUserMode();
2901 InitReg(MISCREG_ATS12NSOPR
)
2902 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2903 InitReg(MISCREG_ATS12NSOPW
)
2904 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2905 InitReg(MISCREG_ATS12NSOUR
)
2906 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2907 InitReg(MISCREG_ATS12NSOUW
)
2908 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2909 InitReg(MISCREG_DCCMVAC
)
2910 .writes(1).exceptUserMode();
2911 InitReg(MISCREG_DCCSW
)
2914 .writes(1).exceptUserMode();
2915 InitReg(MISCREG_CP15DSB
)
2917 InitReg(MISCREG_CP15DMB
)
2919 InitReg(MISCREG_DCCMVAU
)
2922 .writes(1).exceptUserMode();
2923 InitReg(MISCREG_DCCIMVAC
)
2926 .writes(1).exceptUserMode();
2927 InitReg(MISCREG_DCCISW
)
2930 .writes(1).exceptUserMode();
2931 InitReg(MISCREG_ATS1HR
)
2932 .monNonSecureWrite().hypWrite();
2933 InitReg(MISCREG_ATS1HW
)
2934 .monNonSecureWrite().hypWrite();
2935 InitReg(MISCREG_TLBIALLIS
)
2936 .writes(1).exceptUserMode();
2937 InitReg(MISCREG_TLBIMVAIS
)
2938 .writes(1).exceptUserMode();
2939 InitReg(MISCREG_TLBIASIDIS
)
2940 .writes(1).exceptUserMode();
2941 InitReg(MISCREG_TLBIMVAAIS
)
2942 .writes(1).exceptUserMode();
2943 InitReg(MISCREG_TLBIMVALIS
)
2944 .writes(1).exceptUserMode();
2945 InitReg(MISCREG_TLBIMVAALIS
)
2946 .writes(1).exceptUserMode();
2947 InitReg(MISCREG_ITLBIALL
)
2948 .writes(1).exceptUserMode();
2949 InitReg(MISCREG_ITLBIMVA
)
2950 .writes(1).exceptUserMode();
2951 InitReg(MISCREG_ITLBIASID
)
2952 .writes(1).exceptUserMode();
2953 InitReg(MISCREG_DTLBIALL
)
2954 .writes(1).exceptUserMode();
2955 InitReg(MISCREG_DTLBIMVA
)
2956 .writes(1).exceptUserMode();
2957 InitReg(MISCREG_DTLBIASID
)
2958 .writes(1).exceptUserMode();
2959 InitReg(MISCREG_TLBIALL
)
2960 .writes(1).exceptUserMode();
2961 InitReg(MISCREG_TLBIMVA
)
2962 .writes(1).exceptUserMode();
2963 InitReg(MISCREG_TLBIASID
)
2964 .writes(1).exceptUserMode();
2965 InitReg(MISCREG_TLBIMVAA
)
2966 .writes(1).exceptUserMode();
2967 InitReg(MISCREG_TLBIMVAL
)
2968 .writes(1).exceptUserMode();
2969 InitReg(MISCREG_TLBIMVAAL
)
2970 .writes(1).exceptUserMode();
2971 InitReg(MISCREG_TLBIIPAS2IS
)
2972 .monNonSecureWrite().hypWrite();
2973 InitReg(MISCREG_TLBIIPAS2LIS
)
2974 .monNonSecureWrite().hypWrite();
2975 InitReg(MISCREG_TLBIALLHIS
)
2976 .monNonSecureWrite().hypWrite();
2977 InitReg(MISCREG_TLBIMVAHIS
)
2978 .monNonSecureWrite().hypWrite();
2979 InitReg(MISCREG_TLBIALLNSNHIS
)
2980 .monNonSecureWrite().hypWrite();
2981 InitReg(MISCREG_TLBIMVALHIS
)
2982 .monNonSecureWrite().hypWrite();
2983 InitReg(MISCREG_TLBIIPAS2
)
2984 .monNonSecureWrite().hypWrite();
2985 InitReg(MISCREG_TLBIIPAS2L
)
2986 .monNonSecureWrite().hypWrite();
2987 InitReg(MISCREG_TLBIALLH
)
2988 .monNonSecureWrite().hypWrite();
2989 InitReg(MISCREG_TLBIMVAH
)
2990 .monNonSecureWrite().hypWrite();
2991 InitReg(MISCREG_TLBIALLNSNH
)
2992 .monNonSecureWrite().hypWrite();
2993 InitReg(MISCREG_TLBIMVALH
)
2994 .monNonSecureWrite().hypWrite();
2995 InitReg(MISCREG_PMCR
)
2997 InitReg(MISCREG_PMCNTENSET
)
2999 InitReg(MISCREG_PMCNTENCLR
)
3001 InitReg(MISCREG_PMOVSR
)
3003 InitReg(MISCREG_PMSWINC
)
3005 InitReg(MISCREG_PMSELR
)
3007 InitReg(MISCREG_PMCEID0
)
3009 InitReg(MISCREG_PMCEID1
)
3011 InitReg(MISCREG_PMCCNTR
)
3013 InitReg(MISCREG_PMXEVTYPER
)
3015 InitReg(MISCREG_PMCCFILTR
)
3017 InitReg(MISCREG_PMXEVCNTR
)
3019 InitReg(MISCREG_PMUSERENR
)
3020 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
3021 InitReg(MISCREG_PMINTENSET
)
3022 .allPrivileges().exceptUserMode();
3023 InitReg(MISCREG_PMINTENCLR
)
3024 .allPrivileges().exceptUserMode();
3025 InitReg(MISCREG_PMOVSSET
)
3028 InitReg(MISCREG_L2CTLR
)
3029 .allPrivileges().exceptUserMode();
3030 InitReg(MISCREG_L2ECTLR
)
3032 .allPrivileges().exceptUserMode();
3033 InitReg(MISCREG_PRRR
)
3035 InitReg(MISCREG_PRRR_NS
)
3037 .privSecure(!aarch32EL3
)
3038 .nonSecure().exceptUserMode();
3039 InitReg(MISCREG_PRRR_S
)
3041 .secure().exceptUserMode();
3042 InitReg(MISCREG_MAIR0
)
3044 InitReg(MISCREG_MAIR0_NS
)
3046 .privSecure(!aarch32EL3
)
3047 .nonSecure().exceptUserMode();
3048 InitReg(MISCREG_MAIR0_S
)
3050 .secure().exceptUserMode();
3051 InitReg(MISCREG_NMRR
)
3053 InitReg(MISCREG_NMRR_NS
)
3055 .privSecure(!aarch32EL3
)
3056 .nonSecure().exceptUserMode();
3057 InitReg(MISCREG_NMRR_S
)
3059 .secure().exceptUserMode();
3060 InitReg(MISCREG_MAIR1
)
3062 InitReg(MISCREG_MAIR1_NS
)
3064 .privSecure(!aarch32EL3
)
3065 .nonSecure().exceptUserMode();
3066 InitReg(MISCREG_MAIR1_S
)
3068 .secure().exceptUserMode();
3069 InitReg(MISCREG_AMAIR0
)
3071 InitReg(MISCREG_AMAIR0_NS
)
3073 .privSecure(!aarch32EL3
)
3074 .nonSecure().exceptUserMode();
3075 InitReg(MISCREG_AMAIR0_S
)
3077 .secure().exceptUserMode();
3078 InitReg(MISCREG_AMAIR1
)
3080 InitReg(MISCREG_AMAIR1_NS
)
3082 .privSecure(!aarch32EL3
)
3083 .nonSecure().exceptUserMode();
3084 InitReg(MISCREG_AMAIR1_S
)
3086 .secure().exceptUserMode();
3087 InitReg(MISCREG_HMAIR0
)
3088 .hyp().monNonSecure();
3089 InitReg(MISCREG_HMAIR1
)
3090 .hyp().monNonSecure();
3091 InitReg(MISCREG_HAMAIR0
)
3094 .hyp().monNonSecure();
3095 InitReg(MISCREG_HAMAIR1
)
3098 .hyp().monNonSecure();
3099 InitReg(MISCREG_VBAR
)
3101 InitReg(MISCREG_VBAR_NS
)
3103 .privSecure(!aarch32EL3
)
3104 .nonSecure().exceptUserMode();
3105 InitReg(MISCREG_VBAR_S
)
3107 .secure().exceptUserMode();
3108 InitReg(MISCREG_MVBAR
)
3109 .mon().secure().exceptUserMode();
3110 InitReg(MISCREG_RMR
)
3112 .mon().secure().exceptUserMode();
3113 InitReg(MISCREG_ISR
)
3114 .allPrivileges().exceptUserMode().writes(0);
3115 InitReg(MISCREG_HVBAR
)
3116 .hyp().monNonSecure();
3117 InitReg(MISCREG_FCSEIDR
)
3120 .allPrivileges().exceptUserMode();
3121 InitReg(MISCREG_CONTEXTIDR
)
3123 InitReg(MISCREG_CONTEXTIDR_NS
)
3125 .privSecure(!aarch32EL3
)
3126 .nonSecure().exceptUserMode();
3127 InitReg(MISCREG_CONTEXTIDR_S
)
3129 .secure().exceptUserMode();
3130 InitReg(MISCREG_TPIDRURW
)
3132 InitReg(MISCREG_TPIDRURW_NS
)
3135 .privSecure(!aarch32EL3
)
3137 InitReg(MISCREG_TPIDRURW_S
)
3140 InitReg(MISCREG_TPIDRURO
)
3142 InitReg(MISCREG_TPIDRURO_NS
)
3145 .userNonSecureWrite(0).userSecureRead(1)
3146 .privSecure(!aarch32EL3
)
3148 InitReg(MISCREG_TPIDRURO_S
)
3150 .secure().userSecureWrite(0);
3151 InitReg(MISCREG_TPIDRPRW
)
3153 InitReg(MISCREG_TPIDRPRW_NS
)
3155 .nonSecure().exceptUserMode()
3156 .privSecure(!aarch32EL3
);
3157 InitReg(MISCREG_TPIDRPRW_S
)
3159 .secure().exceptUserMode();
3160 InitReg(MISCREG_HTPIDR
)
3161 .hyp().monNonSecure();
3162 InitReg(MISCREG_CNTFRQ
)
3165 InitReg(MISCREG_CNTKCTL
)
3166 .allPrivileges().exceptUserMode();
3167 InitReg(MISCREG_CNTP_TVAL
)
3169 InitReg(MISCREG_CNTP_TVAL_NS
)
3172 .privSecure(!aarch32EL3
)
3174 InitReg(MISCREG_CNTP_TVAL_S
)
3178 InitReg(MISCREG_CNTP_CTL
)
3180 InitReg(MISCREG_CNTP_CTL_NS
)
3183 .privSecure(!aarch32EL3
)
3185 InitReg(MISCREG_CNTP_CTL_S
)
3189 InitReg(MISCREG_CNTV_TVAL
)
3191 InitReg(MISCREG_CNTV_CTL
)
3193 InitReg(MISCREG_CNTHCTL
)
3195 .hypWrite().monNonSecureRead();
3196 InitReg(MISCREG_CNTHP_TVAL
)
3198 .hypWrite().monNonSecureRead();
3199 InitReg(MISCREG_CNTHP_CTL
)
3201 .hypWrite().monNonSecureRead();
3202 InitReg(MISCREG_IL1DATA0
)
3204 .allPrivileges().exceptUserMode();
3205 InitReg(MISCREG_IL1DATA1
)
3207 .allPrivileges().exceptUserMode();
3208 InitReg(MISCREG_IL1DATA2
)
3210 .allPrivileges().exceptUserMode();
3211 InitReg(MISCREG_IL1DATA3
)
3213 .allPrivileges().exceptUserMode();
3214 InitReg(MISCREG_DL1DATA0
)
3216 .allPrivileges().exceptUserMode();
3217 InitReg(MISCREG_DL1DATA1
)
3219 .allPrivileges().exceptUserMode();
3220 InitReg(MISCREG_DL1DATA2
)
3222 .allPrivileges().exceptUserMode();
3223 InitReg(MISCREG_DL1DATA3
)
3225 .allPrivileges().exceptUserMode();
3226 InitReg(MISCREG_DL1DATA4
)
3228 .allPrivileges().exceptUserMode();
3229 InitReg(MISCREG_RAMINDEX
)
3231 .writes(1).exceptUserMode();
3232 InitReg(MISCREG_L2ACTLR
)
3234 .allPrivileges().exceptUserMode();
3235 InitReg(MISCREG_CBAR
)
3237 .allPrivileges().exceptUserMode().writes(0);
3238 InitReg(MISCREG_HTTBR
)
3239 .hyp().monNonSecure();
3240 InitReg(MISCREG_VTTBR
)
3241 .hyp().monNonSecure();
3242 InitReg(MISCREG_CNTPCT
)
3244 InitReg(MISCREG_CNTVCT
)
3247 InitReg(MISCREG_CNTP_CVAL
)
3249 InitReg(MISCREG_CNTP_CVAL_NS
)
3252 .privSecure(!aarch32EL3
)
3254 InitReg(MISCREG_CNTP_CVAL_S
)
3258 InitReg(MISCREG_CNTV_CVAL
)
3260 InitReg(MISCREG_CNTVOFF
)
3261 .hyp().monNonSecure();
3262 InitReg(MISCREG_CNTHP_CVAL
)
3264 .hypWrite().monNonSecureRead();
3265 InitReg(MISCREG_CPUMERRSR
)
3267 .allPrivileges().exceptUserMode();
3268 InitReg(MISCREG_L2MERRSR
)
3271 .allPrivileges().exceptUserMode();
3273 // AArch64 registers (Op0=2);
3274 InitReg(MISCREG_MDCCINT_EL1
)
3276 InitReg(MISCREG_OSDTRRX_EL1
)
3278 .mapsTo(MISCREG_DBGDTRRXext
);
3279 InitReg(MISCREG_MDSCR_EL1
)
3281 .mapsTo(MISCREG_DBGDSCRext
);
3282 InitReg(MISCREG_OSDTRTX_EL1
)
3284 .mapsTo(MISCREG_DBGDTRTXext
);
3285 InitReg(MISCREG_OSECCR_EL1
)
3287 .mapsTo(MISCREG_DBGOSECCR
);
3288 InitReg(MISCREG_DBGBVR0_EL1
)
3290 .mapsTo(MISCREG_DBGBVR0
/*, MISCREG_DBGBXVR0 */);
3291 InitReg(MISCREG_DBGBVR1_EL1
)
3293 .mapsTo(MISCREG_DBGBVR1
/*, MISCREG_DBGBXVR1 */);
3294 InitReg(MISCREG_DBGBVR2_EL1
)
3296 .mapsTo(MISCREG_DBGBVR2
/*, MISCREG_DBGBXVR2 */);
3297 InitReg(MISCREG_DBGBVR3_EL1
)
3299 .mapsTo(MISCREG_DBGBVR3
/*, MISCREG_DBGBXVR3 */);
3300 InitReg(MISCREG_DBGBVR4_EL1
)
3302 .mapsTo(MISCREG_DBGBVR4
/*, MISCREG_DBGBXVR4 */);
3303 InitReg(MISCREG_DBGBVR5_EL1
)
3305 .mapsTo(MISCREG_DBGBVR5
/*, MISCREG_DBGBXVR5 */);
3306 InitReg(MISCREG_DBGBCR0_EL1
)
3308 .mapsTo(MISCREG_DBGBCR0
);
3309 InitReg(MISCREG_DBGBCR1_EL1
)
3311 .mapsTo(MISCREG_DBGBCR1
);
3312 InitReg(MISCREG_DBGBCR2_EL1
)
3314 .mapsTo(MISCREG_DBGBCR2
);
3315 InitReg(MISCREG_DBGBCR3_EL1
)
3317 .mapsTo(MISCREG_DBGBCR3
);
3318 InitReg(MISCREG_DBGBCR4_EL1
)
3320 .mapsTo(MISCREG_DBGBCR4
);
3321 InitReg(MISCREG_DBGBCR5_EL1
)
3323 .mapsTo(MISCREG_DBGBCR5
);
3324 InitReg(MISCREG_DBGWVR0_EL1
)
3326 .mapsTo(MISCREG_DBGWVR0
);
3327 InitReg(MISCREG_DBGWVR1_EL1
)
3329 .mapsTo(MISCREG_DBGWVR1
);
3330 InitReg(MISCREG_DBGWVR2_EL1
)
3332 .mapsTo(MISCREG_DBGWVR2
);
3333 InitReg(MISCREG_DBGWVR3_EL1
)
3335 .mapsTo(MISCREG_DBGWVR3
);
3336 InitReg(MISCREG_DBGWCR0_EL1
)
3338 .mapsTo(MISCREG_DBGWCR0
);
3339 InitReg(MISCREG_DBGWCR1_EL1
)
3341 .mapsTo(MISCREG_DBGWCR1
);
3342 InitReg(MISCREG_DBGWCR2_EL1
)
3344 .mapsTo(MISCREG_DBGWCR2
);
3345 InitReg(MISCREG_DBGWCR3_EL1
)
3347 .mapsTo(MISCREG_DBGWCR3
);
3348 InitReg(MISCREG_MDCCSR_EL0
)
3349 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3350 .mapsTo(MISCREG_DBGDSCRint
);
3351 InitReg(MISCREG_MDDTR_EL0
)
3353 InitReg(MISCREG_MDDTRTX_EL0
)
3355 InitReg(MISCREG_MDDTRRX_EL0
)
3357 InitReg(MISCREG_DBGVCR32_EL2
)
3359 .mapsTo(MISCREG_DBGVCR
);
3360 InitReg(MISCREG_MDRAR_EL1
)
3361 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3362 .mapsTo(MISCREG_DBGDRAR
);
3363 InitReg(MISCREG_OSLAR_EL1
)
3364 .allPrivileges().monSecureRead(0).monNonSecureRead(0)
3365 .mapsTo(MISCREG_DBGOSLAR
);
3366 InitReg(MISCREG_OSLSR_EL1
)
3367 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3368 .mapsTo(MISCREG_DBGOSLSR
);
3369 InitReg(MISCREG_OSDLR_EL1
)
3371 .mapsTo(MISCREG_DBGOSDLR
);
3372 InitReg(MISCREG_DBGPRCR_EL1
)
3374 .mapsTo(MISCREG_DBGPRCR
);
3375 InitReg(MISCREG_DBGCLAIMSET_EL1
)
3377 .mapsTo(MISCREG_DBGCLAIMSET
);
3378 InitReg(MISCREG_DBGCLAIMCLR_EL1
)
3380 .mapsTo(MISCREG_DBGCLAIMCLR
);
3381 InitReg(MISCREG_DBGAUTHSTATUS_EL1
)
3382 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3383 .mapsTo(MISCREG_DBGAUTHSTATUS
);
3384 InitReg(MISCREG_TEECR32_EL1
);
3385 InitReg(MISCREG_TEEHBR32_EL1
);
3387 // AArch64 registers (Op0=1,3);
3388 InitReg(MISCREG_MIDR_EL1
)
3389 .allPrivileges().exceptUserMode().writes(0);
3390 InitReg(MISCREG_MPIDR_EL1
)
3391 .allPrivileges().exceptUserMode().writes(0);
3392 InitReg(MISCREG_REVIDR_EL1
)
3393 .allPrivileges().exceptUserMode().writes(0);
3394 InitReg(MISCREG_ID_PFR0_EL1
)
3395 .allPrivileges().exceptUserMode().writes(0)
3396 .mapsTo(MISCREG_ID_PFR0
);
3397 InitReg(MISCREG_ID_PFR1_EL1
)
3398 .allPrivileges().exceptUserMode().writes(0)
3399 .mapsTo(MISCREG_ID_PFR1
);
3400 InitReg(MISCREG_ID_DFR0_EL1
)
3401 .allPrivileges().exceptUserMode().writes(0)
3402 .mapsTo(MISCREG_ID_DFR0
);
3403 InitReg(MISCREG_ID_AFR0_EL1
)
3404 .allPrivileges().exceptUserMode().writes(0)
3405 .mapsTo(MISCREG_ID_AFR0
);
3406 InitReg(MISCREG_ID_MMFR0_EL1
)
3407 .allPrivileges().exceptUserMode().writes(0)
3408 .mapsTo(MISCREG_ID_MMFR0
);
3409 InitReg(MISCREG_ID_MMFR1_EL1
)
3410 .allPrivileges().exceptUserMode().writes(0)
3411 .mapsTo(MISCREG_ID_MMFR1
);
3412 InitReg(MISCREG_ID_MMFR2_EL1
)
3413 .allPrivileges().exceptUserMode().writes(0)
3414 .mapsTo(MISCREG_ID_MMFR2
);
3415 InitReg(MISCREG_ID_MMFR3_EL1
)
3416 .allPrivileges().exceptUserMode().writes(0)
3417 .mapsTo(MISCREG_ID_MMFR3
);
3418 InitReg(MISCREG_ID_ISAR0_EL1
)
3419 .allPrivileges().exceptUserMode().writes(0)
3420 .mapsTo(MISCREG_ID_ISAR0
);
3421 InitReg(MISCREG_ID_ISAR1_EL1
)
3422 .allPrivileges().exceptUserMode().writes(0)
3423 .mapsTo(MISCREG_ID_ISAR1
);
3424 InitReg(MISCREG_ID_ISAR2_EL1
)
3425 .allPrivileges().exceptUserMode().writes(0)
3426 .mapsTo(MISCREG_ID_ISAR2
);
3427 InitReg(MISCREG_ID_ISAR3_EL1
)
3428 .allPrivileges().exceptUserMode().writes(0)
3429 .mapsTo(MISCREG_ID_ISAR3
);
3430 InitReg(MISCREG_ID_ISAR4_EL1
)
3431 .allPrivileges().exceptUserMode().writes(0)
3432 .mapsTo(MISCREG_ID_ISAR4
);
3433 InitReg(MISCREG_ID_ISAR5_EL1
)
3434 .allPrivileges().exceptUserMode().writes(0)
3435 .mapsTo(MISCREG_ID_ISAR5
);
3436 InitReg(MISCREG_MVFR0_EL1
)
3437 .allPrivileges().exceptUserMode().writes(0);
3438 InitReg(MISCREG_MVFR1_EL1
)
3439 .allPrivileges().exceptUserMode().writes(0);
3440 InitReg(MISCREG_MVFR2_EL1
)
3441 .allPrivileges().exceptUserMode().writes(0);
3442 InitReg(MISCREG_ID_AA64PFR0_EL1
)
3443 .allPrivileges().exceptUserMode().writes(0);
3444 InitReg(MISCREG_ID_AA64PFR1_EL1
)
3445 .allPrivileges().exceptUserMode().writes(0);
3446 InitReg(MISCREG_ID_AA64DFR0_EL1
)
3447 .allPrivileges().exceptUserMode().writes(0);
3448 InitReg(MISCREG_ID_AA64DFR1_EL1
)
3449 .allPrivileges().exceptUserMode().writes(0);
3450 InitReg(MISCREG_ID_AA64AFR0_EL1
)
3451 .allPrivileges().exceptUserMode().writes(0);
3452 InitReg(MISCREG_ID_AA64AFR1_EL1
)
3453 .allPrivileges().exceptUserMode().writes(0);
3454 InitReg(MISCREG_ID_AA64ISAR0_EL1
)
3455 .allPrivileges().exceptUserMode().writes(0);
3456 InitReg(MISCREG_ID_AA64ISAR1_EL1
)
3457 .allPrivileges().exceptUserMode().writes(0);
3458 InitReg(MISCREG_ID_AA64MMFR0_EL1
)
3459 .allPrivileges().exceptUserMode().writes(0);
3460 InitReg(MISCREG_ID_AA64MMFR1_EL1
)
3461 .allPrivileges().exceptUserMode().writes(0);
3462 InitReg(MISCREG_CCSIDR_EL1
)
3463 .allPrivileges().exceptUserMode().writes(0);
3464 InitReg(MISCREG_CLIDR_EL1
)
3465 .allPrivileges().exceptUserMode().writes(0);
3466 InitReg(MISCREG_AIDR_EL1
)
3467 .allPrivileges().exceptUserMode().writes(0);
3468 InitReg(MISCREG_CSSELR_EL1
)
3469 .allPrivileges().exceptUserMode()
3470 .mapsTo(MISCREG_CSSELR_NS
);
3471 InitReg(MISCREG_CTR_EL0
)
3473 InitReg(MISCREG_DCZID_EL0
)
3475 InitReg(MISCREG_VPIDR_EL2
)
3477 .mapsTo(MISCREG_VPIDR
);
3478 InitReg(MISCREG_VMPIDR_EL2
)
3480 .mapsTo(MISCREG_VMPIDR
);
3481 InitReg(MISCREG_SCTLR_EL1
)
3482 .allPrivileges().exceptUserMode()
3483 .mapsTo(MISCREG_SCTLR_NS
);
3484 InitReg(MISCREG_ACTLR_EL1
)
3485 .allPrivileges().exceptUserMode()
3486 .mapsTo(MISCREG_ACTLR_NS
);
3487 InitReg(MISCREG_CPACR_EL1
)
3488 .allPrivileges().exceptUserMode()
3489 .mapsTo(MISCREG_CPACR
);
3490 InitReg(MISCREG_SCTLR_EL2
)
3492 .mapsTo(MISCREG_HSCTLR
);
3493 InitReg(MISCREG_ACTLR_EL2
)
3495 .mapsTo(MISCREG_HACTLR
);
3496 InitReg(MISCREG_HCR_EL2
)
3498 .mapsTo(MISCREG_HCR
/*, MISCREG_HCR2*/);
3499 InitReg(MISCREG_MDCR_EL2
)
3501 .mapsTo(MISCREG_HDCR
);
3502 InitReg(MISCREG_CPTR_EL2
)
3504 .mapsTo(MISCREG_HCPTR
);
3505 InitReg(MISCREG_HSTR_EL2
)
3507 .mapsTo(MISCREG_HSTR
);
3508 InitReg(MISCREG_HACR_EL2
)
3510 .mapsTo(MISCREG_HACR
);
3511 InitReg(MISCREG_SCTLR_EL3
)
3513 InitReg(MISCREG_ACTLR_EL3
)
3515 InitReg(MISCREG_SCR_EL3
)
3517 .mapsTo(MISCREG_SCR
); // NAM D7-2005
3518 InitReg(MISCREG_SDER32_EL3
)
3520 .mapsTo(MISCREG_SDER
);
3521 InitReg(MISCREG_CPTR_EL3
)
3523 InitReg(MISCREG_MDCR_EL3
)
3525 InitReg(MISCREG_TTBR0_EL1
)
3526 .allPrivileges().exceptUserMode()
3527 .mapsTo(MISCREG_TTBR0_NS
);
3528 InitReg(MISCREG_TTBR1_EL1
)
3529 .allPrivileges().exceptUserMode()
3530 .mapsTo(MISCREG_TTBR1_NS
);
3531 InitReg(MISCREG_TCR_EL1
)
3532 .allPrivileges().exceptUserMode()
3533 .mapsTo(MISCREG_TTBCR_NS
);
3534 InitReg(MISCREG_TTBR0_EL2
)
3536 .mapsTo(MISCREG_HTTBR
);
3537 InitReg(MISCREG_TTBR1_EL2
)
3539 InitReg(MISCREG_TCR_EL2
)
3541 .mapsTo(MISCREG_HTCR
);
3542 InitReg(MISCREG_VTTBR_EL2
)
3544 .mapsTo(MISCREG_VTTBR
);
3545 InitReg(MISCREG_VTCR_EL2
)
3547 .mapsTo(MISCREG_VTCR
);
3548 InitReg(MISCREG_TTBR0_EL3
)
3550 InitReg(MISCREG_TCR_EL3
)
3552 InitReg(MISCREG_DACR32_EL2
)
3554 .mapsTo(MISCREG_DACR_NS
);
3555 InitReg(MISCREG_SPSR_EL1
)
3556 .allPrivileges().exceptUserMode()
3557 .mapsTo(MISCREG_SPSR_SVC
); // NAM C5.2.17 SPSR_EL1
3558 InitReg(MISCREG_ELR_EL1
)
3559 .allPrivileges().exceptUserMode();
3560 InitReg(MISCREG_SP_EL0
)
3561 .allPrivileges().exceptUserMode();
3562 InitReg(MISCREG_SPSEL
)
3563 .allPrivileges().exceptUserMode();
3564 InitReg(MISCREG_CURRENTEL
)
3565 .allPrivileges().exceptUserMode().writes(0);
3566 InitReg(MISCREG_NZCV
)
3568 InitReg(MISCREG_DAIF
)
3570 InitReg(MISCREG_FPCR
)
3572 InitReg(MISCREG_FPSR
)
3574 InitReg(MISCREG_DSPSR_EL0
)
3576 InitReg(MISCREG_DLR_EL0
)
3578 InitReg(MISCREG_SPSR_EL2
)
3580 .mapsTo(MISCREG_SPSR_HYP
); // NAM C5.2.18 SPSR_EL2
3581 InitReg(MISCREG_ELR_EL2
)
3583 InitReg(MISCREG_SP_EL1
)
3585 InitReg(MISCREG_SPSR_IRQ_AA64
)
3587 InitReg(MISCREG_SPSR_ABT_AA64
)
3589 InitReg(MISCREG_SPSR_UND_AA64
)
3591 InitReg(MISCREG_SPSR_FIQ_AA64
)
3593 InitReg(MISCREG_SPSR_EL3
)
3595 .mapsTo(MISCREG_SPSR_MON
); // NAM C5.2.19 SPSR_EL3
3596 InitReg(MISCREG_ELR_EL3
)
3598 InitReg(MISCREG_SP_EL2
)
3600 InitReg(MISCREG_AFSR0_EL1
)
3601 .allPrivileges().exceptUserMode()
3602 .mapsTo(MISCREG_ADFSR_NS
);
3603 InitReg(MISCREG_AFSR1_EL1
)
3604 .allPrivileges().exceptUserMode()
3605 .mapsTo(MISCREG_AIFSR_NS
);
3606 InitReg(MISCREG_ESR_EL1
)
3607 .allPrivileges().exceptUserMode();
3608 InitReg(MISCREG_IFSR32_EL2
)
3610 .mapsTo(MISCREG_IFSR_NS
);
3611 InitReg(MISCREG_AFSR0_EL2
)
3613 .mapsTo(MISCREG_HADFSR
);
3614 InitReg(MISCREG_AFSR1_EL2
)
3616 .mapsTo(MISCREG_HAIFSR
);
3617 InitReg(MISCREG_ESR_EL2
)
3619 .mapsTo(MISCREG_HSR
);
3620 InitReg(MISCREG_FPEXC32_EL2
)
3621 .hyp().mon().mapsTo(MISCREG_FPEXC
);
3622 InitReg(MISCREG_AFSR0_EL3
)
3624 InitReg(MISCREG_AFSR1_EL3
)
3626 InitReg(MISCREG_ESR_EL3
)
3628 InitReg(MISCREG_FAR_EL1
)
3629 .allPrivileges().exceptUserMode()
3630 .mapsTo(MISCREG_DFAR_NS
, MISCREG_IFAR_NS
);
3631 InitReg(MISCREG_FAR_EL2
)
3633 .mapsTo(MISCREG_HDFAR
, MISCREG_HIFAR
);
3634 InitReg(MISCREG_HPFAR_EL2
)
3636 .mapsTo(MISCREG_HPFAR
);
3637 InitReg(MISCREG_FAR_EL3
)
3639 InitReg(MISCREG_IC_IALLUIS
)
3641 .writes(1).exceptUserMode();
3642 InitReg(MISCREG_PAR_EL1
)
3643 .allPrivileges().exceptUserMode()
3644 .mapsTo(MISCREG_PAR_NS
);
3645 InitReg(MISCREG_IC_IALLU
)
3647 .writes(1).exceptUserMode();
3648 InitReg(MISCREG_DC_IVAC_Xt
)
3650 .writes(1).exceptUserMode();
3651 InitReg(MISCREG_DC_ISW_Xt
)
3653 .writes(1).exceptUserMode();
3654 InitReg(MISCREG_AT_S1E1R_Xt
)
3655 .writes(1).exceptUserMode();
3656 InitReg(MISCREG_AT_S1E1W_Xt
)
3657 .writes(1).exceptUserMode();
3658 InitReg(MISCREG_AT_S1E0R_Xt
)
3659 .writes(1).exceptUserMode();
3660 InitReg(MISCREG_AT_S1E0W_Xt
)
3661 .writes(1).exceptUserMode();
3662 InitReg(MISCREG_DC_CSW_Xt
)
3664 .writes(1).exceptUserMode();
3665 InitReg(MISCREG_DC_CISW_Xt
)
3667 .writes(1).exceptUserMode();
3668 InitReg(MISCREG_DC_ZVA_Xt
)
3670 .writes(1).userSecureWrite(0);
3671 InitReg(MISCREG_IC_IVAU_Xt
)
3673 InitReg(MISCREG_DC_CVAC_Xt
)
3676 InitReg(MISCREG_DC_CVAU_Xt
)
3679 InitReg(MISCREG_DC_CIVAC_Xt
)
3682 InitReg(MISCREG_AT_S1E2R_Xt
)
3683 .monNonSecureWrite().hypWrite();
3684 InitReg(MISCREG_AT_S1E2W_Xt
)
3685 .monNonSecureWrite().hypWrite();
3686 InitReg(MISCREG_AT_S12E1R_Xt
)
3687 .hypWrite().monSecureWrite().monNonSecureWrite();
3688 InitReg(MISCREG_AT_S12E1W_Xt
)
3689 .hypWrite().monSecureWrite().monNonSecureWrite();
3690 InitReg(MISCREG_AT_S12E0R_Xt
)
3691 .hypWrite().monSecureWrite().monNonSecureWrite();
3692 InitReg(MISCREG_AT_S12E0W_Xt
)
3693 .hypWrite().monSecureWrite().monNonSecureWrite();
3694 InitReg(MISCREG_AT_S1E3R_Xt
)
3695 .monSecureWrite().monNonSecureWrite();
3696 InitReg(MISCREG_AT_S1E3W_Xt
)
3697 .monSecureWrite().monNonSecureWrite();
3698 InitReg(MISCREG_TLBI_VMALLE1IS
)
3699 .writes(1).exceptUserMode();
3700 InitReg(MISCREG_TLBI_VAE1IS_Xt
)
3701 .writes(1).exceptUserMode();
3702 InitReg(MISCREG_TLBI_ASIDE1IS_Xt
)
3703 .writes(1).exceptUserMode();
3704 InitReg(MISCREG_TLBI_VAAE1IS_Xt
)
3705 .writes(1).exceptUserMode();
3706 InitReg(MISCREG_TLBI_VALE1IS_Xt
)
3707 .writes(1).exceptUserMode();
3708 InitReg(MISCREG_TLBI_VAALE1IS_Xt
)
3709 .writes(1).exceptUserMode();
3710 InitReg(MISCREG_TLBI_VMALLE1
)
3711 .writes(1).exceptUserMode();
3712 InitReg(MISCREG_TLBI_VAE1_Xt
)
3713 .writes(1).exceptUserMode();
3714 InitReg(MISCREG_TLBI_ASIDE1_Xt
)
3715 .writes(1).exceptUserMode();
3716 InitReg(MISCREG_TLBI_VAAE1_Xt
)
3717 .writes(1).exceptUserMode();
3718 InitReg(MISCREG_TLBI_VALE1_Xt
)
3719 .writes(1).exceptUserMode();
3720 InitReg(MISCREG_TLBI_VAALE1_Xt
)
3721 .writes(1).exceptUserMode();
3722 InitReg(MISCREG_TLBI_IPAS2E1IS_Xt
)
3723 .hypWrite().monSecureWrite().monNonSecureWrite();
3724 InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt
)
3725 .hypWrite().monSecureWrite().monNonSecureWrite();
3726 InitReg(MISCREG_TLBI_ALLE2IS
)
3727 .monNonSecureWrite().hypWrite();
3728 InitReg(MISCREG_TLBI_VAE2IS_Xt
)
3729 .monNonSecureWrite().hypWrite();
3730 InitReg(MISCREG_TLBI_ALLE1IS
)
3731 .hypWrite().monSecureWrite().monNonSecureWrite();
3732 InitReg(MISCREG_TLBI_VALE2IS_Xt
)
3733 .monNonSecureWrite().hypWrite();
3734 InitReg(MISCREG_TLBI_VMALLS12E1IS
)
3735 .hypWrite().monSecureWrite().monNonSecureWrite();
3736 InitReg(MISCREG_TLBI_IPAS2E1_Xt
)
3737 .hypWrite().monSecureWrite().monNonSecureWrite();
3738 InitReg(MISCREG_TLBI_IPAS2LE1_Xt
)
3739 .hypWrite().monSecureWrite().monNonSecureWrite();
3740 InitReg(MISCREG_TLBI_ALLE2
)
3741 .monNonSecureWrite().hypWrite();
3742 InitReg(MISCREG_TLBI_VAE2_Xt
)
3743 .monNonSecureWrite().hypWrite();
3744 InitReg(MISCREG_TLBI_ALLE1
)
3745 .hypWrite().monSecureWrite().monNonSecureWrite();
3746 InitReg(MISCREG_TLBI_VALE2_Xt
)
3747 .monNonSecureWrite().hypWrite();
3748 InitReg(MISCREG_TLBI_VMALLS12E1
)
3749 .hypWrite().monSecureWrite().monNonSecureWrite();
3750 InitReg(MISCREG_TLBI_ALLE3IS
)
3751 .monSecureWrite().monNonSecureWrite();
3752 InitReg(MISCREG_TLBI_VAE3IS_Xt
)
3753 .monSecureWrite().monNonSecureWrite();
3754 InitReg(MISCREG_TLBI_VALE3IS_Xt
)
3755 .monSecureWrite().monNonSecureWrite();
3756 InitReg(MISCREG_TLBI_ALLE3
)
3757 .monSecureWrite().monNonSecureWrite();
3758 InitReg(MISCREG_TLBI_VAE3_Xt
)
3759 .monSecureWrite().monNonSecureWrite();
3760 InitReg(MISCREG_TLBI_VALE3_Xt
)
3761 .monSecureWrite().monNonSecureWrite();
3762 InitReg(MISCREG_PMINTENSET_EL1
)
3763 .allPrivileges().exceptUserMode()
3764 .mapsTo(MISCREG_PMINTENSET
);
3765 InitReg(MISCREG_PMINTENCLR_EL1
)
3766 .allPrivileges().exceptUserMode()
3767 .mapsTo(MISCREG_PMINTENCLR
);
3768 InitReg(MISCREG_PMCR_EL0
)
3770 .mapsTo(MISCREG_PMCR
);
3771 InitReg(MISCREG_PMCNTENSET_EL0
)
3773 .mapsTo(MISCREG_PMCNTENSET
);
3774 InitReg(MISCREG_PMCNTENCLR_EL0
)
3776 .mapsTo(MISCREG_PMCNTENCLR
);
3777 InitReg(MISCREG_PMOVSCLR_EL0
)
3779 // .mapsTo(MISCREG_PMOVSCLR);
3780 InitReg(MISCREG_PMSWINC_EL0
)
3782 .mapsTo(MISCREG_PMSWINC
);
3783 InitReg(MISCREG_PMSELR_EL0
)
3785 .mapsTo(MISCREG_PMSELR
);
3786 InitReg(MISCREG_PMCEID0_EL0
)
3788 .mapsTo(MISCREG_PMCEID0
);
3789 InitReg(MISCREG_PMCEID1_EL0
)
3791 .mapsTo(MISCREG_PMCEID1
);
3792 InitReg(MISCREG_PMCCNTR_EL0
)
3794 .mapsTo(MISCREG_PMCCNTR
);
3795 InitReg(MISCREG_PMXEVTYPER_EL0
)
3797 .mapsTo(MISCREG_PMXEVTYPER
);
3798 InitReg(MISCREG_PMCCFILTR_EL0
)
3800 InitReg(MISCREG_PMXEVCNTR_EL0
)
3802 .mapsTo(MISCREG_PMXEVCNTR
);
3803 InitReg(MISCREG_PMUSERENR_EL0
)
3804 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
3805 .mapsTo(MISCREG_PMUSERENR
);
3806 InitReg(MISCREG_PMOVSSET_EL0
)
3808 .mapsTo(MISCREG_PMOVSSET
);
3809 InitReg(MISCREG_MAIR_EL1
)
3810 .allPrivileges().exceptUserMode()
3811 .mapsTo(MISCREG_PRRR_NS
, MISCREG_NMRR_NS
);
3812 InitReg(MISCREG_AMAIR_EL1
)
3813 .allPrivileges().exceptUserMode()
3814 .mapsTo(MISCREG_AMAIR0_NS
, MISCREG_AMAIR1_NS
);
3815 InitReg(MISCREG_MAIR_EL2
)
3817 .mapsTo(MISCREG_HMAIR0
, MISCREG_HMAIR1
);
3818 InitReg(MISCREG_AMAIR_EL2
)
3820 .mapsTo(MISCREG_HAMAIR0
, MISCREG_HAMAIR1
);
3821 InitReg(MISCREG_MAIR_EL3
)
3823 InitReg(MISCREG_AMAIR_EL3
)
3825 InitReg(MISCREG_L2CTLR_EL1
)
3826 .allPrivileges().exceptUserMode();
3827 InitReg(MISCREG_L2ECTLR_EL1
)
3828 .allPrivileges().exceptUserMode();
3829 InitReg(MISCREG_VBAR_EL1
)
3830 .allPrivileges().exceptUserMode()
3831 .mapsTo(MISCREG_VBAR_NS
);
3832 InitReg(MISCREG_RVBAR_EL1
)
3833 .allPrivileges().exceptUserMode().writes(0);
3834 InitReg(MISCREG_ISR_EL1
)
3835 .allPrivileges().exceptUserMode().writes(0);
3836 InitReg(MISCREG_VBAR_EL2
)
3838 .mapsTo(MISCREG_HVBAR
);
3839 InitReg(MISCREG_RVBAR_EL2
)
3840 .mon().hyp().writes(0);
3841 InitReg(MISCREG_VBAR_EL3
)
3843 InitReg(MISCREG_RVBAR_EL3
)
3845 InitReg(MISCREG_RMR_EL3
)
3847 InitReg(MISCREG_CONTEXTIDR_EL1
)
3848 .allPrivileges().exceptUserMode()
3849 .mapsTo(MISCREG_CONTEXTIDR_NS
);
3850 InitReg(MISCREG_TPIDR_EL1
)
3851 .allPrivileges().exceptUserMode()
3852 .mapsTo(MISCREG_TPIDRPRW_NS
);
3853 InitReg(MISCREG_TPIDR_EL0
)
3855 .mapsTo(MISCREG_TPIDRURW_NS
);
3856 InitReg(MISCREG_TPIDRRO_EL0
)
3857 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
3858 .mapsTo(MISCREG_TPIDRURO_NS
);
3859 InitReg(MISCREG_TPIDR_EL2
)
3861 .mapsTo(MISCREG_HTPIDR
);
3862 InitReg(MISCREG_TPIDR_EL3
)
3864 InitReg(MISCREG_CNTKCTL_EL1
)
3865 .allPrivileges().exceptUserMode()
3866 .mapsTo(MISCREG_CNTKCTL
);
3867 InitReg(MISCREG_CNTFRQ_EL0
)
3869 .mapsTo(MISCREG_CNTFRQ
);
3870 InitReg(MISCREG_CNTPCT_EL0
)
3872 .mapsTo(MISCREG_CNTPCT
); /* 64b */
3873 InitReg(MISCREG_CNTVCT_EL0
)
3876 .mapsTo(MISCREG_CNTVCT
); /* 64b */
3877 InitReg(MISCREG_CNTP_TVAL_EL0
)
3879 .mapsTo(MISCREG_CNTP_TVAL_NS
);
3880 InitReg(MISCREG_CNTP_CTL_EL0
)
3882 .mapsTo(MISCREG_CNTP_CTL_NS
);
3883 InitReg(MISCREG_CNTP_CVAL_EL0
)
3885 .mapsTo(MISCREG_CNTP_CVAL_NS
); /* 64b */
3886 InitReg(MISCREG_CNTV_TVAL_EL0
)
3888 .mapsTo(MISCREG_CNTV_TVAL
);
3889 InitReg(MISCREG_CNTV_CTL_EL0
)
3891 .mapsTo(MISCREG_CNTV_CTL
);
3892 InitReg(MISCREG_CNTV_CVAL_EL0
)
3894 .mapsTo(MISCREG_CNTV_CVAL
); /* 64b */
3895 InitReg(MISCREG_PMEVCNTR0_EL0
)
3897 // .mapsTo(MISCREG_PMEVCNTR0);
3898 InitReg(MISCREG_PMEVCNTR1_EL0
)
3900 // .mapsTo(MISCREG_PMEVCNTR1);
3901 InitReg(MISCREG_PMEVCNTR2_EL0
)
3903 // .mapsTo(MISCREG_PMEVCNTR2);
3904 InitReg(MISCREG_PMEVCNTR3_EL0
)
3906 // .mapsTo(MISCREG_PMEVCNTR3);
3907 InitReg(MISCREG_PMEVCNTR4_EL0
)
3909 // .mapsTo(MISCREG_PMEVCNTR4);
3910 InitReg(MISCREG_PMEVCNTR5_EL0
)
3912 // .mapsTo(MISCREG_PMEVCNTR5);
3913 InitReg(MISCREG_PMEVTYPER0_EL0
)
3915 // .mapsTo(MISCREG_PMEVTYPER0);
3916 InitReg(MISCREG_PMEVTYPER1_EL0
)
3918 // .mapsTo(MISCREG_PMEVTYPER1);
3919 InitReg(MISCREG_PMEVTYPER2_EL0
)
3921 // .mapsTo(MISCREG_PMEVTYPER2);
3922 InitReg(MISCREG_PMEVTYPER3_EL0
)
3924 // .mapsTo(MISCREG_PMEVTYPER3);
3925 InitReg(MISCREG_PMEVTYPER4_EL0
)
3927 // .mapsTo(MISCREG_PMEVTYPER4);
3928 InitReg(MISCREG_PMEVTYPER5_EL0
)
3930 // .mapsTo(MISCREG_PMEVTYPER5);
3931 InitReg(MISCREG_CNTVOFF_EL2
)
3933 .mapsTo(MISCREG_CNTVOFF
); /* 64b */
3934 InitReg(MISCREG_CNTHCTL_EL2
)
3937 .mon().monNonSecureWrite(0).hypWrite()
3938 .mapsTo(MISCREG_CNTHCTL
);
3939 InitReg(MISCREG_CNTHP_TVAL_EL2
)
3941 .mon().monNonSecureWrite(0).hypWrite()
3942 .mapsTo(MISCREG_CNTHP_TVAL
);
3943 InitReg(MISCREG_CNTHP_CTL_EL2
)
3945 .mon().monNonSecureWrite(0).hypWrite()
3946 .mapsTo(MISCREG_CNTHP_CTL
);
3947 InitReg(MISCREG_CNTHP_CVAL_EL2
)
3949 .mon().monNonSecureWrite(0).hypWrite()
3950 .mapsTo(MISCREG_CNTHP_CVAL
); /* 64b */
3951 InitReg(MISCREG_CNTPS_TVAL_EL1
)
3953 .mon().monNonSecureWrite(0).hypWrite();
3954 InitReg(MISCREG_CNTPS_CTL_EL1
)
3956 .mon().monNonSecureWrite(0).hypWrite();
3957 InitReg(MISCREG_CNTPS_CVAL_EL1
)
3959 .mon().monNonSecureWrite(0).hypWrite();
3960 InitReg(MISCREG_IL1DATA0_EL1
)
3961 .allPrivileges().exceptUserMode();
3962 InitReg(MISCREG_IL1DATA1_EL1
)
3963 .allPrivileges().exceptUserMode();
3964 InitReg(MISCREG_IL1DATA2_EL1
)
3965 .allPrivileges().exceptUserMode();
3966 InitReg(MISCREG_IL1DATA3_EL1
)
3967 .allPrivileges().exceptUserMode();
3968 InitReg(MISCREG_DL1DATA0_EL1
)
3969 .allPrivileges().exceptUserMode();
3970 InitReg(MISCREG_DL1DATA1_EL1
)
3971 .allPrivileges().exceptUserMode();
3972 InitReg(MISCREG_DL1DATA2_EL1
)
3973 .allPrivileges().exceptUserMode();
3974 InitReg(MISCREG_DL1DATA3_EL1
)
3975 .allPrivileges().exceptUserMode();
3976 InitReg(MISCREG_DL1DATA4_EL1
)
3977 .allPrivileges().exceptUserMode();
3978 InitReg(MISCREG_L2ACTLR_EL1
)
3979 .allPrivileges().exceptUserMode();
3980 InitReg(MISCREG_CPUACTLR_EL1
)
3981 .allPrivileges().exceptUserMode();
3982 InitReg(MISCREG_CPUECTLR_EL1
)
3983 .allPrivileges().exceptUserMode();
3984 InitReg(MISCREG_CPUMERRSR_EL1
)
3985 .allPrivileges().exceptUserMode();
3986 InitReg(MISCREG_L2MERRSR_EL1
)
3989 .allPrivileges().exceptUserMode();
3990 InitReg(MISCREG_CBAR_EL1
)
3991 .allPrivileges().exceptUserMode().writes(0);
3992 InitReg(MISCREG_CONTEXTIDR_EL2
)
3996 InitReg(MISCREG_NOP
)
3998 InitReg(MISCREG_RAZ
)
3999 .allPrivileges().exceptUserMode().writes(0);
4000 InitReg(MISCREG_CP14_UNIMPL
)
4003 InitReg(MISCREG_CP15_UNIMPL
)
4006 InitReg(MISCREG_A64_UNIMPL
)
4009 InitReg(MISCREG_UNKNOWN
);
4011 // Register mappings for some unimplemented registers:
4015 // DBGDTR_EL0 -> DBGDTR{R or T}Xint
4016 // DBGDTRRX_EL0 -> DBGDTRRXint
4017 // DBGDTRTX_EL0 -> DBGDTRRXint
4018 // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
4023 } // namespace ArmISA