2 * Copyright (c) 2010 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
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8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
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12 * modified or unmodified, in source code or in binary form.
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15 * modification, are permitted provided that the following conditions are
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18 * redistributions in binary form must reproduce the above copyright
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23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include "arch/arm/miscregs.hh"
46 decodeCP15Reg(unsigned crn
, unsigned opc1
, unsigned crm
, unsigned opc2
)
70 return MISCREG_ID_PFR0
;
72 return MISCREG_ID_PFR1
;
74 return MISCREG_ID_DFR0
;
76 return MISCREG_ID_AFR0
;
78 return MISCREG_ID_MMFR0
;
80 return MISCREG_ID_MMFR1
;
82 return MISCREG_ID_MMFR2
;
84 return MISCREG_ID_MMFR3
;
90 return MISCREG_ID_ISAR0
;
92 return MISCREG_ID_ISAR1
;
94 return MISCREG_ID_ISAR2
;
96 return MISCREG_ID_ISAR3
;
98 return MISCREG_ID_ISAR4
;
100 return MISCREG_ID_ISAR5
;
103 return MISCREG_RAZ
; // read as zero
107 return MISCREG_RAZ
; // read as zero
114 return MISCREG_CCSIDR
;
116 return MISCREG_CLIDR
;
123 if (crm
== 0 && opc2
== 0) {
124 return MISCREG_CSSELR
;
134 return MISCREG_SCTLR
;
136 return MISCREG_ACTLR
;
138 return MISCREG_CPACR
;
140 } else if (crm
== 1) {
147 return MISCREG_NSACR
;
153 if (opc2
== 0 && crm
== 0) {
156 return MISCREG_TTBR0
;
158 return MISCREG_TTBR1
;
160 return MISCREG_TTBCR
;
165 if (opc1
== 0 && crm
== 0 && opc2
== 0) {
174 } else if (opc2
== 1) {
177 } else if (crm
== 1) {
179 return MISCREG_ADFSR
;
180 } else if (opc2
== 1) {
181 return MISCREG_AIFSR
;
187 if (opc1
== 0 && crm
== 0) {
207 return MISCREG_ICIALLUIS
;
209 return MISCREG_BPIALLIS
;
220 return MISCREG_ICIALLU
;
222 return MISCREG_ICIMVAU
;
224 return MISCREG_CP15ISB
;
226 return MISCREG_BPIALL
;
228 return MISCREG_BPIMVA
;
233 return MISCREG_DCIMVAC
;
234 } else if (opc2
== 2) {
235 return MISCREG_DCISW
;
241 return MISCREG_V2PCWPR
;
243 return MISCREG_V2PCWPW
;
245 return MISCREG_V2PCWUR
;
247 return MISCREG_V2PCWUW
;
249 return MISCREG_V2POWPR
;
251 return MISCREG_V2POWPW
;
253 return MISCREG_V2POWUR
;
255 return MISCREG_V2POWUW
;
261 return MISCREG_DCCMVAC
;
263 return MISCREG_MCCSW
;
265 return MISCREG_CP15DSB
;
267 return MISCREG_CP15DMB
;
272 return MISCREG_DCCMVAU
;
282 return MISCREG_DCCIMVAC
;
283 } else if (opc2
== 2) {
284 return MISCREG_DCCISW
;
296 return MISCREG_TLBIALLIS
;
298 return MISCREG_TLBIMVAIS
;
300 return MISCREG_TLBIASIDIS
;
302 return MISCREG_TLBIMVAAIS
;
308 return MISCREG_ITLBIALL
;
310 return MISCREG_ITLBIMVA
;
312 return MISCREG_ITLBIASID
;
318 return MISCREG_DTLBIALL
;
320 return MISCREG_DTLBIMVA
;
322 return MISCREG_DTLBIASID
;
328 return MISCREG_TLBIALL
;
330 return MISCREG_TLBIMVA
;
332 return MISCREG_TLBIASID
;
334 return MISCREG_TLBIMVAA
;
341 if (opc1
>= 0 && opc1
<= 7) {
350 //Reserved for Branch Predictor, Cache and TCM operations
355 // Reserved for Performance monitors
362 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
363 if (crm
== 2) { // TEX Remap Registers
366 } else if (opc2
== 1) {
373 if (opc1
>= 0 && opc1
<=7) {
385 // Reserved for DMA operations for TCM access
395 } else if (opc2
== 1) {
396 return MISCREG_MVBAR
;
398 } else if (crm
== 1) {
410 return MISCREG_FCEIDR
;
412 return MISCREG_CONTEXTIDR
;
414 return MISCREG_TPIDRURW
;
416 return MISCREG_TPIDRURO
;
418 return MISCREG_TPIDRPRW
;
424 // Implementation defined
427 // Unrecognized register