2 * Copyright (c) 2010-2013, 2015-2018 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include "arch/arm/miscregs.hh"
46 #include "arch/arm/isa.hh"
47 #include "base/logging.hh"
48 #include "cpu/thread_context.hh"
49 #include "sim/full_system.hh"
55 decodeCP14Reg(unsigned crn
, unsigned opc1
, unsigned crm
, unsigned opc2
)
65 return MISCREG_DBGDIDR
;
67 return MISCREG_DBGDSCRint
;
91 return MISCREG_TEEHBR
;
101 return MISCREG_JOSCR
;
123 // If we get here then it must be a register that we haven't implemented
124 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
125 crn
, opc1
, crm
, opc2
);
126 return MISCREG_CP14_UNIMPL
;
132 decodeCP15Reg(unsigned crn
, unsigned opc1
, unsigned crm
, unsigned opc2
)
144 return MISCREG_TCMTR
;
146 return MISCREG_TLBTR
;
148 return MISCREG_MPIDR
;
150 return MISCREG_REVIDR
;
158 return MISCREG_ID_PFR0
;
160 return MISCREG_ID_PFR1
;
162 return MISCREG_ID_DFR0
;
164 return MISCREG_ID_AFR0
;
166 return MISCREG_ID_MMFR0
;
168 return MISCREG_ID_MMFR1
;
170 return MISCREG_ID_MMFR2
;
172 return MISCREG_ID_MMFR3
;
178 return MISCREG_ID_ISAR0
;
180 return MISCREG_ID_ISAR1
;
182 return MISCREG_ID_ISAR2
;
184 return MISCREG_ID_ISAR3
;
186 return MISCREG_ID_ISAR4
;
188 return MISCREG_ID_ISAR5
;
191 return MISCREG_RAZ
; // read as zero
195 return MISCREG_RAZ
; // read as zero
202 return MISCREG_CCSIDR
;
204 return MISCREG_CLIDR
;
211 if (crm
== 0 && opc2
== 0) {
212 return MISCREG_CSSELR
;
218 return MISCREG_VPIDR
;
220 return MISCREG_VMPIDR
;
230 return MISCREG_SCTLR
;
232 return MISCREG_ACTLR
;
234 return MISCREG_CPACR
;
236 } else if (crm
== 1) {
243 return MISCREG_NSACR
;
246 } else if (opc1
== 4) {
249 return MISCREG_HSCTLR
;
251 return MISCREG_HACTLR
;
252 } else if (crm
== 1) {
259 return MISCREG_HCPTR
;
269 if (opc1
== 0 && crm
== 0) {
272 return MISCREG_TTBR0
;
274 return MISCREG_TTBR1
;
276 return MISCREG_TTBCR
;
278 } else if (opc1
== 4) {
279 if (crm
== 0 && opc2
== 2)
281 else if (crm
== 1 && opc2
== 2)
286 if (opc1
== 0 && crm
== 0 && opc2
== 0) {
291 if (opc1
== 0 && crm
== 6 && opc2
== 0) {
292 return MISCREG_ICC_PMR
;
300 } else if (opc2
== 1) {
303 } else if (crm
== 1) {
305 return MISCREG_ADFSR
;
306 } else if (opc2
== 1) {
307 return MISCREG_AIFSR
;
310 } else if (opc1
== 4) {
313 return MISCREG_HADFSR
;
315 return MISCREG_HAIFSR
;
316 } else if (crm
== 2 && opc2
== 0) {
322 if (opc1
== 0 && crm
== 0) {
329 } else if (opc1
== 4 && crm
== 0) {
332 return MISCREG_HDFAR
;
334 return MISCREG_HIFAR
;
336 return MISCREG_HPFAR
;
351 return MISCREG_ICIALLUIS
;
353 return MISCREG_BPIALLIS
;
364 return MISCREG_ICIALLU
;
366 return MISCREG_ICIMVAU
;
368 return MISCREG_CP15ISB
;
370 return MISCREG_BPIALL
;
372 return MISCREG_BPIMVA
;
377 return MISCREG_DCIMVAC
;
378 } else if (opc2
== 2) {
379 return MISCREG_DCISW
;
385 return MISCREG_ATS1CPR
;
387 return MISCREG_ATS1CPW
;
389 return MISCREG_ATS1CUR
;
391 return MISCREG_ATS1CUW
;
393 return MISCREG_ATS12NSOPR
;
395 return MISCREG_ATS12NSOPW
;
397 return MISCREG_ATS12NSOUR
;
399 return MISCREG_ATS12NSOUW
;
405 return MISCREG_DCCMVAC
;
407 return MISCREG_DCCSW
;
409 return MISCREG_CP15DSB
;
411 return MISCREG_CP15DMB
;
416 return MISCREG_DCCMVAU
;
426 return MISCREG_DCCIMVAC
;
427 } else if (opc2
== 2) {
428 return MISCREG_DCCISW
;
432 } else if (opc1
== 4 && crm
== 8) {
434 return MISCREG_ATS1HR
;
436 return MISCREG_ATS1HW
;
445 return MISCREG_TLBIALLIS
;
447 return MISCREG_TLBIMVAIS
;
449 return MISCREG_TLBIASIDIS
;
451 return MISCREG_TLBIMVAAIS
;
453 return MISCREG_TLBIMVALIS
;
455 return MISCREG_TLBIMVAALIS
;
461 return MISCREG_ITLBIALL
;
463 return MISCREG_ITLBIMVA
;
465 return MISCREG_ITLBIASID
;
471 return MISCREG_DTLBIALL
;
473 return MISCREG_DTLBIMVA
;
475 return MISCREG_DTLBIASID
;
481 return MISCREG_TLBIALL
;
483 return MISCREG_TLBIMVA
;
485 return MISCREG_TLBIASID
;
487 return MISCREG_TLBIMVAA
;
489 return MISCREG_TLBIMVAL
;
491 return MISCREG_TLBIMVAAL
;
495 } else if (opc1
== 4) {
499 return MISCREG_TLBIIPAS2IS
;
501 return MISCREG_TLBIIPAS2LIS
;
503 } else if (crm
== 3) {
506 return MISCREG_TLBIALLHIS
;
508 return MISCREG_TLBIMVAHIS
;
510 return MISCREG_TLBIALLNSNHIS
;
512 return MISCREG_TLBIMVALHIS
;
514 } else if (crm
== 4) {
517 return MISCREG_TLBIIPAS2
;
519 return MISCREG_TLBIIPAS2L
;
521 } else if (crm
== 7) {
524 return MISCREG_TLBIALLH
;
526 return MISCREG_TLBIMVAH
;
528 return MISCREG_TLBIALLNSNH
;
530 return MISCREG_TLBIMVALH
;
536 // Every cop register with CRn = 9 and CRm in
537 // {0-2}, {5-8} is implementation defined regardless
547 return MISCREG_IMPDEF_UNIMPL
;
556 return MISCREG_PMCNTENSET
;
558 return MISCREG_PMCNTENCLR
;
560 return MISCREG_PMOVSR
;
562 return MISCREG_PMSWINC
;
564 return MISCREG_PMSELR
;
566 return MISCREG_PMCEID0
;
568 return MISCREG_PMCEID1
;
574 return MISCREG_PMCCNTR
;
576 // Selector is PMSELR.SEL
577 return MISCREG_PMXEVTYPER_PMCCFILTR
;
579 return MISCREG_PMXEVCNTR
;
585 return MISCREG_PMUSERENR
;
587 return MISCREG_PMINTENSET
;
589 return MISCREG_PMINTENCLR
;
591 return MISCREG_PMOVSSET
;
595 } else if (opc1
== 1) {
599 case 2: // L2CTLR, L2 Control Register
600 return MISCREG_L2CTLR
;
602 return MISCREG_L2ECTLR
;
611 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
613 return MISCREG_IMPDEF_UNIMPL
;
614 } else if (crm
== 2) { // TEX Remap Registers
616 // Selector is TTBCR.EAE
617 return MISCREG_PRRR_MAIR0
;
618 } else if (opc2
== 1) {
619 // Selector is TTBCR.EAE
620 return MISCREG_NMRR_MAIR1
;
622 } else if (crm
== 3) {
624 return MISCREG_AMAIR0
;
625 } else if (opc2
== 1) {
626 return MISCREG_AMAIR1
;
629 } else if (opc1
== 4) {
630 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
633 return MISCREG_HMAIR0
;
635 return MISCREG_HMAIR1
;
636 } else if (crm
== 3) {
638 return MISCREG_HAMAIR0
;
640 return MISCREG_HAMAIR1
;
657 // Reserved for DMA operations for TCM access
658 return MISCREG_IMPDEF_UNIMPL
;
669 } else if (opc2
== 1) {
670 return MISCREG_MVBAR
;
672 } else if (crm
== 1) {
676 } else if (crm
== 8) {
679 return MISCREG_ICC_IAR0
;
681 return MISCREG_ICC_EOIR0
;
683 return MISCREG_ICC_HPPIR0
;
685 return MISCREG_ICC_BPR0
;
687 return MISCREG_ICC_AP0R0
;
689 return MISCREG_ICC_AP0R1
;
691 return MISCREG_ICC_AP0R2
;
693 return MISCREG_ICC_AP0R3
;
695 } else if (crm
== 9) {
698 return MISCREG_ICC_AP1R0
;
700 return MISCREG_ICC_AP1R1
;
702 return MISCREG_ICC_AP1R2
;
704 return MISCREG_ICC_AP1R3
;
706 } else if (crm
== 11) {
709 return MISCREG_ICC_DIR
;
711 return MISCREG_ICC_RPR
;
713 } else if (crm
== 12) {
716 return MISCREG_ICC_IAR1
;
718 return MISCREG_ICC_EOIR1
;
720 return MISCREG_ICC_HPPIR1
;
722 return MISCREG_ICC_BPR1
;
724 return MISCREG_ICC_CTLR
;
726 return MISCREG_ICC_SRE
;
728 return MISCREG_ICC_IGRPEN0
;
730 return MISCREG_ICC_IGRPEN1
;
733 } else if (opc1
== 4) {
734 if (crm
== 0 && opc2
== 0) {
735 return MISCREG_HVBAR
;
736 } else if (crm
== 8) {
739 return MISCREG_ICH_AP0R0
;
741 return MISCREG_ICH_AP0R1
;
743 return MISCREG_ICH_AP0R2
;
745 return MISCREG_ICH_AP0R3
;
747 } else if (crm
== 9) {
750 return MISCREG_ICH_AP1R0
;
752 return MISCREG_ICH_AP1R1
;
754 return MISCREG_ICH_AP1R2
;
756 return MISCREG_ICH_AP1R3
;
758 return MISCREG_ICC_HSRE
;
760 } else if (crm
== 11) {
763 return MISCREG_ICH_HCR
;
765 return MISCREG_ICH_VTR
;
767 return MISCREG_ICH_MISR
;
769 return MISCREG_ICH_EISR
;
771 return MISCREG_ICH_ELRSR
;
773 return MISCREG_ICH_VMCR
;
775 } else if (crm
== 12) {
778 return MISCREG_ICH_LR0
;
780 return MISCREG_ICH_LR1
;
782 return MISCREG_ICH_LR2
;
784 return MISCREG_ICH_LR3
;
786 return MISCREG_ICH_LR4
;
788 return MISCREG_ICH_LR5
;
790 return MISCREG_ICH_LR6
;
792 return MISCREG_ICH_LR7
;
794 } else if (crm
== 13) {
797 return MISCREG_ICH_LR8
;
799 return MISCREG_ICH_LR9
;
801 return MISCREG_ICH_LR10
;
803 return MISCREG_ICH_LR11
;
805 return MISCREG_ICH_LR12
;
807 return MISCREG_ICH_LR13
;
809 return MISCREG_ICH_LR14
;
811 return MISCREG_ICH_LR15
;
813 } else if (crm
== 14) {
816 return MISCREG_ICH_LRC0
;
818 return MISCREG_ICH_LRC1
;
820 return MISCREG_ICH_LRC2
;
822 return MISCREG_ICH_LRC3
;
824 return MISCREG_ICH_LRC4
;
826 return MISCREG_ICH_LRC5
;
828 return MISCREG_ICH_LRC6
;
830 return MISCREG_ICH_LRC7
;
832 } else if (crm
== 15) {
835 return MISCREG_ICH_LRC8
;
837 return MISCREG_ICH_LRC9
;
839 return MISCREG_ICH_LRC10
;
841 return MISCREG_ICH_LRC11
;
843 return MISCREG_ICH_LRC12
;
845 return MISCREG_ICH_LRC13
;
847 return MISCREG_ICH_LRC14
;
849 return MISCREG_ICH_LRC15
;
852 } else if (opc1
== 6) {
856 return MISCREG_ICC_MCTLR
;
858 return MISCREG_ICC_MSRE
;
860 return MISCREG_ICC_MGRPEN1
;
870 return MISCREG_FCSEIDR
;
872 return MISCREG_CONTEXTIDR
;
874 return MISCREG_TPIDRURW
;
876 return MISCREG_TPIDRURO
;
878 return MISCREG_TPIDRPRW
;
881 } else if (opc1
== 4) {
882 if (crm
== 0 && opc2
== 2)
883 return MISCREG_HTPIDR
;
891 return MISCREG_CNTFRQ
;
895 return MISCREG_CNTKCTL
;
899 return MISCREG_CNTP_TVAL
;
901 return MISCREG_CNTP_CTL
;
905 return MISCREG_CNTV_TVAL
;
907 return MISCREG_CNTV_CTL
;
910 } else if (opc1
== 4) {
911 if (crm
== 1 && opc2
== 0) {
912 return MISCREG_CNTHCTL
;
913 } else if (crm
== 2) {
915 return MISCREG_CNTHP_TVAL
;
917 return MISCREG_CNTHP_CTL
;
922 // Implementation defined
923 return MISCREG_IMPDEF_UNIMPL
;
925 // Unrecognized register
926 return MISCREG_CP15_UNIMPL
;
930 decodeCP15Reg64(unsigned crm
, unsigned opc1
)
936 return MISCREG_TTBR0
;
938 return MISCREG_TTBR1
;
940 return MISCREG_HTTBR
;
942 return MISCREG_VTTBR
;
952 return MISCREG_CNTPCT
;
954 return MISCREG_CNTVCT
;
956 return MISCREG_CNTP_CVAL
;
958 return MISCREG_CNTV_CVAL
;
960 return MISCREG_CNTVOFF
;
962 return MISCREG_CNTHP_CVAL
;
967 return MISCREG_CPUMERRSR
;
969 return MISCREG_L2MERRSR
;
972 // Unrecognized register
973 return MISCREG_CP15_UNIMPL
;
976 std::tuple
<bool, bool>
977 canReadCoprocReg(MiscRegIndex reg
, SCR scr
, CPSR cpsr
)
979 bool secure
= !scr
.ns
;
980 bool canRead
= false;
981 bool undefined
= false;
985 canRead
= secure
? miscRegInfo
[reg
][MISCREG_USR_S_RD
] :
986 miscRegInfo
[reg
][MISCREG_USR_NS_RD
];
994 canRead
= secure
? miscRegInfo
[reg
][MISCREG_PRI_S_RD
] :
995 miscRegInfo
[reg
][MISCREG_PRI_NS_RD
];
998 canRead
= secure
? miscRegInfo
[reg
][MISCREG_MON_NS0_RD
] :
999 miscRegInfo
[reg
][MISCREG_MON_NS1_RD
];
1002 canRead
= miscRegInfo
[reg
][MISCREG_HYP_RD
];
1007 // can't do permissions checkes on the root of a banked pair of regs
1008 assert(!miscRegInfo
[reg
][MISCREG_BANKED
]);
1009 return std::make_tuple(canRead
, undefined
);
1012 std::tuple
<bool, bool>
1013 canWriteCoprocReg(MiscRegIndex reg
, SCR scr
, CPSR cpsr
)
1015 bool secure
= !scr
.ns
;
1016 bool canWrite
= false;
1017 bool undefined
= false;
1019 switch (cpsr
.mode
) {
1021 canWrite
= secure
? miscRegInfo
[reg
][MISCREG_USR_S_WR
] :
1022 miscRegInfo
[reg
][MISCREG_USR_NS_WR
];
1028 case MODE_UNDEFINED
:
1030 canWrite
= secure
? miscRegInfo
[reg
][MISCREG_PRI_S_WR
] :
1031 miscRegInfo
[reg
][MISCREG_PRI_NS_WR
];
1034 canWrite
= secure
? miscRegInfo
[reg
][MISCREG_MON_NS0_WR
] :
1035 miscRegInfo
[reg
][MISCREG_MON_NS1_WR
];
1038 canWrite
= miscRegInfo
[reg
][MISCREG_HYP_WR
];
1043 // can't do permissions checkes on the root of a banked pair of regs
1044 assert(!miscRegInfo
[reg
][MISCREG_BANKED
]);
1045 return std::make_tuple(canWrite
, undefined
);
1049 snsBankedIndex(MiscRegIndex reg
, ThreadContext
*tc
)
1051 SCR scr
= tc
->readMiscReg(MISCREG_SCR
);
1052 return snsBankedIndex(reg
, tc
, scr
.ns
);
1056 snsBankedIndex(MiscRegIndex reg
, ThreadContext
*tc
, bool ns
)
1058 int reg_as_int
= static_cast<int>(reg
);
1059 if (miscRegInfo
[reg
][MISCREG_BANKED
]) {
1060 reg_as_int
+= (ArmSystem::haveSecurity(tc
) &&
1061 !ArmSystem::highestELIs64(tc
) && !ns
) ? 2 : 1;
1068 * If the reg is a child reg of a banked set, then the parent is the last
1069 * banked one in the list. This is messy, and the wish is to eventually have
1070 * the bitmap replaced with a better data structure. the preUnflatten function
1071 * initializes a lookup table to speed up the search for these banked
1075 int unflattenResultMiscReg
[NUM_MISCREGS
];
1078 preUnflattenMiscReg()
1081 for (int i
= 0 ; i
< NUM_MISCREGS
; i
++){
1082 if (miscRegInfo
[i
][MISCREG_BANKED
])
1084 if (miscRegInfo
[i
][MISCREG_BANKED_CHILD
])
1085 unflattenResultMiscReg
[i
] = reg
;
1087 unflattenResultMiscReg
[i
] = i
;
1088 // if this assert fails, no parent was found, and something is broken
1089 assert(unflattenResultMiscReg
[i
] > -1);
1094 unflattenMiscReg(int reg
)
1096 return unflattenResultMiscReg
[reg
];
1100 canReadAArch64SysReg(MiscRegIndex reg
, SCR scr
, CPSR cpsr
, ThreadContext
*tc
)
1102 // Check for SP_EL0 access while SPSEL == 0
1103 if ((reg
== MISCREG_SP_EL0
) && (tc
->readMiscReg(MISCREG_SPSEL
) == 0))
1106 // Check for RVBAR access
1107 if (reg
== MISCREG_RVBAR_EL1
) {
1108 ExceptionLevel highest_el
= ArmSystem::highestEL(tc
);
1109 if (highest_el
== EL2
|| highest_el
== EL3
)
1112 if (reg
== MISCREG_RVBAR_EL2
) {
1113 ExceptionLevel highest_el
= ArmSystem::highestEL(tc
);
1114 if (highest_el
== EL3
)
1118 bool secure
= ArmSystem::haveSecurity(tc
) && !scr
.ns
;
1120 switch (opModeToEL((OperatingMode
) (uint8_t) cpsr
.mode
)) {
1122 return secure
? miscRegInfo
[reg
][MISCREG_USR_S_RD
] :
1123 miscRegInfo
[reg
][MISCREG_USR_NS_RD
];
1125 return secure
? miscRegInfo
[reg
][MISCREG_PRI_S_RD
] :
1126 miscRegInfo
[reg
][MISCREG_PRI_NS_RD
];
1128 return miscRegInfo
[reg
][MISCREG_HYP_RD
];
1130 return secure
? miscRegInfo
[reg
][MISCREG_MON_NS0_RD
] :
1131 miscRegInfo
[reg
][MISCREG_MON_NS1_RD
];
1133 panic("Invalid exception level");
1138 canWriteAArch64SysReg(MiscRegIndex reg
, SCR scr
, CPSR cpsr
, ThreadContext
*tc
)
1140 // Check for SP_EL0 access while SPSEL == 0
1141 if ((reg
== MISCREG_SP_EL0
) && (tc
->readMiscReg(MISCREG_SPSEL
) == 0))
1143 ExceptionLevel el
= opModeToEL((OperatingMode
) (uint8_t) cpsr
.mode
);
1144 if (reg
== MISCREG_DAIF
) {
1145 SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR_EL1
);
1146 if (el
== EL0
&& !sctlr
.uma
)
1149 if (FullSystem
&& reg
== MISCREG_DC_ZVA_Xt
) {
1150 // In syscall-emulation mode, this test is skipped and DCZVA is always
1152 SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR_EL1
);
1153 if (el
== EL0
&& !sctlr
.dze
)
1156 if (reg
== MISCREG_DC_CVAC_Xt
|| reg
== MISCREG_DC_CIVAC_Xt
) {
1157 SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR_EL1
);
1158 if (el
== EL0
&& !sctlr
.uci
)
1162 bool secure
= ArmSystem::haveSecurity(tc
) && !scr
.ns
;
1166 return secure
? miscRegInfo
[reg
][MISCREG_USR_S_WR
] :
1167 miscRegInfo
[reg
][MISCREG_USR_NS_WR
];
1169 return secure
? miscRegInfo
[reg
][MISCREG_PRI_S_WR
] :
1170 miscRegInfo
[reg
][MISCREG_PRI_NS_WR
];
1172 return miscRegInfo
[reg
][MISCREG_HYP_WR
];
1174 return secure
? miscRegInfo
[reg
][MISCREG_MON_NS0_WR
] :
1175 miscRegInfo
[reg
][MISCREG_MON_NS1_WR
];
1177 panic("Invalid exception level");
1182 decodeAArch64SysReg(unsigned op0
, unsigned op1
,
1183 unsigned crn
, unsigned crm
,
1196 return MISCREG_IC_IALLUIS
;
1202 return MISCREG_IC_IALLU
;
1208 return MISCREG_DC_IVAC_Xt
;
1210 return MISCREG_DC_ISW_Xt
;
1216 return MISCREG_AT_S1E1R_Xt
;
1218 return MISCREG_AT_S1E1W_Xt
;
1220 return MISCREG_AT_S1E0R_Xt
;
1222 return MISCREG_AT_S1E0W_Xt
;
1228 return MISCREG_DC_CSW_Xt
;
1234 return MISCREG_DC_CISW_Xt
;
1244 return MISCREG_DC_ZVA_Xt
;
1250 return MISCREG_IC_IVAU_Xt
;
1256 return MISCREG_DC_CVAC_Xt
;
1262 return MISCREG_DC_CVAU_Xt
;
1268 return MISCREG_DC_CIVAC_Xt
;
1278 return MISCREG_AT_S1E2R_Xt
;
1280 return MISCREG_AT_S1E2W_Xt
;
1282 return MISCREG_AT_S12E1R_Xt
;
1284 return MISCREG_AT_S12E1W_Xt
;
1286 return MISCREG_AT_S12E0R_Xt
;
1288 return MISCREG_AT_S12E0W_Xt
;
1298 return MISCREG_AT_S1E3R_Xt
;
1300 return MISCREG_AT_S1E3W_Xt
;
1314 return MISCREG_TLBI_VMALLE1IS
;
1316 return MISCREG_TLBI_VAE1IS_Xt
;
1318 return MISCREG_TLBI_ASIDE1IS_Xt
;
1320 return MISCREG_TLBI_VAAE1IS_Xt
;
1322 return MISCREG_TLBI_VALE1IS_Xt
;
1324 return MISCREG_TLBI_VAALE1IS_Xt
;
1330 return MISCREG_TLBI_VMALLE1
;
1332 return MISCREG_TLBI_VAE1_Xt
;
1334 return MISCREG_TLBI_ASIDE1_Xt
;
1336 return MISCREG_TLBI_VAAE1_Xt
;
1338 return MISCREG_TLBI_VALE1_Xt
;
1340 return MISCREG_TLBI_VAALE1_Xt
;
1350 return MISCREG_TLBI_IPAS2E1IS_Xt
;
1352 return MISCREG_TLBI_IPAS2LE1IS_Xt
;
1358 return MISCREG_TLBI_ALLE2IS
;
1360 return MISCREG_TLBI_VAE2IS_Xt
;
1362 return MISCREG_TLBI_ALLE1IS
;
1364 return MISCREG_TLBI_VALE2IS_Xt
;
1366 return MISCREG_TLBI_VMALLS12E1IS
;
1372 return MISCREG_TLBI_IPAS2E1_Xt
;
1374 return MISCREG_TLBI_IPAS2LE1_Xt
;
1380 return MISCREG_TLBI_ALLE2
;
1382 return MISCREG_TLBI_VAE2_Xt
;
1384 return MISCREG_TLBI_ALLE1
;
1386 return MISCREG_TLBI_VALE2_Xt
;
1388 return MISCREG_TLBI_VMALLS12E1
;
1398 return MISCREG_TLBI_ALLE3IS
;
1400 return MISCREG_TLBI_VAE3IS_Xt
;
1402 return MISCREG_TLBI_VALE3IS_Xt
;
1408 return MISCREG_TLBI_ALLE3
;
1410 return MISCREG_TLBI_VAE3_Xt
;
1412 return MISCREG_TLBI_VALE3_Xt
;
1421 // SYS Instruction with CRn = { 11, 15 }
1422 // (Trappable by HCR_EL2.TIDCP)
1423 return MISCREG_IMPDEF_UNIMPL
;
1435 return MISCREG_OSDTRRX_EL1
;
1437 return MISCREG_DBGBVR0_EL1
;
1439 return MISCREG_DBGBCR0_EL1
;
1441 return MISCREG_DBGWVR0_EL1
;
1443 return MISCREG_DBGWCR0_EL1
;
1449 return MISCREG_DBGBVR1_EL1
;
1451 return MISCREG_DBGBCR1_EL1
;
1453 return MISCREG_DBGWVR1_EL1
;
1455 return MISCREG_DBGWCR1_EL1
;
1461 return MISCREG_MDCCINT_EL1
;
1463 return MISCREG_MDSCR_EL1
;
1465 return MISCREG_DBGBVR2_EL1
;
1467 return MISCREG_DBGBCR2_EL1
;
1469 return MISCREG_DBGWVR2_EL1
;
1471 return MISCREG_DBGWCR2_EL1
;
1477 return MISCREG_OSDTRTX_EL1
;
1479 return MISCREG_DBGBVR3_EL1
;
1481 return MISCREG_DBGBCR3_EL1
;
1483 return MISCREG_DBGWVR3_EL1
;
1485 return MISCREG_DBGWCR3_EL1
;
1491 return MISCREG_DBGBVR4_EL1
;
1493 return MISCREG_DBGBCR4_EL1
;
1499 return MISCREG_DBGBVR5_EL1
;
1501 return MISCREG_DBGBCR5_EL1
;
1507 return MISCREG_OSECCR_EL1
;
1517 return MISCREG_TEECR32_EL1
;
1527 return MISCREG_MDCCSR_EL0
;
1533 return MISCREG_MDDTR_EL0
;
1539 return MISCREG_MDDTRRX_EL0
;
1549 return MISCREG_DBGVCR32_EL2
;
1563 return MISCREG_MDRAR_EL1
;
1565 return MISCREG_OSLAR_EL1
;
1571 return MISCREG_OSLSR_EL1
;
1577 return MISCREG_OSDLR_EL1
;
1583 return MISCREG_DBGPRCR_EL1
;
1593 return MISCREG_TEEHBR32_EL1
;
1607 return MISCREG_DBGCLAIMSET_EL1
;
1613 return MISCREG_DBGCLAIMCLR_EL1
;
1619 return MISCREG_DBGAUTHSTATUS_EL1
;
1637 return MISCREG_MIDR_EL1
;
1639 return MISCREG_MPIDR_EL1
;
1641 return MISCREG_REVIDR_EL1
;
1647 return MISCREG_ID_PFR0_EL1
;
1649 return MISCREG_ID_PFR1_EL1
;
1651 return MISCREG_ID_DFR0_EL1
;
1653 return MISCREG_ID_AFR0_EL1
;
1655 return MISCREG_ID_MMFR0_EL1
;
1657 return MISCREG_ID_MMFR1_EL1
;
1659 return MISCREG_ID_MMFR2_EL1
;
1661 return MISCREG_ID_MMFR3_EL1
;
1667 return MISCREG_ID_ISAR0_EL1
;
1669 return MISCREG_ID_ISAR1_EL1
;
1671 return MISCREG_ID_ISAR2_EL1
;
1673 return MISCREG_ID_ISAR3_EL1
;
1675 return MISCREG_ID_ISAR4_EL1
;
1677 return MISCREG_ID_ISAR5_EL1
;
1683 return MISCREG_MVFR0_EL1
;
1685 return MISCREG_MVFR1_EL1
;
1687 return MISCREG_MVFR2_EL1
;
1695 return MISCREG_ID_AA64PFR0_EL1
;
1697 return MISCREG_ID_AA64PFR1_EL1
;
1701 return MISCREG_ID_AA64ZFR0_EL1
;
1709 return MISCREG_ID_AA64DFR0_EL1
;
1711 return MISCREG_ID_AA64DFR1_EL1
;
1713 return MISCREG_ID_AA64AFR0_EL1
;
1715 return MISCREG_ID_AA64AFR1_EL1
;
1726 return MISCREG_ID_AA64ISAR0_EL1
;
1728 return MISCREG_ID_AA64ISAR1_EL1
;
1736 return MISCREG_ID_AA64MMFR0_EL1
;
1738 return MISCREG_ID_AA64MMFR1_EL1
;
1740 return MISCREG_ID_AA64MMFR2_EL1
;
1752 return MISCREG_CCSIDR_EL1
;
1754 return MISCREG_CLIDR_EL1
;
1756 return MISCREG_AIDR_EL1
;
1766 return MISCREG_CSSELR_EL1
;
1776 return MISCREG_CTR_EL0
;
1778 return MISCREG_DCZID_EL0
;
1788 return MISCREG_VPIDR_EL2
;
1790 return MISCREG_VMPIDR_EL2
;
1804 return MISCREG_SCTLR_EL1
;
1806 return MISCREG_ACTLR_EL1
;
1808 return MISCREG_CPACR_EL1
;
1814 return MISCREG_ZCR_EL1
;
1824 return MISCREG_SCTLR_EL2
;
1826 return MISCREG_ACTLR_EL2
;
1832 return MISCREG_HCR_EL2
;
1834 return MISCREG_MDCR_EL2
;
1836 return MISCREG_CPTR_EL2
;
1838 return MISCREG_HSTR_EL2
;
1840 return MISCREG_HACR_EL2
;
1846 return MISCREG_ZCR_EL2
;
1856 return MISCREG_ZCR_EL12
;
1866 return MISCREG_SCTLR_EL3
;
1868 return MISCREG_ACTLR_EL3
;
1874 return MISCREG_SCR_EL3
;
1876 return MISCREG_SDER32_EL3
;
1878 return MISCREG_CPTR_EL3
;
1884 return MISCREG_ZCR_EL3
;
1890 return MISCREG_MDCR_EL3
;
1904 return MISCREG_TTBR0_EL1
;
1906 return MISCREG_TTBR1_EL1
;
1908 return MISCREG_TCR_EL1
;
1918 return MISCREG_TTBR0_EL2
;
1920 return MISCREG_TTBR1_EL2
;
1922 return MISCREG_TCR_EL2
;
1928 return MISCREG_VTTBR_EL2
;
1930 return MISCREG_VTCR_EL2
;
1940 return MISCREG_TTBR0_EL3
;
1942 return MISCREG_TCR_EL3
;
1956 return MISCREG_DACR32_EL2
;
1970 return MISCREG_SPSR_EL1
;
1972 return MISCREG_ELR_EL1
;
1978 return MISCREG_SP_EL0
;
1984 return MISCREG_SPSEL
;
1986 return MISCREG_CURRENTEL
;
1992 return MISCREG_ICC_PMR_EL1
;
2002 return MISCREG_NZCV
;
2004 return MISCREG_DAIF
;
2010 return MISCREG_FPCR
;
2012 return MISCREG_FPSR
;
2018 return MISCREG_DSPSR_EL0
;
2020 return MISCREG_DLR_EL0
;
2030 return MISCREG_SPSR_EL2
;
2032 return MISCREG_ELR_EL2
;
2038 return MISCREG_SP_EL1
;
2044 return MISCREG_SPSR_IRQ_AA64
;
2046 return MISCREG_SPSR_ABT_AA64
;
2048 return MISCREG_SPSR_UND_AA64
;
2050 return MISCREG_SPSR_FIQ_AA64
;
2060 return MISCREG_SPSR_EL3
;
2062 return MISCREG_ELR_EL3
;
2068 return MISCREG_SP_EL2
;
2082 return MISCREG_AFSR0_EL1
;
2084 return MISCREG_AFSR1_EL1
;
2090 return MISCREG_ESR_EL1
;
2096 return MISCREG_ERRIDR_EL1
;
2098 return MISCREG_ERRSELR_EL1
;
2104 return MISCREG_ERXFR_EL1
;
2106 return MISCREG_ERXCTLR_EL1
;
2108 return MISCREG_ERXSTATUS_EL1
;
2110 return MISCREG_ERXADDR_EL1
;
2116 return MISCREG_ERXMISC0_EL1
;
2118 return MISCREG_ERXMISC1_EL1
;
2128 return MISCREG_IFSR32_EL2
;
2134 return MISCREG_AFSR0_EL2
;
2136 return MISCREG_AFSR1_EL2
;
2142 return MISCREG_ESR_EL2
;
2144 return MISCREG_VSESR_EL2
;
2150 return MISCREG_FPEXC32_EL2
;
2160 return MISCREG_AFSR0_EL3
;
2162 return MISCREG_AFSR1_EL3
;
2168 return MISCREG_ESR_EL3
;
2182 return MISCREG_FAR_EL1
;
2192 return MISCREG_FAR_EL2
;
2194 return MISCREG_HPFAR_EL2
;
2204 return MISCREG_FAR_EL3
;
2218 return MISCREG_PAR_EL1
;
2232 return MISCREG_PMINTENSET_EL1
;
2234 return MISCREG_PMINTENCLR_EL1
;
2244 return MISCREG_PMCR_EL0
;
2246 return MISCREG_PMCNTENSET_EL0
;
2248 return MISCREG_PMCNTENCLR_EL0
;
2250 return MISCREG_PMOVSCLR_EL0
;
2252 return MISCREG_PMSWINC_EL0
;
2254 return MISCREG_PMSELR_EL0
;
2256 return MISCREG_PMCEID0_EL0
;
2258 return MISCREG_PMCEID1_EL0
;
2264 return MISCREG_PMCCNTR_EL0
;
2266 return MISCREG_PMXEVTYPER_EL0
;
2268 return MISCREG_PMXEVCNTR_EL0
;
2274 return MISCREG_PMUSERENR_EL0
;
2276 return MISCREG_PMOVSSET_EL0
;
2290 return MISCREG_MAIR_EL1
;
2296 return MISCREG_AMAIR_EL1
;
2306 return MISCREG_MAIR_EL2
;
2312 return MISCREG_AMAIR_EL2
;
2322 return MISCREG_MAIR_EL3
;
2328 return MISCREG_AMAIR_EL3
;
2342 return MISCREG_L2CTLR_EL1
;
2344 return MISCREG_L2ECTLR_EL1
;
2350 // S3_<op1>_11_<Cm>_<op2>
2351 return MISCREG_IMPDEF_UNIMPL
;
2361 return MISCREG_VBAR_EL1
;
2363 return MISCREG_RVBAR_EL1
;
2369 return MISCREG_ISR_EL1
;
2371 return MISCREG_DISR_EL1
;
2377 return MISCREG_ICC_IAR0_EL1
;
2379 return MISCREG_ICC_EOIR0_EL1
;
2381 return MISCREG_ICC_HPPIR0_EL1
;
2383 return MISCREG_ICC_BPR0_EL1
;
2385 return MISCREG_ICC_AP0R0_EL1
;
2387 return MISCREG_ICC_AP0R1_EL1
;
2389 return MISCREG_ICC_AP0R2_EL1
;
2391 return MISCREG_ICC_AP0R3_EL1
;
2397 return MISCREG_ICC_AP1R0_EL1
;
2399 return MISCREG_ICC_AP1R1_EL1
;
2401 return MISCREG_ICC_AP1R2_EL1
;
2403 return MISCREG_ICC_AP1R3_EL1
;
2409 return MISCREG_ICC_DIR_EL1
;
2411 return MISCREG_ICC_RPR_EL1
;
2413 return MISCREG_ICC_SGI1R_EL1
;
2415 return MISCREG_ICC_ASGI1R_EL1
;
2417 return MISCREG_ICC_SGI0R_EL1
;
2423 return MISCREG_ICC_IAR1_EL1
;
2425 return MISCREG_ICC_EOIR1_EL1
;
2427 return MISCREG_ICC_HPPIR1_EL1
;
2429 return MISCREG_ICC_BPR1_EL1
;
2431 return MISCREG_ICC_CTLR_EL1
;
2433 return MISCREG_ICC_SRE_EL1
;
2435 return MISCREG_ICC_IGRPEN0_EL1
;
2437 return MISCREG_ICC_IGRPEN1_EL1
;
2447 return MISCREG_VBAR_EL2
;
2449 return MISCREG_RVBAR_EL2
;
2455 return MISCREG_VDISR_EL2
;
2461 return MISCREG_ICH_AP0R0_EL2
;
2463 return MISCREG_ICH_AP0R1_EL2
;
2465 return MISCREG_ICH_AP0R2_EL2
;
2467 return MISCREG_ICH_AP0R3_EL2
;
2473 return MISCREG_ICH_AP1R0_EL2
;
2475 return MISCREG_ICH_AP1R1_EL2
;
2477 return MISCREG_ICH_AP1R2_EL2
;
2479 return MISCREG_ICH_AP1R3_EL2
;
2481 return MISCREG_ICC_SRE_EL2
;
2487 return MISCREG_ICH_HCR_EL2
;
2489 return MISCREG_ICH_VTR_EL2
;
2491 return MISCREG_ICH_MISR_EL2
;
2493 return MISCREG_ICH_EISR_EL2
;
2495 return MISCREG_ICH_ELRSR_EL2
;
2497 return MISCREG_ICH_VMCR_EL2
;
2503 return MISCREG_ICH_LR0_EL2
;
2505 return MISCREG_ICH_LR1_EL2
;
2507 return MISCREG_ICH_LR2_EL2
;
2509 return MISCREG_ICH_LR3_EL2
;
2511 return MISCREG_ICH_LR4_EL2
;
2513 return MISCREG_ICH_LR5_EL2
;
2515 return MISCREG_ICH_LR6_EL2
;
2517 return MISCREG_ICH_LR7_EL2
;
2523 return MISCREG_ICH_LR8_EL2
;
2525 return MISCREG_ICH_LR9_EL2
;
2527 return MISCREG_ICH_LR10_EL2
;
2529 return MISCREG_ICH_LR11_EL2
;
2531 return MISCREG_ICH_LR12_EL2
;
2533 return MISCREG_ICH_LR13_EL2
;
2535 return MISCREG_ICH_LR14_EL2
;
2537 return MISCREG_ICH_LR15_EL2
;
2547 return MISCREG_VBAR_EL3
;
2549 return MISCREG_RVBAR_EL3
;
2551 return MISCREG_RMR_EL3
;
2557 return MISCREG_ICC_CTLR_EL3
;
2559 return MISCREG_ICC_SRE_EL3
;
2561 return MISCREG_ICC_IGRPEN1_EL3
;
2575 return MISCREG_CONTEXTIDR_EL1
;
2577 return MISCREG_TPIDR_EL1
;
2587 return MISCREG_TPIDR_EL0
;
2589 return MISCREG_TPIDRRO_EL0
;
2599 return MISCREG_CONTEXTIDR_EL2
;
2601 return MISCREG_TPIDR_EL2
;
2611 return MISCREG_TPIDR_EL3
;
2625 return MISCREG_CNTKCTL_EL1
;
2635 return MISCREG_CNTFRQ_EL0
;
2637 return MISCREG_CNTPCT_EL0
;
2639 return MISCREG_CNTVCT_EL0
;
2645 return MISCREG_CNTP_TVAL_EL0
;
2647 return MISCREG_CNTP_CTL_EL0
;
2649 return MISCREG_CNTP_CVAL_EL0
;
2655 return MISCREG_CNTV_TVAL_EL0
;
2657 return MISCREG_CNTV_CTL_EL0
;
2659 return MISCREG_CNTV_CVAL_EL0
;
2665 return MISCREG_PMEVCNTR0_EL0
;
2667 return MISCREG_PMEVCNTR1_EL0
;
2669 return MISCREG_PMEVCNTR2_EL0
;
2671 return MISCREG_PMEVCNTR3_EL0
;
2673 return MISCREG_PMEVCNTR4_EL0
;
2675 return MISCREG_PMEVCNTR5_EL0
;
2681 return MISCREG_PMEVTYPER0_EL0
;
2683 return MISCREG_PMEVTYPER1_EL0
;
2685 return MISCREG_PMEVTYPER2_EL0
;
2687 return MISCREG_PMEVTYPER3_EL0
;
2689 return MISCREG_PMEVTYPER4_EL0
;
2691 return MISCREG_PMEVTYPER5_EL0
;
2697 return MISCREG_PMCCFILTR_EL0
;
2706 return MISCREG_CNTVOFF_EL2
;
2712 return MISCREG_CNTHCTL_EL2
;
2718 return MISCREG_CNTHP_TVAL_EL2
;
2720 return MISCREG_CNTHP_CTL_EL2
;
2722 return MISCREG_CNTHP_CVAL_EL2
;
2728 return MISCREG_CNTHV_TVAL_EL2
;
2730 return MISCREG_CNTHV_CTL_EL2
;
2732 return MISCREG_CNTHV_CVAL_EL2
;
2742 return MISCREG_CNTPS_TVAL_EL1
;
2744 return MISCREG_CNTPS_CTL_EL1
;
2746 return MISCREG_CNTPS_CVAL_EL1
;
2760 return MISCREG_IL1DATA0_EL1
;
2762 return MISCREG_IL1DATA1_EL1
;
2764 return MISCREG_IL1DATA2_EL1
;
2766 return MISCREG_IL1DATA3_EL1
;
2772 return MISCREG_DL1DATA0_EL1
;
2774 return MISCREG_DL1DATA1_EL1
;
2776 return MISCREG_DL1DATA2_EL1
;
2778 return MISCREG_DL1DATA3_EL1
;
2780 return MISCREG_DL1DATA4_EL1
;
2790 return MISCREG_L2ACTLR_EL1
;
2796 return MISCREG_CPUACTLR_EL1
;
2798 return MISCREG_CPUECTLR_EL1
;
2800 return MISCREG_CPUMERRSR_EL1
;
2802 return MISCREG_L2MERRSR_EL1
;
2808 return MISCREG_CBAR_EL1
;
2815 // S3_<op1>_15_<Cm>_<op2>
2816 return MISCREG_IMPDEF_UNIMPL
;
2821 return MISCREG_UNKNOWN
;
2824 bitset
<NUM_MISCREG_INFOS
> miscRegInfo
[NUM_MISCREGS
]; // initialized below
2827 ISA::initializeMiscRegMetadata()
2829 // the MiscReg metadata tables are shared across all instances of the
2830 // ISA object, so there's no need to initialize them multiple times.
2831 static bool completed
= false;
2835 // This boolean variable specifies if the system is running in aarch32 at
2836 // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
2837 // is running in aarch64 (aarch32EL3 = false)
2838 bool aarch32EL3
= haveSecurity
&& !highestELIs64
;
2840 // Set Privileged Access Never on taking an exception to EL1 (Arm 8.1+),
2844 // Implicit error synchronization event enable (Arm 8.2+), unsupported
2847 // Load Multiple and Store Multiple Atomicity and Ordering (Arm 8.2+),
2849 bool LSMAOE
= false;
2851 // No Trap Load Multiple and Store Multiple (Arm 8.2+), unsupported
2852 bool nTLSMD
= false;
2854 // Pointer authentication (Arm 8.3+), unsupported
2855 bool EnDA
= false; // using APDAKey_EL1 key of instr addrs in ELs 0,1
2856 bool EnDB
= false; // using APDBKey_EL1 key of instr addrs in ELs 0,1
2857 bool EnIA
= false; // using APIAKey_EL1 key of instr addrs in ELs 0,1
2858 bool EnIB
= false; // using APIBKey_EL1 key of instr addrs in ELs 0,1
2861 * Some registers alias with others, and therefore need to be translated.
2862 * When two mapping registers are given, they are the 32b lower and
2863 * upper halves, respectively, of the 64b register being mapped.
2864 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
2866 * NAM = "not architecturally mandated",
2867 * from ARM DDI 0487A.i, template text
2868 * "AArch64 System register ___ can be mapped to
2869 * AArch32 System register ___, but this is not
2870 * architecturally mandated."
2873 InitReg(MISCREG_CPSR
)
2875 InitReg(MISCREG_SPSR
)
2877 InitReg(MISCREG_SPSR_FIQ
)
2879 InitReg(MISCREG_SPSR_IRQ
)
2881 InitReg(MISCREG_SPSR_SVC
)
2883 InitReg(MISCREG_SPSR_MON
)
2885 InitReg(MISCREG_SPSR_ABT
)
2887 InitReg(MISCREG_SPSR_HYP
)
2889 InitReg(MISCREG_SPSR_UND
)
2891 InitReg(MISCREG_ELR_HYP
)
2893 InitReg(MISCREG_FPSID
)
2895 InitReg(MISCREG_FPSCR
)
2897 InitReg(MISCREG_MVFR1
)
2899 InitReg(MISCREG_MVFR0
)
2901 InitReg(MISCREG_FPEXC
)
2905 InitReg(MISCREG_CPSR_MODE
)
2907 InitReg(MISCREG_CPSR_Q
)
2909 InitReg(MISCREG_FPSCR_EXC
)
2911 InitReg(MISCREG_FPSCR_QC
)
2913 InitReg(MISCREG_LOCKADDR
)
2915 InitReg(MISCREG_LOCKFLAG
)
2917 InitReg(MISCREG_PRRR_MAIR0
)
2920 InitReg(MISCREG_PRRR_MAIR0_NS
)
2922 .privSecure(!aarch32EL3
)
2924 InitReg(MISCREG_PRRR_MAIR0_S
)
2927 InitReg(MISCREG_NMRR_MAIR1
)
2930 InitReg(MISCREG_NMRR_MAIR1_NS
)
2932 .privSecure(!aarch32EL3
)
2934 InitReg(MISCREG_NMRR_MAIR1_S
)
2937 InitReg(MISCREG_PMXEVTYPER_PMCCFILTR
)
2939 InitReg(MISCREG_SCTLR_RST
)
2941 InitReg(MISCREG_SEV_MAILBOX
)
2944 // AArch32 CP14 registers
2945 InitReg(MISCREG_DBGDIDR
)
2946 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2947 InitReg(MISCREG_DBGDSCRint
)
2948 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2949 InitReg(MISCREG_DBGDCCINT
)
2952 InitReg(MISCREG_DBGDTRTXint
)
2955 InitReg(MISCREG_DBGDTRRXint
)
2958 InitReg(MISCREG_DBGWFAR
)
2961 InitReg(MISCREG_DBGVCR
)
2964 InitReg(MISCREG_DBGDTRRXext
)
2967 InitReg(MISCREG_DBGDSCRext
)
2971 InitReg(MISCREG_DBGDTRTXext
)
2974 InitReg(MISCREG_DBGOSECCR
)
2977 InitReg(MISCREG_DBGBVR0
)
2980 InitReg(MISCREG_DBGBVR1
)
2983 InitReg(MISCREG_DBGBVR2
)
2986 InitReg(MISCREG_DBGBVR3
)
2989 InitReg(MISCREG_DBGBVR4
)
2992 InitReg(MISCREG_DBGBVR5
)
2995 InitReg(MISCREG_DBGBCR0
)
2998 InitReg(MISCREG_DBGBCR1
)
3001 InitReg(MISCREG_DBGBCR2
)
3004 InitReg(MISCREG_DBGBCR3
)
3007 InitReg(MISCREG_DBGBCR4
)
3010 InitReg(MISCREG_DBGBCR5
)
3013 InitReg(MISCREG_DBGWVR0
)
3016 InitReg(MISCREG_DBGWVR1
)
3019 InitReg(MISCREG_DBGWVR2
)
3022 InitReg(MISCREG_DBGWVR3
)
3025 InitReg(MISCREG_DBGWCR0
)
3028 InitReg(MISCREG_DBGWCR1
)
3031 InitReg(MISCREG_DBGWCR2
)
3034 InitReg(MISCREG_DBGWCR3
)
3037 InitReg(MISCREG_DBGDRAR
)
3039 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3040 InitReg(MISCREG_DBGBXVR4
)
3043 InitReg(MISCREG_DBGBXVR5
)
3046 InitReg(MISCREG_DBGOSLAR
)
3048 .allPrivileges().monSecureRead(0).monNonSecureRead(0);
3049 InitReg(MISCREG_DBGOSLSR
)
3051 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3052 InitReg(MISCREG_DBGOSDLR
)
3055 InitReg(MISCREG_DBGPRCR
)
3058 InitReg(MISCREG_DBGDSAR
)
3060 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3061 InitReg(MISCREG_DBGCLAIMSET
)
3064 InitReg(MISCREG_DBGCLAIMCLR
)
3067 InitReg(MISCREG_DBGAUTHSTATUS
)
3069 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3070 InitReg(MISCREG_DBGDEVID2
)
3072 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3073 InitReg(MISCREG_DBGDEVID1
)
3075 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3076 InitReg(MISCREG_DBGDEVID0
)
3078 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3079 InitReg(MISCREG_TEECR
)
3082 InitReg(MISCREG_JIDR
)
3084 InitReg(MISCREG_TEEHBR
)
3086 InitReg(MISCREG_JOSCR
)
3088 InitReg(MISCREG_JMCR
)
3091 // AArch32 CP15 registers
3092 InitReg(MISCREG_MIDR
)
3093 .allPrivileges().exceptUserMode().writes(0);
3094 InitReg(MISCREG_CTR
)
3095 .allPrivileges().exceptUserMode().writes(0);
3096 InitReg(MISCREG_TCMTR
)
3097 .allPrivileges().exceptUserMode().writes(0);
3098 InitReg(MISCREG_TLBTR
)
3099 .allPrivileges().exceptUserMode().writes(0);
3100 InitReg(MISCREG_MPIDR
)
3101 .allPrivileges().exceptUserMode().writes(0);
3102 InitReg(MISCREG_REVIDR
)
3105 .allPrivileges().exceptUserMode().writes(0);
3106 InitReg(MISCREG_ID_PFR0
)
3107 .allPrivileges().exceptUserMode().writes(0);
3108 InitReg(MISCREG_ID_PFR1
)
3109 .allPrivileges().exceptUserMode().writes(0);
3110 InitReg(MISCREG_ID_DFR0
)
3111 .allPrivileges().exceptUserMode().writes(0);
3112 InitReg(MISCREG_ID_AFR0
)
3113 .allPrivileges().exceptUserMode().writes(0);
3114 InitReg(MISCREG_ID_MMFR0
)
3115 .allPrivileges().exceptUserMode().writes(0);
3116 InitReg(MISCREG_ID_MMFR1
)
3117 .allPrivileges().exceptUserMode().writes(0);
3118 InitReg(MISCREG_ID_MMFR2
)
3119 .allPrivileges().exceptUserMode().writes(0);
3120 InitReg(MISCREG_ID_MMFR3
)
3121 .allPrivileges().exceptUserMode().writes(0);
3122 InitReg(MISCREG_ID_ISAR0
)
3123 .allPrivileges().exceptUserMode().writes(0);
3124 InitReg(MISCREG_ID_ISAR1
)
3125 .allPrivileges().exceptUserMode().writes(0);
3126 InitReg(MISCREG_ID_ISAR2
)
3127 .allPrivileges().exceptUserMode().writes(0);
3128 InitReg(MISCREG_ID_ISAR3
)
3129 .allPrivileges().exceptUserMode().writes(0);
3130 InitReg(MISCREG_ID_ISAR4
)
3131 .allPrivileges().exceptUserMode().writes(0);
3132 InitReg(MISCREG_ID_ISAR5
)
3133 .allPrivileges().exceptUserMode().writes(0);
3134 InitReg(MISCREG_CCSIDR
)
3135 .allPrivileges().exceptUserMode().writes(0);
3136 InitReg(MISCREG_CLIDR
)
3137 .allPrivileges().exceptUserMode().writes(0);
3138 InitReg(MISCREG_AIDR
)
3139 .allPrivileges().exceptUserMode().writes(0);
3140 InitReg(MISCREG_CSSELR
)
3142 InitReg(MISCREG_CSSELR_NS
)
3144 .privSecure(!aarch32EL3
)
3145 .nonSecure().exceptUserMode();
3146 InitReg(MISCREG_CSSELR_S
)
3148 .secure().exceptUserMode();
3149 InitReg(MISCREG_VPIDR
)
3150 .hyp().monNonSecure();
3151 InitReg(MISCREG_VMPIDR
)
3152 .hyp().monNonSecure();
3153 InitReg(MISCREG_SCTLR
)
3155 // readMiscRegNoEffect() uses this metadata
3156 // despite using children (below) as backing store
3158 .res1(0x00400800 | (SPAN
? 0 : 0x800000)
3159 | (LSMAOE
? 0 : 0x10)
3160 | (nTLSMD
? 0 : 0x8));
3161 InitReg(MISCREG_SCTLR_NS
)
3163 .privSecure(!aarch32EL3
)
3164 .nonSecure().exceptUserMode();
3165 InitReg(MISCREG_SCTLR_S
)
3167 .secure().exceptUserMode();
3168 InitReg(MISCREG_ACTLR
)
3170 InitReg(MISCREG_ACTLR_NS
)
3172 .privSecure(!aarch32EL3
)
3173 .nonSecure().exceptUserMode();
3174 InitReg(MISCREG_ACTLR_S
)
3176 .secure().exceptUserMode();
3177 InitReg(MISCREG_CPACR
)
3178 .allPrivileges().exceptUserMode();
3179 InitReg(MISCREG_SCR
)
3180 .mon().secure().exceptUserMode()
3181 .res0(0xff40) // [31:16], [6]
3182 .res1(0x0030); // [5:4]
3183 InitReg(MISCREG_SDER
)
3185 InitReg(MISCREG_NSACR
)
3186 .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
3187 InitReg(MISCREG_HSCTLR
)
3188 .hyp().monNonSecure()
3189 .res0(0x0512c7c0 | (EnDB
? 0 : 0x2000)
3190 | (IESB
? 0 : 0x200000)
3191 | (EnDA
? 0 : 0x8000000)
3192 | (EnIB
? 0 : 0x40000000)
3193 | (EnIA
? 0 : 0x80000000))
3195 InitReg(MISCREG_HACTLR
)
3196 .hyp().monNonSecure();
3197 InitReg(MISCREG_HCR
)
3198 .hyp().monNonSecure();
3199 InitReg(MISCREG_HDCR
)
3200 .hyp().monNonSecure();
3201 InitReg(MISCREG_HCPTR
)
3202 .hyp().monNonSecure();
3203 InitReg(MISCREG_HSTR
)
3204 .hyp().monNonSecure();
3205 InitReg(MISCREG_HACR
)
3208 .hyp().monNonSecure();
3209 InitReg(MISCREG_TTBR0
)
3211 InitReg(MISCREG_TTBR0_NS
)
3213 .privSecure(!aarch32EL3
)
3214 .nonSecure().exceptUserMode();
3215 InitReg(MISCREG_TTBR0_S
)
3217 .secure().exceptUserMode();
3218 InitReg(MISCREG_TTBR1
)
3220 InitReg(MISCREG_TTBR1_NS
)
3222 .privSecure(!aarch32EL3
)
3223 .nonSecure().exceptUserMode();
3224 InitReg(MISCREG_TTBR1_S
)
3226 .secure().exceptUserMode();
3227 InitReg(MISCREG_TTBCR
)
3229 InitReg(MISCREG_TTBCR_NS
)
3231 .privSecure(!aarch32EL3
)
3232 .nonSecure().exceptUserMode();
3233 InitReg(MISCREG_TTBCR_S
)
3235 .secure().exceptUserMode();
3236 InitReg(MISCREG_HTCR
)
3237 .hyp().monNonSecure();
3238 InitReg(MISCREG_VTCR
)
3239 .hyp().monNonSecure();
3240 InitReg(MISCREG_DACR
)
3242 InitReg(MISCREG_DACR_NS
)
3244 .privSecure(!aarch32EL3
)
3245 .nonSecure().exceptUserMode();
3246 InitReg(MISCREG_DACR_S
)
3248 .secure().exceptUserMode();
3249 InitReg(MISCREG_DFSR
)
3251 InitReg(MISCREG_DFSR_NS
)
3253 .privSecure(!aarch32EL3
)
3254 .nonSecure().exceptUserMode();
3255 InitReg(MISCREG_DFSR_S
)
3257 .secure().exceptUserMode();
3258 InitReg(MISCREG_IFSR
)
3260 InitReg(MISCREG_IFSR_NS
)
3262 .privSecure(!aarch32EL3
)
3263 .nonSecure().exceptUserMode();
3264 InitReg(MISCREG_IFSR_S
)
3266 .secure().exceptUserMode();
3267 InitReg(MISCREG_ADFSR
)
3271 InitReg(MISCREG_ADFSR_NS
)
3275 .privSecure(!aarch32EL3
)
3276 .nonSecure().exceptUserMode();
3277 InitReg(MISCREG_ADFSR_S
)
3281 .secure().exceptUserMode();
3282 InitReg(MISCREG_AIFSR
)
3286 InitReg(MISCREG_AIFSR_NS
)
3290 .privSecure(!aarch32EL3
)
3291 .nonSecure().exceptUserMode();
3292 InitReg(MISCREG_AIFSR_S
)
3296 .secure().exceptUserMode();
3297 InitReg(MISCREG_HADFSR
)
3298 .hyp().monNonSecure();
3299 InitReg(MISCREG_HAIFSR
)
3300 .hyp().monNonSecure();
3301 InitReg(MISCREG_HSR
)
3302 .hyp().monNonSecure();
3303 InitReg(MISCREG_DFAR
)
3305 InitReg(MISCREG_DFAR_NS
)
3307 .privSecure(!aarch32EL3
)
3308 .nonSecure().exceptUserMode();
3309 InitReg(MISCREG_DFAR_S
)
3311 .secure().exceptUserMode();
3312 InitReg(MISCREG_IFAR
)
3314 InitReg(MISCREG_IFAR_NS
)
3316 .privSecure(!aarch32EL3
)
3317 .nonSecure().exceptUserMode();
3318 InitReg(MISCREG_IFAR_S
)
3320 .secure().exceptUserMode();
3321 InitReg(MISCREG_HDFAR
)
3322 .hyp().monNonSecure();
3323 InitReg(MISCREG_HIFAR
)
3324 .hyp().monNonSecure();
3325 InitReg(MISCREG_HPFAR
)
3326 .hyp().monNonSecure();
3327 InitReg(MISCREG_ICIALLUIS
)
3330 .writes(1).exceptUserMode();
3331 InitReg(MISCREG_BPIALLIS
)
3334 .writes(1).exceptUserMode();
3335 InitReg(MISCREG_PAR
)
3337 InitReg(MISCREG_PAR_NS
)
3339 .privSecure(!aarch32EL3
)
3340 .nonSecure().exceptUserMode();
3341 InitReg(MISCREG_PAR_S
)
3343 .secure().exceptUserMode();
3344 InitReg(MISCREG_ICIALLU
)
3345 .writes(1).exceptUserMode();
3346 InitReg(MISCREG_ICIMVAU
)
3349 .writes(1).exceptUserMode();
3350 InitReg(MISCREG_CP15ISB
)
3352 InitReg(MISCREG_BPIALL
)
3355 .writes(1).exceptUserMode();
3356 InitReg(MISCREG_BPIMVA
)
3359 .writes(1).exceptUserMode();
3360 InitReg(MISCREG_DCIMVAC
)
3363 .writes(1).exceptUserMode();
3364 InitReg(MISCREG_DCISW
)
3367 .writes(1).exceptUserMode();
3368 InitReg(MISCREG_ATS1CPR
)
3369 .writes(1).exceptUserMode();
3370 InitReg(MISCREG_ATS1CPW
)
3371 .writes(1).exceptUserMode();
3372 InitReg(MISCREG_ATS1CUR
)
3373 .writes(1).exceptUserMode();
3374 InitReg(MISCREG_ATS1CUW
)
3375 .writes(1).exceptUserMode();
3376 InitReg(MISCREG_ATS12NSOPR
)
3377 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3378 InitReg(MISCREG_ATS12NSOPW
)
3379 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3380 InitReg(MISCREG_ATS12NSOUR
)
3381 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3382 InitReg(MISCREG_ATS12NSOUW
)
3383 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3384 InitReg(MISCREG_DCCMVAC
)
3385 .writes(1).exceptUserMode();
3386 InitReg(MISCREG_DCCSW
)
3389 .writes(1).exceptUserMode();
3390 InitReg(MISCREG_CP15DSB
)
3392 InitReg(MISCREG_CP15DMB
)
3394 InitReg(MISCREG_DCCMVAU
)
3397 .writes(1).exceptUserMode();
3398 InitReg(MISCREG_DCCIMVAC
)
3401 .writes(1).exceptUserMode();
3402 InitReg(MISCREG_DCCISW
)
3405 .writes(1).exceptUserMode();
3406 InitReg(MISCREG_ATS1HR
)
3407 .monNonSecureWrite().hypWrite();
3408 InitReg(MISCREG_ATS1HW
)
3409 .monNonSecureWrite().hypWrite();
3410 InitReg(MISCREG_TLBIALLIS
)
3411 .writes(1).exceptUserMode();
3412 InitReg(MISCREG_TLBIMVAIS
)
3413 .writes(1).exceptUserMode();
3414 InitReg(MISCREG_TLBIASIDIS
)
3415 .writes(1).exceptUserMode();
3416 InitReg(MISCREG_TLBIMVAAIS
)
3417 .writes(1).exceptUserMode();
3418 InitReg(MISCREG_TLBIMVALIS
)
3419 .writes(1).exceptUserMode();
3420 InitReg(MISCREG_TLBIMVAALIS
)
3421 .writes(1).exceptUserMode();
3422 InitReg(MISCREG_ITLBIALL
)
3423 .writes(1).exceptUserMode();
3424 InitReg(MISCREG_ITLBIMVA
)
3425 .writes(1).exceptUserMode();
3426 InitReg(MISCREG_ITLBIASID
)
3427 .writes(1).exceptUserMode();
3428 InitReg(MISCREG_DTLBIALL
)
3429 .writes(1).exceptUserMode();
3430 InitReg(MISCREG_DTLBIMVA
)
3431 .writes(1).exceptUserMode();
3432 InitReg(MISCREG_DTLBIASID
)
3433 .writes(1).exceptUserMode();
3434 InitReg(MISCREG_TLBIALL
)
3435 .writes(1).exceptUserMode();
3436 InitReg(MISCREG_TLBIMVA
)
3437 .writes(1).exceptUserMode();
3438 InitReg(MISCREG_TLBIASID
)
3439 .writes(1).exceptUserMode();
3440 InitReg(MISCREG_TLBIMVAA
)
3441 .writes(1).exceptUserMode();
3442 InitReg(MISCREG_TLBIMVAL
)
3443 .writes(1).exceptUserMode();
3444 InitReg(MISCREG_TLBIMVAAL
)
3445 .writes(1).exceptUserMode();
3446 InitReg(MISCREG_TLBIIPAS2IS
)
3447 .monNonSecureWrite().hypWrite();
3448 InitReg(MISCREG_TLBIIPAS2LIS
)
3449 .monNonSecureWrite().hypWrite();
3450 InitReg(MISCREG_TLBIALLHIS
)
3451 .monNonSecureWrite().hypWrite();
3452 InitReg(MISCREG_TLBIMVAHIS
)
3453 .monNonSecureWrite().hypWrite();
3454 InitReg(MISCREG_TLBIALLNSNHIS
)
3455 .monNonSecureWrite().hypWrite();
3456 InitReg(MISCREG_TLBIMVALHIS
)
3457 .monNonSecureWrite().hypWrite();
3458 InitReg(MISCREG_TLBIIPAS2
)
3459 .monNonSecureWrite().hypWrite();
3460 InitReg(MISCREG_TLBIIPAS2L
)
3461 .monNonSecureWrite().hypWrite();
3462 InitReg(MISCREG_TLBIALLH
)
3463 .monNonSecureWrite().hypWrite();
3464 InitReg(MISCREG_TLBIMVAH
)
3465 .monNonSecureWrite().hypWrite();
3466 InitReg(MISCREG_TLBIALLNSNH
)
3467 .monNonSecureWrite().hypWrite();
3468 InitReg(MISCREG_TLBIMVALH
)
3469 .monNonSecureWrite().hypWrite();
3470 InitReg(MISCREG_PMCR
)
3472 InitReg(MISCREG_PMCNTENSET
)
3474 InitReg(MISCREG_PMCNTENCLR
)
3476 InitReg(MISCREG_PMOVSR
)
3478 InitReg(MISCREG_PMSWINC
)
3480 InitReg(MISCREG_PMSELR
)
3482 InitReg(MISCREG_PMCEID0
)
3484 InitReg(MISCREG_PMCEID1
)
3486 InitReg(MISCREG_PMCCNTR
)
3488 InitReg(MISCREG_PMXEVTYPER
)
3490 InitReg(MISCREG_PMCCFILTR
)
3492 InitReg(MISCREG_PMXEVCNTR
)
3494 InitReg(MISCREG_PMUSERENR
)
3495 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
3496 InitReg(MISCREG_PMINTENSET
)
3497 .allPrivileges().exceptUserMode();
3498 InitReg(MISCREG_PMINTENCLR
)
3499 .allPrivileges().exceptUserMode();
3500 InitReg(MISCREG_PMOVSSET
)
3503 InitReg(MISCREG_L2CTLR
)
3504 .allPrivileges().exceptUserMode();
3505 InitReg(MISCREG_L2ECTLR
)
3507 .allPrivileges().exceptUserMode();
3508 InitReg(MISCREG_PRRR
)
3510 InitReg(MISCREG_PRRR_NS
)
3512 .privSecure(!aarch32EL3
)
3513 .nonSecure().exceptUserMode();
3514 InitReg(MISCREG_PRRR_S
)
3516 .secure().exceptUserMode();
3517 InitReg(MISCREG_MAIR0
)
3519 InitReg(MISCREG_MAIR0_NS
)
3521 .privSecure(!aarch32EL3
)
3522 .nonSecure().exceptUserMode();
3523 InitReg(MISCREG_MAIR0_S
)
3525 .secure().exceptUserMode();
3526 InitReg(MISCREG_NMRR
)
3528 InitReg(MISCREG_NMRR_NS
)
3530 .privSecure(!aarch32EL3
)
3531 .nonSecure().exceptUserMode();
3532 InitReg(MISCREG_NMRR_S
)
3534 .secure().exceptUserMode();
3535 InitReg(MISCREG_MAIR1
)
3537 InitReg(MISCREG_MAIR1_NS
)
3539 .privSecure(!aarch32EL3
)
3540 .nonSecure().exceptUserMode();
3541 InitReg(MISCREG_MAIR1_S
)
3543 .secure().exceptUserMode();
3544 InitReg(MISCREG_AMAIR0
)
3546 InitReg(MISCREG_AMAIR0_NS
)
3548 .privSecure(!aarch32EL3
)
3549 .nonSecure().exceptUserMode();
3550 InitReg(MISCREG_AMAIR0_S
)
3552 .secure().exceptUserMode();
3553 InitReg(MISCREG_AMAIR1
)
3555 InitReg(MISCREG_AMAIR1_NS
)
3557 .privSecure(!aarch32EL3
)
3558 .nonSecure().exceptUserMode();
3559 InitReg(MISCREG_AMAIR1_S
)
3561 .secure().exceptUserMode();
3562 InitReg(MISCREG_HMAIR0
)
3563 .hyp().monNonSecure();
3564 InitReg(MISCREG_HMAIR1
)
3565 .hyp().monNonSecure();
3566 InitReg(MISCREG_HAMAIR0
)
3569 .hyp().monNonSecure();
3570 InitReg(MISCREG_HAMAIR1
)
3573 .hyp().monNonSecure();
3574 InitReg(MISCREG_VBAR
)
3576 InitReg(MISCREG_VBAR_NS
)
3578 .privSecure(!aarch32EL3
)
3579 .nonSecure().exceptUserMode();
3580 InitReg(MISCREG_VBAR_S
)
3582 .secure().exceptUserMode();
3583 InitReg(MISCREG_MVBAR
)
3585 .hypRead(FullSystem
&& system
->highestEL() == EL2
)
3586 .privRead(FullSystem
&& system
->highestEL() == EL1
)
3588 InitReg(MISCREG_RMR
)
3590 .mon().secure().exceptUserMode();
3591 InitReg(MISCREG_ISR
)
3592 .allPrivileges().exceptUserMode().writes(0);
3593 InitReg(MISCREG_HVBAR
)
3594 .hyp().monNonSecure()
3596 InitReg(MISCREG_FCSEIDR
)
3599 .allPrivileges().exceptUserMode();
3600 InitReg(MISCREG_CONTEXTIDR
)
3602 InitReg(MISCREG_CONTEXTIDR_NS
)
3604 .privSecure(!aarch32EL3
)
3605 .nonSecure().exceptUserMode();
3606 InitReg(MISCREG_CONTEXTIDR_S
)
3608 .secure().exceptUserMode();
3609 InitReg(MISCREG_TPIDRURW
)
3611 InitReg(MISCREG_TPIDRURW_NS
)
3614 .privSecure(!aarch32EL3
)
3616 InitReg(MISCREG_TPIDRURW_S
)
3619 InitReg(MISCREG_TPIDRURO
)
3621 InitReg(MISCREG_TPIDRURO_NS
)
3624 .userNonSecureWrite(0).userSecureRead(1)
3625 .privSecure(!aarch32EL3
)
3627 InitReg(MISCREG_TPIDRURO_S
)
3629 .secure().userSecureWrite(0);
3630 InitReg(MISCREG_TPIDRPRW
)
3632 InitReg(MISCREG_TPIDRPRW_NS
)
3634 .nonSecure().exceptUserMode()
3635 .privSecure(!aarch32EL3
);
3636 InitReg(MISCREG_TPIDRPRW_S
)
3638 .secure().exceptUserMode();
3639 InitReg(MISCREG_HTPIDR
)
3640 .hyp().monNonSecure();
3641 InitReg(MISCREG_CNTFRQ
)
3644 InitReg(MISCREG_CNTKCTL
)
3645 .allPrivileges().exceptUserMode();
3646 InitReg(MISCREG_CNTP_TVAL
)
3648 InitReg(MISCREG_CNTP_TVAL_NS
)
3651 .privSecure(!aarch32EL3
)
3653 InitReg(MISCREG_CNTP_TVAL_S
)
3656 InitReg(MISCREG_CNTP_CTL
)
3658 InitReg(MISCREG_CNTP_CTL_NS
)
3661 .privSecure(!aarch32EL3
)
3663 InitReg(MISCREG_CNTP_CTL_S
)
3666 InitReg(MISCREG_CNTV_TVAL
)
3668 InitReg(MISCREG_CNTV_CTL
)
3670 InitReg(MISCREG_CNTHCTL
)
3671 .hypWrite().monNonSecureRead();
3672 InitReg(MISCREG_CNTHP_TVAL
)
3673 .hypWrite().monNonSecureRead();
3674 InitReg(MISCREG_CNTHP_CTL
)
3675 .hypWrite().monNonSecureRead();
3676 InitReg(MISCREG_IL1DATA0
)
3678 .allPrivileges().exceptUserMode();
3679 InitReg(MISCREG_IL1DATA1
)
3681 .allPrivileges().exceptUserMode();
3682 InitReg(MISCREG_IL1DATA2
)
3684 .allPrivileges().exceptUserMode();
3685 InitReg(MISCREG_IL1DATA3
)
3687 .allPrivileges().exceptUserMode();
3688 InitReg(MISCREG_DL1DATA0
)
3690 .allPrivileges().exceptUserMode();
3691 InitReg(MISCREG_DL1DATA1
)
3693 .allPrivileges().exceptUserMode();
3694 InitReg(MISCREG_DL1DATA2
)
3696 .allPrivileges().exceptUserMode();
3697 InitReg(MISCREG_DL1DATA3
)
3699 .allPrivileges().exceptUserMode();
3700 InitReg(MISCREG_DL1DATA4
)
3702 .allPrivileges().exceptUserMode();
3703 InitReg(MISCREG_RAMINDEX
)
3705 .writes(1).exceptUserMode();
3706 InitReg(MISCREG_L2ACTLR
)
3708 .allPrivileges().exceptUserMode();
3709 InitReg(MISCREG_CBAR
)
3711 .allPrivileges().exceptUserMode().writes(0);
3712 InitReg(MISCREG_HTTBR
)
3713 .hyp().monNonSecure();
3714 InitReg(MISCREG_VTTBR
)
3715 .hyp().monNonSecure();
3716 InitReg(MISCREG_CNTPCT
)
3718 InitReg(MISCREG_CNTVCT
)
3721 InitReg(MISCREG_CNTP_CVAL
)
3723 InitReg(MISCREG_CNTP_CVAL_NS
)
3726 .privSecure(!aarch32EL3
)
3728 InitReg(MISCREG_CNTP_CVAL_S
)
3731 InitReg(MISCREG_CNTV_CVAL
)
3733 InitReg(MISCREG_CNTVOFF
)
3734 .hyp().monNonSecure();
3735 InitReg(MISCREG_CNTHP_CVAL
)
3736 .hypWrite().monNonSecureRead();
3737 InitReg(MISCREG_CPUMERRSR
)
3739 .allPrivileges().exceptUserMode();
3740 InitReg(MISCREG_L2MERRSR
)
3743 .allPrivileges().exceptUserMode();
3745 // AArch64 registers (Op0=2);
3746 InitReg(MISCREG_MDCCINT_EL1
)
3748 InitReg(MISCREG_OSDTRRX_EL1
)
3750 .mapsTo(MISCREG_DBGDTRRXext
);
3751 InitReg(MISCREG_MDSCR_EL1
)
3753 .mapsTo(MISCREG_DBGDSCRext
);
3754 InitReg(MISCREG_OSDTRTX_EL1
)
3756 .mapsTo(MISCREG_DBGDTRTXext
);
3757 InitReg(MISCREG_OSECCR_EL1
)
3759 .mapsTo(MISCREG_DBGOSECCR
);
3760 InitReg(MISCREG_DBGBVR0_EL1
)
3762 .mapsTo(MISCREG_DBGBVR0
/*, MISCREG_DBGBXVR0 */);
3763 InitReg(MISCREG_DBGBVR1_EL1
)
3765 .mapsTo(MISCREG_DBGBVR1
/*, MISCREG_DBGBXVR1 */);
3766 InitReg(MISCREG_DBGBVR2_EL1
)
3768 .mapsTo(MISCREG_DBGBVR2
/*, MISCREG_DBGBXVR2 */);
3769 InitReg(MISCREG_DBGBVR3_EL1
)
3771 .mapsTo(MISCREG_DBGBVR3
/*, MISCREG_DBGBXVR3 */);
3772 InitReg(MISCREG_DBGBVR4_EL1
)
3774 .mapsTo(MISCREG_DBGBVR4
/*, MISCREG_DBGBXVR4 */);
3775 InitReg(MISCREG_DBGBVR5_EL1
)
3777 .mapsTo(MISCREG_DBGBVR5
/*, MISCREG_DBGBXVR5 */);
3778 InitReg(MISCREG_DBGBCR0_EL1
)
3780 .mapsTo(MISCREG_DBGBCR0
);
3781 InitReg(MISCREG_DBGBCR1_EL1
)
3783 .mapsTo(MISCREG_DBGBCR1
);
3784 InitReg(MISCREG_DBGBCR2_EL1
)
3786 .mapsTo(MISCREG_DBGBCR2
);
3787 InitReg(MISCREG_DBGBCR3_EL1
)
3789 .mapsTo(MISCREG_DBGBCR3
);
3790 InitReg(MISCREG_DBGBCR4_EL1
)
3792 .mapsTo(MISCREG_DBGBCR4
);
3793 InitReg(MISCREG_DBGBCR5_EL1
)
3795 .mapsTo(MISCREG_DBGBCR5
);
3796 InitReg(MISCREG_DBGWVR0_EL1
)
3798 .mapsTo(MISCREG_DBGWVR0
);
3799 InitReg(MISCREG_DBGWVR1_EL1
)
3801 .mapsTo(MISCREG_DBGWVR1
);
3802 InitReg(MISCREG_DBGWVR2_EL1
)
3804 .mapsTo(MISCREG_DBGWVR2
);
3805 InitReg(MISCREG_DBGWVR3_EL1
)
3807 .mapsTo(MISCREG_DBGWVR3
);
3808 InitReg(MISCREG_DBGWCR0_EL1
)
3810 .mapsTo(MISCREG_DBGWCR0
);
3811 InitReg(MISCREG_DBGWCR1_EL1
)
3813 .mapsTo(MISCREG_DBGWCR1
);
3814 InitReg(MISCREG_DBGWCR2_EL1
)
3816 .mapsTo(MISCREG_DBGWCR2
);
3817 InitReg(MISCREG_DBGWCR3_EL1
)
3819 .mapsTo(MISCREG_DBGWCR3
);
3820 InitReg(MISCREG_MDCCSR_EL0
)
3821 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3822 .mapsTo(MISCREG_DBGDSCRint
);
3823 InitReg(MISCREG_MDDTR_EL0
)
3825 InitReg(MISCREG_MDDTRTX_EL0
)
3827 InitReg(MISCREG_MDDTRRX_EL0
)
3829 InitReg(MISCREG_DBGVCR32_EL2
)
3831 .mapsTo(MISCREG_DBGVCR
);
3832 InitReg(MISCREG_MDRAR_EL1
)
3833 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3834 .mapsTo(MISCREG_DBGDRAR
);
3835 InitReg(MISCREG_OSLAR_EL1
)
3836 .allPrivileges().monSecureRead(0).monNonSecureRead(0)
3837 .mapsTo(MISCREG_DBGOSLAR
);
3838 InitReg(MISCREG_OSLSR_EL1
)
3839 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3840 .mapsTo(MISCREG_DBGOSLSR
);
3841 InitReg(MISCREG_OSDLR_EL1
)
3843 .mapsTo(MISCREG_DBGOSDLR
);
3844 InitReg(MISCREG_DBGPRCR_EL1
)
3846 .mapsTo(MISCREG_DBGPRCR
);
3847 InitReg(MISCREG_DBGCLAIMSET_EL1
)
3849 .mapsTo(MISCREG_DBGCLAIMSET
);
3850 InitReg(MISCREG_DBGCLAIMCLR_EL1
)
3852 .mapsTo(MISCREG_DBGCLAIMCLR
);
3853 InitReg(MISCREG_DBGAUTHSTATUS_EL1
)
3854 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3855 .mapsTo(MISCREG_DBGAUTHSTATUS
);
3856 InitReg(MISCREG_TEECR32_EL1
);
3857 InitReg(MISCREG_TEEHBR32_EL1
);
3859 // AArch64 registers (Op0=1,3);
3860 InitReg(MISCREG_MIDR_EL1
)
3861 .allPrivileges().exceptUserMode().writes(0);
3862 InitReg(MISCREG_MPIDR_EL1
)
3863 .allPrivileges().exceptUserMode().writes(0);
3864 InitReg(MISCREG_REVIDR_EL1
)
3865 .allPrivileges().exceptUserMode().writes(0);
3866 InitReg(MISCREG_ID_PFR0_EL1
)
3867 .allPrivileges().exceptUserMode().writes(0)
3868 .mapsTo(MISCREG_ID_PFR0
);
3869 InitReg(MISCREG_ID_PFR1_EL1
)
3870 .allPrivileges().exceptUserMode().writes(0)
3871 .mapsTo(MISCREG_ID_PFR1
);
3872 InitReg(MISCREG_ID_DFR0_EL1
)
3873 .allPrivileges().exceptUserMode().writes(0)
3874 .mapsTo(MISCREG_ID_DFR0
);
3875 InitReg(MISCREG_ID_AFR0_EL1
)
3876 .allPrivileges().exceptUserMode().writes(0)
3877 .mapsTo(MISCREG_ID_AFR0
);
3878 InitReg(MISCREG_ID_MMFR0_EL1
)
3879 .allPrivileges().exceptUserMode().writes(0)
3880 .mapsTo(MISCREG_ID_MMFR0
);
3881 InitReg(MISCREG_ID_MMFR1_EL1
)
3882 .allPrivileges().exceptUserMode().writes(0)
3883 .mapsTo(MISCREG_ID_MMFR1
);
3884 InitReg(MISCREG_ID_MMFR2_EL1
)
3885 .allPrivileges().exceptUserMode().writes(0)
3886 .mapsTo(MISCREG_ID_MMFR2
);
3887 InitReg(MISCREG_ID_MMFR3_EL1
)
3888 .allPrivileges().exceptUserMode().writes(0)
3889 .mapsTo(MISCREG_ID_MMFR3
);
3890 InitReg(MISCREG_ID_ISAR0_EL1
)
3891 .allPrivileges().exceptUserMode().writes(0)
3892 .mapsTo(MISCREG_ID_ISAR0
);
3893 InitReg(MISCREG_ID_ISAR1_EL1
)
3894 .allPrivileges().exceptUserMode().writes(0)
3895 .mapsTo(MISCREG_ID_ISAR1
);
3896 InitReg(MISCREG_ID_ISAR2_EL1
)
3897 .allPrivileges().exceptUserMode().writes(0)
3898 .mapsTo(MISCREG_ID_ISAR2
);
3899 InitReg(MISCREG_ID_ISAR3_EL1
)
3900 .allPrivileges().exceptUserMode().writes(0)
3901 .mapsTo(MISCREG_ID_ISAR3
);
3902 InitReg(MISCREG_ID_ISAR4_EL1
)
3903 .allPrivileges().exceptUserMode().writes(0)
3904 .mapsTo(MISCREG_ID_ISAR4
);
3905 InitReg(MISCREG_ID_ISAR5_EL1
)
3906 .allPrivileges().exceptUserMode().writes(0)
3907 .mapsTo(MISCREG_ID_ISAR5
);
3908 InitReg(MISCREG_MVFR0_EL1
)
3909 .allPrivileges().exceptUserMode().writes(0);
3910 InitReg(MISCREG_MVFR1_EL1
)
3911 .allPrivileges().exceptUserMode().writes(0);
3912 InitReg(MISCREG_MVFR2_EL1
)
3913 .allPrivileges().exceptUserMode().writes(0);
3914 InitReg(MISCREG_ID_AA64PFR0_EL1
)
3915 .allPrivileges().exceptUserMode().writes(0);
3916 InitReg(MISCREG_ID_AA64PFR1_EL1
)
3917 .allPrivileges().exceptUserMode().writes(0);
3918 InitReg(MISCREG_ID_AA64DFR0_EL1
)
3919 .allPrivileges().exceptUserMode().writes(0);
3920 InitReg(MISCREG_ID_AA64DFR1_EL1
)
3921 .allPrivileges().exceptUserMode().writes(0);
3922 InitReg(MISCREG_ID_AA64AFR0_EL1
)
3923 .allPrivileges().exceptUserMode().writes(0);
3924 InitReg(MISCREG_ID_AA64AFR1_EL1
)
3925 .allPrivileges().exceptUserMode().writes(0);
3926 InitReg(MISCREG_ID_AA64ISAR0_EL1
)
3927 .allPrivileges().exceptUserMode().writes(0);
3928 InitReg(MISCREG_ID_AA64ISAR1_EL1
)
3929 .allPrivileges().exceptUserMode().writes(0);
3930 InitReg(MISCREG_ID_AA64MMFR0_EL1
)
3931 .allPrivileges().exceptUserMode().writes(0);
3932 InitReg(MISCREG_ID_AA64MMFR1_EL1
)
3933 .allPrivileges().exceptUserMode().writes(0);
3934 InitReg(MISCREG_ID_AA64MMFR2_EL1
)
3935 .allPrivileges().exceptUserMode().writes(0);
3936 InitReg(MISCREG_CCSIDR_EL1
)
3937 .allPrivileges().exceptUserMode().writes(0);
3938 InitReg(MISCREG_CLIDR_EL1
)
3939 .allPrivileges().exceptUserMode().writes(0);
3940 InitReg(MISCREG_AIDR_EL1
)
3941 .allPrivileges().exceptUserMode().writes(0);
3942 InitReg(MISCREG_CSSELR_EL1
)
3943 .allPrivileges().exceptUserMode()
3944 .mapsTo(MISCREG_CSSELR_NS
);
3945 InitReg(MISCREG_CTR_EL0
)
3947 InitReg(MISCREG_DCZID_EL0
)
3949 InitReg(MISCREG_VPIDR_EL2
)
3951 .mapsTo(MISCREG_VPIDR
);
3952 InitReg(MISCREG_VMPIDR_EL2
)
3954 .mapsTo(MISCREG_VMPIDR
);
3955 InitReg(MISCREG_SCTLR_EL1
)
3956 .allPrivileges().exceptUserMode()
3957 .res0( 0x20440 | (EnDB
? 0 : 0x2000)
3958 | (IESB
? 0 : 0x200000)
3959 | (EnDA
? 0 : 0x8000000)
3960 | (EnIB
? 0 : 0x40000000)
3961 | (EnIA
? 0 : 0x80000000))
3962 .res1(0x500800 | (SPAN
? 0 : 0x800000)
3963 | (nTLSMD
? 0 : 0x8000000)
3964 | (LSMAOE
? 0 : 0x10000000))
3965 .mapsTo(MISCREG_SCTLR_NS
);
3966 InitReg(MISCREG_ACTLR_EL1
)
3967 .allPrivileges().exceptUserMode()
3968 .mapsTo(MISCREG_ACTLR_NS
);
3969 InitReg(MISCREG_CPACR_EL1
)
3970 .allPrivileges().exceptUserMode()
3971 .mapsTo(MISCREG_CPACR
);
3972 InitReg(MISCREG_SCTLR_EL2
)
3974 .res0(0x0512c7c0 | (EnDB
? 0 : 0x2000)
3975 | (IESB
? 0 : 0x200000)
3976 | (EnDA
? 0 : 0x8000000)
3977 | (EnIB
? 0 : 0x40000000)
3978 | (EnIA
? 0 : 0x80000000))
3980 .mapsTo(MISCREG_HSCTLR
);
3981 InitReg(MISCREG_ACTLR_EL2
)
3983 .mapsTo(MISCREG_HACTLR
);
3984 InitReg(MISCREG_HCR_EL2
)
3986 .mapsTo(MISCREG_HCR
/*, MISCREG_HCR2*/);
3987 InitReg(MISCREG_MDCR_EL2
)
3989 .mapsTo(MISCREG_HDCR
);
3990 InitReg(MISCREG_CPTR_EL2
)
3992 .mapsTo(MISCREG_HCPTR
);
3993 InitReg(MISCREG_HSTR_EL2
)
3995 .mapsTo(MISCREG_HSTR
);
3996 InitReg(MISCREG_HACR_EL2
)
3998 .mapsTo(MISCREG_HACR
);
3999 InitReg(MISCREG_SCTLR_EL3
)
4001 .res0(0x0512c7c0 | (EnDB
? 0 : 0x2000)
4002 | (IESB
? 0 : 0x200000)
4003 | (EnDA
? 0 : 0x8000000)
4004 | (EnIB
? 0 : 0x40000000)
4005 | (EnIA
? 0 : 0x80000000))
4007 InitReg(MISCREG_ACTLR_EL3
)
4009 InitReg(MISCREG_SCR_EL3
)
4011 .mapsTo(MISCREG_SCR
); // NAM D7-2005
4012 InitReg(MISCREG_SDER32_EL3
)
4014 .mapsTo(MISCREG_SDER
);
4015 InitReg(MISCREG_CPTR_EL3
)
4017 InitReg(MISCREG_MDCR_EL3
)
4019 InitReg(MISCREG_TTBR0_EL1
)
4020 .allPrivileges().exceptUserMode()
4021 .mapsTo(MISCREG_TTBR0_NS
);
4022 InitReg(MISCREG_TTBR1_EL1
)
4023 .allPrivileges().exceptUserMode()
4024 .mapsTo(MISCREG_TTBR1_NS
);
4025 InitReg(MISCREG_TCR_EL1
)
4026 .allPrivileges().exceptUserMode()
4027 .mapsTo(MISCREG_TTBCR_NS
);
4028 InitReg(MISCREG_TTBR0_EL2
)
4030 .mapsTo(MISCREG_HTTBR
);
4031 InitReg(MISCREG_TTBR1_EL2
)
4033 InitReg(MISCREG_TCR_EL2
)
4035 .mapsTo(MISCREG_HTCR
);
4036 InitReg(MISCREG_VTTBR_EL2
)
4038 .mapsTo(MISCREG_VTTBR
);
4039 InitReg(MISCREG_VTCR_EL2
)
4041 .mapsTo(MISCREG_VTCR
);
4042 InitReg(MISCREG_TTBR0_EL3
)
4044 InitReg(MISCREG_TCR_EL3
)
4046 InitReg(MISCREG_DACR32_EL2
)
4048 .mapsTo(MISCREG_DACR_NS
);
4049 InitReg(MISCREG_SPSR_EL1
)
4050 .allPrivileges().exceptUserMode()
4051 .mapsTo(MISCREG_SPSR_SVC
); // NAM C5.2.17 SPSR_EL1
4052 InitReg(MISCREG_ELR_EL1
)
4053 .allPrivileges().exceptUserMode();
4054 InitReg(MISCREG_SP_EL0
)
4055 .allPrivileges().exceptUserMode();
4056 InitReg(MISCREG_SPSEL
)
4057 .allPrivileges().exceptUserMode();
4058 InitReg(MISCREG_CURRENTEL
)
4059 .allPrivileges().exceptUserMode().writes(0);
4060 InitReg(MISCREG_NZCV
)
4062 InitReg(MISCREG_DAIF
)
4064 InitReg(MISCREG_FPCR
)
4066 InitReg(MISCREG_FPSR
)
4068 InitReg(MISCREG_DSPSR_EL0
)
4070 InitReg(MISCREG_DLR_EL0
)
4072 InitReg(MISCREG_SPSR_EL2
)
4074 .mapsTo(MISCREG_SPSR_HYP
); // NAM C5.2.18 SPSR_EL2
4075 InitReg(MISCREG_ELR_EL2
)
4077 InitReg(MISCREG_SP_EL1
)
4079 InitReg(MISCREG_SPSR_IRQ_AA64
)
4081 InitReg(MISCREG_SPSR_ABT_AA64
)
4083 InitReg(MISCREG_SPSR_UND_AA64
)
4085 InitReg(MISCREG_SPSR_FIQ_AA64
)
4087 InitReg(MISCREG_SPSR_EL3
)
4089 .mapsTo(MISCREG_SPSR_MON
); // NAM C5.2.19 SPSR_EL3
4090 InitReg(MISCREG_ELR_EL3
)
4092 InitReg(MISCREG_SP_EL2
)
4094 InitReg(MISCREG_AFSR0_EL1
)
4095 .allPrivileges().exceptUserMode()
4096 .mapsTo(MISCREG_ADFSR_NS
);
4097 InitReg(MISCREG_AFSR1_EL1
)
4098 .allPrivileges().exceptUserMode()
4099 .mapsTo(MISCREG_AIFSR_NS
);
4100 InitReg(MISCREG_ESR_EL1
)
4101 .allPrivileges().exceptUserMode();
4102 InitReg(MISCREG_IFSR32_EL2
)
4104 .mapsTo(MISCREG_IFSR_NS
);
4105 InitReg(MISCREG_AFSR0_EL2
)
4107 .mapsTo(MISCREG_HADFSR
);
4108 InitReg(MISCREG_AFSR1_EL2
)
4110 .mapsTo(MISCREG_HAIFSR
);
4111 InitReg(MISCREG_ESR_EL2
)
4113 .mapsTo(MISCREG_HSR
);
4114 InitReg(MISCREG_FPEXC32_EL2
)
4115 .hyp().mon().mapsTo(MISCREG_FPEXC
);
4116 InitReg(MISCREG_AFSR0_EL3
)
4118 InitReg(MISCREG_AFSR1_EL3
)
4120 InitReg(MISCREG_ESR_EL3
)
4122 InitReg(MISCREG_FAR_EL1
)
4123 .allPrivileges().exceptUserMode()
4124 .mapsTo(MISCREG_DFAR_NS
, MISCREG_IFAR_NS
);
4125 InitReg(MISCREG_FAR_EL2
)
4127 .mapsTo(MISCREG_HDFAR
, MISCREG_HIFAR
);
4128 InitReg(MISCREG_HPFAR_EL2
)
4130 .mapsTo(MISCREG_HPFAR
);
4131 InitReg(MISCREG_FAR_EL3
)
4133 InitReg(MISCREG_IC_IALLUIS
)
4135 .writes(1).exceptUserMode();
4136 InitReg(MISCREG_PAR_EL1
)
4137 .allPrivileges().exceptUserMode()
4138 .mapsTo(MISCREG_PAR_NS
);
4139 InitReg(MISCREG_IC_IALLU
)
4141 .writes(1).exceptUserMode();
4142 InitReg(MISCREG_DC_IVAC_Xt
)
4144 .writes(1).exceptUserMode();
4145 InitReg(MISCREG_DC_ISW_Xt
)
4147 .writes(1).exceptUserMode();
4148 InitReg(MISCREG_AT_S1E1R_Xt
)
4149 .writes(1).exceptUserMode();
4150 InitReg(MISCREG_AT_S1E1W_Xt
)
4151 .writes(1).exceptUserMode();
4152 InitReg(MISCREG_AT_S1E0R_Xt
)
4153 .writes(1).exceptUserMode();
4154 InitReg(MISCREG_AT_S1E0W_Xt
)
4155 .writes(1).exceptUserMode();
4156 InitReg(MISCREG_DC_CSW_Xt
)
4158 .writes(1).exceptUserMode();
4159 InitReg(MISCREG_DC_CISW_Xt
)
4161 .writes(1).exceptUserMode();
4162 InitReg(MISCREG_DC_ZVA_Xt
)
4164 .writes(1).userSecureWrite(0);
4165 InitReg(MISCREG_IC_IVAU_Xt
)
4167 InitReg(MISCREG_DC_CVAC_Xt
)
4170 InitReg(MISCREG_DC_CVAU_Xt
)
4173 InitReg(MISCREG_DC_CIVAC_Xt
)
4176 InitReg(MISCREG_AT_S1E2R_Xt
)
4177 .monNonSecureWrite().hypWrite();
4178 InitReg(MISCREG_AT_S1E2W_Xt
)
4179 .monNonSecureWrite().hypWrite();
4180 InitReg(MISCREG_AT_S12E1R_Xt
)
4181 .hypWrite().monSecureWrite().monNonSecureWrite();
4182 InitReg(MISCREG_AT_S12E1W_Xt
)
4183 .hypWrite().monSecureWrite().monNonSecureWrite();
4184 InitReg(MISCREG_AT_S12E0R_Xt
)
4185 .hypWrite().monSecureWrite().monNonSecureWrite();
4186 InitReg(MISCREG_AT_S12E0W_Xt
)
4187 .hypWrite().monSecureWrite().monNonSecureWrite();
4188 InitReg(MISCREG_AT_S1E3R_Xt
)
4189 .monSecureWrite().monNonSecureWrite();
4190 InitReg(MISCREG_AT_S1E3W_Xt
)
4191 .monSecureWrite().monNonSecureWrite();
4192 InitReg(MISCREG_TLBI_VMALLE1IS
)
4193 .writes(1).exceptUserMode();
4194 InitReg(MISCREG_TLBI_VAE1IS_Xt
)
4195 .writes(1).exceptUserMode();
4196 InitReg(MISCREG_TLBI_ASIDE1IS_Xt
)
4197 .writes(1).exceptUserMode();
4198 InitReg(MISCREG_TLBI_VAAE1IS_Xt
)
4199 .writes(1).exceptUserMode();
4200 InitReg(MISCREG_TLBI_VALE1IS_Xt
)
4201 .writes(1).exceptUserMode();
4202 InitReg(MISCREG_TLBI_VAALE1IS_Xt
)
4203 .writes(1).exceptUserMode();
4204 InitReg(MISCREG_TLBI_VMALLE1
)
4205 .writes(1).exceptUserMode();
4206 InitReg(MISCREG_TLBI_VAE1_Xt
)
4207 .writes(1).exceptUserMode();
4208 InitReg(MISCREG_TLBI_ASIDE1_Xt
)
4209 .writes(1).exceptUserMode();
4210 InitReg(MISCREG_TLBI_VAAE1_Xt
)
4211 .writes(1).exceptUserMode();
4212 InitReg(MISCREG_TLBI_VALE1_Xt
)
4213 .writes(1).exceptUserMode();
4214 InitReg(MISCREG_TLBI_VAALE1_Xt
)
4215 .writes(1).exceptUserMode();
4216 InitReg(MISCREG_TLBI_IPAS2E1IS_Xt
)
4217 .hypWrite().monSecureWrite().monNonSecureWrite();
4218 InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt
)
4219 .hypWrite().monSecureWrite().monNonSecureWrite();
4220 InitReg(MISCREG_TLBI_ALLE2IS
)
4221 .monNonSecureWrite().hypWrite();
4222 InitReg(MISCREG_TLBI_VAE2IS_Xt
)
4223 .monNonSecureWrite().hypWrite();
4224 InitReg(MISCREG_TLBI_ALLE1IS
)
4225 .hypWrite().monSecureWrite().monNonSecureWrite();
4226 InitReg(MISCREG_TLBI_VALE2IS_Xt
)
4227 .monNonSecureWrite().hypWrite();
4228 InitReg(MISCREG_TLBI_VMALLS12E1IS
)
4229 .hypWrite().monSecureWrite().monNonSecureWrite();
4230 InitReg(MISCREG_TLBI_IPAS2E1_Xt
)
4231 .hypWrite().monSecureWrite().monNonSecureWrite();
4232 InitReg(MISCREG_TLBI_IPAS2LE1_Xt
)
4233 .hypWrite().monSecureWrite().monNonSecureWrite();
4234 InitReg(MISCREG_TLBI_ALLE2
)
4235 .monNonSecureWrite().hypWrite();
4236 InitReg(MISCREG_TLBI_VAE2_Xt
)
4237 .monNonSecureWrite().hypWrite();
4238 InitReg(MISCREG_TLBI_ALLE1
)
4239 .hypWrite().monSecureWrite().monNonSecureWrite();
4240 InitReg(MISCREG_TLBI_VALE2_Xt
)
4241 .monNonSecureWrite().hypWrite();
4242 InitReg(MISCREG_TLBI_VMALLS12E1
)
4243 .hypWrite().monSecureWrite().monNonSecureWrite();
4244 InitReg(MISCREG_TLBI_ALLE3IS
)
4245 .monSecureWrite().monNonSecureWrite();
4246 InitReg(MISCREG_TLBI_VAE3IS_Xt
)
4247 .monSecureWrite().monNonSecureWrite();
4248 InitReg(MISCREG_TLBI_VALE3IS_Xt
)
4249 .monSecureWrite().monNonSecureWrite();
4250 InitReg(MISCREG_TLBI_ALLE3
)
4251 .monSecureWrite().monNonSecureWrite();
4252 InitReg(MISCREG_TLBI_VAE3_Xt
)
4253 .monSecureWrite().monNonSecureWrite();
4254 InitReg(MISCREG_TLBI_VALE3_Xt
)
4255 .monSecureWrite().monNonSecureWrite();
4256 InitReg(MISCREG_PMINTENSET_EL1
)
4257 .allPrivileges().exceptUserMode()
4258 .mapsTo(MISCREG_PMINTENSET
);
4259 InitReg(MISCREG_PMINTENCLR_EL1
)
4260 .allPrivileges().exceptUserMode()
4261 .mapsTo(MISCREG_PMINTENCLR
);
4262 InitReg(MISCREG_PMCR_EL0
)
4264 .mapsTo(MISCREG_PMCR
);
4265 InitReg(MISCREG_PMCNTENSET_EL0
)
4267 .mapsTo(MISCREG_PMCNTENSET
);
4268 InitReg(MISCREG_PMCNTENCLR_EL0
)
4270 .mapsTo(MISCREG_PMCNTENCLR
);
4271 InitReg(MISCREG_PMOVSCLR_EL0
)
4273 // .mapsTo(MISCREG_PMOVSCLR);
4274 InitReg(MISCREG_PMSWINC_EL0
)
4276 .mapsTo(MISCREG_PMSWINC
);
4277 InitReg(MISCREG_PMSELR_EL0
)
4279 .mapsTo(MISCREG_PMSELR
);
4280 InitReg(MISCREG_PMCEID0_EL0
)
4282 .mapsTo(MISCREG_PMCEID0
);
4283 InitReg(MISCREG_PMCEID1_EL0
)
4285 .mapsTo(MISCREG_PMCEID1
);
4286 InitReg(MISCREG_PMCCNTR_EL0
)
4288 .mapsTo(MISCREG_PMCCNTR
);
4289 InitReg(MISCREG_PMXEVTYPER_EL0
)
4291 .mapsTo(MISCREG_PMXEVTYPER
);
4292 InitReg(MISCREG_PMCCFILTR_EL0
)
4294 InitReg(MISCREG_PMXEVCNTR_EL0
)
4296 .mapsTo(MISCREG_PMXEVCNTR
);
4297 InitReg(MISCREG_PMUSERENR_EL0
)
4298 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
4299 .mapsTo(MISCREG_PMUSERENR
);
4300 InitReg(MISCREG_PMOVSSET_EL0
)
4302 .mapsTo(MISCREG_PMOVSSET
);
4303 InitReg(MISCREG_MAIR_EL1
)
4304 .allPrivileges().exceptUserMode()
4305 .mapsTo(MISCREG_PRRR_NS
, MISCREG_NMRR_NS
);
4306 InitReg(MISCREG_AMAIR_EL1
)
4307 .allPrivileges().exceptUserMode()
4308 .mapsTo(MISCREG_AMAIR0_NS
, MISCREG_AMAIR1_NS
);
4309 InitReg(MISCREG_MAIR_EL2
)
4311 .mapsTo(MISCREG_HMAIR0
, MISCREG_HMAIR1
);
4312 InitReg(MISCREG_AMAIR_EL2
)
4314 .mapsTo(MISCREG_HAMAIR0
, MISCREG_HAMAIR1
);
4315 InitReg(MISCREG_MAIR_EL3
)
4317 InitReg(MISCREG_AMAIR_EL3
)
4319 InitReg(MISCREG_L2CTLR_EL1
)
4320 .allPrivileges().exceptUserMode();
4321 InitReg(MISCREG_L2ECTLR_EL1
)
4322 .allPrivileges().exceptUserMode();
4323 InitReg(MISCREG_VBAR_EL1
)
4324 .allPrivileges().exceptUserMode()
4325 .mapsTo(MISCREG_VBAR_NS
);
4326 InitReg(MISCREG_RVBAR_EL1
)
4327 .allPrivileges().exceptUserMode().writes(0);
4328 InitReg(MISCREG_ISR_EL1
)
4329 .allPrivileges().exceptUserMode().writes(0);
4330 InitReg(MISCREG_VBAR_EL2
)
4333 .mapsTo(MISCREG_HVBAR
);
4334 InitReg(MISCREG_RVBAR_EL2
)
4335 .mon().hyp().writes(0);
4336 InitReg(MISCREG_VBAR_EL3
)
4338 InitReg(MISCREG_RVBAR_EL3
)
4340 InitReg(MISCREG_RMR_EL3
)
4342 InitReg(MISCREG_CONTEXTIDR_EL1
)
4343 .allPrivileges().exceptUserMode()
4344 .mapsTo(MISCREG_CONTEXTIDR_NS
);
4345 InitReg(MISCREG_TPIDR_EL1
)
4346 .allPrivileges().exceptUserMode()
4347 .mapsTo(MISCREG_TPIDRPRW_NS
);
4348 InitReg(MISCREG_TPIDR_EL0
)
4350 .mapsTo(MISCREG_TPIDRURW_NS
);
4351 InitReg(MISCREG_TPIDRRO_EL0
)
4352 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
4353 .mapsTo(MISCREG_TPIDRURO_NS
);
4354 InitReg(MISCREG_TPIDR_EL2
)
4356 .mapsTo(MISCREG_HTPIDR
);
4357 InitReg(MISCREG_TPIDR_EL3
)
4359 InitReg(MISCREG_CNTKCTL_EL1
)
4360 .allPrivileges().exceptUserMode()
4361 .mapsTo(MISCREG_CNTKCTL
);
4362 InitReg(MISCREG_CNTFRQ_EL0
)
4364 .mapsTo(MISCREG_CNTFRQ
);
4365 InitReg(MISCREG_CNTPCT_EL0
)
4367 .mapsTo(MISCREG_CNTPCT
); /* 64b */
4368 InitReg(MISCREG_CNTVCT_EL0
)
4371 .mapsTo(MISCREG_CNTVCT
); /* 64b */
4372 InitReg(MISCREG_CNTP_TVAL_EL0
)
4374 .mapsTo(MISCREG_CNTP_TVAL_NS
);
4375 InitReg(MISCREG_CNTP_CTL_EL0
)
4377 .mapsTo(MISCREG_CNTP_CTL_NS
);
4378 InitReg(MISCREG_CNTP_CVAL_EL0
)
4380 .mapsTo(MISCREG_CNTP_CVAL_NS
); /* 64b */
4381 InitReg(MISCREG_CNTV_TVAL_EL0
)
4383 .mapsTo(MISCREG_CNTV_TVAL
);
4384 InitReg(MISCREG_CNTV_CTL_EL0
)
4386 .mapsTo(MISCREG_CNTV_CTL
);
4387 InitReg(MISCREG_CNTV_CVAL_EL0
)
4389 .mapsTo(MISCREG_CNTV_CVAL
); /* 64b */
4390 InitReg(MISCREG_PMEVCNTR0_EL0
)
4392 // .mapsTo(MISCREG_PMEVCNTR0);
4393 InitReg(MISCREG_PMEVCNTR1_EL0
)
4395 // .mapsTo(MISCREG_PMEVCNTR1);
4396 InitReg(MISCREG_PMEVCNTR2_EL0
)
4398 // .mapsTo(MISCREG_PMEVCNTR2);
4399 InitReg(MISCREG_PMEVCNTR3_EL0
)
4401 // .mapsTo(MISCREG_PMEVCNTR3);
4402 InitReg(MISCREG_PMEVCNTR4_EL0
)
4404 // .mapsTo(MISCREG_PMEVCNTR4);
4405 InitReg(MISCREG_PMEVCNTR5_EL0
)
4407 // .mapsTo(MISCREG_PMEVCNTR5);
4408 InitReg(MISCREG_PMEVTYPER0_EL0
)
4410 // .mapsTo(MISCREG_PMEVTYPER0);
4411 InitReg(MISCREG_PMEVTYPER1_EL0
)
4413 // .mapsTo(MISCREG_PMEVTYPER1);
4414 InitReg(MISCREG_PMEVTYPER2_EL0
)
4416 // .mapsTo(MISCREG_PMEVTYPER2);
4417 InitReg(MISCREG_PMEVTYPER3_EL0
)
4419 // .mapsTo(MISCREG_PMEVTYPER3);
4420 InitReg(MISCREG_PMEVTYPER4_EL0
)
4422 // .mapsTo(MISCREG_PMEVTYPER4);
4423 InitReg(MISCREG_PMEVTYPER5_EL0
)
4425 // .mapsTo(MISCREG_PMEVTYPER5);
4426 InitReg(MISCREG_CNTVOFF_EL2
)
4428 .mapsTo(MISCREG_CNTVOFF
); /* 64b */
4429 InitReg(MISCREG_CNTHCTL_EL2
)
4431 .mapsTo(MISCREG_CNTHCTL
);
4432 InitReg(MISCREG_CNTHP_TVAL_EL2
)
4434 .mapsTo(MISCREG_CNTHP_TVAL
);
4435 InitReg(MISCREG_CNTHP_CTL_EL2
)
4437 .mapsTo(MISCREG_CNTHP_CTL
);
4438 InitReg(MISCREG_CNTHP_CVAL_EL2
)
4440 .mapsTo(MISCREG_CNTHP_CVAL
); /* 64b */
4441 InitReg(MISCREG_CNTPS_TVAL_EL1
)
4442 .mon().privSecure();
4443 InitReg(MISCREG_CNTPS_CTL_EL1
)
4444 .mon().privSecure();
4445 InitReg(MISCREG_CNTPS_CVAL_EL1
)
4446 .mon().privSecure();
4447 InitReg(MISCREG_IL1DATA0_EL1
)
4448 .allPrivileges().exceptUserMode();
4449 InitReg(MISCREG_IL1DATA1_EL1
)
4450 .allPrivileges().exceptUserMode();
4451 InitReg(MISCREG_IL1DATA2_EL1
)
4452 .allPrivileges().exceptUserMode();
4453 InitReg(MISCREG_IL1DATA3_EL1
)
4454 .allPrivileges().exceptUserMode();
4455 InitReg(MISCREG_DL1DATA0_EL1
)
4456 .allPrivileges().exceptUserMode();
4457 InitReg(MISCREG_DL1DATA1_EL1
)
4458 .allPrivileges().exceptUserMode();
4459 InitReg(MISCREG_DL1DATA2_EL1
)
4460 .allPrivileges().exceptUserMode();
4461 InitReg(MISCREG_DL1DATA3_EL1
)
4462 .allPrivileges().exceptUserMode();
4463 InitReg(MISCREG_DL1DATA4_EL1
)
4464 .allPrivileges().exceptUserMode();
4465 InitReg(MISCREG_L2ACTLR_EL1
)
4466 .allPrivileges().exceptUserMode();
4467 InitReg(MISCREG_CPUACTLR_EL1
)
4468 .allPrivileges().exceptUserMode();
4469 InitReg(MISCREG_CPUECTLR_EL1
)
4470 .allPrivileges().exceptUserMode();
4471 InitReg(MISCREG_CPUMERRSR_EL1
)
4472 .allPrivileges().exceptUserMode();
4473 InitReg(MISCREG_L2MERRSR_EL1
)
4476 .allPrivileges().exceptUserMode();
4477 InitReg(MISCREG_CBAR_EL1
)
4478 .allPrivileges().exceptUserMode().writes(0);
4479 InitReg(MISCREG_CONTEXTIDR_EL2
)
4483 InitReg(MISCREG_ICC_PMR_EL1
)
4484 .res0(0xffffff00) // [31:8]
4485 .allPrivileges().exceptUserMode()
4486 .mapsTo(MISCREG_ICC_PMR
);
4487 InitReg(MISCREG_ICC_IAR0_EL1
)
4488 .allPrivileges().exceptUserMode().writes(0)
4489 .mapsTo(MISCREG_ICC_IAR0
);
4490 InitReg(MISCREG_ICC_EOIR0_EL1
)
4491 .allPrivileges().exceptUserMode().reads(0)
4492 .mapsTo(MISCREG_ICC_EOIR0
);
4493 InitReg(MISCREG_ICC_HPPIR0_EL1
)
4494 .allPrivileges().exceptUserMode().writes(0)
4495 .mapsTo(MISCREG_ICC_HPPIR0
);
4496 InitReg(MISCREG_ICC_BPR0_EL1
)
4497 .res0(0xfffffff8) // [31:3]
4498 .allPrivileges().exceptUserMode()
4499 .mapsTo(MISCREG_ICC_BPR0
);
4500 InitReg(MISCREG_ICC_AP0R0_EL1
)
4501 .allPrivileges().exceptUserMode()
4502 .mapsTo(MISCREG_ICC_AP0R0
);
4503 InitReg(MISCREG_ICC_AP0R1_EL1
)
4504 .allPrivileges().exceptUserMode()
4505 .mapsTo(MISCREG_ICC_AP0R1
);
4506 InitReg(MISCREG_ICC_AP0R2_EL1
)
4507 .allPrivileges().exceptUserMode()
4508 .mapsTo(MISCREG_ICC_AP0R2
);
4509 InitReg(MISCREG_ICC_AP0R3_EL1
)
4510 .allPrivileges().exceptUserMode()
4511 .mapsTo(MISCREG_ICC_AP0R3
);
4512 InitReg(MISCREG_ICC_AP1R0_EL1
)
4514 .mapsTo(MISCREG_ICC_AP1R0
);
4515 InitReg(MISCREG_ICC_AP1R0_EL1_NS
)
4517 .allPrivileges().exceptUserMode()
4518 .mapsTo(MISCREG_ICC_AP1R0_NS
);
4519 InitReg(MISCREG_ICC_AP1R0_EL1_S
)
4521 .allPrivileges().exceptUserMode()
4522 .mapsTo(MISCREG_ICC_AP1R0_S
);
4523 InitReg(MISCREG_ICC_AP1R1_EL1
)
4525 .mapsTo(MISCREG_ICC_AP1R1
);
4526 InitReg(MISCREG_ICC_AP1R1_EL1_NS
)
4528 .allPrivileges().exceptUserMode()
4529 .mapsTo(MISCREG_ICC_AP1R1_NS
);
4530 InitReg(MISCREG_ICC_AP1R1_EL1_S
)
4532 .allPrivileges().exceptUserMode()
4533 .mapsTo(MISCREG_ICC_AP1R1_S
);
4534 InitReg(MISCREG_ICC_AP1R2_EL1
)
4536 .mapsTo(MISCREG_ICC_AP1R2
);
4537 InitReg(MISCREG_ICC_AP1R2_EL1_NS
)
4539 .allPrivileges().exceptUserMode()
4540 .mapsTo(MISCREG_ICC_AP1R2_NS
);
4541 InitReg(MISCREG_ICC_AP1R2_EL1_S
)
4543 .allPrivileges().exceptUserMode()
4544 .mapsTo(MISCREG_ICC_AP1R2_S
);
4545 InitReg(MISCREG_ICC_AP1R3_EL1
)
4547 .mapsTo(MISCREG_ICC_AP1R3
);
4548 InitReg(MISCREG_ICC_AP1R3_EL1_NS
)
4550 .allPrivileges().exceptUserMode()
4551 .mapsTo(MISCREG_ICC_AP1R3_NS
);
4552 InitReg(MISCREG_ICC_AP1R3_EL1_S
)
4554 .allPrivileges().exceptUserMode()
4555 .mapsTo(MISCREG_ICC_AP1R3_S
);
4556 InitReg(MISCREG_ICC_DIR_EL1
)
4557 .res0(0xFF000000) // [31:24]
4558 .allPrivileges().exceptUserMode().reads(0)
4559 .mapsTo(MISCREG_ICC_DIR
);
4560 InitReg(MISCREG_ICC_RPR_EL1
)
4561 .allPrivileges().exceptUserMode().writes(0)
4562 .mapsTo(MISCREG_ICC_RPR
);
4563 InitReg(MISCREG_ICC_SGI1R_EL1
)
4564 .allPrivileges().exceptUserMode().reads(0)
4565 .mapsTo(MISCREG_ICC_SGI1R
);
4566 InitReg(MISCREG_ICC_ASGI1R_EL1
)
4567 .allPrivileges().exceptUserMode().reads(0)
4568 .mapsTo(MISCREG_ICC_ASGI1R
);
4569 InitReg(MISCREG_ICC_SGI0R_EL1
)
4570 .allPrivileges().exceptUserMode().reads(0)
4571 .mapsTo(MISCREG_ICC_SGI0R
);
4572 InitReg(MISCREG_ICC_IAR1_EL1
)
4573 .allPrivileges().exceptUserMode().writes(0)
4574 .mapsTo(MISCREG_ICC_IAR1
);
4575 InitReg(MISCREG_ICC_EOIR1_EL1
)
4576 .res0(0xFF000000) // [31:24]
4577 .allPrivileges().exceptUserMode().reads(0)
4578 .mapsTo(MISCREG_ICC_EOIR1
);
4579 InitReg(MISCREG_ICC_HPPIR1_EL1
)
4580 .allPrivileges().exceptUserMode().writes(0)
4581 .mapsTo(MISCREG_ICC_HPPIR1
);
4582 InitReg(MISCREG_ICC_BPR1_EL1
)
4584 .mapsTo(MISCREG_ICC_BPR1
);
4585 InitReg(MISCREG_ICC_BPR1_EL1_NS
)
4587 .res0(0xfffffff8) // [31:3]
4588 .allPrivileges().exceptUserMode()
4589 .mapsTo(MISCREG_ICC_BPR1_NS
);
4590 InitReg(MISCREG_ICC_BPR1_EL1_S
)
4592 .res0(0xfffffff8) // [31:3]
4593 .secure().exceptUserMode()
4594 .mapsTo(MISCREG_ICC_BPR1_S
);
4595 InitReg(MISCREG_ICC_CTLR_EL1
)
4597 .mapsTo(MISCREG_ICC_CTLR
);
4598 InitReg(MISCREG_ICC_CTLR_EL1_NS
)
4600 .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
4601 .allPrivileges().exceptUserMode()
4602 .mapsTo(MISCREG_ICC_CTLR_NS
);
4603 InitReg(MISCREG_ICC_CTLR_EL1_S
)
4605 .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
4606 .secure().exceptUserMode()
4607 .mapsTo(MISCREG_ICC_CTLR_S
);
4608 InitReg(MISCREG_ICC_SRE_EL1
)
4610 .mapsTo(MISCREG_ICC_SRE
);
4611 InitReg(MISCREG_ICC_SRE_EL1_NS
)
4613 .res0(0xFFFFFFF8) // [31:3]
4614 .allPrivileges().exceptUserMode()
4615 .mapsTo(MISCREG_ICC_SRE_NS
);
4616 InitReg(MISCREG_ICC_SRE_EL1_S
)
4618 .res0(0xFFFFFFF8) // [31:3]
4619 .secure().exceptUserMode()
4620 .mapsTo(MISCREG_ICC_SRE_S
);
4621 InitReg(MISCREG_ICC_IGRPEN0_EL1
)
4622 .res0(0xFFFFFFFE) // [31:1]
4623 .allPrivileges().exceptUserMode()
4624 .mapsTo(MISCREG_ICC_IGRPEN0
);
4625 InitReg(MISCREG_ICC_IGRPEN1_EL1
)
4627 .mapsTo(MISCREG_ICC_IGRPEN1
);
4628 InitReg(MISCREG_ICC_IGRPEN1_EL1_NS
)
4630 .res0(0xFFFFFFFE) // [31:1]
4631 .allPrivileges().exceptUserMode()
4632 .mapsTo(MISCREG_ICC_IGRPEN1_NS
);
4633 InitReg(MISCREG_ICC_IGRPEN1_EL1_S
)
4635 .res0(0xFFFFFFFE) // [31:1]
4636 .secure().exceptUserMode()
4637 .mapsTo(MISCREG_ICC_IGRPEN1_S
);
4638 InitReg(MISCREG_ICC_SRE_EL2
)
4640 .mapsTo(MISCREG_ICC_HSRE
);
4641 InitReg(MISCREG_ICC_CTLR_EL3
)
4642 .allPrivileges().exceptUserMode()
4643 .mapsTo(MISCREG_ICC_MCTLR
);
4644 InitReg(MISCREG_ICC_SRE_EL3
)
4645 .allPrivileges().exceptUserMode()
4646 .mapsTo(MISCREG_ICC_MSRE
);
4647 InitReg(MISCREG_ICC_IGRPEN1_EL3
)
4648 .allPrivileges().exceptUserMode()
4649 .mapsTo(MISCREG_ICC_MGRPEN1
);
4651 InitReg(MISCREG_ICH_AP0R0_EL2
)
4653 .mapsTo(MISCREG_ICH_AP0R0
);
4654 InitReg(MISCREG_ICH_AP0R1_EL2
)
4657 .mapsTo(MISCREG_ICH_AP0R1
);
4658 InitReg(MISCREG_ICH_AP0R2_EL2
)
4661 .mapsTo(MISCREG_ICH_AP0R2
);
4662 InitReg(MISCREG_ICH_AP0R3_EL2
)
4665 .mapsTo(MISCREG_ICH_AP0R3
);
4666 InitReg(MISCREG_ICH_AP1R0_EL2
)
4668 .mapsTo(MISCREG_ICH_AP1R0
);
4669 InitReg(MISCREG_ICH_AP1R1_EL2
)
4672 .mapsTo(MISCREG_ICH_AP1R1
);
4673 InitReg(MISCREG_ICH_AP1R2_EL2
)
4676 .mapsTo(MISCREG_ICH_AP1R2
);
4677 InitReg(MISCREG_ICH_AP1R3_EL2
)
4680 .mapsTo(MISCREG_ICH_AP1R3
);
4681 InitReg(MISCREG_ICH_HCR_EL2
)
4683 .mapsTo(MISCREG_ICH_HCR
);
4684 InitReg(MISCREG_ICH_VTR_EL2
)
4685 .hyp().mon().writes(0)
4686 .mapsTo(MISCREG_ICH_VTR
);
4687 InitReg(MISCREG_ICH_MISR_EL2
)
4688 .hyp().mon().writes(0)
4689 .mapsTo(MISCREG_ICH_MISR
);
4690 InitReg(MISCREG_ICH_EISR_EL2
)
4691 .hyp().mon().writes(0)
4692 .mapsTo(MISCREG_ICH_EISR
);
4693 InitReg(MISCREG_ICH_ELRSR_EL2
)
4694 .hyp().mon().writes(0)
4695 .mapsTo(MISCREG_ICH_ELRSR
);
4696 InitReg(MISCREG_ICH_VMCR_EL2
)
4698 .mapsTo(MISCREG_ICH_VMCR
);
4699 InitReg(MISCREG_ICH_LR0_EL2
)
4701 .allPrivileges().exceptUserMode();
4702 InitReg(MISCREG_ICH_LR1_EL2
)
4704 .allPrivileges().exceptUserMode();
4705 InitReg(MISCREG_ICH_LR2_EL2
)
4707 .allPrivileges().exceptUserMode();
4708 InitReg(MISCREG_ICH_LR3_EL2
)
4710 .allPrivileges().exceptUserMode();
4711 InitReg(MISCREG_ICH_LR4_EL2
)
4713 .allPrivileges().exceptUserMode();
4714 InitReg(MISCREG_ICH_LR5_EL2
)
4716 .allPrivileges().exceptUserMode();
4717 InitReg(MISCREG_ICH_LR6_EL2
)
4719 .allPrivileges().exceptUserMode();
4720 InitReg(MISCREG_ICH_LR7_EL2
)
4722 .allPrivileges().exceptUserMode();
4723 InitReg(MISCREG_ICH_LR8_EL2
)
4725 .allPrivileges().exceptUserMode();
4726 InitReg(MISCREG_ICH_LR9_EL2
)
4728 .allPrivileges().exceptUserMode();
4729 InitReg(MISCREG_ICH_LR10_EL2
)
4731 .allPrivileges().exceptUserMode();
4732 InitReg(MISCREG_ICH_LR11_EL2
)
4734 .allPrivileges().exceptUserMode();
4735 InitReg(MISCREG_ICH_LR12_EL2
)
4737 .allPrivileges().exceptUserMode();
4738 InitReg(MISCREG_ICH_LR13_EL2
)
4740 .allPrivileges().exceptUserMode();
4741 InitReg(MISCREG_ICH_LR14_EL2
)
4743 .allPrivileges().exceptUserMode();
4744 InitReg(MISCREG_ICH_LR15_EL2
)
4746 .allPrivileges().exceptUserMode();
4749 InitReg(MISCREG_ICC_AP0R0
)
4750 .allPrivileges().exceptUserMode();
4751 InitReg(MISCREG_ICC_AP0R1
)
4752 .allPrivileges().exceptUserMode();
4753 InitReg(MISCREG_ICC_AP0R2
)
4754 .allPrivileges().exceptUserMode();
4755 InitReg(MISCREG_ICC_AP0R3
)
4756 .allPrivileges().exceptUserMode();
4757 InitReg(MISCREG_ICC_AP1R0
)
4758 .allPrivileges().exceptUserMode();
4759 InitReg(MISCREG_ICC_AP1R0_NS
)
4760 .allPrivileges().exceptUserMode();
4761 InitReg(MISCREG_ICC_AP1R0_S
)
4762 .allPrivileges().exceptUserMode();
4763 InitReg(MISCREG_ICC_AP1R1
)
4764 .allPrivileges().exceptUserMode();
4765 InitReg(MISCREG_ICC_AP1R1_NS
)
4766 .allPrivileges().exceptUserMode();
4767 InitReg(MISCREG_ICC_AP1R1_S
)
4768 .allPrivileges().exceptUserMode();
4769 InitReg(MISCREG_ICC_AP1R2
)
4770 .allPrivileges().exceptUserMode();
4771 InitReg(MISCREG_ICC_AP1R2_NS
)
4772 .allPrivileges().exceptUserMode();
4773 InitReg(MISCREG_ICC_AP1R2_S
)
4774 .allPrivileges().exceptUserMode();
4775 InitReg(MISCREG_ICC_AP1R3
)
4776 .allPrivileges().exceptUserMode();
4777 InitReg(MISCREG_ICC_AP1R3_NS
)
4778 .allPrivileges().exceptUserMode();
4779 InitReg(MISCREG_ICC_AP1R3_S
)
4780 .allPrivileges().exceptUserMode();
4781 InitReg(MISCREG_ICC_ASGI1R
)
4782 .allPrivileges().exceptUserMode().reads(0);
4783 InitReg(MISCREG_ICC_BPR0
)
4784 .allPrivileges().exceptUserMode();
4785 InitReg(MISCREG_ICC_BPR1
)
4786 .allPrivileges().exceptUserMode();
4787 InitReg(MISCREG_ICC_BPR1_NS
)
4788 .allPrivileges().exceptUserMode();
4789 InitReg(MISCREG_ICC_BPR1_S
)
4790 .allPrivileges().exceptUserMode();
4791 InitReg(MISCREG_ICC_CTLR
)
4792 .allPrivileges().exceptUserMode();
4793 InitReg(MISCREG_ICC_CTLR_NS
)
4794 .allPrivileges().exceptUserMode();
4795 InitReg(MISCREG_ICC_CTLR_S
)
4796 .allPrivileges().exceptUserMode();
4797 InitReg(MISCREG_ICC_DIR
)
4798 .allPrivileges().exceptUserMode().reads(0);
4799 InitReg(MISCREG_ICC_EOIR0
)
4800 .allPrivileges().exceptUserMode().reads(0);
4801 InitReg(MISCREG_ICC_EOIR1
)
4802 .allPrivileges().exceptUserMode().reads(0);
4803 InitReg(MISCREG_ICC_HPPIR0
)
4804 .allPrivileges().exceptUserMode().writes(0);
4805 InitReg(MISCREG_ICC_HPPIR1
)
4806 .allPrivileges().exceptUserMode().writes(0);
4807 InitReg(MISCREG_ICC_HSRE
)
4808 .allPrivileges().exceptUserMode();
4809 InitReg(MISCREG_ICC_IAR0
)
4810 .allPrivileges().exceptUserMode().writes(0);
4811 InitReg(MISCREG_ICC_IAR1
)
4812 .allPrivileges().exceptUserMode().writes(0);
4813 InitReg(MISCREG_ICC_IGRPEN0
)
4814 .allPrivileges().exceptUserMode();
4815 InitReg(MISCREG_ICC_IGRPEN1
)
4816 .allPrivileges().exceptUserMode();
4817 InitReg(MISCREG_ICC_IGRPEN1_NS
)
4818 .allPrivileges().exceptUserMode();
4819 InitReg(MISCREG_ICC_IGRPEN1_S
)
4820 .allPrivileges().exceptUserMode();
4821 InitReg(MISCREG_ICC_MCTLR
)
4822 .allPrivileges().exceptUserMode();
4823 InitReg(MISCREG_ICC_MGRPEN1
)
4824 .allPrivileges().exceptUserMode();
4825 InitReg(MISCREG_ICC_MSRE
)
4826 .allPrivileges().exceptUserMode();
4827 InitReg(MISCREG_ICC_PMR
)
4828 .allPrivileges().exceptUserMode();
4829 InitReg(MISCREG_ICC_RPR
)
4830 .allPrivileges().exceptUserMode().writes(0);
4831 InitReg(MISCREG_ICC_SGI0R
)
4832 .allPrivileges().exceptUserMode().reads(0);
4833 InitReg(MISCREG_ICC_SGI1R
)
4834 .allPrivileges().exceptUserMode().reads(0);
4835 InitReg(MISCREG_ICC_SRE
)
4836 .allPrivileges().exceptUserMode();
4837 InitReg(MISCREG_ICC_SRE_NS
)
4838 .allPrivileges().exceptUserMode();
4839 InitReg(MISCREG_ICC_SRE_S
)
4840 .allPrivileges().exceptUserMode();
4842 InitReg(MISCREG_ICH_AP0R0
)
4844 InitReg(MISCREG_ICH_AP0R1
)
4846 InitReg(MISCREG_ICH_AP0R2
)
4848 InitReg(MISCREG_ICH_AP0R3
)
4850 InitReg(MISCREG_ICH_AP1R0
)
4852 InitReg(MISCREG_ICH_AP1R1
)
4854 InitReg(MISCREG_ICH_AP1R2
)
4856 InitReg(MISCREG_ICH_AP1R3
)
4858 InitReg(MISCREG_ICH_HCR
)
4860 InitReg(MISCREG_ICH_VTR
)
4861 .hyp().mon().writes(0);
4862 InitReg(MISCREG_ICH_MISR
)
4863 .hyp().mon().writes(0);
4864 InitReg(MISCREG_ICH_EISR
)
4865 .hyp().mon().writes(0);
4866 InitReg(MISCREG_ICH_ELRSR
)
4867 .hyp().mon().writes(0);
4868 InitReg(MISCREG_ICH_VMCR
)
4870 InitReg(MISCREG_ICH_LR0
)
4872 InitReg(MISCREG_ICH_LR1
)
4874 InitReg(MISCREG_ICH_LR2
)
4876 InitReg(MISCREG_ICH_LR3
)
4878 InitReg(MISCREG_ICH_LR4
)
4880 InitReg(MISCREG_ICH_LR5
)
4882 InitReg(MISCREG_ICH_LR6
)
4884 InitReg(MISCREG_ICH_LR7
)
4886 InitReg(MISCREG_ICH_LR8
)
4888 InitReg(MISCREG_ICH_LR9
)
4890 InitReg(MISCREG_ICH_LR10
)
4892 InitReg(MISCREG_ICH_LR11
)
4894 InitReg(MISCREG_ICH_LR12
)
4896 InitReg(MISCREG_ICH_LR13
)
4898 InitReg(MISCREG_ICH_LR14
)
4900 InitReg(MISCREG_ICH_LR15
)
4902 InitReg(MISCREG_ICH_LRC0
)
4903 .mapsTo(MISCREG_ICH_LR0
)
4905 InitReg(MISCREG_ICH_LRC1
)
4906 .mapsTo(MISCREG_ICH_LR1
)
4908 InitReg(MISCREG_ICH_LRC2
)
4909 .mapsTo(MISCREG_ICH_LR2
)
4911 InitReg(MISCREG_ICH_LRC3
)
4912 .mapsTo(MISCREG_ICH_LR3
)
4914 InitReg(MISCREG_ICH_LRC4
)
4915 .mapsTo(MISCREG_ICH_LR4
)
4917 InitReg(MISCREG_ICH_LRC5
)
4918 .mapsTo(MISCREG_ICH_LR5
)
4920 InitReg(MISCREG_ICH_LRC6
)
4921 .mapsTo(MISCREG_ICH_LR6
)
4923 InitReg(MISCREG_ICH_LRC7
)
4924 .mapsTo(MISCREG_ICH_LR7
)
4926 InitReg(MISCREG_ICH_LRC8
)
4927 .mapsTo(MISCREG_ICH_LR8
)
4929 InitReg(MISCREG_ICH_LRC9
)
4930 .mapsTo(MISCREG_ICH_LR9
)
4932 InitReg(MISCREG_ICH_LRC10
)
4933 .mapsTo(MISCREG_ICH_LR10
)
4935 InitReg(MISCREG_ICH_LRC11
)
4936 .mapsTo(MISCREG_ICH_LR11
)
4938 InitReg(MISCREG_ICH_LRC12
)
4939 .mapsTo(MISCREG_ICH_LR12
)
4941 InitReg(MISCREG_ICH_LRC13
)
4942 .mapsTo(MISCREG_ICH_LR13
)
4944 InitReg(MISCREG_ICH_LRC14
)
4945 .mapsTo(MISCREG_ICH_LR14
)
4947 InitReg(MISCREG_ICH_LRC15
)
4948 .mapsTo(MISCREG_ICH_LR15
)
4951 InitReg(MISCREG_CNTHV_CTL_EL2
)
4953 InitReg(MISCREG_CNTHV_CVAL_EL2
)
4955 InitReg(MISCREG_CNTHV_TVAL_EL2
)
4959 InitReg(MISCREG_ID_AA64ZFR0_EL1
)
4960 .allPrivileges().exceptUserMode().writes(0);
4961 InitReg(MISCREG_ZCR_EL3
)
4963 InitReg(MISCREG_ZCR_EL2
)
4965 InitReg(MISCREG_ZCR_EL12
)
4966 .unimplemented().warnNotFail();
4967 InitReg(MISCREG_ZCR_EL1
)
4968 .allPrivileges().exceptUserMode();
4971 InitReg(MISCREG_NOP
)
4973 InitReg(MISCREG_RAZ
)
4974 .allPrivileges().exceptUserMode().writes(0);
4975 InitReg(MISCREG_CP14_UNIMPL
)
4978 InitReg(MISCREG_CP15_UNIMPL
)
4981 InitReg(MISCREG_UNKNOWN
);
4982 InitReg(MISCREG_IMPDEF_UNIMPL
)
4984 .warnNotFail(impdefAsNop
);
4986 // RAS extension (unimplemented)
4987 InitReg(MISCREG_ERRIDR_EL1
)
4990 InitReg(MISCREG_ERRSELR_EL1
)
4993 InitReg(MISCREG_ERXFR_EL1
)
4996 InitReg(MISCREG_ERXCTLR_EL1
)
4999 InitReg(MISCREG_ERXSTATUS_EL1
)
5002 InitReg(MISCREG_ERXADDR_EL1
)
5005 InitReg(MISCREG_ERXMISC0_EL1
)
5008 InitReg(MISCREG_ERXMISC1_EL1
)
5011 InitReg(MISCREG_DISR_EL1
)
5014 InitReg(MISCREG_VSESR_EL2
)
5017 InitReg(MISCREG_VDISR_EL2
)
5021 // Register mappings for some unimplemented registers:
5025 // DBGDTR_EL0 -> DBGDTR{R or T}Xint
5026 // DBGDTRRX_EL0 -> DBGDTRRXint
5027 // DBGDTRTX_EL0 -> DBGDTRRXint
5028 // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
5033 } // namespace ArmISA