projects / gem5.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
arm: Use static_cast to get access the ARM specific ISA functions.
[gem5.git] / src / arch / arm / miscregs.cc
1 /*
2 * Copyright (c) 2010-2013, 2015-2020 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 * Giacomo Gabrielli
40 */
41
42 #include "arch/arm/miscregs.hh"
43
44 #include <tuple>
45
46 #include "arch/arm/isa.hh"
47 #include "base/logging.hh"
48 #include "cpu/thread_context.hh"
49 #include "sim/full_system.hh"
50
51 namespace ArmISA
52 {
53
54 MiscRegIndex
55 decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
56 {
57 switch(crn) {
58 case 0:
59 switch (opc1) {
60 case 0:
61 switch (opc2) {
62 case 0:
63 switch (crm) {
64 case 0:
65 return MISCREG_DBGDIDR;
66 case 1:
67 return MISCREG_DBGDSCRint;
68 }
69 break;
70 }
71 break;
72 case 7:
73 switch (opc2) {
74 case 0:
75 switch (crm) {
76 case 0:
77 return MISCREG_JIDR;
78 }
79 break;
80 }
81 break;
82 }
83 break;
84 case 1:
85 switch (opc1) {
86 case 6:
87 switch (crm) {
88 case 0:
89 switch (opc2) {
90 case 0:
91 return MISCREG_TEEHBR;
92 }
93 break;
94 }
95 break;
96 case 7:
97 switch (crm) {
98 case 0:
99 switch (opc2) {
100 case 0:
101 return MISCREG_JOSCR;
102 }
103 break;
104 }
105 break;
106 }
107 break;
108 case 2:
109 switch (opc1) {
110 case 7:
111 switch (crm) {
112 case 0:
113 switch (opc2) {
114 case 0:
115 return MISCREG_JMCR;
116 }
117 break;
118 }
119 break;
120 }
121 break;
122 }
123 // If we get here then it must be a register that we haven't implemented
124 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
125 crn, opc1, crm, opc2);
126 return MISCREG_CP14_UNIMPL;
127 }
128
129 using namespace std;
130
131 MiscRegIndex
132 decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
133 {
134 switch (crn) {
135 case 0:
136 switch (opc1) {
137 case 0:
138 switch (crm) {
139 case 0:
140 switch (opc2) {
141 case 1:
142 return MISCREG_CTR;
143 case 2:
144 return MISCREG_TCMTR;
145 case 3:
146 return MISCREG_TLBTR;
147 case 5:
148 return MISCREG_MPIDR;
149 case 6:
150 return MISCREG_REVIDR;
151 default:
152 return MISCREG_MIDR;
153 }
154 break;
155 case 1:
156 switch (opc2) {
157 case 0:
158 return MISCREG_ID_PFR0;
159 case 1:
160 return MISCREG_ID_PFR1;
161 case 2:
162 return MISCREG_ID_DFR0;
163 case 3:
164 return MISCREG_ID_AFR0;
165 case 4:
166 return MISCREG_ID_MMFR0;
167 case 5:
168 return MISCREG_ID_MMFR1;
169 case 6:
170 return MISCREG_ID_MMFR2;
171 case 7:
172 return MISCREG_ID_MMFR3;
173 }
174 break;
175 case 2:
176 switch (opc2) {
177 case 0:
178 return MISCREG_ID_ISAR0;
179 case 1:
180 return MISCREG_ID_ISAR1;
181 case 2:
182 return MISCREG_ID_ISAR2;
183 case 3:
184 return MISCREG_ID_ISAR3;
185 case 4:
186 return MISCREG_ID_ISAR4;
187 case 5:
188 return MISCREG_ID_ISAR5;
189 case 6:
190 case 7:
191 return MISCREG_RAZ; // read as zero
192 }
193 break;
194 default:
195 return MISCREG_RAZ; // read as zero
196 }
197 break;
198 case 1:
199 if (crm == 0) {
200 switch (opc2) {
201 case 0:
202 return MISCREG_CCSIDR;
203 case 1:
204 return MISCREG_CLIDR;
205 case 7:
206 return MISCREG_AIDR;
207 }
208 }
209 break;
210 case 2:
211 if (crm == 0 && opc2 == 0) {
212 return MISCREG_CSSELR;
213 }
214 break;
215 case 4:
216 if (crm == 0) {
217 if (opc2 == 0)
218 return MISCREG_VPIDR;
219 else if (opc2 == 5)
220 return MISCREG_VMPIDR;
221 }
222 break;
223 }
224 break;
225 case 1:
226 if (opc1 == 0) {
227 if (crm == 0) {
228 switch (opc2) {
229 case 0:
230 return MISCREG_SCTLR;
231 case 1:
232 return MISCREG_ACTLR;
233 case 0x2:
234 return MISCREG_CPACR;
235 }
236 } else if (crm == 1) {
237 switch (opc2) {
238 case 0:
239 return MISCREG_SCR;
240 case 1:
241 return MISCREG_SDER;
242 case 2:
243 return MISCREG_NSACR;
244 }
245 }
246 } else if (opc1 == 4) {
247 if (crm == 0) {
248 if (opc2 == 0)
249 return MISCREG_HSCTLR;
250 else if (opc2 == 1)
251 return MISCREG_HACTLR;
252 } else if (crm == 1) {
253 switch (opc2) {
254 case 0:
255 return MISCREG_HCR;
256 case 1:
257 return MISCREG_HDCR;
258 case 2:
259 return MISCREG_HCPTR;
260 case 4:
261 return MISCREG_HCR2;
262 case 3:
263 return MISCREG_HSTR;
264 case 7:
265 return MISCREG_HACR;
266 }
267 }
268 }
269 break;
270 case 2:
271 if (opc1 == 0 && crm == 0) {
272 switch (opc2) {
273 case 0:
274 return MISCREG_TTBR0;
275 case 1:
276 return MISCREG_TTBR1;
277 case 2:
278 return MISCREG_TTBCR;
279 }
280 } else if (opc1 == 4) {
281 if (crm == 0 && opc2 == 2)
282 return MISCREG_HTCR;
283 else if (crm == 1 && opc2 == 2)
284 return MISCREG_VTCR;
285 }
286 break;
287 case 3:
288 if (opc1 == 0 && crm == 0 && opc2 == 0) {
289 return MISCREG_DACR;
290 }
291 break;
292 case 4:
293 if (opc1 == 0 && crm == 6 && opc2 == 0) {
294 return MISCREG_ICC_PMR;
295 }
296 break;
297 case 5:
298 if (opc1 == 0) {
299 if (crm == 0) {
300 if (opc2 == 0) {
301 return MISCREG_DFSR;
302 } else if (opc2 == 1) {
303 return MISCREG_IFSR;
304 }
305 } else if (crm == 1) {
306 if (opc2 == 0) {
307 return MISCREG_ADFSR;
308 } else if (opc2 == 1) {
309 return MISCREG_AIFSR;
310 }
311 }
312 } else if (opc1 == 4) {
313 if (crm == 1) {
314 if (opc2 == 0)
315 return MISCREG_HADFSR;
316 else if (opc2 == 1)
317 return MISCREG_HAIFSR;
318 } else if (crm == 2 && opc2 == 0) {
319 return MISCREG_HSR;
320 }
321 }
322 break;
323 case 6:
324 if (opc1 == 0 && crm == 0) {
325 switch (opc2) {
326 case 0:
327 return MISCREG_DFAR;
328 case 2:
329 return MISCREG_IFAR;
330 }
331 } else if (opc1 == 4 && crm == 0) {
332 switch (opc2) {
333 case 0:
334 return MISCREG_HDFAR;
335 case 2:
336 return MISCREG_HIFAR;
337 case 4:
338 return MISCREG_HPFAR;
339 }
340 }
341 break;
342 case 7:
343 if (opc1 == 0) {
344 switch (crm) {
345 case 0:
346 if (opc2 == 4) {
347 return MISCREG_NOP;
348 }
349 break;
350 case 1:
351 switch (opc2) {
352 case 0:
353 return MISCREG_ICIALLUIS;
354 case 6:
355 return MISCREG_BPIALLIS;
356 }
357 break;
358 case 4:
359 if (opc2 == 0) {
360 return MISCREG_PAR;
361 }
362 break;
363 case 5:
364 switch (opc2) {
365 case 0:
366 return MISCREG_ICIALLU;
367 case 1:
368 return MISCREG_ICIMVAU;
369 case 4:
370 return MISCREG_CP15ISB;
371 case 6:
372 return MISCREG_BPIALL;
373 case 7:
374 return MISCREG_BPIMVA;
375 }
376 break;
377 case 6:
378 if (opc2 == 1) {
379 return MISCREG_DCIMVAC;
380 } else if (opc2 == 2) {
381 return MISCREG_DCISW;
382 }
383 break;
384 case 8:
385 switch (opc2) {
386 case 0:
387 return MISCREG_ATS1CPR;
388 case 1:
389 return MISCREG_ATS1CPW;
390 case 2:
391 return MISCREG_ATS1CUR;
392 case 3:
393 return MISCREG_ATS1CUW;
394 case 4:
395 return MISCREG_ATS12NSOPR;
396 case 5:
397 return MISCREG_ATS12NSOPW;
398 case 6:
399 return MISCREG_ATS12NSOUR;
400 case 7:
401 return MISCREG_ATS12NSOUW;
402 }
403 break;
404 case 10:
405 switch (opc2) {
406 case 1:
407 return MISCREG_DCCMVAC;
408 case 2:
409 return MISCREG_DCCSW;
410 case 4:
411 return MISCREG_CP15DSB;
412 case 5:
413 return MISCREG_CP15DMB;
414 }
415 break;
416 case 11:
417 if (opc2 == 1) {
418 return MISCREG_DCCMVAU;
419 }
420 break;
421 case 13:
422 if (opc2 == 1) {
423 return MISCREG_NOP;
424 }
425 break;
426 case 14:
427 if (opc2 == 1) {
428 return MISCREG_DCCIMVAC;
429 } else if (opc2 == 2) {
430 return MISCREG_DCCISW;
431 }
432 break;
433 }
434 } else if (opc1 == 4 && crm == 8) {
435 if (opc2 == 0)
436 return MISCREG_ATS1HR;
437 else if (opc2 == 1)
438 return MISCREG_ATS1HW;
439 }
440 break;
441 case 8:
442 if (opc1 == 0) {
443 switch (crm) {
444 case 3:
445 switch (opc2) {
446 case 0:
447 return MISCREG_TLBIALLIS;
448 case 1:
449 return MISCREG_TLBIMVAIS;
450 case 2:
451 return MISCREG_TLBIASIDIS;
452 case 3:
453 return MISCREG_TLBIMVAAIS;
454 case 5:
455 return MISCREG_TLBIMVALIS;
456 case 7:
457 return MISCREG_TLBIMVAALIS;
458 }
459 break;
460 case 5:
461 switch (opc2) {
462 case 0:
463 return MISCREG_ITLBIALL;
464 case 1:
465 return MISCREG_ITLBIMVA;
466 case 2:
467 return MISCREG_ITLBIASID;
468 }
469 break;
470 case 6:
471 switch (opc2) {
472 case 0:
473 return MISCREG_DTLBIALL;
474 case 1:
475 return MISCREG_DTLBIMVA;
476 case 2:
477 return MISCREG_DTLBIASID;
478 }
479 break;
480 case 7:
481 switch (opc2) {
482 case 0:
483 return MISCREG_TLBIALL;
484 case 1:
485 return MISCREG_TLBIMVA;
486 case 2:
487 return MISCREG_TLBIASID;
488 case 3:
489 return MISCREG_TLBIMVAA;
490 case 5:
491 return MISCREG_TLBIMVAL;
492 case 7:
493 return MISCREG_TLBIMVAAL;
494 }
495 break;
496 }
497 } else if (opc1 == 4) {
498 if (crm == 0) {
499 switch (opc2) {
500 case 1:
501 return MISCREG_TLBIIPAS2IS;
502 case 5:
503 return MISCREG_TLBIIPAS2LIS;
504 }
505 } else if (crm == 3) {
506 switch (opc2) {
507 case 0:
508 return MISCREG_TLBIALLHIS;
509 case 1:
510 return MISCREG_TLBIMVAHIS;
511 case 4:
512 return MISCREG_TLBIALLNSNHIS;
513 case 5:
514 return MISCREG_TLBIMVALHIS;
515 }
516 } else if (crm == 4) {
517 switch (opc2) {
518 case 1:
519 return MISCREG_TLBIIPAS2;
520 case 5:
521 return MISCREG_TLBIIPAS2L;
522 }
523 } else if (crm == 7) {
524 switch (opc2) {
525 case 0:
526 return MISCREG_TLBIALLH;
527 case 1:
528 return MISCREG_TLBIMVAH;
529 case 4:
530 return MISCREG_TLBIALLNSNH;
531 case 5:
532 return MISCREG_TLBIMVALH;
533 }
534 }
535 }
536 break;
537 case 9:
538 // Every cop register with CRn = 9 and CRm in
539 // {0-2}, {5-8} is implementation defined regardless
540 // of opc1 and opc2.
541 switch (crm) {
542 case 0:
543 case 1:
544 case 2:
545 case 5:
546 case 6:
547 case 7:
548 case 8:
549 return MISCREG_IMPDEF_UNIMPL;
550 }
551 if (opc1 == 0) {
552 switch (crm) {
553 case 12:
554 switch (opc2) {
555 case 0:
556 return MISCREG_PMCR;
557 case 1:
558 return MISCREG_PMCNTENSET;
559 case 2:
560 return MISCREG_PMCNTENCLR;
561 case 3:
562 return MISCREG_PMOVSR;
563 case 4:
564 return MISCREG_PMSWINC;
565 case 5:
566 return MISCREG_PMSELR;
567 case 6:
568 return MISCREG_PMCEID0;
569 case 7:
570 return MISCREG_PMCEID1;
571 }
572 break;
573 case 13:
574 switch (opc2) {
575 case 0:
576 return MISCREG_PMCCNTR;
577 case 1:
578 // Selector is PMSELR.SEL
579 return MISCREG_PMXEVTYPER_PMCCFILTR;
580 case 2:
581 return MISCREG_PMXEVCNTR;
582 }
583 break;
584 case 14:
585 switch (opc2) {
586 case 0:
587 return MISCREG_PMUSERENR;
588 case 1:
589 return MISCREG_PMINTENSET;
590 case 2:
591 return MISCREG_PMINTENCLR;
592 case 3:
593 return MISCREG_PMOVSSET;
594 }
595 break;
596 }
597 } else if (opc1 == 1) {
598 switch (crm) {
599 case 0:
600 switch (opc2) {
601 case 2: // L2CTLR, L2 Control Register
602 return MISCREG_L2CTLR;
603 case 3:
604 return MISCREG_L2ECTLR;
605 }
606 break;
607 break;
608 }
609 }
610 break;
611 case 10:
612 if (opc1 == 0) {
613 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
614 if (crm < 2) {
615 return MISCREG_IMPDEF_UNIMPL;
616 } else if (crm == 2) { // TEX Remap Registers
617 if (opc2 == 0) {
618 // Selector is TTBCR.EAE
619 return MISCREG_PRRR_MAIR0;
620 } else if (opc2 == 1) {
621 // Selector is TTBCR.EAE
622 return MISCREG_NMRR_MAIR1;
623 }
624 } else if (crm == 3) {
625 if (opc2 == 0) {
626 return MISCREG_AMAIR0;
627 } else if (opc2 == 1) {
628 return MISCREG_AMAIR1;
629 }
630 }
631 } else if (opc1 == 4) {
632 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
633 if (crm == 2) {
634 if (opc2 == 0)
635 return MISCREG_HMAIR0;
636 else if (opc2 == 1)
637 return MISCREG_HMAIR1;
638 } else if (crm == 3) {
639 if (opc2 == 0)
640 return MISCREG_HAMAIR0;
641 else if (opc2 == 1)
642 return MISCREG_HAMAIR1;
643 }
644 }
645 break;
646 case 11:
647 if (opc1 <=7) {
648 switch (crm) {
649 case 0:
650 case 1:
651 case 2:
652 case 3:
653 case 4:
654 case 5:
655 case 6:
656 case 7:
657 case 8:
658 case 15:
659 // Reserved for DMA operations for TCM access
660 return MISCREG_IMPDEF_UNIMPL;
661 default:
662 break;
663 }
664 }
665 break;
666 case 12:
667 if (opc1 == 0) {
668 if (crm == 0) {
669 if (opc2 == 0) {
670 return MISCREG_VBAR;
671 } else if (opc2 == 1) {
672 return MISCREG_MVBAR;
673 }
674 } else if (crm == 1) {
675 if (opc2 == 0) {
676 return MISCREG_ISR;
677 }
678 } else if (crm == 8) {
679 switch (opc2) {
680 case 0:
681 return MISCREG_ICC_IAR0;
682 case 1:
683 return MISCREG_ICC_EOIR0;
684 case 2:
685 return MISCREG_ICC_HPPIR0;
686 case 3:
687 return MISCREG_ICC_BPR0;
688 case 4:
689 return MISCREG_ICC_AP0R0;
690 case 5:
691 return MISCREG_ICC_AP0R1;
692 case 6:
693 return MISCREG_ICC_AP0R2;
694 case 7:
695 return MISCREG_ICC_AP0R3;
696 }
697 } else if (crm == 9) {
698 switch (opc2) {
699 case 0:
700 return MISCREG_ICC_AP1R0;
701 case 1:
702 return MISCREG_ICC_AP1R1;
703 case 2:
704 return MISCREG_ICC_AP1R2;
705 case 3:
706 return MISCREG_ICC_AP1R3;
707 }
708 } else if (crm == 11) {
709 switch (opc2) {
710 case 1:
711 return MISCREG_ICC_DIR;
712 case 3:
713 return MISCREG_ICC_RPR;
714 }
715 } else if (crm == 12) {
716 switch (opc2) {
717 case 0:
718 return MISCREG_ICC_IAR1;
719 case 1:
720 return MISCREG_ICC_EOIR1;
721 case 2:
722 return MISCREG_ICC_HPPIR1;
723 case 3:
724 return MISCREG_ICC_BPR1;
725 case 4:
726 return MISCREG_ICC_CTLR;
727 case 5:
728 return MISCREG_ICC_SRE;
729 case 6:
730 return MISCREG_ICC_IGRPEN0;
731 case 7:
732 return MISCREG_ICC_IGRPEN1;
733 }
734 }
735 } else if (opc1 == 4) {
736 if (crm == 0 && opc2 == 0) {
737 return MISCREG_HVBAR;
738 } else if (crm == 8) {
739 switch (opc2) {
740 case 0:
741 return MISCREG_ICH_AP0R0;
742 case 1:
743 return MISCREG_ICH_AP0R1;
744 case 2:
745 return MISCREG_ICH_AP0R2;
746 case 3:
747 return MISCREG_ICH_AP0R3;
748 }
749 } else if (crm == 9) {
750 switch (opc2) {
751 case 0:
752 return MISCREG_ICH_AP1R0;
753 case 1:
754 return MISCREG_ICH_AP1R1;
755 case 2:
756 return MISCREG_ICH_AP1R2;
757 case 3:
758 return MISCREG_ICH_AP1R3;
759 case 5:
760 return MISCREG_ICC_HSRE;
761 }
762 } else if (crm == 11) {
763 switch (opc2) {
764 case 0:
765 return MISCREG_ICH_HCR;
766 case 1:
767 return MISCREG_ICH_VTR;
768 case 2:
769 return MISCREG_ICH_MISR;
770 case 3:
771 return MISCREG_ICH_EISR;
772 case 5:
773 return MISCREG_ICH_ELRSR;
774 case 7:
775 return MISCREG_ICH_VMCR;
776 }
777 } else if (crm == 12) {
778 switch (opc2) {
779 case 0:
780 return MISCREG_ICH_LR0;
781 case 1:
782 return MISCREG_ICH_LR1;
783 case 2:
784 return MISCREG_ICH_LR2;
785 case 3:
786 return MISCREG_ICH_LR3;
787 case 4:
788 return MISCREG_ICH_LR4;
789 case 5:
790 return MISCREG_ICH_LR5;
791 case 6:
792 return MISCREG_ICH_LR6;
793 case 7:
794 return MISCREG_ICH_LR7;
795 }
796 } else if (crm == 13) {
797 switch (opc2) {
798 case 0:
799 return MISCREG_ICH_LR8;
800 case 1:
801 return MISCREG_ICH_LR9;
802 case 2:
803 return MISCREG_ICH_LR10;
804 case 3:
805 return MISCREG_ICH_LR11;
806 case 4:
807 return MISCREG_ICH_LR12;
808 case 5:
809 return MISCREG_ICH_LR13;
810 case 6:
811 return MISCREG_ICH_LR14;
812 case 7:
813 return MISCREG_ICH_LR15;
814 }
815 } else if (crm == 14) {
816 switch (opc2) {
817 case 0:
818 return MISCREG_ICH_LRC0;
819 case 1:
820 return MISCREG_ICH_LRC1;
821 case 2:
822 return MISCREG_ICH_LRC2;
823 case 3:
824 return MISCREG_ICH_LRC3;
825 case 4:
826 return MISCREG_ICH_LRC4;
827 case 5:
828 return MISCREG_ICH_LRC5;
829 case 6:
830 return MISCREG_ICH_LRC6;
831 case 7:
832 return MISCREG_ICH_LRC7;
833 }
834 } else if (crm == 15) {
835 switch (opc2) {
836 case 0:
837 return MISCREG_ICH_LRC8;
838 case 1:
839 return MISCREG_ICH_LRC9;
840 case 2:
841 return MISCREG_ICH_LRC10;
842 case 3:
843 return MISCREG_ICH_LRC11;
844 case 4:
845 return MISCREG_ICH_LRC12;
846 case 5:
847 return MISCREG_ICH_LRC13;
848 case 6:
849 return MISCREG_ICH_LRC14;
850 case 7:
851 return MISCREG_ICH_LRC15;
852 }
853 }
854 } else if (opc1 == 6) {
855 if (crm == 12) {
856 switch (opc2) {
857 case 4:
858 return MISCREG_ICC_MCTLR;
859 case 5:
860 return MISCREG_ICC_MSRE;
861 case 7:
862 return MISCREG_ICC_MGRPEN1;
863 }
864 }
865 }
866 break;
867 case 13:
868 if (opc1 == 0) {
869 if (crm == 0) {
870 switch (opc2) {
871 case 0:
872 return MISCREG_FCSEIDR;
873 case 1:
874 return MISCREG_CONTEXTIDR;
875 case 2:
876 return MISCREG_TPIDRURW;
877 case 3:
878 return MISCREG_TPIDRURO;
879 case 4:
880 return MISCREG_TPIDRPRW;
881 }
882 }
883 } else if (opc1 == 4) {
884 if (crm == 0 && opc2 == 2)
885 return MISCREG_HTPIDR;
886 }
887 break;
888 case 14:
889 if (opc1 == 0) {
890 switch (crm) {
891 case 0:
892 if (opc2 == 0)
893 return MISCREG_CNTFRQ;
894 break;
895 case 1:
896 if (opc2 == 0)
897 return MISCREG_CNTKCTL;
898 break;
899 case 2:
900 if (opc2 == 0)
901 return MISCREG_CNTP_TVAL;
902 else if (opc2 == 1)
903 return MISCREG_CNTP_CTL;
904 break;
905 case 3:
906 if (opc2 == 0)
907 return MISCREG_CNTV_TVAL;
908 else if (opc2 == 1)
909 return MISCREG_CNTV_CTL;
910 break;
911 }
912 } else if (opc1 == 4) {
913 if (crm == 1 && opc2 == 0) {
914 return MISCREG_CNTHCTL;
915 } else if (crm == 2) {
916 if (opc2 == 0)
917 return MISCREG_CNTHP_TVAL;
918 else if (opc2 == 1)
919 return MISCREG_CNTHP_CTL;
920 }
921 }
922 break;
923 case 15:
924 // Implementation defined
925 return MISCREG_IMPDEF_UNIMPL;
926 }
927 // Unrecognized register
928 return MISCREG_CP15_UNIMPL;
929 }
930
931 MiscRegIndex
932 decodeCP15Reg64(unsigned crm, unsigned opc1)
933 {
934 switch (crm) {
935 case 2:
936 switch (opc1) {
937 case 0:
938 return MISCREG_TTBR0;
939 case 1:
940 return MISCREG_TTBR1;
941 case 4:
942 return MISCREG_HTTBR;
943 case 6:
944 return MISCREG_VTTBR;
945 }
946 break;
947 case 7:
948 if (opc1 == 0)
949 return MISCREG_PAR;
950 break;
951 case 14:
952 switch (opc1) {
953 case 0:
954 return MISCREG_CNTPCT;
955 case 1:
956 return MISCREG_CNTVCT;
957 case 2:
958 return MISCREG_CNTP_CVAL;
959 case 3:
960 return MISCREG_CNTV_CVAL;
961 case 4:
962 return MISCREG_CNTVOFF;
963 case 6:
964 return MISCREG_CNTHP_CVAL;
965 }
966 break;
967 case 12:
968 switch (opc1) {
969 case 0:
970 return MISCREG_ICC_SGI1R;
971 case 1:
972 return MISCREG_ICC_ASGI1R;
973 case 2:
974 return MISCREG_ICC_SGI0R;
975 default:
976 break;
977 }
978 break;
979 case 15:
980 if (opc1 == 0)
981 return MISCREG_CPUMERRSR;
982 else if (opc1 == 1)
983 return MISCREG_L2MERRSR;
984 break;
985 }
986 // Unrecognized register
987 return MISCREG_CP15_UNIMPL;
988 }
989
990 std::tuple<bool, bool>
991 canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
992 {
993 bool secure = !scr.ns;
994 bool canRead = false;
995 bool undefined = false;
996
997 switch (cpsr.mode) {
998 case MODE_USER:
999 canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
1000 miscRegInfo[reg][MISCREG_USR_NS_RD];
1001 break;
1002 case MODE_FIQ:
1003 case MODE_IRQ:
1004 case MODE_SVC:
1005 case MODE_ABORT:
1006 case MODE_UNDEFINED:
1007 case MODE_SYSTEM:
1008 canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1009 miscRegInfo[reg][MISCREG_PRI_NS_RD];
1010 break;
1011 case MODE_MON:
1012 canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1013 miscRegInfo[reg][MISCREG_MON_NS1_RD];
1014 break;
1015 case MODE_HYP:
1016 canRead = miscRegInfo[reg][MISCREG_HYP_RD];
1017 break;
1018 default:
1019 undefined = true;
1020 }
1021 // can't do permissions checkes on the root of a banked pair of regs
1022 assert(!miscRegInfo[reg][MISCREG_BANKED]);
1023 return std::make_tuple(canRead, undefined);
1024 }
1025
1026 std::tuple<bool, bool>
1027 canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
1028 {
1029 bool secure = !scr.ns;
1030 bool canWrite = false;
1031 bool undefined = false;
1032
1033 switch (cpsr.mode) {
1034 case MODE_USER:
1035 canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1036 miscRegInfo[reg][MISCREG_USR_NS_WR];
1037 break;
1038 case MODE_FIQ:
1039 case MODE_IRQ:
1040 case MODE_SVC:
1041 case MODE_ABORT:
1042 case MODE_UNDEFINED:
1043 case MODE_SYSTEM:
1044 canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1045 miscRegInfo[reg][MISCREG_PRI_NS_WR];
1046 break;
1047 case MODE_MON:
1048 canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1049 miscRegInfo[reg][MISCREG_MON_NS1_WR];
1050 break;
1051 case MODE_HYP:
1052 canWrite = miscRegInfo[reg][MISCREG_HYP_WR];
1053 break;
1054 default:
1055 undefined = true;
1056 }
1057 // can't do permissions checkes on the root of a banked pair of regs
1058 assert(!miscRegInfo[reg][MISCREG_BANKED]);
1059 return std::make_tuple(canWrite, undefined);
1060 }
1061
1062 int
1063 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
1064 {
1065 SCR scr = tc->readMiscReg(MISCREG_SCR);
1066 return snsBankedIndex(reg, tc, scr.ns);
1067 }
1068
1069 int
1070 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
1071 {
1072 int reg_as_int = static_cast<int>(reg);
1073 if (miscRegInfo[reg][MISCREG_BANKED]) {
1074 reg_as_int += (ArmSystem::haveSecurity(tc) &&
1075 !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
1076 }
1077 return reg_as_int;
1078 }
1079
1080 int
1081 snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc)
1082 {
1083 auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
1084 SCR scr = tc->readMiscReg(MISCREG_SCR);
1085 return isa->snsBankedIndex64(reg, scr.ns);
1086 }
1087
1088 /**
1089 * If the reg is a child reg of a banked set, then the parent is the last
1090 * banked one in the list. This is messy, and the wish is to eventually have
1091 * the bitmap replaced with a better data structure. the preUnflatten function
1092 * initializes a lookup table to speed up the search for these banked
1093 * registers.
1094 */
1095
1096 int unflattenResultMiscReg[NUM_MISCREGS];
1097
1098 void
1099 preUnflattenMiscReg()
1100 {
1101 int reg = -1;
1102 for (int i = 0 ; i < NUM_MISCREGS; i++){
1103 if (miscRegInfo[i][MISCREG_BANKED])
1104 reg = i;
1105 if (miscRegInfo[i][MISCREG_BANKED_CHILD])
1106 unflattenResultMiscReg[i] = reg;
1107 else
1108 unflattenResultMiscReg[i] = i;
1109 // if this assert fails, no parent was found, and something is broken
1110 assert(unflattenResultMiscReg[i] > -1);
1111 }
1112 }
1113
1114 int
1115 unflattenMiscReg(int reg)
1116 {
1117 return unflattenResultMiscReg[reg];
1118 }
1119
1120 bool
1121 canReadAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
1122 ThreadContext *tc)
1123 {
1124 // Check for SP_EL0 access while SPSEL == 0
1125 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1126 return false;
1127
1128 // Check for RVBAR access
1129 if (reg == MISCREG_RVBAR_EL1) {
1130 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1131 if (highest_el == EL2 || highest_el == EL3)
1132 return false;
1133 }
1134 if (reg == MISCREG_RVBAR_EL2) {
1135 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1136 if (highest_el == EL3)
1137 return false;
1138 }
1139
1140 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
1141 bool el2_host = EL2Enabled(tc) && hcr.e2h;
1142
1143 switch (currEL(cpsr)) {
1144 case EL0:
1145 return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
1146 miscRegInfo[reg][MISCREG_USR_NS_RD];
1147 case EL1:
1148 return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1149 miscRegInfo[reg][MISCREG_PRI_NS_RD];
1150 case EL2:
1151 return el2_host ? miscRegInfo[reg][MISCREG_HYP_E2H_RD] :
1152 miscRegInfo[reg][MISCREG_HYP_RD];
1153 case EL3:
1154 return el2_host ? miscRegInfo[reg][MISCREG_MON_E2H_RD] :
1155 secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1156 miscRegInfo[reg][MISCREG_MON_NS1_RD];
1157 default:
1158 panic("Invalid exception level");
1159 }
1160 }
1161
1162 bool
1163 canWriteAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
1164 ThreadContext *tc)
1165 {
1166 // Check for SP_EL0 access while SPSEL == 0
1167 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1168 return false;
1169 ExceptionLevel el = currEL(cpsr);
1170 if (reg == MISCREG_DAIF) {
1171 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1172 if (el == EL0 && !sctlr.uma)
1173 return false;
1174 }
1175 if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
1176 // In syscall-emulation mode, this test is skipped and DCZVA is always
1177 // allowed at EL0
1178 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1179 if (el == EL0 && !sctlr.dze)
1180 return false;
1181 }
1182 if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
1183 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1184 if (el == EL0 && !sctlr.uci)
1185 return false;
1186 }
1187
1188 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
1189 bool el2_host = EL2Enabled(tc) && hcr.e2h;
1190
1191 switch (el) {
1192 case EL0:
1193 return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1194 miscRegInfo[reg][MISCREG_USR_NS_WR];
1195 case EL1:
1196 return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1197 miscRegInfo[reg][MISCREG_PRI_NS_WR];
1198 case EL2:
1199 return el2_host ? miscRegInfo[reg][MISCREG_HYP_E2H_WR] :
1200 miscRegInfo[reg][MISCREG_HYP_WR];
1201 case EL3:
1202 return el2_host ? miscRegInfo[reg][MISCREG_MON_E2H_WR] :
1203 secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1204 miscRegInfo[reg][MISCREG_MON_NS1_WR];
1205 default:
1206 panic("Invalid exception level");
1207 }
1208 }
1209
1210 MiscRegIndex
1211 decodeAArch64SysReg(unsigned op0, unsigned op1,
1212 unsigned crn, unsigned crm,
1213 unsigned op2)
1214 {
1215 switch (op0) {
1216 case 1:
1217 switch (crn) {
1218 case 7:
1219 switch (op1) {
1220 case 0:
1221 switch (crm) {
1222 case 1:
1223 switch (op2) {
1224 case 0:
1225 return MISCREG_IC_IALLUIS;
1226 }
1227 break;
1228 case 5:
1229 switch (op2) {
1230 case 0:
1231 return MISCREG_IC_IALLU;
1232 }
1233 break;
1234 case 6:
1235 switch (op2) {
1236 case 1:
1237 return MISCREG_DC_IVAC_Xt;
1238 case 2:
1239 return MISCREG_DC_ISW_Xt;
1240 }
1241 break;
1242 case 8:
1243 switch (op2) {
1244 case 0:
1245 return MISCREG_AT_S1E1R_Xt;
1246 case 1:
1247 return MISCREG_AT_S1E1W_Xt;
1248 case 2:
1249 return MISCREG_AT_S1E0R_Xt;
1250 case 3:
1251 return MISCREG_AT_S1E0W_Xt;
1252 }
1253 break;
1254 case 10:
1255 switch (op2) {
1256 case 2:
1257 return MISCREG_DC_CSW_Xt;
1258 }
1259 break;
1260 case 14:
1261 switch (op2) {
1262 case 2:
1263 return MISCREG_DC_CISW_Xt;
1264 }
1265 break;
1266 }
1267 break;
1268 case 3:
1269 switch (crm) {
1270 case 4:
1271 switch (op2) {
1272 case 1:
1273 return MISCREG_DC_ZVA_Xt;
1274 }
1275 break;
1276 case 5:
1277 switch (op2) {
1278 case 1:
1279 return MISCREG_IC_IVAU_Xt;
1280 }
1281 break;
1282 case 10:
1283 switch (op2) {
1284 case 1:
1285 return MISCREG_DC_CVAC_Xt;
1286 }
1287 break;
1288 case 11:
1289 switch (op2) {
1290 case 1:
1291 return MISCREG_DC_CVAU_Xt;
1292 }
1293 break;
1294 case 14:
1295 switch (op2) {
1296 case 1:
1297 return MISCREG_DC_CIVAC_Xt;
1298 }
1299 break;
1300 }
1301 break;
1302 case 4:
1303 switch (crm) {
1304 case 8:
1305 switch (op2) {
1306 case 0:
1307 return MISCREG_AT_S1E2R_Xt;
1308 case 1:
1309 return MISCREG_AT_S1E2W_Xt;
1310 case 4:
1311 return MISCREG_AT_S12E1R_Xt;
1312 case 5:
1313 return MISCREG_AT_S12E1W_Xt;
1314 case 6:
1315 return MISCREG_AT_S12E0R_Xt;
1316 case 7:
1317 return MISCREG_AT_S12E0W_Xt;
1318 }
1319 break;
1320 }
1321 break;
1322 case 6:
1323 switch (crm) {
1324 case 8:
1325 switch (op2) {
1326 case 0:
1327 return MISCREG_AT_S1E3R_Xt;
1328 case 1:
1329 return MISCREG_AT_S1E3W_Xt;
1330 }
1331 break;
1332 }
1333 break;
1334 }
1335 break;
1336 case 8:
1337 switch (op1) {
1338 case 0:
1339 switch (crm) {
1340 case 3:
1341 switch (op2) {
1342 case 0:
1343 return MISCREG_TLBI_VMALLE1IS;
1344 case 1:
1345 return MISCREG_TLBI_VAE1IS_Xt;
1346 case 2:
1347 return MISCREG_TLBI_ASIDE1IS_Xt;
1348 case 3:
1349 return MISCREG_TLBI_VAAE1IS_Xt;
1350 case 5:
1351 return MISCREG_TLBI_VALE1IS_Xt;
1352 case 7:
1353 return MISCREG_TLBI_VAALE1IS_Xt;
1354 }
1355 break;
1356 case 7:
1357 switch (op2) {
1358 case 0:
1359 return MISCREG_TLBI_VMALLE1;
1360 case 1:
1361 return MISCREG_TLBI_VAE1_Xt;
1362 case 2:
1363 return MISCREG_TLBI_ASIDE1_Xt;
1364 case 3:
1365 return MISCREG_TLBI_VAAE1_Xt;
1366 case 5:
1367 return MISCREG_TLBI_VALE1_Xt;
1368 case 7:
1369 return MISCREG_TLBI_VAALE1_Xt;
1370 }
1371 break;
1372 }
1373 break;
1374 case 4:
1375 switch (crm) {
1376 case 0:
1377 switch (op2) {
1378 case 1:
1379 return MISCREG_TLBI_IPAS2E1IS_Xt;
1380 case 5:
1381 return MISCREG_TLBI_IPAS2LE1IS_Xt;
1382 }
1383 break;
1384 case 3:
1385 switch (op2) {
1386 case 0:
1387 return MISCREG_TLBI_ALLE2IS;
1388 case 1:
1389 return MISCREG_TLBI_VAE2IS_Xt;
1390 case 4:
1391 return MISCREG_TLBI_ALLE1IS;
1392 case 5:
1393 return MISCREG_TLBI_VALE2IS_Xt;
1394 case 6:
1395 return MISCREG_TLBI_VMALLS12E1IS;
1396 }
1397 break;
1398 case 4:
1399 switch (op2) {
1400 case 1:
1401 return MISCREG_TLBI_IPAS2E1_Xt;
1402 case 5:
1403 return MISCREG_TLBI_IPAS2LE1_Xt;
1404 }
1405 break;
1406 case 7:
1407 switch (op2) {
1408 case 0:
1409 return MISCREG_TLBI_ALLE2;
1410 case 1:
1411 return MISCREG_TLBI_VAE2_Xt;
1412 case 4:
1413 return MISCREG_TLBI_ALLE1;
1414 case 5:
1415 return MISCREG_TLBI_VALE2_Xt;
1416 case 6:
1417 return MISCREG_TLBI_VMALLS12E1;
1418 }
1419 break;
1420 }
1421 break;
1422 case 6:
1423 switch (crm) {
1424 case 3:
1425 switch (op2) {
1426 case 0:
1427 return MISCREG_TLBI_ALLE3IS;
1428 case 1:
1429 return MISCREG_TLBI_VAE3IS_Xt;
1430 case 5:
1431 return MISCREG_TLBI_VALE3IS_Xt;
1432 }
1433 break;
1434 case 7:
1435 switch (op2) {
1436 case 0:
1437 return MISCREG_TLBI_ALLE3;
1438 case 1:
1439 return MISCREG_TLBI_VAE3_Xt;
1440 case 5:
1441 return MISCREG_TLBI_VALE3_Xt;
1442 }
1443 break;
1444 }
1445 break;
1446 }
1447 break;
1448 case 11:
1449 case 15:
1450 // SYS Instruction with CRn = { 11, 15 }
1451 // (Trappable by HCR_EL2.TIDCP)
1452 return MISCREG_IMPDEF_UNIMPL;
1453 }
1454 break;
1455 case 2:
1456 switch (crn) {
1457 case 0:
1458 switch (op1) {
1459 case 0:
1460 switch (crm) {
1461 case 0:
1462 switch (op2) {
1463 case 2:
1464 return MISCREG_OSDTRRX_EL1;
1465 case 4:
1466 return MISCREG_DBGBVR0_EL1;
1467 case 5:
1468 return MISCREG_DBGBCR0_EL1;
1469 case 6:
1470 return MISCREG_DBGWVR0_EL1;
1471 case 7:
1472 return MISCREG_DBGWCR0_EL1;
1473 }
1474 break;
1475 case 1:
1476 switch (op2) {
1477 case 4:
1478 return MISCREG_DBGBVR1_EL1;
1479 case 5:
1480 return MISCREG_DBGBCR1_EL1;
1481 case 6:
1482 return MISCREG_DBGWVR1_EL1;
1483 case 7:
1484 return MISCREG_DBGWCR1_EL1;
1485 }
1486 break;
1487 case 2:
1488 switch (op2) {
1489 case 0:
1490 return MISCREG_MDCCINT_EL1;
1491 case 2:
1492 return MISCREG_MDSCR_EL1;
1493 case 4:
1494 return MISCREG_DBGBVR2_EL1;
1495 case 5:
1496 return MISCREG_DBGBCR2_EL1;
1497 case 6:
1498 return MISCREG_DBGWVR2_EL1;
1499 case 7:
1500 return MISCREG_DBGWCR2_EL1;
1501 }
1502 break;
1503 case 3:
1504 switch (op2) {
1505 case 2:
1506 return MISCREG_OSDTRTX_EL1;
1507 case 4:
1508 return MISCREG_DBGBVR3_EL1;
1509 case 5:
1510 return MISCREG_DBGBCR3_EL1;
1511 case 6:
1512 return MISCREG_DBGWVR3_EL1;
1513 case 7:
1514 return MISCREG_DBGWCR3_EL1;
1515 }
1516 break;
1517 case 4:
1518 switch (op2) {
1519 case 4:
1520 return MISCREG_DBGBVR4_EL1;
1521 case 5:
1522 return MISCREG_DBGBCR4_EL1;
1523 }
1524 break;
1525 case 5:
1526 switch (op2) {
1527 case 4:
1528 return MISCREG_DBGBVR5_EL1;
1529 case 5:
1530 return MISCREG_DBGBCR5_EL1;
1531 }
1532 break;
1533 case 6:
1534 switch (op2) {
1535 case 2:
1536 return MISCREG_OSECCR_EL1;
1537 }
1538 break;
1539 }
1540 break;
1541 case 2:
1542 switch (crm) {
1543 case 0:
1544 switch (op2) {
1545 case 0:
1546 return MISCREG_TEECR32_EL1;
1547 }
1548 break;
1549 }
1550 break;
1551 case 3:
1552 switch (crm) {
1553 case 1:
1554 switch (op2) {
1555 case 0:
1556 return MISCREG_MDCCSR_EL0;
1557 }
1558 break;
1559 case 4:
1560 switch (op2) {
1561 case 0:
1562 return MISCREG_MDDTR_EL0;
1563 }
1564 break;
1565 case 5:
1566 switch (op2) {
1567 case 0:
1568 return MISCREG_MDDTRRX_EL0;
1569 }
1570 break;
1571 }
1572 break;
1573 case 4:
1574 switch (crm) {
1575 case 7:
1576 switch (op2) {
1577 case 0:
1578 return MISCREG_DBGVCR32_EL2;
1579 }
1580 break;
1581 }
1582 break;
1583 }
1584 break;
1585 case 1:
1586 switch (op1) {
1587 case 0:
1588 switch (crm) {
1589 case 0:
1590 switch (op2) {
1591 case 0:
1592 return MISCREG_MDRAR_EL1;
1593 case 4:
1594 return MISCREG_OSLAR_EL1;
1595 }
1596 break;
1597 case 1:
1598 switch (op2) {
1599 case 4:
1600 return MISCREG_OSLSR_EL1;
1601 }
1602 break;
1603 case 3:
1604 switch (op2) {
1605 case 4:
1606 return MISCREG_OSDLR_EL1;
1607 }
1608 break;
1609 case 4:
1610 switch (op2) {
1611 case 4:
1612 return MISCREG_DBGPRCR_EL1;
1613 }
1614 break;
1615 }
1616 break;
1617 case 2:
1618 switch (crm) {
1619 case 0:
1620 switch (op2) {
1621 case 0:
1622 return MISCREG_TEEHBR32_EL1;
1623 }
1624 break;
1625 }
1626 break;
1627 }
1628 break;
1629 case 7:
1630 switch (op1) {
1631 case 0:
1632 switch (crm) {
1633 case 8:
1634 switch (op2) {
1635 case 6:
1636 return MISCREG_DBGCLAIMSET_EL1;
1637 }
1638 break;
1639 case 9:
1640 switch (op2) {
1641 case 6:
1642 return MISCREG_DBGCLAIMCLR_EL1;
1643 }
1644 break;
1645 case 14:
1646 switch (op2) {
1647 case 6:
1648 return MISCREG_DBGAUTHSTATUS_EL1;
1649 }
1650 break;
1651 }
1652 break;
1653 }
1654 break;
1655 }
1656 break;
1657 case 3:
1658 switch (crn) {
1659 case 0:
1660 switch (op1) {
1661 case 0:
1662 switch (crm) {
1663 case 0:
1664 switch (op2) {
1665 case 0:
1666 return MISCREG_MIDR_EL1;
1667 case 5:
1668 return MISCREG_MPIDR_EL1;
1669 case 6:
1670 return MISCREG_REVIDR_EL1;
1671 }
1672 break;
1673 case 1:
1674 switch (op2) {
1675 case 0:
1676 return MISCREG_ID_PFR0_EL1;
1677 case 1:
1678 return MISCREG_ID_PFR1_EL1;
1679 case 2:
1680 return MISCREG_ID_DFR0_EL1;
1681 case 3:
1682 return MISCREG_ID_AFR0_EL1;
1683 case 4:
1684 return MISCREG_ID_MMFR0_EL1;
1685 case 5:
1686 return MISCREG_ID_MMFR1_EL1;
1687 case 6:
1688 return MISCREG_ID_MMFR2_EL1;
1689 case 7:
1690 return MISCREG_ID_MMFR3_EL1;
1691 }
1692 break;
1693 case 2:
1694 switch (op2) {
1695 case 0:
1696 return MISCREG_ID_ISAR0_EL1;
1697 case 1:
1698 return MISCREG_ID_ISAR1_EL1;
1699 case 2:
1700 return MISCREG_ID_ISAR2_EL1;
1701 case 3:
1702 return MISCREG_ID_ISAR3_EL1;
1703 case 4:
1704 return MISCREG_ID_ISAR4_EL1;
1705 case 5:
1706 return MISCREG_ID_ISAR5_EL1;
1707 }
1708 break;
1709 case 3:
1710 switch (op2) {
1711 case 0:
1712 return MISCREG_MVFR0_EL1;
1713 case 1:
1714 return MISCREG_MVFR1_EL1;
1715 case 2:
1716 return MISCREG_MVFR2_EL1;
1717 case 3 ... 7:
1718 return MISCREG_RAZ;
1719 }
1720 break;
1721 case 4:
1722 switch (op2) {
1723 case 0:
1724 return MISCREG_ID_AA64PFR0_EL1;
1725 case 1:
1726 return MISCREG_ID_AA64PFR1_EL1;
1727 case 2 ... 3:
1728 return MISCREG_RAZ;
1729 case 4:
1730 return MISCREG_ID_AA64ZFR0_EL1;
1731 case 5 ... 7:
1732 return MISCREG_RAZ;
1733 }
1734 break;
1735 case 5:
1736 switch (op2) {
1737 case 0:
1738 return MISCREG_ID_AA64DFR0_EL1;
1739 case 1:
1740 return MISCREG_ID_AA64DFR1_EL1;
1741 case 4:
1742 return MISCREG_ID_AA64AFR0_EL1;
1743 case 5:
1744 return MISCREG_ID_AA64AFR1_EL1;
1745 case 2:
1746 case 3:
1747 case 6:
1748 case 7:
1749 return MISCREG_RAZ;
1750 }
1751 break;
1752 case 6:
1753 switch (op2) {
1754 case 0:
1755 return MISCREG_ID_AA64ISAR0_EL1;
1756 case 1:
1757 return MISCREG_ID_AA64ISAR1_EL1;
1758 case 2 ... 7:
1759 return MISCREG_RAZ;
1760 }
1761 break;
1762 case 7:
1763 switch (op2) {
1764 case 0:
1765 return MISCREG_ID_AA64MMFR0_EL1;
1766 case 1:
1767 return MISCREG_ID_AA64MMFR1_EL1;
1768 case 2:
1769 return MISCREG_ID_AA64MMFR2_EL1;
1770 case 3 ... 7:
1771 return MISCREG_RAZ;
1772 }
1773 break;
1774 }
1775 break;
1776 case 1:
1777 switch (crm) {
1778 case 0:
1779 switch (op2) {
1780 case 0:
1781 return MISCREG_CCSIDR_EL1;
1782 case 1:
1783 return MISCREG_CLIDR_EL1;
1784 case 7:
1785 return MISCREG_AIDR_EL1;
1786 }
1787 break;
1788 }
1789 break;
1790 case 2:
1791 switch (crm) {
1792 case 0:
1793 switch (op2) {
1794 case 0:
1795 return MISCREG_CSSELR_EL1;
1796 }
1797 break;
1798 }
1799 break;
1800 case 3:
1801 switch (crm) {
1802 case 0:
1803 switch (op2) {
1804 case 1:
1805 return MISCREG_CTR_EL0;
1806 case 7:
1807 return MISCREG_DCZID_EL0;
1808 }
1809 break;
1810 }
1811 break;
1812 case 4:
1813 switch (crm) {
1814 case 0:
1815 switch (op2) {
1816 case 0:
1817 return MISCREG_VPIDR_EL2;
1818 case 5:
1819 return MISCREG_VMPIDR_EL2;
1820 }
1821 break;
1822 }
1823 break;
1824 }
1825 break;
1826 case 1:
1827 switch (op1) {
1828 case 0:
1829 switch (crm) {
1830 case 0:
1831 switch (op2) {
1832 case 0:
1833 return MISCREG_SCTLR_EL1;
1834 case 1:
1835 return MISCREG_ACTLR_EL1;
1836 case 2:
1837 return MISCREG_CPACR_EL1;
1838 }
1839 break;
1840 case 2:
1841 switch (op2) {
1842 case 0:
1843 return MISCREG_ZCR_EL1;
1844 }
1845 break;
1846 }
1847 break;
1848 case 4:
1849 switch (crm) {
1850 case 0:
1851 switch (op2) {
1852 case 0:
1853 return MISCREG_SCTLR_EL2;
1854 case 1:
1855 return MISCREG_ACTLR_EL2;
1856 }
1857 break;
1858 case 1:
1859 switch (op2) {
1860 case 0:
1861 return MISCREG_HCR_EL2;
1862 case 1:
1863 return MISCREG_MDCR_EL2;
1864 case 2:
1865 return MISCREG_CPTR_EL2;
1866 case 3:
1867 return MISCREG_HSTR_EL2;
1868 case 7:
1869 return MISCREG_HACR_EL2;
1870 }
1871 break;
1872 case 2:
1873 switch (op2) {
1874 case 0:
1875 return MISCREG_ZCR_EL2;
1876 }
1877 break;
1878 }
1879 break;
1880 case 5:
1881 switch (crm) {
1882 case 2:
1883 switch (op2) {
1884 case 0:
1885 return MISCREG_ZCR_EL12;
1886 }
1887 break;
1888 }
1889 break;
1890 case 6:
1891 switch (crm) {
1892 case 0:
1893 switch (op2) {
1894 case 0:
1895 return MISCREG_SCTLR_EL3;
1896 case 1:
1897 return MISCREG_ACTLR_EL3;
1898 }
1899 break;
1900 case 1:
1901 switch (op2) {
1902 case 0:
1903 return MISCREG_SCR_EL3;
1904 case 1:
1905 return MISCREG_SDER32_EL3;
1906 case 2:
1907 return MISCREG_CPTR_EL3;
1908 }
1909 break;
1910 case 2:
1911 switch (op2) {
1912 case 0:
1913 return MISCREG_ZCR_EL3;
1914 }
1915 break;
1916 case 3:
1917 switch (op2) {
1918 case 1:
1919 return MISCREG_MDCR_EL3;
1920 }
1921 break;
1922 }
1923 break;
1924 }
1925 break;
1926 case 2:
1927 switch (op1) {
1928 case 0:
1929 switch (crm) {
1930 case 0:
1931 switch (op2) {
1932 case 0:
1933 return MISCREG_TTBR0_EL1;
1934 case 1:
1935 return MISCREG_TTBR1_EL1;
1936 case 2:
1937 return MISCREG_TCR_EL1;
1938 }
1939 break;
1940 }
1941 break;
1942 case 4:
1943 switch (crm) {
1944 case 0:
1945 switch (op2) {
1946 case 0:
1947 return MISCREG_TTBR0_EL2;
1948 case 1:
1949 return MISCREG_TTBR1_EL2;
1950 case 2:
1951 return MISCREG_TCR_EL2;
1952 }
1953 break;
1954 case 1:
1955 switch (op2) {
1956 case 0:
1957 return MISCREG_VTTBR_EL2;
1958 case 2:
1959 return MISCREG_VTCR_EL2;
1960 }
1961 break;
1962 }
1963 break;
1964 case 6:
1965 switch (crm) {
1966 case 0:
1967 switch (op2) {
1968 case 0:
1969 return MISCREG_TTBR0_EL3;
1970 case 2:
1971 return MISCREG_TCR_EL3;
1972 }
1973 break;
1974 }
1975 break;
1976 }
1977 break;
1978 case 3:
1979 switch (op1) {
1980 case 4:
1981 switch (crm) {
1982 case 0:
1983 switch (op2) {
1984 case 0:
1985 return MISCREG_DACR32_EL2;
1986 }
1987 break;
1988 }
1989 break;
1990 }
1991 break;
1992 case 4:
1993 switch (op1) {
1994 case 0:
1995 switch (crm) {
1996 case 0:
1997 switch (op2) {
1998 case 0:
1999 return MISCREG_SPSR_EL1;
2000 case 1:
2001 return MISCREG_ELR_EL1;
2002 }
2003 break;
2004 case 1:
2005 switch (op2) {
2006 case 0:
2007 return MISCREG_SP_EL0;
2008 }
2009 break;
2010 case 2:
2011 switch (op2) {
2012 case 0:
2013 return MISCREG_SPSEL;
2014 case 2:
2015 return MISCREG_CURRENTEL;
2016 case 3:
2017 return MISCREG_PAN;
2018 }
2019 break;
2020 case 6:
2021 switch (op2) {
2022 case 0:
2023 return MISCREG_ICC_PMR_EL1;
2024 }
2025 break;
2026 }
2027 break;
2028 case 3:
2029 switch (crm) {
2030 case 2:
2031 switch (op2) {
2032 case 0:
2033 return MISCREG_NZCV;
2034 case 1:
2035 return MISCREG_DAIF;
2036 }
2037 break;
2038 case 4:
2039 switch (op2) {
2040 case 0:
2041 return MISCREG_FPCR;
2042 case 1:
2043 return MISCREG_FPSR;
2044 }
2045 break;
2046 case 5:
2047 switch (op2) {
2048 case 0:
2049 return MISCREG_DSPSR_EL0;
2050 case 1:
2051 return MISCREG_DLR_EL0;
2052 }
2053 break;
2054 }
2055 break;
2056 case 4:
2057 switch (crm) {
2058 case 0:
2059 switch (op2) {
2060 case 0:
2061 return MISCREG_SPSR_EL2;
2062 case 1:
2063 return MISCREG_ELR_EL2;
2064 }
2065 break;
2066 case 1:
2067 switch (op2) {
2068 case 0:
2069 return MISCREG_SP_EL1;
2070 }
2071 break;
2072 case 3:
2073 switch (op2) {
2074 case 0:
2075 return MISCREG_SPSR_IRQ_AA64;
2076 case 1:
2077 return MISCREG_SPSR_ABT_AA64;
2078 case 2:
2079 return MISCREG_SPSR_UND_AA64;
2080 case 3:
2081 return MISCREG_SPSR_FIQ_AA64;
2082 }
2083 break;
2084 }
2085 break;
2086 case 6:
2087 switch (crm) {
2088 case 0:
2089 switch (op2) {
2090 case 0:
2091 return MISCREG_SPSR_EL3;
2092 case 1:
2093 return MISCREG_ELR_EL3;
2094 }
2095 break;
2096 case 1:
2097 switch (op2) {
2098 case 0:
2099 return MISCREG_SP_EL2;
2100 }
2101 break;
2102 }
2103 break;
2104 }
2105 break;
2106 case 5:
2107 switch (op1) {
2108 case 0:
2109 switch (crm) {
2110 case 1:
2111 switch (op2) {
2112 case 0:
2113 return MISCREG_AFSR0_EL1;
2114 case 1:
2115 return MISCREG_AFSR1_EL1;
2116 }
2117 break;
2118 case 2:
2119 switch (op2) {
2120 case 0:
2121 return MISCREG_ESR_EL1;
2122 }
2123 break;
2124 case 3:
2125 switch (op2) {
2126 case 0:
2127 return MISCREG_ERRIDR_EL1;
2128 case 1:
2129 return MISCREG_ERRSELR_EL1;
2130 }
2131 break;
2132 case 4:
2133 switch (op2) {
2134 case 0:
2135 return MISCREG_ERXFR_EL1;
2136 case 1:
2137 return MISCREG_ERXCTLR_EL1;
2138 case 2:
2139 return MISCREG_ERXSTATUS_EL1;
2140 case 3:
2141 return MISCREG_ERXADDR_EL1;
2142 }
2143 break;
2144 case 5:
2145 switch (op2) {
2146 case 0:
2147 return MISCREG_ERXMISC0_EL1;
2148 case 1:
2149 return MISCREG_ERXMISC1_EL1;
2150 }
2151 break;
2152 }
2153 break;
2154 case 4:
2155 switch (crm) {
2156 case 0:
2157 switch (op2) {
2158 case 1:
2159 return MISCREG_IFSR32_EL2;
2160 }
2161 break;
2162 case 1:
2163 switch (op2) {
2164 case 0:
2165 return MISCREG_AFSR0_EL2;
2166 case 1:
2167 return MISCREG_AFSR1_EL2;
2168 }
2169 break;
2170 case 2:
2171 switch (op2) {
2172 case 0:
2173 return MISCREG_ESR_EL2;
2174 case 3:
2175 return MISCREG_VSESR_EL2;
2176 }
2177 break;
2178 case 3:
2179 switch (op2) {
2180 case 0:
2181 return MISCREG_FPEXC32_EL2;
2182 }
2183 break;
2184 }
2185 break;
2186 case 6:
2187 switch (crm) {
2188 case 1:
2189 switch (op2) {
2190 case 0:
2191 return MISCREG_AFSR0_EL3;
2192 case 1:
2193 return MISCREG_AFSR1_EL3;
2194 }
2195 break;
2196 case 2:
2197 switch (op2) {
2198 case 0:
2199 return MISCREG_ESR_EL3;
2200 }
2201 break;
2202 }
2203 break;
2204 }
2205 break;
2206 case 6:
2207 switch (op1) {
2208 case 0:
2209 switch (crm) {
2210 case 0:
2211 switch (op2) {
2212 case 0:
2213 return MISCREG_FAR_EL1;
2214 }
2215 break;
2216 }
2217 break;
2218 case 4:
2219 switch (crm) {
2220 case 0:
2221 switch (op2) {
2222 case 0:
2223 return MISCREG_FAR_EL2;
2224 case 4:
2225 return MISCREG_HPFAR_EL2;
2226 }
2227 break;
2228 }
2229 break;
2230 case 6:
2231 switch (crm) {
2232 case 0:
2233 switch (op2) {
2234 case 0:
2235 return MISCREG_FAR_EL3;
2236 }
2237 break;
2238 }
2239 break;
2240 }
2241 break;
2242 case 7:
2243 switch (op1) {
2244 case 0:
2245 switch (crm) {
2246 case 4:
2247 switch (op2) {
2248 case 0:
2249 return MISCREG_PAR_EL1;
2250 }
2251 break;
2252 }
2253 break;
2254 }
2255 break;
2256 case 9:
2257 switch (op1) {
2258 case 0:
2259 switch (crm) {
2260 case 14:
2261 switch (op2) {
2262 case 1:
2263 return MISCREG_PMINTENSET_EL1;
2264 case 2:
2265 return MISCREG_PMINTENCLR_EL1;
2266 }
2267 break;
2268 }
2269 break;
2270 case 3:
2271 switch (crm) {
2272 case 12:
2273 switch (op2) {
2274 case 0:
2275 return MISCREG_PMCR_EL0;
2276 case 1:
2277 return MISCREG_PMCNTENSET_EL0;
2278 case 2:
2279 return MISCREG_PMCNTENCLR_EL0;
2280 case 3:
2281 return MISCREG_PMOVSCLR_EL0;
2282 case 4:
2283 return MISCREG_PMSWINC_EL0;
2284 case 5:
2285 return MISCREG_PMSELR_EL0;
2286 case 6:
2287 return MISCREG_PMCEID0_EL0;
2288 case 7:
2289 return MISCREG_PMCEID1_EL0;
2290 }
2291 break;
2292 case 13:
2293 switch (op2) {
2294 case 0:
2295 return MISCREG_PMCCNTR_EL0;
2296 case 1:
2297 return MISCREG_PMXEVTYPER_EL0;
2298 case 2:
2299 return MISCREG_PMXEVCNTR_EL0;
2300 }
2301 break;
2302 case 14:
2303 switch (op2) {
2304 case 0:
2305 return MISCREG_PMUSERENR_EL0;
2306 case 3:
2307 return MISCREG_PMOVSSET_EL0;
2308 }
2309 break;
2310 }
2311 break;
2312 }
2313 break;
2314 case 10:
2315 switch (op1) {
2316 case 0:
2317 switch (crm) {
2318 case 2:
2319 switch (op2) {
2320 case 0:
2321 return MISCREG_MAIR_EL1;
2322 }
2323 break;
2324 case 3:
2325 switch (op2) {
2326 case 0:
2327 return MISCREG_AMAIR_EL1;
2328 }
2329 break;
2330 }
2331 break;
2332 case 4:
2333 switch (crm) {
2334 case 2:
2335 switch (op2) {
2336 case 0:
2337 return MISCREG_MAIR_EL2;
2338 }
2339 break;
2340 case 3:
2341 switch (op2) {
2342 case 0:
2343 return MISCREG_AMAIR_EL2;
2344 }
2345 break;
2346 }
2347 break;
2348 case 6:
2349 switch (crm) {
2350 case 2:
2351 switch (op2) {
2352 case 0:
2353 return MISCREG_MAIR_EL3;
2354 }
2355 break;
2356 case 3:
2357 switch (op2) {
2358 case 0:
2359 return MISCREG_AMAIR_EL3;
2360 }
2361 break;
2362 }
2363 break;
2364 }
2365 break;
2366 case 11:
2367 switch (op1) {
2368 case 1:
2369 switch (crm) {
2370 case 0:
2371 switch (op2) {
2372 case 2:
2373 return MISCREG_L2CTLR_EL1;
2374 case 3:
2375 return MISCREG_L2ECTLR_EL1;
2376 }
2377 break;
2378 }
2379 M5_FALLTHROUGH;
2380 default:
2381 // S3_<op1>_11_<Cm>_<op2>
2382 return MISCREG_IMPDEF_UNIMPL;
2383 }
2384 M5_UNREACHABLE;
2385 case 12:
2386 switch (op1) {
2387 case 0:
2388 switch (crm) {
2389 case 0:
2390 switch (op2) {
2391 case 0:
2392 return MISCREG_VBAR_EL1;
2393 case 1:
2394 return MISCREG_RVBAR_EL1;
2395 }
2396 break;
2397 case 1:
2398 switch (op2) {
2399 case 0:
2400 return MISCREG_ISR_EL1;
2401 case 1:
2402 return MISCREG_DISR_EL1;
2403 }
2404 break;
2405 case 8:
2406 switch (op2) {
2407 case 0:
2408 return MISCREG_ICC_IAR0_EL1;
2409 case 1:
2410 return MISCREG_ICC_EOIR0_EL1;
2411 case 2:
2412 return MISCREG_ICC_HPPIR0_EL1;
2413 case 3:
2414 return MISCREG_ICC_BPR0_EL1;
2415 case 4:
2416 return MISCREG_ICC_AP0R0_EL1;
2417 case 5:
2418 return MISCREG_ICC_AP0R1_EL1;
2419 case 6:
2420 return MISCREG_ICC_AP0R2_EL1;
2421 case 7:
2422 return MISCREG_ICC_AP0R3_EL1;
2423 }
2424 break;
2425 case 9:
2426 switch (op2) {
2427 case 0:
2428 return MISCREG_ICC_AP1R0_EL1;
2429 case 1:
2430 return MISCREG_ICC_AP1R1_EL1;
2431 case 2:
2432 return MISCREG_ICC_AP1R2_EL1;
2433 case 3:
2434 return MISCREG_ICC_AP1R3_EL1;
2435 }
2436 break;
2437 case 11:
2438 switch (op2) {
2439 case 1:
2440 return MISCREG_ICC_DIR_EL1;
2441 case 3:
2442 return MISCREG_ICC_RPR_EL1;
2443 case 5:
2444 return MISCREG_ICC_SGI1R_EL1;
2445 case 6:
2446 return MISCREG_ICC_ASGI1R_EL1;
2447 case 7:
2448 return MISCREG_ICC_SGI0R_EL1;
2449 }
2450 break;
2451 case 12:
2452 switch (op2) {
2453 case 0:
2454 return MISCREG_ICC_IAR1_EL1;
2455 case 1:
2456 return MISCREG_ICC_EOIR1_EL1;
2457 case 2:
2458 return MISCREG_ICC_HPPIR1_EL1;
2459 case 3:
2460 return MISCREG_ICC_BPR1_EL1;
2461 case 4:
2462 return MISCREG_ICC_CTLR_EL1;
2463 case 5:
2464 return MISCREG_ICC_SRE_EL1;
2465 case 6:
2466 return MISCREG_ICC_IGRPEN0_EL1;
2467 case 7:
2468 return MISCREG_ICC_IGRPEN1_EL1;
2469 }
2470 break;
2471 }
2472 break;
2473 case 4:
2474 switch (crm) {
2475 case 0:
2476 switch (op2) {
2477 case 0:
2478 return MISCREG_VBAR_EL2;
2479 case 1:
2480 return MISCREG_RVBAR_EL2;
2481 }
2482 break;
2483 case 1:
2484 switch (op2) {
2485 case 1:
2486 return MISCREG_VDISR_EL2;
2487 }
2488 break;
2489 case 8:
2490 switch (op2) {
2491 case 0:
2492 return MISCREG_ICH_AP0R0_EL2;
2493 case 1:
2494 return MISCREG_ICH_AP0R1_EL2;
2495 case 2:
2496 return MISCREG_ICH_AP0R2_EL2;
2497 case 3:
2498 return MISCREG_ICH_AP0R3_EL2;
2499 }
2500 break;
2501 case 9:
2502 switch (op2) {
2503 case 0:
2504 return MISCREG_ICH_AP1R0_EL2;
2505 case 1:
2506 return MISCREG_ICH_AP1R1_EL2;
2507 case 2:
2508 return MISCREG_ICH_AP1R2_EL2;
2509 case 3:
2510 return MISCREG_ICH_AP1R3_EL2;
2511 case 5:
2512 return MISCREG_ICC_SRE_EL2;
2513 }
2514 break;
2515 case 11:
2516 switch (op2) {
2517 case 0:
2518 return MISCREG_ICH_HCR_EL2;
2519 case 1:
2520 return MISCREG_ICH_VTR_EL2;
2521 case 2:
2522 return MISCREG_ICH_MISR_EL2;
2523 case 3:
2524 return MISCREG_ICH_EISR_EL2;
2525 case 5:
2526 return MISCREG_ICH_ELRSR_EL2;
2527 case 7:
2528 return MISCREG_ICH_VMCR_EL2;
2529 }
2530 break;
2531 case 12:
2532 switch (op2) {
2533 case 0:
2534 return MISCREG_ICH_LR0_EL2;
2535 case 1:
2536 return MISCREG_ICH_LR1_EL2;
2537 case 2:
2538 return MISCREG_ICH_LR2_EL2;
2539 case 3:
2540 return MISCREG_ICH_LR3_EL2;
2541 case 4:
2542 return MISCREG_ICH_LR4_EL2;
2543 case 5:
2544 return MISCREG_ICH_LR5_EL2;
2545 case 6:
2546 return MISCREG_ICH_LR6_EL2;
2547 case 7:
2548 return MISCREG_ICH_LR7_EL2;
2549 }
2550 break;
2551 case 13:
2552 switch (op2) {
2553 case 0:
2554 return MISCREG_ICH_LR8_EL2;
2555 case 1:
2556 return MISCREG_ICH_LR9_EL2;
2557 case 2:
2558 return MISCREG_ICH_LR10_EL2;
2559 case 3:
2560 return MISCREG_ICH_LR11_EL2;
2561 case 4:
2562 return MISCREG_ICH_LR12_EL2;
2563 case 5:
2564 return MISCREG_ICH_LR13_EL2;
2565 case 6:
2566 return MISCREG_ICH_LR14_EL2;
2567 case 7:
2568 return MISCREG_ICH_LR15_EL2;
2569 }
2570 break;
2571 }
2572 break;
2573 case 6:
2574 switch (crm) {
2575 case 0:
2576 switch (op2) {
2577 case 0:
2578 return MISCREG_VBAR_EL3;
2579 case 1:
2580 return MISCREG_RVBAR_EL3;
2581 case 2:
2582 return MISCREG_RMR_EL3;
2583 }
2584 break;
2585 case 12:
2586 switch (op2) {
2587 case 4:
2588 return MISCREG_ICC_CTLR_EL3;
2589 case 5:
2590 return MISCREG_ICC_SRE_EL3;
2591 case 7:
2592 return MISCREG_ICC_IGRPEN1_EL3;
2593 }
2594 break;
2595 }
2596 break;
2597 }
2598 break;
2599 case 13:
2600 switch (op1) {
2601 case 0:
2602 switch (crm) {
2603 case 0:
2604 switch (op2) {
2605 case 1:
2606 return MISCREG_CONTEXTIDR_EL1;
2607 case 4:
2608 return MISCREG_TPIDR_EL1;
2609 }
2610 break;
2611 }
2612 break;
2613 case 3:
2614 switch (crm) {
2615 case 0:
2616 switch (op2) {
2617 case 2:
2618 return MISCREG_TPIDR_EL0;
2619 case 3:
2620 return MISCREG_TPIDRRO_EL0;
2621 }
2622 break;
2623 }
2624 break;
2625 case 4:
2626 switch (crm) {
2627 case 0:
2628 switch (op2) {
2629 case 1:
2630 return MISCREG_CONTEXTIDR_EL2;
2631 case 2:
2632 return MISCREG_TPIDR_EL2;
2633 }
2634 break;
2635 }
2636 break;
2637 case 6:
2638 switch (crm) {
2639 case 0:
2640 switch (op2) {
2641 case 2:
2642 return MISCREG_TPIDR_EL3;
2643 }
2644 break;
2645 }
2646 break;
2647 }
2648 break;
2649 case 14:
2650 switch (op1) {
2651 case 0:
2652 switch (crm) {
2653 case 1:
2654 switch (op2) {
2655 case 0:
2656 return MISCREG_CNTKCTL_EL1;
2657 }
2658 break;
2659 }
2660 break;
2661 case 3:
2662 switch (crm) {
2663 case 0:
2664 switch (op2) {
2665 case 0:
2666 return MISCREG_CNTFRQ_EL0;
2667 case 1:
2668 return MISCREG_CNTPCT_EL0;
2669 case 2:
2670 return MISCREG_CNTVCT_EL0;
2671 }
2672 break;
2673 case 2:
2674 switch (op2) {
2675 case 0:
2676 return MISCREG_CNTP_TVAL_EL0;
2677 case 1:
2678 return MISCREG_CNTP_CTL_EL0;
2679 case 2:
2680 return MISCREG_CNTP_CVAL_EL0;
2681 }
2682 break;
2683 case 3:
2684 switch (op2) {
2685 case 0:
2686 return MISCREG_CNTV_TVAL_EL0;
2687 case 1:
2688 return MISCREG_CNTV_CTL_EL0;
2689 case 2:
2690 return MISCREG_CNTV_CVAL_EL0;
2691 }
2692 break;
2693 case 8:
2694 switch (op2) {
2695 case 0:
2696 return MISCREG_PMEVCNTR0_EL0;
2697 case 1:
2698 return MISCREG_PMEVCNTR1_EL0;
2699 case 2:
2700 return MISCREG_PMEVCNTR2_EL0;
2701 case 3:
2702 return MISCREG_PMEVCNTR3_EL0;
2703 case 4:
2704 return MISCREG_PMEVCNTR4_EL0;
2705 case 5:
2706 return MISCREG_PMEVCNTR5_EL0;
2707 }
2708 break;
2709 case 12:
2710 switch (op2) {
2711 case 0:
2712 return MISCREG_PMEVTYPER0_EL0;
2713 case 1:
2714 return MISCREG_PMEVTYPER1_EL0;
2715 case 2:
2716 return MISCREG_PMEVTYPER2_EL0;
2717 case 3:
2718 return MISCREG_PMEVTYPER3_EL0;
2719 case 4:
2720 return MISCREG_PMEVTYPER4_EL0;
2721 case 5:
2722 return MISCREG_PMEVTYPER5_EL0;
2723 }
2724 break;
2725 case 15:
2726 switch (op2) {
2727 case 7:
2728 return MISCREG_PMCCFILTR_EL0;
2729 }
2730 }
2731 break;
2732 case 4:
2733 switch (crm) {
2734 case 0:
2735 switch (op2) {
2736 case 3:
2737 return MISCREG_CNTVOFF_EL2;
2738 }
2739 break;
2740 case 1:
2741 switch (op2) {
2742 case 0:
2743 return MISCREG_CNTHCTL_EL2;
2744 }
2745 break;
2746 case 2:
2747 switch (op2) {
2748 case 0:
2749 return MISCREG_CNTHP_TVAL_EL2;
2750 case 1:
2751 return MISCREG_CNTHP_CTL_EL2;
2752 case 2:
2753 return MISCREG_CNTHP_CVAL_EL2;
2754 }
2755 break;
2756 case 3:
2757 switch (op2) {
2758 case 0:
2759 return MISCREG_CNTHV_TVAL_EL2;
2760 case 1:
2761 return MISCREG_CNTHV_CTL_EL2;
2762 case 2:
2763 return MISCREG_CNTHV_CVAL_EL2;
2764 }
2765 break;
2766 }
2767 break;
2768 case 7:
2769 switch (crm) {
2770 case 2:
2771 switch (op2) {
2772 case 0:
2773 return MISCREG_CNTPS_TVAL_EL1;
2774 case 1:
2775 return MISCREG_CNTPS_CTL_EL1;
2776 case 2:
2777 return MISCREG_CNTPS_CVAL_EL1;
2778 }
2779 break;
2780 }
2781 break;
2782 }
2783 break;
2784 case 15:
2785 switch (op1) {
2786 case 0:
2787 switch (crm) {
2788 case 0:
2789 switch (op2) {
2790 case 0:
2791 return MISCREG_IL1DATA0_EL1;
2792 case 1:
2793 return MISCREG_IL1DATA1_EL1;
2794 case 2:
2795 return MISCREG_IL1DATA2_EL1;
2796 case 3:
2797 return MISCREG_IL1DATA3_EL1;
2798 }
2799 break;
2800 case 1:
2801 switch (op2) {
2802 case 0:
2803 return MISCREG_DL1DATA0_EL1;
2804 case 1:
2805 return MISCREG_DL1DATA1_EL1;
2806 case 2:
2807 return MISCREG_DL1DATA2_EL1;
2808 case 3:
2809 return MISCREG_DL1DATA3_EL1;
2810 case 4:
2811 return MISCREG_DL1DATA4_EL1;
2812 }
2813 break;
2814 }
2815 break;
2816 case 1:
2817 switch (crm) {
2818 case 0:
2819 switch (op2) {
2820 case 0:
2821 return MISCREG_L2ACTLR_EL1;
2822 }
2823 break;
2824 case 2:
2825 switch (op2) {
2826 case 0:
2827 return MISCREG_CPUACTLR_EL1;
2828 case 1:
2829 return MISCREG_CPUECTLR_EL1;
2830 case 2:
2831 return MISCREG_CPUMERRSR_EL1;
2832 case 3:
2833 return MISCREG_L2MERRSR_EL1;
2834 }
2835 break;
2836 case 3:
2837 switch (op2) {
2838 case 0:
2839 return MISCREG_CBAR_EL1;
2840
2841 }
2842 break;
2843 }
2844 break;
2845 }
2846 // S3_<op1>_15_<Cm>_<op2>
2847 return MISCREG_IMPDEF_UNIMPL;
2848 }
2849 break;
2850 }
2851
2852 return MISCREG_UNKNOWN;
2853 }
2854
2855 bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below
2856
2857 void
2858 ISA::initializeMiscRegMetadata()
2859 {
2860 // the MiscReg metadata tables are shared across all instances of the
2861 // ISA object, so there's no need to initialize them multiple times.
2862 static bool completed = false;
2863 if (completed)
2864 return;
2865
2866 // This boolean variable specifies if the system is running in aarch32 at
2867 // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
2868 // is running in aarch64 (aarch32EL3 = false)
2869 bool aarch32EL3 = haveSecurity && !highestELIs64;
2870
2871 // Set Privileged Access Never on taking an exception to EL1 (Arm 8.1+),
2872 // unsupported
2873 bool SPAN = false;
2874
2875 // Implicit error synchronization event enable (Arm 8.2+), unsupported
2876 bool IESB = false;
2877
2878 // Load Multiple and Store Multiple Atomicity and Ordering (Arm 8.2+),
2879 // unsupported
2880 bool LSMAOE = false;
2881
2882 // No Trap Load Multiple and Store Multiple (Arm 8.2+), unsupported
2883 bool nTLSMD = false;
2884
2885 // Pointer authentication (Arm 8.3+), unsupported
2886 bool EnDA = false; // using APDAKey_EL1 key of instr addrs in ELs 0,1
2887 bool EnDB = false; // using APDBKey_EL1 key of instr addrs in ELs 0,1
2888 bool EnIA = false; // using APIAKey_EL1 key of instr addrs in ELs 0,1
2889 bool EnIB = false; // using APIBKey_EL1 key of instr addrs in ELs 0,1
2890
2891 /**
2892 * Some registers alias with others, and therefore need to be translated.
2893 * When two mapping registers are given, they are the 32b lower and
2894 * upper halves, respectively, of the 64b register being mapped.
2895 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
2896 *
2897 * NAM = "not architecturally mandated",
2898 * from ARM DDI 0487A.i, template text
2899 * "AArch64 System register ___ can be mapped to
2900 * AArch32 System register ___, but this is not
2901 * architecturally mandated."
2902 */
2903
2904 InitReg(MISCREG_CPSR)
2905 .allPrivileges();
2906 InitReg(MISCREG_SPSR)
2907 .allPrivileges();
2908 InitReg(MISCREG_SPSR_FIQ)
2909 .allPrivileges();
2910 InitReg(MISCREG_SPSR_IRQ)
2911 .allPrivileges();
2912 InitReg(MISCREG_SPSR_SVC)
2913 .allPrivileges();
2914 InitReg(MISCREG_SPSR_MON)
2915 .allPrivileges();
2916 InitReg(MISCREG_SPSR_ABT)
2917 .allPrivileges();
2918 InitReg(MISCREG_SPSR_HYP)
2919 .allPrivileges();
2920 InitReg(MISCREG_SPSR_UND)
2921 .allPrivileges();
2922 InitReg(MISCREG_ELR_HYP)
2923 .allPrivileges();
2924 InitReg(MISCREG_FPSID)
2925 .allPrivileges();
2926 InitReg(MISCREG_FPSCR)
2927 .allPrivileges();
2928 InitReg(MISCREG_MVFR1)
2929 .allPrivileges();
2930 InitReg(MISCREG_MVFR0)
2931 .allPrivileges();
2932 InitReg(MISCREG_FPEXC)
2933 .allPrivileges();
2934
2935 // Helper registers
2936 InitReg(MISCREG_CPSR_MODE)
2937 .allPrivileges();
2938 InitReg(MISCREG_CPSR_Q)
2939 .allPrivileges();
2940 InitReg(MISCREG_FPSCR_EXC)
2941 .allPrivileges();
2942 InitReg(MISCREG_FPSCR_QC)
2943 .allPrivileges();
2944 InitReg(MISCREG_LOCKADDR)
2945 .allPrivileges();
2946 InitReg(MISCREG_LOCKFLAG)
2947 .allPrivileges();
2948 InitReg(MISCREG_PRRR_MAIR0)
2949 .mutex()
2950 .banked();
2951 InitReg(MISCREG_PRRR_MAIR0_NS)
2952 .mutex()
2953 .privSecure(!aarch32EL3)
2954 .bankedChild();
2955 InitReg(MISCREG_PRRR_MAIR0_S)
2956 .mutex()
2957 .bankedChild();
2958 InitReg(MISCREG_NMRR_MAIR1)
2959 .mutex()
2960 .banked();
2961 InitReg(MISCREG_NMRR_MAIR1_NS)
2962 .mutex()
2963 .privSecure(!aarch32EL3)
2964 .bankedChild();
2965 InitReg(MISCREG_NMRR_MAIR1_S)
2966 .mutex()
2967 .bankedChild();
2968 InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
2969 .mutex();
2970 InitReg(MISCREG_SCTLR_RST)
2971 .allPrivileges();
2972 InitReg(MISCREG_SEV_MAILBOX)
2973 .allPrivileges();
2974
2975 // AArch32 CP14 registers
2976 InitReg(MISCREG_DBGDIDR)
2977 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2978 InitReg(MISCREG_DBGDSCRint)
2979 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2980 InitReg(MISCREG_DBGDCCINT)
2981 .unimplemented()
2982 .allPrivileges();
2983 InitReg(MISCREG_DBGDTRTXint)
2984 .unimplemented()
2985 .allPrivileges();
2986 InitReg(MISCREG_DBGDTRRXint)
2987 .unimplemented()
2988 .allPrivileges();
2989 InitReg(MISCREG_DBGWFAR)
2990 .unimplemented()
2991 .allPrivileges();
2992 InitReg(MISCREG_DBGVCR)
2993 .unimplemented()
2994 .allPrivileges();
2995 InitReg(MISCREG_DBGDTRRXext)
2996 .unimplemented()
2997 .allPrivileges();
2998 InitReg(MISCREG_DBGDSCRext)
2999 .unimplemented()
3000 .warnNotFail()
3001 .allPrivileges();
3002 InitReg(MISCREG_DBGDTRTXext)
3003 .unimplemented()
3004 .allPrivileges();
3005 InitReg(MISCREG_DBGOSECCR)
3006 .unimplemented()
3007 .allPrivileges();
3008 InitReg(MISCREG_DBGBVR0)
3009 .unimplemented()
3010 .allPrivileges();
3011 InitReg(MISCREG_DBGBVR1)
3012 .unimplemented()
3013 .allPrivileges();
3014 InitReg(MISCREG_DBGBVR2)
3015 .unimplemented()
3016 .allPrivileges();
3017 InitReg(MISCREG_DBGBVR3)
3018 .unimplemented()
3019 .allPrivileges();
3020 InitReg(MISCREG_DBGBVR4)
3021 .unimplemented()
3022 .allPrivileges();
3023 InitReg(MISCREG_DBGBVR5)
3024 .unimplemented()
3025 .allPrivileges();
3026 InitReg(MISCREG_DBGBCR0)
3027 .unimplemented()
3028 .allPrivileges();
3029 InitReg(MISCREG_DBGBCR1)
3030 .unimplemented()
3031 .allPrivileges();
3032 InitReg(MISCREG_DBGBCR2)
3033 .unimplemented()
3034 .allPrivileges();
3035 InitReg(MISCREG_DBGBCR3)
3036 .unimplemented()
3037 .allPrivileges();
3038 InitReg(MISCREG_DBGBCR4)
3039 .unimplemented()
3040 .allPrivileges();
3041 InitReg(MISCREG_DBGBCR5)
3042 .unimplemented()
3043 .allPrivileges();
3044 InitReg(MISCREG_DBGWVR0)
3045 .unimplemented()
3046 .allPrivileges();
3047 InitReg(MISCREG_DBGWVR1)
3048 .unimplemented()
3049 .allPrivileges();
3050 InitReg(MISCREG_DBGWVR2)
3051 .unimplemented()
3052 .allPrivileges();
3053 InitReg(MISCREG_DBGWVR3)
3054 .unimplemented()
3055 .allPrivileges();
3056 InitReg(MISCREG_DBGWCR0)
3057 .unimplemented()
3058 .allPrivileges();
3059 InitReg(MISCREG_DBGWCR1)
3060 .unimplemented()
3061 .allPrivileges();
3062 InitReg(MISCREG_DBGWCR2)
3063 .unimplemented()
3064 .allPrivileges();
3065 InitReg(MISCREG_DBGWCR3)
3066 .unimplemented()
3067 .allPrivileges();
3068 InitReg(MISCREG_DBGDRAR)
3069 .unimplemented()
3070 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3071 InitReg(MISCREG_DBGBXVR4)
3072 .unimplemented()
3073 .allPrivileges();
3074 InitReg(MISCREG_DBGBXVR5)
3075 .unimplemented()
3076 .allPrivileges();
3077 InitReg(MISCREG_DBGOSLAR)
3078 .unimplemented()
3079 .allPrivileges().monSecureRead(0).monNonSecureRead(0);
3080 InitReg(MISCREG_DBGOSLSR)
3081 .unimplemented()
3082 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3083 InitReg(MISCREG_DBGOSDLR)
3084 .unimplemented()
3085 .allPrivileges();
3086 InitReg(MISCREG_DBGPRCR)
3087 .unimplemented()
3088 .allPrivileges();
3089 InitReg(MISCREG_DBGDSAR)
3090 .unimplemented()
3091 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3092 InitReg(MISCREG_DBGCLAIMSET)
3093 .unimplemented()
3094 .allPrivileges();
3095 InitReg(MISCREG_DBGCLAIMCLR)
3096 .unimplemented()
3097 .allPrivileges();
3098 InitReg(MISCREG_DBGAUTHSTATUS)
3099 .unimplemented()
3100 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3101 InitReg(MISCREG_DBGDEVID2)
3102 .unimplemented()
3103 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3104 InitReg(MISCREG_DBGDEVID1)
3105 .unimplemented()
3106 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3107 InitReg(MISCREG_DBGDEVID0)
3108 .unimplemented()
3109 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3110 InitReg(MISCREG_TEECR)
3111 .unimplemented()
3112 .allPrivileges();
3113 InitReg(MISCREG_JIDR)
3114 .allPrivileges();
3115 InitReg(MISCREG_TEEHBR)
3116 .allPrivileges();
3117 InitReg(MISCREG_JOSCR)
3118 .allPrivileges();
3119 InitReg(MISCREG_JMCR)
3120 .allPrivileges();
3121
3122 // AArch32 CP15 registers
3123 InitReg(MISCREG_MIDR)
3124 .allPrivileges().exceptUserMode().writes(0);
3125 InitReg(MISCREG_CTR)
3126 .allPrivileges().exceptUserMode().writes(0);
3127 InitReg(MISCREG_TCMTR)
3128 .allPrivileges().exceptUserMode().writes(0);
3129 InitReg(MISCREG_TLBTR)
3130 .allPrivileges().exceptUserMode().writes(0);
3131 InitReg(MISCREG_MPIDR)
3132 .allPrivileges().exceptUserMode().writes(0);
3133 InitReg(MISCREG_REVIDR)
3134 .unimplemented()
3135 .warnNotFail()
3136 .allPrivileges().exceptUserMode().writes(0);
3137 InitReg(MISCREG_ID_PFR0)
3138 .allPrivileges().exceptUserMode().writes(0);
3139 InitReg(MISCREG_ID_PFR1)
3140 .allPrivileges().exceptUserMode().writes(0);
3141 InitReg(MISCREG_ID_DFR0)
3142 .allPrivileges().exceptUserMode().writes(0);
3143 InitReg(MISCREG_ID_AFR0)
3144 .allPrivileges().exceptUserMode().writes(0);
3145 InitReg(MISCREG_ID_MMFR0)
3146 .allPrivileges().exceptUserMode().writes(0);
3147 InitReg(MISCREG_ID_MMFR1)
3148 .allPrivileges().exceptUserMode().writes(0);
3149 InitReg(MISCREG_ID_MMFR2)
3150 .allPrivileges().exceptUserMode().writes(0);
3151 InitReg(MISCREG_ID_MMFR3)
3152 .allPrivileges().exceptUserMode().writes(0);
3153 InitReg(MISCREG_ID_ISAR0)
3154 .allPrivileges().exceptUserMode().writes(0);
3155 InitReg(MISCREG_ID_ISAR1)
3156 .allPrivileges().exceptUserMode().writes(0);
3157 InitReg(MISCREG_ID_ISAR2)
3158 .allPrivileges().exceptUserMode().writes(0);
3159 InitReg(MISCREG_ID_ISAR3)
3160 .allPrivileges().exceptUserMode().writes(0);
3161 InitReg(MISCREG_ID_ISAR4)
3162 .allPrivileges().exceptUserMode().writes(0);
3163 InitReg(MISCREG_ID_ISAR5)
3164 .allPrivileges().exceptUserMode().writes(0);
3165 InitReg(MISCREG_CCSIDR)
3166 .allPrivileges().exceptUserMode().writes(0);
3167 InitReg(MISCREG_CLIDR)
3168 .allPrivileges().exceptUserMode().writes(0);
3169 InitReg(MISCREG_AIDR)
3170 .allPrivileges().exceptUserMode().writes(0);
3171 InitReg(MISCREG_CSSELR)
3172 .banked();
3173 InitReg(MISCREG_CSSELR_NS)
3174 .bankedChild()
3175 .privSecure(!aarch32EL3)
3176 .nonSecure().exceptUserMode();
3177 InitReg(MISCREG_CSSELR_S)
3178 .bankedChild()
3179 .secure().exceptUserMode();
3180 InitReg(MISCREG_VPIDR)
3181 .hyp().monNonSecure();
3182 InitReg(MISCREG_VMPIDR)
3183 .hyp().monNonSecure();
3184 InitReg(MISCREG_SCTLR)
3185 .banked()
3186 // readMiscRegNoEffect() uses this metadata
3187 // despite using children (below) as backing store
3188 .res0(0x8d22c600)
3189 .res1(0x00400800 | (SPAN ? 0 : 0x800000)
3190 | (LSMAOE ? 0 : 0x10)
3191 | (nTLSMD ? 0 : 0x8));
3192 InitReg(MISCREG_SCTLR_NS)
3193 .bankedChild()
3194 .privSecure(!aarch32EL3)
3195 .nonSecure().exceptUserMode();
3196 InitReg(MISCREG_SCTLR_S)
3197 .bankedChild()
3198 .secure().exceptUserMode();
3199 InitReg(MISCREG_ACTLR)
3200 .banked();
3201 InitReg(MISCREG_ACTLR_NS)
3202 .bankedChild()
3203 .privSecure(!aarch32EL3)
3204 .nonSecure().exceptUserMode();
3205 InitReg(MISCREG_ACTLR_S)
3206 .bankedChild()
3207 .secure().exceptUserMode();
3208 InitReg(MISCREG_CPACR)
3209 .allPrivileges().exceptUserMode();
3210 InitReg(MISCREG_SCR)
3211 .mon().secure().exceptUserMode()
3212 .res0(0xff40) // [31:16], [6]
3213 .res1(0x0030); // [5:4]
3214 InitReg(MISCREG_SDER)
3215 .mon();
3216 InitReg(MISCREG_NSACR)
3217 .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
3218 InitReg(MISCREG_HSCTLR)
3219 .hyp().monNonSecure()
3220 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
3221 | (IESB ? 0 : 0x200000)
3222 | (EnDA ? 0 : 0x8000000)
3223 | (EnIB ? 0 : 0x40000000)
3224 | (EnIA ? 0 : 0x80000000))
3225 .res1(0x30c50830);
3226 InitReg(MISCREG_HACTLR)
3227 .hyp().monNonSecure();
3228 InitReg(MISCREG_HCR)
3229 .hyp().monNonSecure()
3230 .res0(0x90000000);
3231 InitReg(MISCREG_HCR2)
3232 .hyp().monNonSecure()
3233 .res0(0xffa9ff8c);
3234 InitReg(MISCREG_HDCR)
3235 .hyp().monNonSecure();
3236 InitReg(MISCREG_HCPTR)
3237 .hyp().monNonSecure();
3238 InitReg(MISCREG_HSTR)
3239 .hyp().monNonSecure();
3240 InitReg(MISCREG_HACR)
3241 .unimplemented()
3242 .warnNotFail()
3243 .hyp().monNonSecure();
3244 InitReg(MISCREG_TTBR0)
3245 .banked();
3246 InitReg(MISCREG_TTBR0_NS)
3247 .bankedChild()
3248 .privSecure(!aarch32EL3)
3249 .nonSecure().exceptUserMode();
3250 InitReg(MISCREG_TTBR0_S)
3251 .bankedChild()
3252 .secure().exceptUserMode();
3253 InitReg(MISCREG_TTBR1)
3254 .banked();
3255 InitReg(MISCREG_TTBR1_NS)
3256 .bankedChild()
3257 .privSecure(!aarch32EL3)
3258 .nonSecure().exceptUserMode();
3259 InitReg(MISCREG_TTBR1_S)
3260 .bankedChild()
3261 .secure().exceptUserMode();
3262 InitReg(MISCREG_TTBCR)
3263 .banked();
3264 InitReg(MISCREG_TTBCR_NS)
3265 .bankedChild()
3266 .privSecure(!aarch32EL3)
3267 .nonSecure().exceptUserMode();
3268 InitReg(MISCREG_TTBCR_S)
3269 .bankedChild()
3270 .secure().exceptUserMode();
3271 InitReg(MISCREG_HTCR)
3272 .hyp().monNonSecure();
3273 InitReg(MISCREG_VTCR)
3274 .hyp().monNonSecure();
3275 InitReg(MISCREG_DACR)
3276 .banked();
3277 InitReg(MISCREG_DACR_NS)
3278 .bankedChild()
3279 .privSecure(!aarch32EL3)
3280 .nonSecure().exceptUserMode();
3281 InitReg(MISCREG_DACR_S)
3282 .bankedChild()
3283 .secure().exceptUserMode();
3284 InitReg(MISCREG_DFSR)
3285 .banked();
3286 InitReg(MISCREG_DFSR_NS)
3287 .bankedChild()
3288 .privSecure(!aarch32EL3)
3289 .nonSecure().exceptUserMode();
3290 InitReg(MISCREG_DFSR_S)
3291 .bankedChild()
3292 .secure().exceptUserMode();
3293 InitReg(MISCREG_IFSR)
3294 .banked();
3295 InitReg(MISCREG_IFSR_NS)
3296 .bankedChild()
3297 .privSecure(!aarch32EL3)
3298 .nonSecure().exceptUserMode();
3299 InitReg(MISCREG_IFSR_S)
3300 .bankedChild()
3301 .secure().exceptUserMode();
3302 InitReg(MISCREG_ADFSR)
3303 .unimplemented()
3304 .warnNotFail()
3305 .banked();
3306 InitReg(MISCREG_ADFSR_NS)
3307 .unimplemented()
3308 .warnNotFail()
3309 .bankedChild()
3310 .privSecure(!aarch32EL3)
3311 .nonSecure().exceptUserMode();
3312 InitReg(MISCREG_ADFSR_S)
3313 .unimplemented()
3314 .warnNotFail()
3315 .bankedChild()
3316 .secure().exceptUserMode();
3317 InitReg(MISCREG_AIFSR)
3318 .unimplemented()
3319 .warnNotFail()
3320 .banked();
3321 InitReg(MISCREG_AIFSR_NS)
3322 .unimplemented()
3323 .warnNotFail()
3324 .bankedChild()
3325 .privSecure(!aarch32EL3)
3326 .nonSecure().exceptUserMode();
3327 InitReg(MISCREG_AIFSR_S)
3328 .unimplemented()
3329 .warnNotFail()
3330 .bankedChild()
3331 .secure().exceptUserMode();
3332 InitReg(MISCREG_HADFSR)
3333 .hyp().monNonSecure();
3334 InitReg(MISCREG_HAIFSR)
3335 .hyp().monNonSecure();
3336 InitReg(MISCREG_HSR)
3337 .hyp().monNonSecure();
3338 InitReg(MISCREG_DFAR)
3339 .banked();
3340 InitReg(MISCREG_DFAR_NS)
3341 .bankedChild()
3342 .privSecure(!aarch32EL3)
3343 .nonSecure().exceptUserMode();
3344 InitReg(MISCREG_DFAR_S)
3345 .bankedChild()
3346 .secure().exceptUserMode();
3347 InitReg(MISCREG_IFAR)
3348 .banked();
3349 InitReg(MISCREG_IFAR_NS)
3350 .bankedChild()
3351 .privSecure(!aarch32EL3)
3352 .nonSecure().exceptUserMode();
3353 InitReg(MISCREG_IFAR_S)
3354 .bankedChild()
3355 .secure().exceptUserMode();
3356 InitReg(MISCREG_HDFAR)
3357 .hyp().monNonSecure();
3358 InitReg(MISCREG_HIFAR)
3359 .hyp().monNonSecure();
3360 InitReg(MISCREG_HPFAR)
3361 .hyp().monNonSecure();
3362 InitReg(MISCREG_ICIALLUIS)
3363 .unimplemented()
3364 .warnNotFail()
3365 .writes(1).exceptUserMode();
3366 InitReg(MISCREG_BPIALLIS)
3367 .unimplemented()
3368 .warnNotFail()
3369 .writes(1).exceptUserMode();
3370 InitReg(MISCREG_PAR)
3371 .banked();
3372 InitReg(MISCREG_PAR_NS)
3373 .bankedChild()
3374 .privSecure(!aarch32EL3)
3375 .nonSecure().exceptUserMode();
3376 InitReg(MISCREG_PAR_S)
3377 .bankedChild()
3378 .secure().exceptUserMode();
3379 InitReg(MISCREG_ICIALLU)
3380 .writes(1).exceptUserMode();
3381 InitReg(MISCREG_ICIMVAU)
3382 .unimplemented()
3383 .warnNotFail()
3384 .writes(1).exceptUserMode();
3385 InitReg(MISCREG_CP15ISB)
3386 .writes(1);
3387 InitReg(MISCREG_BPIALL)
3388 .unimplemented()
3389 .warnNotFail()
3390 .writes(1).exceptUserMode();
3391 InitReg(MISCREG_BPIMVA)
3392 .unimplemented()
3393 .warnNotFail()
3394 .writes(1).exceptUserMode();
3395 InitReg(MISCREG_DCIMVAC)
3396 .unimplemented()
3397 .warnNotFail()
3398 .writes(1).exceptUserMode();
3399 InitReg(MISCREG_DCISW)
3400 .unimplemented()
3401 .warnNotFail()
3402 .writes(1).exceptUserMode();
3403 InitReg(MISCREG_ATS1CPR)
3404 .writes(1).exceptUserMode();
3405 InitReg(MISCREG_ATS1CPW)
3406 .writes(1).exceptUserMode();
3407 InitReg(MISCREG_ATS1CUR)
3408 .writes(1).exceptUserMode();
3409 InitReg(MISCREG_ATS1CUW)
3410 .writes(1).exceptUserMode();
3411 InitReg(MISCREG_ATS12NSOPR)
3412 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3413 InitReg(MISCREG_ATS12NSOPW)
3414 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3415 InitReg(MISCREG_ATS12NSOUR)
3416 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3417 InitReg(MISCREG_ATS12NSOUW)
3418 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3419 InitReg(MISCREG_DCCMVAC)
3420 .writes(1).exceptUserMode();
3421 InitReg(MISCREG_DCCSW)
3422 .unimplemented()
3423 .warnNotFail()
3424 .writes(1).exceptUserMode();
3425 InitReg(MISCREG_CP15DSB)
3426 .writes(1);
3427 InitReg(MISCREG_CP15DMB)
3428 .writes(1);
3429 InitReg(MISCREG_DCCMVAU)
3430 .unimplemented()
3431 .warnNotFail()
3432 .writes(1).exceptUserMode();
3433 InitReg(MISCREG_DCCIMVAC)
3434 .unimplemented()
3435 .warnNotFail()
3436 .writes(1).exceptUserMode();
3437 InitReg(MISCREG_DCCISW)
3438 .unimplemented()
3439 .warnNotFail()
3440 .writes(1).exceptUserMode();
3441 InitReg(MISCREG_ATS1HR)
3442 .monNonSecureWrite().hypWrite();
3443 InitReg(MISCREG_ATS1HW)
3444 .monNonSecureWrite().hypWrite();
3445 InitReg(MISCREG_TLBIALLIS)
3446 .writes(1).exceptUserMode();
3447 InitReg(MISCREG_TLBIMVAIS)
3448 .writes(1).exceptUserMode();
3449 InitReg(MISCREG_TLBIASIDIS)
3450 .writes(1).exceptUserMode();
3451 InitReg(MISCREG_TLBIMVAAIS)
3452 .writes(1).exceptUserMode();
3453 InitReg(MISCREG_TLBIMVALIS)
3454 .writes(1).exceptUserMode();
3455 InitReg(MISCREG_TLBIMVAALIS)
3456 .writes(1).exceptUserMode();
3457 InitReg(MISCREG_ITLBIALL)
3458 .writes(1).exceptUserMode();
3459 InitReg(MISCREG_ITLBIMVA)
3460 .writes(1).exceptUserMode();
3461 InitReg(MISCREG_ITLBIASID)
3462 .writes(1).exceptUserMode();
3463 InitReg(MISCREG_DTLBIALL)
3464 .writes(1).exceptUserMode();
3465 InitReg(MISCREG_DTLBIMVA)
3466 .writes(1).exceptUserMode();
3467 InitReg(MISCREG_DTLBIASID)
3468 .writes(1).exceptUserMode();
3469 InitReg(MISCREG_TLBIALL)
3470 .writes(1).exceptUserMode();
3471 InitReg(MISCREG_TLBIMVA)
3472 .writes(1).exceptUserMode();
3473 InitReg(MISCREG_TLBIASID)
3474 .writes(1).exceptUserMode();
3475 InitReg(MISCREG_TLBIMVAA)
3476 .writes(1).exceptUserMode();
3477 InitReg(MISCREG_TLBIMVAL)
3478 .writes(1).exceptUserMode();
3479 InitReg(MISCREG_TLBIMVAAL)
3480 .writes(1).exceptUserMode();
3481 InitReg(MISCREG_TLBIIPAS2IS)
3482 .monNonSecureWrite().hypWrite();
3483 InitReg(MISCREG_TLBIIPAS2LIS)
3484 .monNonSecureWrite().hypWrite();
3485 InitReg(MISCREG_TLBIALLHIS)
3486 .monNonSecureWrite().hypWrite();
3487 InitReg(MISCREG_TLBIMVAHIS)
3488 .monNonSecureWrite().hypWrite();
3489 InitReg(MISCREG_TLBIALLNSNHIS)
3490 .monNonSecureWrite().hypWrite();
3491 InitReg(MISCREG_TLBIMVALHIS)
3492 .monNonSecureWrite().hypWrite();
3493 InitReg(MISCREG_TLBIIPAS2)
3494 .monNonSecureWrite().hypWrite();
3495 InitReg(MISCREG_TLBIIPAS2L)
3496 .monNonSecureWrite().hypWrite();
3497 InitReg(MISCREG_TLBIALLH)
3498 .monNonSecureWrite().hypWrite();
3499 InitReg(MISCREG_TLBIMVAH)
3500 .monNonSecureWrite().hypWrite();
3501 InitReg(MISCREG_TLBIALLNSNH)
3502 .monNonSecureWrite().hypWrite();
3503 InitReg(MISCREG_TLBIMVALH)
3504 .monNonSecureWrite().hypWrite();
3505 InitReg(MISCREG_PMCR)
3506 .allPrivileges();
3507 InitReg(MISCREG_PMCNTENSET)
3508 .allPrivileges();
3509 InitReg(MISCREG_PMCNTENCLR)
3510 .allPrivileges();
3511 InitReg(MISCREG_PMOVSR)
3512 .allPrivileges();
3513 InitReg(MISCREG_PMSWINC)
3514 .allPrivileges();
3515 InitReg(MISCREG_PMSELR)
3516 .allPrivileges();
3517 InitReg(MISCREG_PMCEID0)
3518 .allPrivileges();
3519 InitReg(MISCREG_PMCEID1)
3520 .allPrivileges();
3521 InitReg(MISCREG_PMCCNTR)
3522 .allPrivileges();
3523 InitReg(MISCREG_PMXEVTYPER)
3524 .allPrivileges();
3525 InitReg(MISCREG_PMCCFILTR)
3526 .allPrivileges();
3527 InitReg(MISCREG_PMXEVCNTR)
3528 .allPrivileges();
3529 InitReg(MISCREG_PMUSERENR)
3530 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
3531 InitReg(MISCREG_PMINTENSET)
3532 .allPrivileges().exceptUserMode();
3533 InitReg(MISCREG_PMINTENCLR)
3534 .allPrivileges().exceptUserMode();
3535 InitReg(MISCREG_PMOVSSET)
3536 .unimplemented()
3537 .allPrivileges();
3538 InitReg(MISCREG_L2CTLR)
3539 .allPrivileges().exceptUserMode();
3540 InitReg(MISCREG_L2ECTLR)
3541 .unimplemented()
3542 .allPrivileges().exceptUserMode();
3543 InitReg(MISCREG_PRRR)
3544 .banked();
3545 InitReg(MISCREG_PRRR_NS)
3546 .bankedChild()
3547 .privSecure(!aarch32EL3)
3548 .nonSecure().exceptUserMode();
3549 InitReg(MISCREG_PRRR_S)
3550 .bankedChild()
3551 .secure().exceptUserMode();
3552 InitReg(MISCREG_MAIR0)
3553 .banked();
3554 InitReg(MISCREG_MAIR0_NS)
3555 .bankedChild()
3556 .privSecure(!aarch32EL3)
3557 .nonSecure().exceptUserMode();
3558 InitReg(MISCREG_MAIR0_S)
3559 .bankedChild()
3560 .secure().exceptUserMode();
3561 InitReg(MISCREG_NMRR)
3562 .banked();
3563 InitReg(MISCREG_NMRR_NS)
3564 .bankedChild()
3565 .privSecure(!aarch32EL3)
3566 .nonSecure().exceptUserMode();
3567 InitReg(MISCREG_NMRR_S)
3568 .bankedChild()
3569 .secure().exceptUserMode();
3570 InitReg(MISCREG_MAIR1)
3571 .banked();
3572 InitReg(MISCREG_MAIR1_NS)
3573 .bankedChild()
3574 .privSecure(!aarch32EL3)
3575 .nonSecure().exceptUserMode();
3576 InitReg(MISCREG_MAIR1_S)
3577 .bankedChild()
3578 .secure().exceptUserMode();
3579 InitReg(MISCREG_AMAIR0)
3580 .banked();
3581 InitReg(MISCREG_AMAIR0_NS)
3582 .bankedChild()
3583 .privSecure(!aarch32EL3)
3584 .nonSecure().exceptUserMode();
3585 InitReg(MISCREG_AMAIR0_S)
3586 .bankedChild()
3587 .secure().exceptUserMode();
3588 InitReg(MISCREG_AMAIR1)
3589 .banked();
3590 InitReg(MISCREG_AMAIR1_NS)
3591 .bankedChild()
3592 .privSecure(!aarch32EL3)
3593 .nonSecure().exceptUserMode();
3594 InitReg(MISCREG_AMAIR1_S)
3595 .bankedChild()
3596 .secure().exceptUserMode();
3597 InitReg(MISCREG_HMAIR0)
3598 .hyp().monNonSecure();
3599 InitReg(MISCREG_HMAIR1)
3600 .hyp().monNonSecure();
3601 InitReg(MISCREG_HAMAIR0)
3602 .unimplemented()
3603 .warnNotFail()
3604 .hyp().monNonSecure();
3605 InitReg(MISCREG_HAMAIR1)
3606 .unimplemented()
3607 .warnNotFail()
3608 .hyp().monNonSecure();
3609 InitReg(MISCREG_VBAR)
3610 .banked();
3611 InitReg(MISCREG_VBAR_NS)
3612 .bankedChild()
3613 .privSecure(!aarch32EL3)
3614 .nonSecure().exceptUserMode();
3615 InitReg(MISCREG_VBAR_S)
3616 .bankedChild()
3617 .secure().exceptUserMode();
3618 InitReg(MISCREG_MVBAR)
3619 .mon().secure()
3620 .hypRead(FullSystem && system->highestEL() == EL2)
3621 .privRead(FullSystem && system->highestEL() == EL1)
3622 .exceptUserMode();
3623 InitReg(MISCREG_RMR)
3624 .unimplemented()
3625 .mon().secure().exceptUserMode();
3626 InitReg(MISCREG_ISR)
3627 .allPrivileges().exceptUserMode().writes(0);
3628 InitReg(MISCREG_HVBAR)
3629 .hyp().monNonSecure()
3630 .res0(0x1f);
3631 InitReg(MISCREG_FCSEIDR)
3632 .unimplemented()
3633 .warnNotFail()
3634 .allPrivileges().exceptUserMode();
3635 InitReg(MISCREG_CONTEXTIDR)
3636 .banked();
3637 InitReg(MISCREG_CONTEXTIDR_NS)
3638 .bankedChild()
3639 .privSecure(!aarch32EL3)
3640 .nonSecure().exceptUserMode();
3641 InitReg(MISCREG_CONTEXTIDR_S)
3642 .bankedChild()
3643 .secure().exceptUserMode();
3644 InitReg(MISCREG_TPIDRURW)
3645 .banked();
3646 InitReg(MISCREG_TPIDRURW_NS)
3647 .bankedChild()
3648 .allPrivileges()
3649 .privSecure(!aarch32EL3)
3650 .monSecure(0);
3651 InitReg(MISCREG_TPIDRURW_S)
3652 .bankedChild()
3653 .secure();
3654 InitReg(MISCREG_TPIDRURO)
3655 .banked();
3656 InitReg(MISCREG_TPIDRURO_NS)
3657 .bankedChild()
3658 .allPrivileges()
3659 .userNonSecureWrite(0).userSecureRead(1)
3660 .privSecure(!aarch32EL3)
3661 .monSecure(0);
3662 InitReg(MISCREG_TPIDRURO_S)
3663 .bankedChild()
3664 .secure().userSecureWrite(0);
3665 InitReg(MISCREG_TPIDRPRW)
3666 .banked();
3667 InitReg(MISCREG_TPIDRPRW_NS)
3668 .bankedChild()
3669 .nonSecure().exceptUserMode()
3670 .privSecure(!aarch32EL3);
3671 InitReg(MISCREG_TPIDRPRW_S)
3672 .bankedChild()
3673 .secure().exceptUserMode();
3674 InitReg(MISCREG_HTPIDR)
3675 .hyp().monNonSecure();
3676 InitReg(MISCREG_CNTFRQ)
3677 .unverifiable()
3678 .reads(1).mon();
3679 InitReg(MISCREG_CNTKCTL)
3680 .allPrivileges().exceptUserMode();
3681 InitReg(MISCREG_CNTP_TVAL)
3682 .banked();
3683 InitReg(MISCREG_CNTP_TVAL_NS)
3684 .bankedChild()
3685 .allPrivileges()
3686 .privSecure(!aarch32EL3)
3687 .monSecure(0);
3688 InitReg(MISCREG_CNTP_TVAL_S)
3689 .bankedChild()
3690 .secure().user(1);
3691 InitReg(MISCREG_CNTP_CTL)
3692 .banked();
3693 InitReg(MISCREG_CNTP_CTL_NS)
3694 .bankedChild()
3695 .allPrivileges()
3696 .privSecure(!aarch32EL3)
3697 .monSecure(0);
3698 InitReg(MISCREG_CNTP_CTL_S)
3699 .bankedChild()
3700 .secure().user(1);
3701 InitReg(MISCREG_CNTV_TVAL)
3702 .allPrivileges();
3703 InitReg(MISCREG_CNTV_CTL)
3704 .allPrivileges();
3705 InitReg(MISCREG_CNTHCTL)
3706 .hypWrite().monNonSecureRead();
3707 InitReg(MISCREG_CNTHP_TVAL)
3708 .hypWrite().monNonSecureRead();
3709 InitReg(MISCREG_CNTHP_CTL)
3710 .hypWrite().monNonSecureRead();
3711 InitReg(MISCREG_IL1DATA0)
3712 .unimplemented()
3713 .allPrivileges().exceptUserMode();
3714 InitReg(MISCREG_IL1DATA1)
3715 .unimplemented()
3716 .allPrivileges().exceptUserMode();
3717 InitReg(MISCREG_IL1DATA2)
3718 .unimplemented()
3719 .allPrivileges().exceptUserMode();
3720 InitReg(MISCREG_IL1DATA3)
3721 .unimplemented()
3722 .allPrivileges().exceptUserMode();
3723 InitReg(MISCREG_DL1DATA0)
3724 .unimplemented()
3725 .allPrivileges().exceptUserMode();
3726 InitReg(MISCREG_DL1DATA1)
3727 .unimplemented()
3728 .allPrivileges().exceptUserMode();
3729 InitReg(MISCREG_DL1DATA2)
3730 .unimplemented()
3731 .allPrivileges().exceptUserMode();
3732 InitReg(MISCREG_DL1DATA3)
3733 .unimplemented()
3734 .allPrivileges().exceptUserMode();
3735 InitReg(MISCREG_DL1DATA4)
3736 .unimplemented()
3737 .allPrivileges().exceptUserMode();
3738 InitReg(MISCREG_RAMINDEX)
3739 .unimplemented()
3740 .writes(1).exceptUserMode();
3741 InitReg(MISCREG_L2ACTLR)
3742 .unimplemented()
3743 .allPrivileges().exceptUserMode();
3744 InitReg(MISCREG_CBAR)
3745 .unimplemented()
3746 .allPrivileges().exceptUserMode().writes(0);
3747 InitReg(MISCREG_HTTBR)
3748 .hyp().monNonSecure();
3749 InitReg(MISCREG_VTTBR)
3750 .hyp().monNonSecure();
3751 InitReg(MISCREG_CNTPCT)
3752 .reads(1);
3753 InitReg(MISCREG_CNTVCT)
3754 .unverifiable()
3755 .reads(1);
3756 InitReg(MISCREG_CNTP_CVAL)
3757 .banked();
3758 InitReg(MISCREG_CNTP_CVAL_NS)
3759 .bankedChild()
3760 .allPrivileges()
3761 .privSecure(!aarch32EL3)
3762 .monSecure(0);
3763 InitReg(MISCREG_CNTP_CVAL_S)
3764 .bankedChild()
3765 .secure().user(1);
3766 InitReg(MISCREG_CNTV_CVAL)
3767 .allPrivileges();
3768 InitReg(MISCREG_CNTVOFF)
3769 .hyp().monNonSecure();
3770 InitReg(MISCREG_CNTHP_CVAL)
3771 .hypWrite().monNonSecureRead();
3772 InitReg(MISCREG_CPUMERRSR)
3773 .unimplemented()
3774 .allPrivileges().exceptUserMode();
3775 InitReg(MISCREG_L2MERRSR)
3776 .unimplemented()
3777 .warnNotFail()
3778 .allPrivileges().exceptUserMode();
3779
3780 // AArch64 registers (Op0=2);
3781 InitReg(MISCREG_MDCCINT_EL1)
3782 .allPrivileges();
3783 InitReg(MISCREG_OSDTRRX_EL1)
3784 .allPrivileges()
3785 .mapsTo(MISCREG_DBGDTRRXext);
3786 InitReg(MISCREG_MDSCR_EL1)
3787 .allPrivileges()
3788 .mapsTo(MISCREG_DBGDSCRext);
3789 InitReg(MISCREG_OSDTRTX_EL1)
3790 .allPrivileges()
3791 .mapsTo(MISCREG_DBGDTRTXext);
3792 InitReg(MISCREG_OSECCR_EL1)
3793 .allPrivileges()
3794 .mapsTo(MISCREG_DBGOSECCR);
3795 InitReg(MISCREG_DBGBVR0_EL1)
3796 .allPrivileges()
3797 .mapsTo(MISCREG_DBGBVR0 /*, MISCREG_DBGBXVR0 */);
3798 InitReg(MISCREG_DBGBVR1_EL1)
3799 .allPrivileges()
3800 .mapsTo(MISCREG_DBGBVR1 /*, MISCREG_DBGBXVR1 */);
3801 InitReg(MISCREG_DBGBVR2_EL1)
3802 .allPrivileges()
3803 .mapsTo(MISCREG_DBGBVR2 /*, MISCREG_DBGBXVR2 */);
3804 InitReg(MISCREG_DBGBVR3_EL1)
3805 .allPrivileges()
3806 .mapsTo(MISCREG_DBGBVR3 /*, MISCREG_DBGBXVR3 */);
3807 InitReg(MISCREG_DBGBVR4_EL1)
3808 .allPrivileges()
3809 .mapsTo(MISCREG_DBGBVR4 /*, MISCREG_DBGBXVR4 */);
3810 InitReg(MISCREG_DBGBVR5_EL1)
3811 .allPrivileges()
3812 .mapsTo(MISCREG_DBGBVR5 /*, MISCREG_DBGBXVR5 */);
3813 InitReg(MISCREG_DBGBCR0_EL1)
3814 .allPrivileges()
3815 .mapsTo(MISCREG_DBGBCR0);
3816 InitReg(MISCREG_DBGBCR1_EL1)
3817 .allPrivileges()
3818 .mapsTo(MISCREG_DBGBCR1);
3819 InitReg(MISCREG_DBGBCR2_EL1)
3820 .allPrivileges()
3821 .mapsTo(MISCREG_DBGBCR2);
3822 InitReg(MISCREG_DBGBCR3_EL1)
3823 .allPrivileges()
3824 .mapsTo(MISCREG_DBGBCR3);
3825 InitReg(MISCREG_DBGBCR4_EL1)
3826 .allPrivileges()
3827 .mapsTo(MISCREG_DBGBCR4);
3828 InitReg(MISCREG_DBGBCR5_EL1)
3829 .allPrivileges()
3830 .mapsTo(MISCREG_DBGBCR5);
3831 InitReg(MISCREG_DBGWVR0_EL1)
3832 .allPrivileges()
3833 .mapsTo(MISCREG_DBGWVR0);
3834 InitReg(MISCREG_DBGWVR1_EL1)
3835 .allPrivileges()
3836 .mapsTo(MISCREG_DBGWVR1);
3837 InitReg(MISCREG_DBGWVR2_EL1)
3838 .allPrivileges()
3839 .mapsTo(MISCREG_DBGWVR2);
3840 InitReg(MISCREG_DBGWVR3_EL1)
3841 .allPrivileges()
3842 .mapsTo(MISCREG_DBGWVR3);
3843 InitReg(MISCREG_DBGWCR0_EL1)
3844 .allPrivileges()
3845 .mapsTo(MISCREG_DBGWCR0);
3846 InitReg(MISCREG_DBGWCR1_EL1)
3847 .allPrivileges()
3848 .mapsTo(MISCREG_DBGWCR1);
3849 InitReg(MISCREG_DBGWCR2_EL1)
3850 .allPrivileges()
3851 .mapsTo(MISCREG_DBGWCR2);
3852 InitReg(MISCREG_DBGWCR3_EL1)
3853 .allPrivileges()
3854 .mapsTo(MISCREG_DBGWCR3);
3855 InitReg(MISCREG_MDCCSR_EL0)
3856 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3857 .mapsTo(MISCREG_DBGDSCRint);
3858 InitReg(MISCREG_MDDTR_EL0)
3859 .allPrivileges();
3860 InitReg(MISCREG_MDDTRTX_EL0)
3861 .allPrivileges();
3862 InitReg(MISCREG_MDDTRRX_EL0)
3863 .allPrivileges();
3864 InitReg(MISCREG_DBGVCR32_EL2)
3865 .allPrivileges()
3866 .mapsTo(MISCREG_DBGVCR);
3867 InitReg(MISCREG_MDRAR_EL1)
3868 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3869 .mapsTo(MISCREG_DBGDRAR);
3870 InitReg(MISCREG_OSLAR_EL1)
3871 .allPrivileges().monSecureRead(0).monNonSecureRead(0)
3872 .mapsTo(MISCREG_DBGOSLAR);
3873 InitReg(MISCREG_OSLSR_EL1)
3874 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3875 .mapsTo(MISCREG_DBGOSLSR);
3876 InitReg(MISCREG_OSDLR_EL1)
3877 .allPrivileges()
3878 .mapsTo(MISCREG_DBGOSDLR);
3879 InitReg(MISCREG_DBGPRCR_EL1)
3880 .allPrivileges()
3881 .mapsTo(MISCREG_DBGPRCR);
3882 InitReg(MISCREG_DBGCLAIMSET_EL1)
3883 .allPrivileges()
3884 .mapsTo(MISCREG_DBGCLAIMSET);
3885 InitReg(MISCREG_DBGCLAIMCLR_EL1)
3886 .allPrivileges()
3887 .mapsTo(MISCREG_DBGCLAIMCLR);
3888 InitReg(MISCREG_DBGAUTHSTATUS_EL1)
3889 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3890 .mapsTo(MISCREG_DBGAUTHSTATUS);
3891 InitReg(MISCREG_TEECR32_EL1);
3892 InitReg(MISCREG_TEEHBR32_EL1);
3893
3894 // AArch64 registers (Op0=1,3);
3895 InitReg(MISCREG_MIDR_EL1)
3896 .allPrivileges().exceptUserMode().writes(0);
3897 InitReg(MISCREG_MPIDR_EL1)
3898 .allPrivileges().exceptUserMode().writes(0);
3899 InitReg(MISCREG_REVIDR_EL1)
3900 .allPrivileges().exceptUserMode().writes(0);
3901 InitReg(MISCREG_ID_PFR0_EL1)
3902 .allPrivileges().exceptUserMode().writes(0)
3903 .mapsTo(MISCREG_ID_PFR0);
3904 InitReg(MISCREG_ID_PFR1_EL1)
3905 .allPrivileges().exceptUserMode().writes(0)
3906 .mapsTo(MISCREG_ID_PFR1);
3907 InitReg(MISCREG_ID_DFR0_EL1)
3908 .allPrivileges().exceptUserMode().writes(0)
3909 .mapsTo(MISCREG_ID_DFR0);
3910 InitReg(MISCREG_ID_AFR0_EL1)
3911 .allPrivileges().exceptUserMode().writes(0)
3912 .mapsTo(MISCREG_ID_AFR0);
3913 InitReg(MISCREG_ID_MMFR0_EL1)
3914 .allPrivileges().exceptUserMode().writes(0)
3915 .mapsTo(MISCREG_ID_MMFR0);
3916 InitReg(MISCREG_ID_MMFR1_EL1)
3917 .allPrivileges().exceptUserMode().writes(0)
3918 .mapsTo(MISCREG_ID_MMFR1);
3919 InitReg(MISCREG_ID_MMFR2_EL1)
3920 .allPrivileges().exceptUserMode().writes(0)
3921 .mapsTo(MISCREG_ID_MMFR2);
3922 InitReg(MISCREG_ID_MMFR3_EL1)
3923 .allPrivileges().exceptUserMode().writes(0)
3924 .mapsTo(MISCREG_ID_MMFR3);
3925 InitReg(MISCREG_ID_ISAR0_EL1)
3926 .allPrivileges().exceptUserMode().writes(0)
3927 .mapsTo(MISCREG_ID_ISAR0);
3928 InitReg(MISCREG_ID_ISAR1_EL1)
3929 .allPrivileges().exceptUserMode().writes(0)
3930 .mapsTo(MISCREG_ID_ISAR1);
3931 InitReg(MISCREG_ID_ISAR2_EL1)
3932 .allPrivileges().exceptUserMode().writes(0)
3933 .mapsTo(MISCREG_ID_ISAR2);
3934 InitReg(MISCREG_ID_ISAR3_EL1)
3935 .allPrivileges().exceptUserMode().writes(0)
3936 .mapsTo(MISCREG_ID_ISAR3);
3937 InitReg(MISCREG_ID_ISAR4_EL1)
3938 .allPrivileges().exceptUserMode().writes(0)
3939 .mapsTo(MISCREG_ID_ISAR4);
3940 InitReg(MISCREG_ID_ISAR5_EL1)
3941 .allPrivileges().exceptUserMode().writes(0)
3942 .mapsTo(MISCREG_ID_ISAR5);
3943 InitReg(MISCREG_MVFR0_EL1)
3944 .allPrivileges().exceptUserMode().writes(0);
3945 InitReg(MISCREG_MVFR1_EL1)
3946 .allPrivileges().exceptUserMode().writes(0);
3947 InitReg(MISCREG_MVFR2_EL1)
3948 .allPrivileges().exceptUserMode().writes(0);
3949 InitReg(MISCREG_ID_AA64PFR0_EL1)
3950 .allPrivileges().exceptUserMode().writes(0);
3951 InitReg(MISCREG_ID_AA64PFR1_EL1)
3952 .allPrivileges().exceptUserMode().writes(0);
3953 InitReg(MISCREG_ID_AA64DFR0_EL1)
3954 .allPrivileges().exceptUserMode().writes(0);
3955 InitReg(MISCREG_ID_AA64DFR1_EL1)
3956 .allPrivileges().exceptUserMode().writes(0);
3957 InitReg(MISCREG_ID_AA64AFR0_EL1)
3958 .allPrivileges().exceptUserMode().writes(0);
3959 InitReg(MISCREG_ID_AA64AFR1_EL1)
3960 .allPrivileges().exceptUserMode().writes(0);
3961 InitReg(MISCREG_ID_AA64ISAR0_EL1)
3962 .allPrivileges().exceptUserMode().writes(0);
3963 InitReg(MISCREG_ID_AA64ISAR1_EL1)
3964 .allPrivileges().exceptUserMode().writes(0);
3965 InitReg(MISCREG_ID_AA64MMFR0_EL1)
3966 .allPrivileges().exceptUserMode().writes(0);
3967 InitReg(MISCREG_ID_AA64MMFR1_EL1)
3968 .allPrivileges().exceptUserMode().writes(0);
3969 InitReg(MISCREG_ID_AA64MMFR2_EL1)
3970 .allPrivileges().exceptUserMode().writes(0);
3971 InitReg(MISCREG_CCSIDR_EL1)
3972 .allPrivileges().exceptUserMode().writes(0);
3973 InitReg(MISCREG_CLIDR_EL1)
3974 .allPrivileges().exceptUserMode().writes(0);
3975 InitReg(MISCREG_AIDR_EL1)
3976 .allPrivileges().exceptUserMode().writes(0);
3977 InitReg(MISCREG_CSSELR_EL1)
3978 .allPrivileges().exceptUserMode()
3979 .mapsTo(MISCREG_CSSELR_NS);
3980 InitReg(MISCREG_CTR_EL0)
3981 .reads(1);
3982 InitReg(MISCREG_DCZID_EL0)
3983 .reads(1);
3984 InitReg(MISCREG_VPIDR_EL2)
3985 .hyp().mon()
3986 .mapsTo(MISCREG_VPIDR);
3987 InitReg(MISCREG_VMPIDR_EL2)
3988 .hyp().mon()
3989 .mapsTo(MISCREG_VMPIDR);
3990 InitReg(MISCREG_SCTLR_EL1)
3991 .allPrivileges().exceptUserMode()
3992 .res0( 0x20440 | (EnDB ? 0 : 0x2000)
3993 | (IESB ? 0 : 0x200000)
3994 | (EnDA ? 0 : 0x8000000)
3995 | (EnIB ? 0 : 0x40000000)
3996 | (EnIA ? 0 : 0x80000000))
3997 .res1(0x500800 | (SPAN ? 0 : 0x800000)
3998 | (nTLSMD ? 0 : 0x8000000)
3999 | (LSMAOE ? 0 : 0x10000000))
4000 .mapsTo(MISCREG_SCTLR_NS);
4001 InitReg(MISCREG_ACTLR_EL1)
4002 .allPrivileges().exceptUserMode()
4003 .mapsTo(MISCREG_ACTLR_NS);
4004 InitReg(MISCREG_CPACR_EL1)
4005 .allPrivileges().exceptUserMode()
4006 .mapsTo(MISCREG_CPACR);
4007 InitReg(MISCREG_SCTLR_EL2)
4008 .hyp().mon()
4009 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
4010 | (IESB ? 0 : 0x200000)
4011 | (EnDA ? 0 : 0x8000000)
4012 | (EnIB ? 0 : 0x40000000)
4013 | (EnIA ? 0 : 0x80000000))
4014 .res1(0x30c50830)
4015 .mapsTo(MISCREG_HSCTLR);
4016 InitReg(MISCREG_ACTLR_EL2)
4017 .hyp().mon()
4018 .mapsTo(MISCREG_HACTLR);
4019 InitReg(MISCREG_HCR_EL2)
4020 .hyp().mon()
4021 .mapsTo(MISCREG_HCR, MISCREG_HCR2);
4022 InitReg(MISCREG_MDCR_EL2)
4023 .hyp().mon()
4024 .mapsTo(MISCREG_HDCR);
4025 InitReg(MISCREG_CPTR_EL2)
4026 .hyp().mon()
4027 .mapsTo(MISCREG_HCPTR);
4028 InitReg(MISCREG_HSTR_EL2)
4029 .hyp().mon()
4030 .mapsTo(MISCREG_HSTR);
4031 InitReg(MISCREG_HACR_EL2)
4032 .hyp().mon()
4033 .mapsTo(MISCREG_HACR);
4034 InitReg(MISCREG_SCTLR_EL3)
4035 .mon()
4036 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
4037 | (IESB ? 0 : 0x200000)
4038 | (EnDA ? 0 : 0x8000000)
4039 | (EnIB ? 0 : 0x40000000)
4040 | (EnIA ? 0 : 0x80000000))
4041 .res1(0x30c50830);
4042 InitReg(MISCREG_ACTLR_EL3)
4043 .mon();
4044 InitReg(MISCREG_SCR_EL3)
4045 .mon()
4046 .mapsTo(MISCREG_SCR); // NAM D7-2005
4047 InitReg(MISCREG_SDER32_EL3)
4048 .mon()
4049 .mapsTo(MISCREG_SDER);
4050 InitReg(MISCREG_CPTR_EL3)
4051 .mon();
4052 InitReg(MISCREG_MDCR_EL3)
4053 .mon();
4054 InitReg(MISCREG_TTBR0_EL1)
4055 .allPrivileges().exceptUserMode()
4056 .mapsTo(MISCREG_TTBR0_NS);
4057 InitReg(MISCREG_TTBR1_EL1)
4058 .allPrivileges().exceptUserMode()
4059 .mapsTo(MISCREG_TTBR1_NS);
4060 InitReg(MISCREG_TCR_EL1)
4061 .allPrivileges().exceptUserMode()
4062 .mapsTo(MISCREG_TTBCR_NS);
4063 InitReg(MISCREG_TTBR0_EL2)
4064 .hyp().mon()
4065 .mapsTo(MISCREG_HTTBR);
4066 InitReg(MISCREG_TTBR1_EL2)
4067 .hyp().mon();
4068 InitReg(MISCREG_TCR_EL2)
4069 .hyp().mon()
4070 .mapsTo(MISCREG_HTCR);
4071 InitReg(MISCREG_VTTBR_EL2)
4072 .hyp().mon()
4073 .mapsTo(MISCREG_VTTBR);
4074 InitReg(MISCREG_VTCR_EL2)
4075 .hyp().mon()
4076 .mapsTo(MISCREG_VTCR);
4077 InitReg(MISCREG_TTBR0_EL3)
4078 .mon();
4079 InitReg(MISCREG_TCR_EL3)
4080 .mon();
4081 InitReg(MISCREG_DACR32_EL2)
4082 .hyp().mon()
4083 .mapsTo(MISCREG_DACR_NS);
4084 InitReg(MISCREG_SPSR_EL1)
4085 .allPrivileges().exceptUserMode()
4086 .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
4087 InitReg(MISCREG_ELR_EL1)
4088 .allPrivileges().exceptUserMode();
4089 InitReg(MISCREG_SP_EL0)
4090 .allPrivileges().exceptUserMode();
4091 InitReg(MISCREG_SPSEL)
4092 .allPrivileges().exceptUserMode();
4093 InitReg(MISCREG_CURRENTEL)
4094 .allPrivileges().exceptUserMode().writes(0);
4095 InitReg(MISCREG_PAN)
4096 .allPrivileges().exceptUserMode()
4097 .implemented(havePAN);
4098 InitReg(MISCREG_NZCV)
4099 .allPrivileges();
4100 InitReg(MISCREG_DAIF)
4101 .allPrivileges();
4102 InitReg(MISCREG_FPCR)
4103 .allPrivileges();
4104 InitReg(MISCREG_FPSR)
4105 .allPrivileges();
4106 InitReg(MISCREG_DSPSR_EL0)
4107 .allPrivileges();
4108 InitReg(MISCREG_DLR_EL0)
4109 .allPrivileges();
4110 InitReg(MISCREG_SPSR_EL2)
4111 .hyp().mon()
4112 .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2
4113 InitReg(MISCREG_ELR_EL2)
4114 .hyp().mon();
4115 InitReg(MISCREG_SP_EL1)
4116 .hyp().mon();
4117 InitReg(MISCREG_SPSR_IRQ_AA64)
4118 .hyp().mon();
4119 InitReg(MISCREG_SPSR_ABT_AA64)
4120 .hyp().mon();
4121 InitReg(MISCREG_SPSR_UND_AA64)
4122 .hyp().mon();
4123 InitReg(MISCREG_SPSR_FIQ_AA64)
4124 .hyp().mon();
4125 InitReg(MISCREG_SPSR_EL3)
4126 .mon()
4127 .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3
4128 InitReg(MISCREG_ELR_EL3)
4129 .mon();
4130 InitReg(MISCREG_SP_EL2)
4131 .mon();
4132 InitReg(MISCREG_AFSR0_EL1)
4133 .allPrivileges().exceptUserMode()
4134 .mapsTo(MISCREG_ADFSR_NS);
4135 InitReg(MISCREG_AFSR1_EL1)
4136 .allPrivileges().exceptUserMode()
4137 .mapsTo(MISCREG_AIFSR_NS);
4138 InitReg(MISCREG_ESR_EL1)
4139 .allPrivileges().exceptUserMode();
4140 InitReg(MISCREG_IFSR32_EL2)
4141 .hyp().mon()
4142 .mapsTo(MISCREG_IFSR_NS);
4143 InitReg(MISCREG_AFSR0_EL2)
4144 .hyp().mon()
4145 .mapsTo(MISCREG_HADFSR);
4146 InitReg(MISCREG_AFSR1_EL2)
4147 .hyp().mon()
4148 .mapsTo(MISCREG_HAIFSR);
4149 InitReg(MISCREG_ESR_EL2)
4150 .hyp().mon()
4151 .mapsTo(MISCREG_HSR);
4152 InitReg(MISCREG_FPEXC32_EL2)
4153 .hyp().mon().mapsTo(MISCREG_FPEXC);
4154 InitReg(MISCREG_AFSR0_EL3)
4155 .mon();
4156 InitReg(MISCREG_AFSR1_EL3)
4157 .mon();
4158 InitReg(MISCREG_ESR_EL3)
4159 .mon();
4160 InitReg(MISCREG_FAR_EL1)
4161 .allPrivileges().exceptUserMode()
4162 .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
4163 InitReg(MISCREG_FAR_EL2)
4164 .hyp().mon()
4165 .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR);
4166 InitReg(MISCREG_HPFAR_EL2)
4167 .hyp().mon()
4168 .mapsTo(MISCREG_HPFAR);
4169 InitReg(MISCREG_FAR_EL3)
4170 .mon();
4171 InitReg(MISCREG_IC_IALLUIS)
4172 .warnNotFail()
4173 .writes(1).exceptUserMode();
4174 InitReg(MISCREG_PAR_EL1)
4175 .allPrivileges().exceptUserMode()
4176 .mapsTo(MISCREG_PAR_NS);
4177 InitReg(MISCREG_IC_IALLU)
4178 .warnNotFail()
4179 .writes(1).exceptUserMode();
4180 InitReg(MISCREG_DC_IVAC_Xt)
4181 .warnNotFail()
4182 .writes(1).exceptUserMode();
4183 InitReg(MISCREG_DC_ISW_Xt)
4184 .warnNotFail()
4185 .writes(1).exceptUserMode();
4186 InitReg(MISCREG_AT_S1E1R_Xt)
4187 .writes(1).exceptUserMode();
4188 InitReg(MISCREG_AT_S1E1W_Xt)
4189 .writes(1).exceptUserMode();
4190 InitReg(MISCREG_AT_S1E0R_Xt)
4191 .writes(1).exceptUserMode();
4192 InitReg(MISCREG_AT_S1E0W_Xt)
4193 .writes(1).exceptUserMode();
4194 InitReg(MISCREG_DC_CSW_Xt)
4195 .warnNotFail()
4196 .writes(1).exceptUserMode();
4197 InitReg(MISCREG_DC_CISW_Xt)
4198 .warnNotFail()
4199 .writes(1).exceptUserMode();
4200 InitReg(MISCREG_DC_ZVA_Xt)
4201 .warnNotFail()
4202 .writes(1).userSecureWrite(0);
4203 InitReg(MISCREG_IC_IVAU_Xt)
4204 .writes(1);
4205 InitReg(MISCREG_DC_CVAC_Xt)
4206 .warnNotFail()
4207 .writes(1);
4208 InitReg(MISCREG_DC_CVAU_Xt)
4209 .warnNotFail()
4210 .writes(1);
4211 InitReg(MISCREG_DC_CIVAC_Xt)
4212 .warnNotFail()
4213 .writes(1);
4214 InitReg(MISCREG_AT_S1E2R_Xt)
4215 .monNonSecureWrite().hypWrite();
4216 InitReg(MISCREG_AT_S1E2W_Xt)
4217 .monNonSecureWrite().hypWrite();
4218 InitReg(MISCREG_AT_S12E1R_Xt)
4219 .hypWrite().monSecureWrite().monNonSecureWrite();
4220 InitReg(MISCREG_AT_S12E1W_Xt)
4221 .hypWrite().monSecureWrite().monNonSecureWrite();
4222 InitReg(MISCREG_AT_S12E0R_Xt)
4223 .hypWrite().monSecureWrite().monNonSecureWrite();
4224 InitReg(MISCREG_AT_S12E0W_Xt)
4225 .hypWrite().monSecureWrite().monNonSecureWrite();
4226 InitReg(MISCREG_AT_S1E3R_Xt)
4227 .monSecureWrite().monNonSecureWrite();
4228 InitReg(MISCREG_AT_S1E3W_Xt)
4229 .monSecureWrite().monNonSecureWrite();
4230 InitReg(MISCREG_TLBI_VMALLE1IS)
4231 .writes(1).exceptUserMode();
4232 InitReg(MISCREG_TLBI_VAE1IS_Xt)
4233 .writes(1).exceptUserMode();
4234 InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
4235 .writes(1).exceptUserMode();
4236 InitReg(MISCREG_TLBI_VAAE1IS_Xt)
4237 .writes(1).exceptUserMode();
4238 InitReg(MISCREG_TLBI_VALE1IS_Xt)
4239 .writes(1).exceptUserMode();
4240 InitReg(MISCREG_TLBI_VAALE1IS_Xt)
4241 .writes(1).exceptUserMode();
4242 InitReg(MISCREG_TLBI_VMALLE1)
4243 .writes(1).exceptUserMode();
4244 InitReg(MISCREG_TLBI_VAE1_Xt)
4245 .writes(1).exceptUserMode();
4246 InitReg(MISCREG_TLBI_ASIDE1_Xt)
4247 .writes(1).exceptUserMode();
4248 InitReg(MISCREG_TLBI_VAAE1_Xt)
4249 .writes(1).exceptUserMode();
4250 InitReg(MISCREG_TLBI_VALE1_Xt)
4251 .writes(1).exceptUserMode();
4252 InitReg(MISCREG_TLBI_VAALE1_Xt)
4253 .writes(1).exceptUserMode();
4254 InitReg(MISCREG_TLBI_IPAS2E1IS_Xt)
4255 .hypWrite().monSecureWrite().monNonSecureWrite();
4256 InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt)
4257 .hypWrite().monSecureWrite().monNonSecureWrite();
4258 InitReg(MISCREG_TLBI_ALLE2IS)
4259 .monNonSecureWrite().hypWrite();
4260 InitReg(MISCREG_TLBI_VAE2IS_Xt)
4261 .monNonSecureWrite().hypWrite();
4262 InitReg(MISCREG_TLBI_ALLE1IS)
4263 .hypWrite().monSecureWrite().monNonSecureWrite();
4264 InitReg(MISCREG_TLBI_VALE2IS_Xt)
4265 .monNonSecureWrite().hypWrite();
4266 InitReg(MISCREG_TLBI_VMALLS12E1IS)
4267 .hypWrite().monSecureWrite().monNonSecureWrite();
4268 InitReg(MISCREG_TLBI_IPAS2E1_Xt)
4269 .hypWrite().monSecureWrite().monNonSecureWrite();
4270 InitReg(MISCREG_TLBI_IPAS2LE1_Xt)
4271 .hypWrite().monSecureWrite().monNonSecureWrite();
4272 InitReg(MISCREG_TLBI_ALLE2)
4273 .monNonSecureWrite().hypWrite();
4274 InitReg(MISCREG_TLBI_VAE2_Xt)
4275 .monNonSecureWrite().hypWrite();
4276 InitReg(MISCREG_TLBI_ALLE1)
4277 .hypWrite().monSecureWrite().monNonSecureWrite();
4278 InitReg(MISCREG_TLBI_VALE2_Xt)
4279 .monNonSecureWrite().hypWrite();
4280 InitReg(MISCREG_TLBI_VMALLS12E1)
4281 .hypWrite().monSecureWrite().monNonSecureWrite();
4282 InitReg(MISCREG_TLBI_ALLE3IS)
4283 .monSecureWrite().monNonSecureWrite();
4284 InitReg(MISCREG_TLBI_VAE3IS_Xt)
4285 .monSecureWrite().monNonSecureWrite();
4286 InitReg(MISCREG_TLBI_VALE3IS_Xt)
4287 .monSecureWrite().monNonSecureWrite();
4288 InitReg(MISCREG_TLBI_ALLE3)
4289 .monSecureWrite().monNonSecureWrite();
4290 InitReg(MISCREG_TLBI_VAE3_Xt)
4291 .monSecureWrite().monNonSecureWrite();
4292 InitReg(MISCREG_TLBI_VALE3_Xt)
4293 .monSecureWrite().monNonSecureWrite();
4294 InitReg(MISCREG_PMINTENSET_EL1)
4295 .allPrivileges().exceptUserMode()
4296 .mapsTo(MISCREG_PMINTENSET);
4297 InitReg(MISCREG_PMINTENCLR_EL1)
4298 .allPrivileges().exceptUserMode()
4299 .mapsTo(MISCREG_PMINTENCLR);
4300 InitReg(MISCREG_PMCR_EL0)
4301 .allPrivileges()
4302 .mapsTo(MISCREG_PMCR);
4303 InitReg(MISCREG_PMCNTENSET_EL0)
4304 .allPrivileges()
4305 .mapsTo(MISCREG_PMCNTENSET);
4306 InitReg(MISCREG_PMCNTENCLR_EL0)
4307 .allPrivileges()
4308 .mapsTo(MISCREG_PMCNTENCLR);
4309 InitReg(MISCREG_PMOVSCLR_EL0)
4310 .allPrivileges();
4311 // .mapsTo(MISCREG_PMOVSCLR);
4312 InitReg(MISCREG_PMSWINC_EL0)
4313 .writes(1).user()
4314 .mapsTo(MISCREG_PMSWINC);
4315 InitReg(MISCREG_PMSELR_EL0)
4316 .allPrivileges()
4317 .mapsTo(MISCREG_PMSELR);
4318 InitReg(MISCREG_PMCEID0_EL0)
4319 .reads(1).user()
4320 .mapsTo(MISCREG_PMCEID0);
4321 InitReg(MISCREG_PMCEID1_EL0)
4322 .reads(1).user()
4323 .mapsTo(MISCREG_PMCEID1);
4324 InitReg(MISCREG_PMCCNTR_EL0)
4325 .allPrivileges()
4326 .mapsTo(MISCREG_PMCCNTR);
4327 InitReg(MISCREG_PMXEVTYPER_EL0)
4328 .allPrivileges()
4329 .mapsTo(MISCREG_PMXEVTYPER);
4330 InitReg(MISCREG_PMCCFILTR_EL0)
4331 .allPrivileges();
4332 InitReg(MISCREG_PMXEVCNTR_EL0)
4333 .allPrivileges()
4334 .mapsTo(MISCREG_PMXEVCNTR);
4335 InitReg(MISCREG_PMUSERENR_EL0)
4336 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
4337 .mapsTo(MISCREG_PMUSERENR);
4338 InitReg(MISCREG_PMOVSSET_EL0)
4339 .allPrivileges()
4340 .mapsTo(MISCREG_PMOVSSET);
4341 InitReg(MISCREG_MAIR_EL1)
4342 .allPrivileges().exceptUserMode()
4343 .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
4344 InitReg(MISCREG_AMAIR_EL1)
4345 .allPrivileges().exceptUserMode()
4346 .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
4347 InitReg(MISCREG_MAIR_EL2)
4348 .hyp().mon()
4349 .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1);
4350 InitReg(MISCREG_AMAIR_EL2)
4351 .hyp().mon()
4352 .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1);
4353 InitReg(MISCREG_MAIR_EL3)
4354 .mon();
4355 InitReg(MISCREG_AMAIR_EL3)
4356 .mon();
4357 InitReg(MISCREG_L2CTLR_EL1)
4358 .allPrivileges().exceptUserMode();
4359 InitReg(MISCREG_L2ECTLR_EL1)
4360 .allPrivileges().exceptUserMode();
4361 InitReg(MISCREG_VBAR_EL1)
4362 .allPrivileges().exceptUserMode()
4363 .mapsTo(MISCREG_VBAR_NS);
4364 InitReg(MISCREG_RVBAR_EL1)
4365 .allPrivileges().exceptUserMode().writes(0);
4366 InitReg(MISCREG_ISR_EL1)
4367 .allPrivileges().exceptUserMode().writes(0);
4368 InitReg(MISCREG_VBAR_EL2)
4369 .hyp().mon()
4370 .res0(0x7ff)
4371 .mapsTo(MISCREG_HVBAR);
4372 InitReg(MISCREG_RVBAR_EL2)
4373 .mon().hyp().writes(0);
4374 InitReg(MISCREG_VBAR_EL3)
4375 .mon();
4376 InitReg(MISCREG_RVBAR_EL3)
4377 .mon().writes(0);
4378 InitReg(MISCREG_RMR_EL3)
4379 .mon();
4380 InitReg(MISCREG_CONTEXTIDR_EL1)
4381 .allPrivileges().exceptUserMode()
4382 .mapsTo(MISCREG_CONTEXTIDR_NS);
4383 InitReg(MISCREG_TPIDR_EL1)
4384 .allPrivileges().exceptUserMode()
4385 .mapsTo(MISCREG_TPIDRPRW_NS);
4386 InitReg(MISCREG_TPIDR_EL0)
4387 .allPrivileges()
4388 .mapsTo(MISCREG_TPIDRURW_NS);
4389 InitReg(MISCREG_TPIDRRO_EL0)
4390 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
4391 .mapsTo(MISCREG_TPIDRURO_NS);
4392 InitReg(MISCREG_TPIDR_EL2)
4393 .hyp().mon()
4394 .mapsTo(MISCREG_HTPIDR);
4395 InitReg(MISCREG_TPIDR_EL3)
4396 .mon();
4397 InitReg(MISCREG_CNTKCTL_EL1)
4398 .allPrivileges().exceptUserMode()
4399 .mapsTo(MISCREG_CNTKCTL);
4400 InitReg(MISCREG_CNTFRQ_EL0)
4401 .reads(1).mon()
4402 .mapsTo(MISCREG_CNTFRQ);
4403 InitReg(MISCREG_CNTPCT_EL0)
4404 .reads(1)
4405 .mapsTo(MISCREG_CNTPCT); /* 64b */
4406 InitReg(MISCREG_CNTVCT_EL0)
4407 .unverifiable()
4408 .reads(1)
4409 .mapsTo(MISCREG_CNTVCT); /* 64b */
4410 InitReg(MISCREG_CNTP_TVAL_EL0)
4411 .allPrivileges()
4412 .mapsTo(MISCREG_CNTP_TVAL_NS);
4413 InitReg(MISCREG_CNTP_CTL_EL0)
4414 .allPrivileges()
4415 .mapsTo(MISCREG_CNTP_CTL_NS);
4416 InitReg(MISCREG_CNTP_CVAL_EL0)
4417 .allPrivileges()
4418 .mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b */
4419 InitReg(MISCREG_CNTV_TVAL_EL0)
4420 .allPrivileges()
4421 .mapsTo(MISCREG_CNTV_TVAL);
4422 InitReg(MISCREG_CNTV_CTL_EL0)
4423 .allPrivileges()
4424 .mapsTo(MISCREG_CNTV_CTL);
4425 InitReg(MISCREG_CNTV_CVAL_EL0)
4426 .allPrivileges()
4427 .mapsTo(MISCREG_CNTV_CVAL); /* 64b */
4428 InitReg(MISCREG_PMEVCNTR0_EL0)
4429 .allPrivileges();
4430 // .mapsTo(MISCREG_PMEVCNTR0);
4431 InitReg(MISCREG_PMEVCNTR1_EL0)
4432 .allPrivileges();
4433 // .mapsTo(MISCREG_PMEVCNTR1);
4434 InitReg(MISCREG_PMEVCNTR2_EL0)
4435 .allPrivileges();
4436 // .mapsTo(MISCREG_PMEVCNTR2);
4437 InitReg(MISCREG_PMEVCNTR3_EL0)
4438 .allPrivileges();
4439 // .mapsTo(MISCREG_PMEVCNTR3);
4440 InitReg(MISCREG_PMEVCNTR4_EL0)
4441 .allPrivileges();
4442 // .mapsTo(MISCREG_PMEVCNTR4);
4443 InitReg(MISCREG_PMEVCNTR5_EL0)
4444 .allPrivileges();
4445 // .mapsTo(MISCREG_PMEVCNTR5);
4446 InitReg(MISCREG_PMEVTYPER0_EL0)
4447 .allPrivileges();
4448 // .mapsTo(MISCREG_PMEVTYPER0);
4449 InitReg(MISCREG_PMEVTYPER1_EL0)
4450 .allPrivileges();
4451 // .mapsTo(MISCREG_PMEVTYPER1);
4452 InitReg(MISCREG_PMEVTYPER2_EL0)
4453 .allPrivileges();
4454 // .mapsTo(MISCREG_PMEVTYPER2);
4455 InitReg(MISCREG_PMEVTYPER3_EL0)
4456 .allPrivileges();
4457 // .mapsTo(MISCREG_PMEVTYPER3);
4458 InitReg(MISCREG_PMEVTYPER4_EL0)
4459 .allPrivileges();
4460 // .mapsTo(MISCREG_PMEVTYPER4);
4461 InitReg(MISCREG_PMEVTYPER5_EL0)
4462 .allPrivileges();
4463 // .mapsTo(MISCREG_PMEVTYPER5);
4464 InitReg(MISCREG_CNTVOFF_EL2)
4465 .hyp().mon()
4466 .mapsTo(MISCREG_CNTVOFF); /* 64b */
4467 InitReg(MISCREG_CNTHCTL_EL2)
4468 .mon().hyp()
4469 .mapsTo(MISCREG_CNTHCTL);
4470 InitReg(MISCREG_CNTHP_TVAL_EL2)
4471 .mon().hyp()
4472 .mapsTo(MISCREG_CNTHP_TVAL);
4473 InitReg(MISCREG_CNTHP_CTL_EL2)
4474 .mon().hyp()
4475 .mapsTo(MISCREG_CNTHP_CTL);
4476 InitReg(MISCREG_CNTHP_CVAL_EL2)
4477 .mon().hyp()
4478 .mapsTo(MISCREG_CNTHP_CVAL); /* 64b */
4479 InitReg(MISCREG_CNTPS_TVAL_EL1)
4480 .mon().privSecure();
4481 InitReg(MISCREG_CNTPS_CTL_EL1)
4482 .mon().privSecure();
4483 InitReg(MISCREG_CNTPS_CVAL_EL1)
4484 .mon().privSecure();
4485 InitReg(MISCREG_IL1DATA0_EL1)
4486 .allPrivileges().exceptUserMode();
4487 InitReg(MISCREG_IL1DATA1_EL1)
4488 .allPrivileges().exceptUserMode();
4489 InitReg(MISCREG_IL1DATA2_EL1)
4490 .allPrivileges().exceptUserMode();
4491 InitReg(MISCREG_IL1DATA3_EL1)
4492 .allPrivileges().exceptUserMode();
4493 InitReg(MISCREG_DL1DATA0_EL1)
4494 .allPrivileges().exceptUserMode();
4495 InitReg(MISCREG_DL1DATA1_EL1)
4496 .allPrivileges().exceptUserMode();
4497 InitReg(MISCREG_DL1DATA2_EL1)
4498 .allPrivileges().exceptUserMode();
4499 InitReg(MISCREG_DL1DATA3_EL1)
4500 .allPrivileges().exceptUserMode();
4501 InitReg(MISCREG_DL1DATA4_EL1)
4502 .allPrivileges().exceptUserMode();
4503 InitReg(MISCREG_L2ACTLR_EL1)
4504 .allPrivileges().exceptUserMode();
4505 InitReg(MISCREG_CPUACTLR_EL1)
4506 .allPrivileges().exceptUserMode();
4507 InitReg(MISCREG_CPUECTLR_EL1)
4508 .allPrivileges().exceptUserMode();
4509 InitReg(MISCREG_CPUMERRSR_EL1)
4510 .allPrivileges().exceptUserMode();
4511 InitReg(MISCREG_L2MERRSR_EL1)
4512 .unimplemented()
4513 .warnNotFail()
4514 .allPrivileges().exceptUserMode();
4515 InitReg(MISCREG_CBAR_EL1)
4516 .allPrivileges().exceptUserMode().writes(0);
4517 InitReg(MISCREG_CONTEXTIDR_EL2)
4518 .mon().hyp();
4519
4520 // GICv3 AArch64
4521 InitReg(MISCREG_ICC_PMR_EL1)
4522 .res0(0xffffff00) // [31:8]
4523 .allPrivileges().exceptUserMode()
4524 .mapsTo(MISCREG_ICC_PMR);
4525 InitReg(MISCREG_ICC_IAR0_EL1)
4526 .allPrivileges().exceptUserMode().writes(0)
4527 .mapsTo(MISCREG_ICC_IAR0);
4528 InitReg(MISCREG_ICC_EOIR0_EL1)
4529 .allPrivileges().exceptUserMode().reads(0)
4530 .mapsTo(MISCREG_ICC_EOIR0);
4531 InitReg(MISCREG_ICC_HPPIR0_EL1)
4532 .allPrivileges().exceptUserMode().writes(0)
4533 .mapsTo(MISCREG_ICC_HPPIR0);
4534 InitReg(MISCREG_ICC_BPR0_EL1)
4535 .res0(0xfffffff8) // [31:3]
4536 .allPrivileges().exceptUserMode()
4537 .mapsTo(MISCREG_ICC_BPR0);
4538 InitReg(MISCREG_ICC_AP0R0_EL1)
4539 .allPrivileges().exceptUserMode()
4540 .mapsTo(MISCREG_ICC_AP0R0);
4541 InitReg(MISCREG_ICC_AP0R1_EL1)
4542 .allPrivileges().exceptUserMode()
4543 .mapsTo(MISCREG_ICC_AP0R1);
4544 InitReg(MISCREG_ICC_AP0R2_EL1)
4545 .allPrivileges().exceptUserMode()
4546 .mapsTo(MISCREG_ICC_AP0R2);
4547 InitReg(MISCREG_ICC_AP0R3_EL1)
4548 .allPrivileges().exceptUserMode()
4549 .mapsTo(MISCREG_ICC_AP0R3);
4550 InitReg(MISCREG_ICC_AP1R0_EL1)
4551 .banked64()
4552 .mapsTo(MISCREG_ICC_AP1R0);
4553 InitReg(MISCREG_ICC_AP1R0_EL1_NS)
4554 .bankedChild()
4555 .allPrivileges().exceptUserMode()
4556 .mapsTo(MISCREG_ICC_AP1R0_NS);
4557 InitReg(MISCREG_ICC_AP1R0_EL1_S)
4558 .bankedChild()
4559 .allPrivileges().exceptUserMode()
4560 .mapsTo(MISCREG_ICC_AP1R0_S);
4561 InitReg(MISCREG_ICC_AP1R1_EL1)
4562 .banked64()
4563 .mapsTo(MISCREG_ICC_AP1R1);
4564 InitReg(MISCREG_ICC_AP1R1_EL1_NS)
4565 .bankedChild()
4566 .allPrivileges().exceptUserMode()
4567 .mapsTo(MISCREG_ICC_AP1R1_NS);
4568 InitReg(MISCREG_ICC_AP1R1_EL1_S)
4569 .bankedChild()
4570 .allPrivileges().exceptUserMode()
4571 .mapsTo(MISCREG_ICC_AP1R1_S);
4572 InitReg(MISCREG_ICC_AP1R2_EL1)
4573 .banked64()
4574 .mapsTo(MISCREG_ICC_AP1R2);
4575 InitReg(MISCREG_ICC_AP1R2_EL1_NS)
4576 .bankedChild()
4577 .allPrivileges().exceptUserMode()
4578 .mapsTo(MISCREG_ICC_AP1R2_NS);
4579 InitReg(MISCREG_ICC_AP1R2_EL1_S)
4580 .bankedChild()
4581 .allPrivileges().exceptUserMode()
4582 .mapsTo(MISCREG_ICC_AP1R2_S);
4583 InitReg(MISCREG_ICC_AP1R3_EL1)
4584 .banked64()
4585 .mapsTo(MISCREG_ICC_AP1R3);
4586 InitReg(MISCREG_ICC_AP1R3_EL1_NS)
4587 .bankedChild()
4588 .allPrivileges().exceptUserMode()
4589 .mapsTo(MISCREG_ICC_AP1R3_NS);
4590 InitReg(MISCREG_ICC_AP1R3_EL1_S)
4591 .bankedChild()
4592 .allPrivileges().exceptUserMode()
4593 .mapsTo(MISCREG_ICC_AP1R3_S);
4594 InitReg(MISCREG_ICC_DIR_EL1)
4595 .res0(0xFF000000) // [31:24]
4596 .allPrivileges().exceptUserMode().reads(0)
4597 .mapsTo(MISCREG_ICC_DIR);
4598 InitReg(MISCREG_ICC_RPR_EL1)
4599 .allPrivileges().exceptUserMode().writes(0)
4600 .mapsTo(MISCREG_ICC_RPR);
4601 InitReg(MISCREG_ICC_SGI1R_EL1)
4602 .allPrivileges().exceptUserMode().reads(0)
4603 .mapsTo(MISCREG_ICC_SGI1R);
4604 InitReg(MISCREG_ICC_ASGI1R_EL1)
4605 .allPrivileges().exceptUserMode().reads(0)
4606 .mapsTo(MISCREG_ICC_ASGI1R);
4607 InitReg(MISCREG_ICC_SGI0R_EL1)
4608 .allPrivileges().exceptUserMode().reads(0)
4609 .mapsTo(MISCREG_ICC_SGI0R);
4610 InitReg(MISCREG_ICC_IAR1_EL1)
4611 .allPrivileges().exceptUserMode().writes(0)
4612 .mapsTo(MISCREG_ICC_IAR1);
4613 InitReg(MISCREG_ICC_EOIR1_EL1)
4614 .res0(0xFF000000) // [31:24]
4615 .allPrivileges().exceptUserMode().reads(0)
4616 .mapsTo(MISCREG_ICC_EOIR1);
4617 InitReg(MISCREG_ICC_HPPIR1_EL1)
4618 .allPrivileges().exceptUserMode().writes(0)
4619 .mapsTo(MISCREG_ICC_HPPIR1);
4620 InitReg(MISCREG_ICC_BPR1_EL1)
4621 .banked64()
4622 .mapsTo(MISCREG_ICC_BPR1);
4623 InitReg(MISCREG_ICC_BPR1_EL1_NS)
4624 .bankedChild()
4625 .res0(0xfffffff8) // [31:3]
4626 .allPrivileges().exceptUserMode()
4627 .mapsTo(MISCREG_ICC_BPR1_NS);
4628 InitReg(MISCREG_ICC_BPR1_EL1_S)
4629 .bankedChild()
4630 .res0(0xfffffff8) // [31:3]
4631 .secure().exceptUserMode()
4632 .mapsTo(MISCREG_ICC_BPR1_S);
4633 InitReg(MISCREG_ICC_CTLR_EL1)
4634 .banked64()
4635 .mapsTo(MISCREG_ICC_CTLR);
4636 InitReg(MISCREG_ICC_CTLR_EL1_NS)
4637 .bankedChild()
4638 .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
4639 .allPrivileges().exceptUserMode()
4640 .mapsTo(MISCREG_ICC_CTLR_NS);
4641 InitReg(MISCREG_ICC_CTLR_EL1_S)
4642 .bankedChild()
4643 .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
4644 .secure().exceptUserMode()
4645 .mapsTo(MISCREG_ICC_CTLR_S);
4646 InitReg(MISCREG_ICC_SRE_EL1)
4647 .banked()
4648 .mapsTo(MISCREG_ICC_SRE);
4649 InitReg(MISCREG_ICC_SRE_EL1_NS)
4650 .bankedChild()
4651 .res0(0xFFFFFFF8) // [31:3]
4652 .allPrivileges().exceptUserMode()
4653 .mapsTo(MISCREG_ICC_SRE_NS);
4654 InitReg(MISCREG_ICC_SRE_EL1_S)
4655 .bankedChild()
4656 .res0(0xFFFFFFF8) // [31:3]
4657 .secure().exceptUserMode()
4658 .mapsTo(MISCREG_ICC_SRE_S);
4659 InitReg(MISCREG_ICC_IGRPEN0_EL1)
4660 .res0(0xFFFFFFFE) // [31:1]
4661 .allPrivileges().exceptUserMode()
4662 .mapsTo(MISCREG_ICC_IGRPEN0);
4663 InitReg(MISCREG_ICC_IGRPEN1_EL1)
4664 .banked64()
4665 .mapsTo(MISCREG_ICC_IGRPEN1);
4666 InitReg(MISCREG_ICC_IGRPEN1_EL1_NS)
4667 .bankedChild()
4668 .res0(0xFFFFFFFE) // [31:1]
4669 .allPrivileges().exceptUserMode()
4670 .mapsTo(MISCREG_ICC_IGRPEN1_NS);
4671 InitReg(MISCREG_ICC_IGRPEN1_EL1_S)
4672 .bankedChild()
4673 .res0(0xFFFFFFFE) // [31:1]
4674 .secure().exceptUserMode()
4675 .mapsTo(MISCREG_ICC_IGRPEN1_S);
4676 InitReg(MISCREG_ICC_SRE_EL2)
4677 .hyp().mon()
4678 .mapsTo(MISCREG_ICC_HSRE);
4679 InitReg(MISCREG_ICC_CTLR_EL3)
4680 .allPrivileges().exceptUserMode()
4681 .mapsTo(MISCREG_ICC_MCTLR);
4682 InitReg(MISCREG_ICC_SRE_EL3)
4683 .allPrivileges().exceptUserMode()
4684 .mapsTo(MISCREG_ICC_MSRE);
4685 InitReg(MISCREG_ICC_IGRPEN1_EL3)
4686 .allPrivileges().exceptUserMode()
4687 .mapsTo(MISCREG_ICC_MGRPEN1);
4688
4689 InitReg(MISCREG_ICH_AP0R0_EL2)
4690 .hyp().mon()
4691 .mapsTo(MISCREG_ICH_AP0R0);
4692 InitReg(MISCREG_ICH_AP0R1_EL2)
4693 .hyp().mon()
4694 .unimplemented()
4695 .mapsTo(MISCREG_ICH_AP0R1);
4696 InitReg(MISCREG_ICH_AP0R2_EL2)
4697 .hyp().mon()
4698 .unimplemented()
4699 .mapsTo(MISCREG_ICH_AP0R2);
4700 InitReg(MISCREG_ICH_AP0R3_EL2)
4701 .hyp().mon()
4702 .unimplemented()
4703 .mapsTo(MISCREG_ICH_AP0R3);
4704 InitReg(MISCREG_ICH_AP1R0_EL2)
4705 .hyp().mon()
4706 .mapsTo(MISCREG_ICH_AP1R0);
4707 InitReg(MISCREG_ICH_AP1R1_EL2)
4708 .hyp().mon()
4709 .unimplemented()
4710 .mapsTo(MISCREG_ICH_AP1R1);
4711 InitReg(MISCREG_ICH_AP1R2_EL2)
4712 .hyp().mon()
4713 .unimplemented()
4714 .mapsTo(MISCREG_ICH_AP1R2);
4715 InitReg(MISCREG_ICH_AP1R3_EL2)
4716 .hyp().mon()
4717 .unimplemented()
4718 .mapsTo(MISCREG_ICH_AP1R3);
4719 InitReg(MISCREG_ICH_HCR_EL2)
4720 .hyp().mon()
4721 .mapsTo(MISCREG_ICH_HCR);
4722 InitReg(MISCREG_ICH_VTR_EL2)
4723 .hyp().mon().writes(0)
4724 .mapsTo(MISCREG_ICH_VTR);
4725 InitReg(MISCREG_ICH_MISR_EL2)
4726 .hyp().mon().writes(0)
4727 .mapsTo(MISCREG_ICH_MISR);
4728 InitReg(MISCREG_ICH_EISR_EL2)
4729 .hyp().mon().writes(0)
4730 .mapsTo(MISCREG_ICH_EISR);
4731 InitReg(MISCREG_ICH_ELRSR_EL2)
4732 .hyp().mon().writes(0)
4733 .mapsTo(MISCREG_ICH_ELRSR);
4734 InitReg(MISCREG_ICH_VMCR_EL2)
4735 .hyp().mon()
4736 .mapsTo(MISCREG_ICH_VMCR);
4737 InitReg(MISCREG_ICH_LR0_EL2)
4738 .hyp().mon()
4739 .allPrivileges().exceptUserMode();
4740 InitReg(MISCREG_ICH_LR1_EL2)
4741 .hyp().mon()
4742 .allPrivileges().exceptUserMode();
4743 InitReg(MISCREG_ICH_LR2_EL2)
4744 .hyp().mon()
4745 .allPrivileges().exceptUserMode();
4746 InitReg(MISCREG_ICH_LR3_EL2)
4747 .hyp().mon()
4748 .allPrivileges().exceptUserMode();
4749 InitReg(MISCREG_ICH_LR4_EL2)
4750 .hyp().mon()
4751 .allPrivileges().exceptUserMode();
4752 InitReg(MISCREG_ICH_LR5_EL2)
4753 .hyp().mon()
4754 .allPrivileges().exceptUserMode();
4755 InitReg(MISCREG_ICH_LR6_EL2)
4756 .hyp().mon()
4757 .allPrivileges().exceptUserMode();
4758 InitReg(MISCREG_ICH_LR7_EL2)
4759 .hyp().mon()
4760 .allPrivileges().exceptUserMode();
4761 InitReg(MISCREG_ICH_LR8_EL2)
4762 .hyp().mon()
4763 .allPrivileges().exceptUserMode();
4764 InitReg(MISCREG_ICH_LR9_EL2)
4765 .hyp().mon()
4766 .allPrivileges().exceptUserMode();
4767 InitReg(MISCREG_ICH_LR10_EL2)
4768 .hyp().mon()
4769 .allPrivileges().exceptUserMode();
4770 InitReg(MISCREG_ICH_LR11_EL2)
4771 .hyp().mon()
4772 .allPrivileges().exceptUserMode();
4773 InitReg(MISCREG_ICH_LR12_EL2)
4774 .hyp().mon()
4775 .allPrivileges().exceptUserMode();
4776 InitReg(MISCREG_ICH_LR13_EL2)
4777 .hyp().mon()
4778 .allPrivileges().exceptUserMode();
4779 InitReg(MISCREG_ICH_LR14_EL2)
4780 .hyp().mon()
4781 .allPrivileges().exceptUserMode();
4782 InitReg(MISCREG_ICH_LR15_EL2)
4783 .hyp().mon()
4784 .allPrivileges().exceptUserMode();
4785
4786 // GICv3 AArch32
4787 InitReg(MISCREG_ICC_AP0R0)
4788 .allPrivileges().exceptUserMode();
4789 InitReg(MISCREG_ICC_AP0R1)
4790 .allPrivileges().exceptUserMode();
4791 InitReg(MISCREG_ICC_AP0R2)
4792 .allPrivileges().exceptUserMode();
4793 InitReg(MISCREG_ICC_AP0R3)
4794 .allPrivileges().exceptUserMode();
4795 InitReg(MISCREG_ICC_AP1R0)
4796 .allPrivileges().exceptUserMode();
4797 InitReg(MISCREG_ICC_AP1R0_NS)
4798 .allPrivileges().exceptUserMode();
4799 InitReg(MISCREG_ICC_AP1R0_S)
4800 .allPrivileges().exceptUserMode();
4801 InitReg(MISCREG_ICC_AP1R1)
4802 .allPrivileges().exceptUserMode();
4803 InitReg(MISCREG_ICC_AP1R1_NS)
4804 .allPrivileges().exceptUserMode();
4805 InitReg(MISCREG_ICC_AP1R1_S)
4806 .allPrivileges().exceptUserMode();
4807 InitReg(MISCREG_ICC_AP1R2)
4808 .allPrivileges().exceptUserMode();
4809 InitReg(MISCREG_ICC_AP1R2_NS)
4810 .allPrivileges().exceptUserMode();
4811 InitReg(MISCREG_ICC_AP1R2_S)
4812 .allPrivileges().exceptUserMode();
4813 InitReg(MISCREG_ICC_AP1R3)
4814 .allPrivileges().exceptUserMode();
4815 InitReg(MISCREG_ICC_AP1R3_NS)
4816 .allPrivileges().exceptUserMode();
4817 InitReg(MISCREG_ICC_AP1R3_S)
4818 .allPrivileges().exceptUserMode();
4819 InitReg(MISCREG_ICC_ASGI1R)
4820 .allPrivileges().exceptUserMode().reads(0);
4821 InitReg(MISCREG_ICC_BPR0)
4822 .allPrivileges().exceptUserMode();
4823 InitReg(MISCREG_ICC_BPR1)
4824 .allPrivileges().exceptUserMode();
4825 InitReg(MISCREG_ICC_BPR1_NS)
4826 .allPrivileges().exceptUserMode();
4827 InitReg(MISCREG_ICC_BPR1_S)
4828 .allPrivileges().exceptUserMode();
4829 InitReg(MISCREG_ICC_CTLR)
4830 .allPrivileges().exceptUserMode();
4831 InitReg(MISCREG_ICC_CTLR_NS)
4832 .allPrivileges().exceptUserMode();
4833 InitReg(MISCREG_ICC_CTLR_S)
4834 .allPrivileges().exceptUserMode();
4835 InitReg(MISCREG_ICC_DIR)
4836 .allPrivileges().exceptUserMode().reads(0);
4837 InitReg(MISCREG_ICC_EOIR0)
4838 .allPrivileges().exceptUserMode().reads(0);
4839 InitReg(MISCREG_ICC_EOIR1)
4840 .allPrivileges().exceptUserMode().reads(0);
4841 InitReg(MISCREG_ICC_HPPIR0)
4842 .allPrivileges().exceptUserMode().writes(0);
4843 InitReg(MISCREG_ICC_HPPIR1)
4844 .allPrivileges().exceptUserMode().writes(0);
4845 InitReg(MISCREG_ICC_HSRE)
4846 .allPrivileges().exceptUserMode();
4847 InitReg(MISCREG_ICC_IAR0)
4848 .allPrivileges().exceptUserMode().writes(0);
4849 InitReg(MISCREG_ICC_IAR1)
4850 .allPrivileges().exceptUserMode().writes(0);
4851 InitReg(MISCREG_ICC_IGRPEN0)
4852 .allPrivileges().exceptUserMode();
4853 InitReg(MISCREG_ICC_IGRPEN1)
4854 .allPrivileges().exceptUserMode();
4855 InitReg(MISCREG_ICC_IGRPEN1_NS)
4856 .allPrivileges().exceptUserMode();
4857 InitReg(MISCREG_ICC_IGRPEN1_S)
4858 .allPrivileges().exceptUserMode();
4859 InitReg(MISCREG_ICC_MCTLR)
4860 .allPrivileges().exceptUserMode();
4861 InitReg(MISCREG_ICC_MGRPEN1)
4862 .allPrivileges().exceptUserMode();
4863 InitReg(MISCREG_ICC_MSRE)
4864 .allPrivileges().exceptUserMode();
4865 InitReg(MISCREG_ICC_PMR)
4866 .allPrivileges().exceptUserMode();
4867 InitReg(MISCREG_ICC_RPR)
4868 .allPrivileges().exceptUserMode().writes(0);
4869 InitReg(MISCREG_ICC_SGI0R)
4870 .allPrivileges().exceptUserMode().reads(0);
4871 InitReg(MISCREG_ICC_SGI1R)
4872 .allPrivileges().exceptUserMode().reads(0);
4873 InitReg(MISCREG_ICC_SRE)
4874 .allPrivileges().exceptUserMode();
4875 InitReg(MISCREG_ICC_SRE_NS)
4876 .allPrivileges().exceptUserMode();
4877 InitReg(MISCREG_ICC_SRE_S)
4878 .allPrivileges().exceptUserMode();
4879
4880 InitReg(MISCREG_ICH_AP0R0)
4881 .hyp().mon();
4882 InitReg(MISCREG_ICH_AP0R1)
4883 .hyp().mon();
4884 InitReg(MISCREG_ICH_AP0R2)
4885 .hyp().mon();
4886 InitReg(MISCREG_ICH_AP0R3)
4887 .hyp().mon();
4888 InitReg(MISCREG_ICH_AP1R0)
4889 .hyp().mon();
4890 InitReg(MISCREG_ICH_AP1R1)
4891 .hyp().mon();
4892 InitReg(MISCREG_ICH_AP1R2)
4893 .hyp().mon();
4894 InitReg(MISCREG_ICH_AP1R3)
4895 .hyp().mon();
4896 InitReg(MISCREG_ICH_HCR)
4897 .hyp().mon();
4898 InitReg(MISCREG_ICH_VTR)
4899 .hyp().mon().writes(0);
4900 InitReg(MISCREG_ICH_MISR)
4901 .hyp().mon().writes(0);
4902 InitReg(MISCREG_ICH_EISR)
4903 .hyp().mon().writes(0);
4904 InitReg(MISCREG_ICH_ELRSR)
4905 .hyp().mon().writes(0);
4906 InitReg(MISCREG_ICH_VMCR)
4907 .hyp().mon();
4908 InitReg(MISCREG_ICH_LR0)
4909 .hyp().mon();
4910 InitReg(MISCREG_ICH_LR1)
4911 .hyp().mon();
4912 InitReg(MISCREG_ICH_LR2)
4913 .hyp().mon();
4914 InitReg(MISCREG_ICH_LR3)
4915 .hyp().mon();
4916 InitReg(MISCREG_ICH_LR4)
4917 .hyp().mon();
4918 InitReg(MISCREG_ICH_LR5)
4919 .hyp().mon();
4920 InitReg(MISCREG_ICH_LR6)
4921 .hyp().mon();
4922 InitReg(MISCREG_ICH_LR7)
4923 .hyp().mon();
4924 InitReg(MISCREG_ICH_LR8)
4925 .hyp().mon();
4926 InitReg(MISCREG_ICH_LR9)
4927 .hyp().mon();
4928 InitReg(MISCREG_ICH_LR10)
4929 .hyp().mon();
4930 InitReg(MISCREG_ICH_LR11)
4931 .hyp().mon();
4932 InitReg(MISCREG_ICH_LR12)
4933 .hyp().mon();
4934 InitReg(MISCREG_ICH_LR13)
4935 .hyp().mon();
4936 InitReg(MISCREG_ICH_LR14)
4937 .hyp().mon();
4938 InitReg(MISCREG_ICH_LR15)
4939 .hyp().mon();
4940 InitReg(MISCREG_ICH_LRC0)
4941 .mapsTo(MISCREG_ICH_LR0)
4942 .hyp().mon();
4943 InitReg(MISCREG_ICH_LRC1)
4944 .mapsTo(MISCREG_ICH_LR1)
4945 .hyp().mon();
4946 InitReg(MISCREG_ICH_LRC2)
4947 .mapsTo(MISCREG_ICH_LR2)
4948 .hyp().mon();
4949 InitReg(MISCREG_ICH_LRC3)
4950 .mapsTo(MISCREG_ICH_LR3)
4951 .hyp().mon();
4952 InitReg(MISCREG_ICH_LRC4)
4953 .mapsTo(MISCREG_ICH_LR4)
4954 .hyp().mon();
4955 InitReg(MISCREG_ICH_LRC5)
4956 .mapsTo(MISCREG_ICH_LR5)
4957 .hyp().mon();
4958 InitReg(MISCREG_ICH_LRC6)
4959 .mapsTo(MISCREG_ICH_LR6)
4960 .hyp().mon();
4961 InitReg(MISCREG_ICH_LRC7)
4962 .mapsTo(MISCREG_ICH_LR7)
4963 .hyp().mon();
4964 InitReg(MISCREG_ICH_LRC8)
4965 .mapsTo(MISCREG_ICH_LR8)
4966 .hyp().mon();
4967 InitReg(MISCREG_ICH_LRC9)
4968 .mapsTo(MISCREG_ICH_LR9)
4969 .hyp().mon();
4970 InitReg(MISCREG_ICH_LRC10)
4971 .mapsTo(MISCREG_ICH_LR10)
4972 .hyp().mon();
4973 InitReg(MISCREG_ICH_LRC11)
4974 .mapsTo(MISCREG_ICH_LR11)
4975 .hyp().mon();
4976 InitReg(MISCREG_ICH_LRC12)
4977 .mapsTo(MISCREG_ICH_LR12)
4978 .hyp().mon();
4979 InitReg(MISCREG_ICH_LRC13)
4980 .mapsTo(MISCREG_ICH_LR13)
4981 .hyp().mon();
4982 InitReg(MISCREG_ICH_LRC14)
4983 .mapsTo(MISCREG_ICH_LR14)
4984 .hyp().mon();
4985 InitReg(MISCREG_ICH_LRC15)
4986 .mapsTo(MISCREG_ICH_LR15)
4987 .hyp().mon();
4988
4989 InitReg(MISCREG_CNTHV_CTL_EL2)
4990 .mon().hyp();
4991 InitReg(MISCREG_CNTHV_CVAL_EL2)
4992 .mon().hyp();
4993 InitReg(MISCREG_CNTHV_TVAL_EL2)
4994 .mon().hyp();
4995
4996 // SVE
4997 InitReg(MISCREG_ID_AA64ZFR0_EL1)
4998 .allPrivileges().exceptUserMode().writes(0);
4999 InitReg(MISCREG_ZCR_EL3)
5000 .mon();
5001 InitReg(MISCREG_ZCR_EL2)
5002 .hyp().mon();
5003 InitReg(MISCREG_ZCR_EL12)
5004 .unimplemented().warnNotFail();
5005 InitReg(MISCREG_ZCR_EL1)
5006 .allPrivileges().exceptUserMode();
5007
5008 // Dummy registers
5009 InitReg(MISCREG_NOP)
5010 .allPrivileges();
5011 InitReg(MISCREG_RAZ)
5012 .allPrivileges().exceptUserMode().writes(0);
5013 InitReg(MISCREG_CP14_UNIMPL)
5014 .unimplemented()
5015 .warnNotFail();
5016 InitReg(MISCREG_CP15_UNIMPL)
5017 .unimplemented()
5018 .warnNotFail();
5019 InitReg(MISCREG_UNKNOWN);
5020 InitReg(MISCREG_IMPDEF_UNIMPL)
5021 .unimplemented()
5022 .warnNotFail(impdefAsNop);
5023
5024 // RAS extension (unimplemented)
5025 InitReg(MISCREG_ERRIDR_EL1)
5026 .unimplemented()
5027 .warnNotFail();
5028 InitReg(MISCREG_ERRSELR_EL1)
5029 .unimplemented()
5030 .warnNotFail();
5031 InitReg(MISCREG_ERXFR_EL1)
5032 .unimplemented()
5033 .warnNotFail();
5034 InitReg(MISCREG_ERXCTLR_EL1)
5035 .unimplemented()
5036 .warnNotFail();
5037 InitReg(MISCREG_ERXSTATUS_EL1)
5038 .unimplemented()
5039 .warnNotFail();
5040 InitReg(MISCREG_ERXADDR_EL1)
5041 .unimplemented()
5042 .warnNotFail();
5043 InitReg(MISCREG_ERXMISC0_EL1)
5044 .unimplemented()
5045 .warnNotFail();
5046 InitReg(MISCREG_ERXMISC1_EL1)
5047 .unimplemented()
5048 .warnNotFail();
5049 InitReg(MISCREG_DISR_EL1)
5050 .unimplemented()
5051 .warnNotFail();
5052 InitReg(MISCREG_VSESR_EL2)
5053 .unimplemented()
5054 .warnNotFail();
5055 InitReg(MISCREG_VDISR_EL2)
5056 .unimplemented()
5057 .warnNotFail();
5058
5059 // Register mappings for some unimplemented registers:
5060 // ESR_EL1 -> DFSR
5061 // RMR_EL1 -> RMR
5062 // RMR_EL2 -> HRMR
5063 // DBGDTR_EL0 -> DBGDTR{R or T}Xint
5064 // DBGDTRRX_EL0 -> DBGDTRRXint
5065 // DBGDTRTX_EL0 -> DBGDTRRXint
5066 // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
5067
5068 completed = true;
5069 }
5070
5071 } // namespace ArmISA