2 * Copyright (c) 2010-2013, 2015-2018 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include "arch/arm/miscregs.hh"
46 #include "arch/arm/isa.hh"
47 #include "base/logging.hh"
48 #include "cpu/thread_context.hh"
49 #include "sim/full_system.hh"
55 decodeCP14Reg(unsigned crn
, unsigned opc1
, unsigned crm
, unsigned opc2
)
65 return MISCREG_DBGDIDR
;
67 return MISCREG_DBGDSCRint
;
91 return MISCREG_TEEHBR
;
101 return MISCREG_JOSCR
;
123 // If we get here then it must be a register that we haven't implemented
124 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
125 crn
, opc1
, crm
, opc2
);
126 return MISCREG_CP14_UNIMPL
;
132 decodeCP15Reg(unsigned crn
, unsigned opc1
, unsigned crm
, unsigned opc2
)
144 return MISCREG_TCMTR
;
146 return MISCREG_TLBTR
;
148 return MISCREG_MPIDR
;
150 return MISCREG_REVIDR
;
158 return MISCREG_ID_PFR0
;
160 return MISCREG_ID_PFR1
;
162 return MISCREG_ID_DFR0
;
164 return MISCREG_ID_AFR0
;
166 return MISCREG_ID_MMFR0
;
168 return MISCREG_ID_MMFR1
;
170 return MISCREG_ID_MMFR2
;
172 return MISCREG_ID_MMFR3
;
178 return MISCREG_ID_ISAR0
;
180 return MISCREG_ID_ISAR1
;
182 return MISCREG_ID_ISAR2
;
184 return MISCREG_ID_ISAR3
;
186 return MISCREG_ID_ISAR4
;
188 return MISCREG_ID_ISAR5
;
191 return MISCREG_RAZ
; // read as zero
195 return MISCREG_RAZ
; // read as zero
202 return MISCREG_CCSIDR
;
204 return MISCREG_CLIDR
;
211 if (crm
== 0 && opc2
== 0) {
212 return MISCREG_CSSELR
;
218 return MISCREG_VPIDR
;
220 return MISCREG_VMPIDR
;
230 return MISCREG_SCTLR
;
232 return MISCREG_ACTLR
;
234 return MISCREG_CPACR
;
236 } else if (crm
== 1) {
243 return MISCREG_NSACR
;
246 } else if (opc1
== 4) {
249 return MISCREG_HSCTLR
;
251 return MISCREG_HACTLR
;
252 } else if (crm
== 1) {
259 return MISCREG_HCPTR
;
269 if (opc1
== 0 && crm
== 0) {
272 return MISCREG_TTBR0
;
274 return MISCREG_TTBR1
;
276 return MISCREG_TTBCR
;
278 } else if (opc1
== 4) {
279 if (crm
== 0 && opc2
== 2)
281 else if (crm
== 1 && opc2
== 2)
286 if (opc1
== 0 && crm
== 0 && opc2
== 0) {
295 } else if (opc2
== 1) {
298 } else if (crm
== 1) {
300 return MISCREG_ADFSR
;
301 } else if (opc2
== 1) {
302 return MISCREG_AIFSR
;
305 } else if (opc1
== 4) {
308 return MISCREG_HADFSR
;
310 return MISCREG_HAIFSR
;
311 } else if (crm
== 2 && opc2
== 0) {
317 if (opc1
== 0 && crm
== 0) {
324 } else if (opc1
== 4 && crm
== 0) {
327 return MISCREG_HDFAR
;
329 return MISCREG_HIFAR
;
331 return MISCREG_HPFAR
;
346 return MISCREG_ICIALLUIS
;
348 return MISCREG_BPIALLIS
;
359 return MISCREG_ICIALLU
;
361 return MISCREG_ICIMVAU
;
363 return MISCREG_CP15ISB
;
365 return MISCREG_BPIALL
;
367 return MISCREG_BPIMVA
;
372 return MISCREG_DCIMVAC
;
373 } else if (opc2
== 2) {
374 return MISCREG_DCISW
;
380 return MISCREG_ATS1CPR
;
382 return MISCREG_ATS1CPW
;
384 return MISCREG_ATS1CUR
;
386 return MISCREG_ATS1CUW
;
388 return MISCREG_ATS12NSOPR
;
390 return MISCREG_ATS12NSOPW
;
392 return MISCREG_ATS12NSOUR
;
394 return MISCREG_ATS12NSOUW
;
400 return MISCREG_DCCMVAC
;
402 return MISCREG_DCCSW
;
404 return MISCREG_CP15DSB
;
406 return MISCREG_CP15DMB
;
411 return MISCREG_DCCMVAU
;
421 return MISCREG_DCCIMVAC
;
422 } else if (opc2
== 2) {
423 return MISCREG_DCCISW
;
427 } else if (opc1
== 4 && crm
== 8) {
429 return MISCREG_ATS1HR
;
431 return MISCREG_ATS1HW
;
440 return MISCREG_TLBIALLIS
;
442 return MISCREG_TLBIMVAIS
;
444 return MISCREG_TLBIASIDIS
;
446 return MISCREG_TLBIMVAAIS
;
448 return MISCREG_TLBIMVALIS
;
450 return MISCREG_TLBIMVAALIS
;
456 return MISCREG_ITLBIALL
;
458 return MISCREG_ITLBIMVA
;
460 return MISCREG_ITLBIASID
;
466 return MISCREG_DTLBIALL
;
468 return MISCREG_DTLBIMVA
;
470 return MISCREG_DTLBIASID
;
476 return MISCREG_TLBIALL
;
478 return MISCREG_TLBIMVA
;
480 return MISCREG_TLBIASID
;
482 return MISCREG_TLBIMVAA
;
484 return MISCREG_TLBIMVAL
;
486 return MISCREG_TLBIMVAAL
;
490 } else if (opc1
== 4) {
494 return MISCREG_TLBIIPAS2IS
;
496 return MISCREG_TLBIIPAS2LIS
;
498 } else if (crm
== 3) {
501 return MISCREG_TLBIALLHIS
;
503 return MISCREG_TLBIMVAHIS
;
505 return MISCREG_TLBIALLNSNHIS
;
507 return MISCREG_TLBIMVALHIS
;
509 } else if (crm
== 4) {
512 return MISCREG_TLBIIPAS2
;
514 return MISCREG_TLBIIPAS2L
;
516 } else if (crm
== 7) {
519 return MISCREG_TLBIALLH
;
521 return MISCREG_TLBIMVAH
;
523 return MISCREG_TLBIALLNSNH
;
525 return MISCREG_TLBIMVALH
;
531 // Every cop register with CRn = 9 and CRm in
532 // {0-2}, {5-8} is implementation defined regardless
542 return MISCREG_IMPDEF_UNIMPL
;
551 return MISCREG_PMCNTENSET
;
553 return MISCREG_PMCNTENCLR
;
555 return MISCREG_PMOVSR
;
557 return MISCREG_PMSWINC
;
559 return MISCREG_PMSELR
;
561 return MISCREG_PMCEID0
;
563 return MISCREG_PMCEID1
;
569 return MISCREG_PMCCNTR
;
571 // Selector is PMSELR.SEL
572 return MISCREG_PMXEVTYPER_PMCCFILTR
;
574 return MISCREG_PMXEVCNTR
;
580 return MISCREG_PMUSERENR
;
582 return MISCREG_PMINTENSET
;
584 return MISCREG_PMINTENCLR
;
586 return MISCREG_PMOVSSET
;
590 } else if (opc1
== 1) {
594 case 2: // L2CTLR, L2 Control Register
595 return MISCREG_L2CTLR
;
597 return MISCREG_L2ECTLR
;
606 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
608 return MISCREG_IMPDEF_UNIMPL
;
609 } else if (crm
== 2) { // TEX Remap Registers
611 // Selector is TTBCR.EAE
612 return MISCREG_PRRR_MAIR0
;
613 } else if (opc2
== 1) {
614 // Selector is TTBCR.EAE
615 return MISCREG_NMRR_MAIR1
;
617 } else if (crm
== 3) {
619 return MISCREG_AMAIR0
;
620 } else if (opc2
== 1) {
621 return MISCREG_AMAIR1
;
624 } else if (opc1
== 4) {
625 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
628 return MISCREG_HMAIR0
;
630 return MISCREG_HMAIR1
;
631 } else if (crm
== 3) {
633 return MISCREG_HAMAIR0
;
635 return MISCREG_HAMAIR1
;
652 // Reserved for DMA operations for TCM access
653 return MISCREG_IMPDEF_UNIMPL
;
664 } else if (opc2
== 1) {
665 return MISCREG_MVBAR
;
667 } else if (crm
== 1) {
672 } else if (opc1
== 4) {
673 if (crm
== 0 && opc2
== 0)
674 return MISCREG_HVBAR
;
682 return MISCREG_FCSEIDR
;
684 return MISCREG_CONTEXTIDR
;
686 return MISCREG_TPIDRURW
;
688 return MISCREG_TPIDRURO
;
690 return MISCREG_TPIDRPRW
;
693 } else if (opc1
== 4) {
694 if (crm
== 0 && opc2
== 2)
695 return MISCREG_HTPIDR
;
703 return MISCREG_CNTFRQ
;
707 return MISCREG_CNTKCTL
;
711 return MISCREG_CNTP_TVAL
;
713 return MISCREG_CNTP_CTL
;
717 return MISCREG_CNTV_TVAL
;
719 return MISCREG_CNTV_CTL
;
722 } else if (opc1
== 4) {
723 if (crm
== 1 && opc2
== 0) {
724 return MISCREG_CNTHCTL
;
725 } else if (crm
== 2) {
727 return MISCREG_CNTHP_TVAL
;
729 return MISCREG_CNTHP_CTL
;
734 // Implementation defined
735 return MISCREG_IMPDEF_UNIMPL
;
737 // Unrecognized register
738 return MISCREG_CP15_UNIMPL
;
742 decodeCP15Reg64(unsigned crm
, unsigned opc1
)
748 return MISCREG_TTBR0
;
750 return MISCREG_TTBR1
;
752 return MISCREG_HTTBR
;
754 return MISCREG_VTTBR
;
764 return MISCREG_CNTPCT
;
766 return MISCREG_CNTVCT
;
768 return MISCREG_CNTP_CVAL
;
770 return MISCREG_CNTV_CVAL
;
772 return MISCREG_CNTVOFF
;
774 return MISCREG_CNTHP_CVAL
;
779 return MISCREG_CPUMERRSR
;
781 return MISCREG_L2MERRSR
;
784 // Unrecognized register
785 return MISCREG_CP15_UNIMPL
;
788 std::tuple
<bool, bool>
789 canReadCoprocReg(MiscRegIndex reg
, SCR scr
, CPSR cpsr
)
791 bool secure
= !scr
.ns
;
792 bool canRead
= false;
793 bool undefined
= false;
797 canRead
= secure
? miscRegInfo
[reg
][MISCREG_USR_S_RD
] :
798 miscRegInfo
[reg
][MISCREG_USR_NS_RD
];
806 canRead
= secure
? miscRegInfo
[reg
][MISCREG_PRI_S_RD
] :
807 miscRegInfo
[reg
][MISCREG_PRI_NS_RD
];
810 canRead
= secure
? miscRegInfo
[reg
][MISCREG_MON_NS0_RD
] :
811 miscRegInfo
[reg
][MISCREG_MON_NS1_RD
];
814 canRead
= miscRegInfo
[reg
][MISCREG_HYP_RD
];
819 // can't do permissions checkes on the root of a banked pair of regs
820 assert(!miscRegInfo
[reg
][MISCREG_BANKED
]);
821 return std::make_tuple(canRead
, undefined
);
824 std::tuple
<bool, bool>
825 canWriteCoprocReg(MiscRegIndex reg
, SCR scr
, CPSR cpsr
)
827 bool secure
= !scr
.ns
;
828 bool canWrite
= false;
829 bool undefined
= false;
833 canWrite
= secure
? miscRegInfo
[reg
][MISCREG_USR_S_WR
] :
834 miscRegInfo
[reg
][MISCREG_USR_NS_WR
];
842 canWrite
= secure
? miscRegInfo
[reg
][MISCREG_PRI_S_WR
] :
843 miscRegInfo
[reg
][MISCREG_PRI_NS_WR
];
846 canWrite
= secure
? miscRegInfo
[reg
][MISCREG_MON_NS0_WR
] :
847 miscRegInfo
[reg
][MISCREG_MON_NS1_WR
];
850 canWrite
= miscRegInfo
[reg
][MISCREG_HYP_WR
];
855 // can't do permissions checkes on the root of a banked pair of regs
856 assert(!miscRegInfo
[reg
][MISCREG_BANKED
]);
857 return std::make_tuple(canWrite
, undefined
);
861 snsBankedIndex(MiscRegIndex reg
, ThreadContext
*tc
)
863 SCR scr
= tc
->readMiscReg(MISCREG_SCR
);
864 return snsBankedIndex(reg
, tc
, scr
.ns
);
868 snsBankedIndex(MiscRegIndex reg
, ThreadContext
*tc
, bool ns
)
870 int reg_as_int
= static_cast<int>(reg
);
871 if (miscRegInfo
[reg
][MISCREG_BANKED
]) {
872 reg_as_int
+= (ArmSystem::haveSecurity(tc
) &&
873 !ArmSystem::highestELIs64(tc
) && !ns
) ? 2 : 1;
880 * If the reg is a child reg of a banked set, then the parent is the last
881 * banked one in the list. This is messy, and the wish is to eventually have
882 * the bitmap replaced with a better data structure. the preUnflatten function
883 * initializes a lookup table to speed up the search for these banked
887 int unflattenResultMiscReg
[NUM_MISCREGS
];
890 preUnflattenMiscReg()
893 for (int i
= 0 ; i
< NUM_MISCREGS
; i
++){
894 if (miscRegInfo
[i
][MISCREG_BANKED
])
896 if (miscRegInfo
[i
][MISCREG_BANKED_CHILD
])
897 unflattenResultMiscReg
[i
] = reg
;
899 unflattenResultMiscReg
[i
] = i
;
900 // if this assert fails, no parent was found, and something is broken
901 assert(unflattenResultMiscReg
[i
] > -1);
906 unflattenMiscReg(int reg
)
908 return unflattenResultMiscReg
[reg
];
912 canReadAArch64SysReg(MiscRegIndex reg
, SCR scr
, CPSR cpsr
, ThreadContext
*tc
)
914 // Check for SP_EL0 access while SPSEL == 0
915 if ((reg
== MISCREG_SP_EL0
) && (tc
->readMiscReg(MISCREG_SPSEL
) == 0))
918 // Check for RVBAR access
919 if (reg
== MISCREG_RVBAR_EL1
) {
920 ExceptionLevel highest_el
= ArmSystem::highestEL(tc
);
921 if (highest_el
== EL2
|| highest_el
== EL3
)
924 if (reg
== MISCREG_RVBAR_EL2
) {
925 ExceptionLevel highest_el
= ArmSystem::highestEL(tc
);
926 if (highest_el
== EL3
)
930 bool secure
= ArmSystem::haveSecurity(tc
) && !scr
.ns
;
932 switch (opModeToEL((OperatingMode
) (uint8_t) cpsr
.mode
)) {
934 return secure
? miscRegInfo
[reg
][MISCREG_USR_S_RD
] :
935 miscRegInfo
[reg
][MISCREG_USR_NS_RD
];
937 return secure
? miscRegInfo
[reg
][MISCREG_PRI_S_RD
] :
938 miscRegInfo
[reg
][MISCREG_PRI_NS_RD
];
940 return miscRegInfo
[reg
][MISCREG_HYP_RD
];
942 return secure
? miscRegInfo
[reg
][MISCREG_MON_NS0_RD
] :
943 miscRegInfo
[reg
][MISCREG_MON_NS1_RD
];
945 panic("Invalid exception level");
950 canWriteAArch64SysReg(MiscRegIndex reg
, SCR scr
, CPSR cpsr
, ThreadContext
*tc
)
952 // Check for SP_EL0 access while SPSEL == 0
953 if ((reg
== MISCREG_SP_EL0
) && (tc
->readMiscReg(MISCREG_SPSEL
) == 0))
955 ExceptionLevel el
= opModeToEL((OperatingMode
) (uint8_t) cpsr
.mode
);
956 if (reg
== MISCREG_DAIF
) {
957 SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR_EL1
);
958 if (el
== EL0
&& !sctlr
.uma
)
961 if (FullSystem
&& reg
== MISCREG_DC_ZVA_Xt
) {
962 // In syscall-emulation mode, this test is skipped and DCZVA is always
964 SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR_EL1
);
965 if (el
== EL0
&& !sctlr
.dze
)
968 if (reg
== MISCREG_DC_CVAC_Xt
|| reg
== MISCREG_DC_CIVAC_Xt
) {
969 SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR_EL1
);
970 if (el
== EL0
&& !sctlr
.uci
)
974 bool secure
= ArmSystem::haveSecurity(tc
) && !scr
.ns
;
978 return secure
? miscRegInfo
[reg
][MISCREG_USR_S_WR
] :
979 miscRegInfo
[reg
][MISCREG_USR_NS_WR
];
981 return secure
? miscRegInfo
[reg
][MISCREG_PRI_S_WR
] :
982 miscRegInfo
[reg
][MISCREG_PRI_NS_WR
];
984 return miscRegInfo
[reg
][MISCREG_HYP_WR
];
986 return secure
? miscRegInfo
[reg
][MISCREG_MON_NS0_WR
] :
987 miscRegInfo
[reg
][MISCREG_MON_NS1_WR
];
989 panic("Invalid exception level");
994 decodeAArch64SysReg(unsigned op0
, unsigned op1
,
995 unsigned crn
, unsigned crm
,
1008 return MISCREG_IC_IALLUIS
;
1014 return MISCREG_IC_IALLU
;
1020 return MISCREG_DC_IVAC_Xt
;
1022 return MISCREG_DC_ISW_Xt
;
1028 return MISCREG_AT_S1E1R_Xt
;
1030 return MISCREG_AT_S1E1W_Xt
;
1032 return MISCREG_AT_S1E0R_Xt
;
1034 return MISCREG_AT_S1E0W_Xt
;
1040 return MISCREG_DC_CSW_Xt
;
1046 return MISCREG_DC_CISW_Xt
;
1056 return MISCREG_DC_ZVA_Xt
;
1062 return MISCREG_IC_IVAU_Xt
;
1068 return MISCREG_DC_CVAC_Xt
;
1074 return MISCREG_DC_CVAU_Xt
;
1080 return MISCREG_DC_CIVAC_Xt
;
1090 return MISCREG_AT_S1E2R_Xt
;
1092 return MISCREG_AT_S1E2W_Xt
;
1094 return MISCREG_AT_S12E1R_Xt
;
1096 return MISCREG_AT_S12E1W_Xt
;
1098 return MISCREG_AT_S12E0R_Xt
;
1100 return MISCREG_AT_S12E0W_Xt
;
1110 return MISCREG_AT_S1E3R_Xt
;
1112 return MISCREG_AT_S1E3W_Xt
;
1126 return MISCREG_TLBI_VMALLE1IS
;
1128 return MISCREG_TLBI_VAE1IS_Xt
;
1130 return MISCREG_TLBI_ASIDE1IS_Xt
;
1132 return MISCREG_TLBI_VAAE1IS_Xt
;
1134 return MISCREG_TLBI_VALE1IS_Xt
;
1136 return MISCREG_TLBI_VAALE1IS_Xt
;
1142 return MISCREG_TLBI_VMALLE1
;
1144 return MISCREG_TLBI_VAE1_Xt
;
1146 return MISCREG_TLBI_ASIDE1_Xt
;
1148 return MISCREG_TLBI_VAAE1_Xt
;
1150 return MISCREG_TLBI_VALE1_Xt
;
1152 return MISCREG_TLBI_VAALE1_Xt
;
1162 return MISCREG_TLBI_IPAS2E1IS_Xt
;
1164 return MISCREG_TLBI_IPAS2LE1IS_Xt
;
1170 return MISCREG_TLBI_ALLE2IS
;
1172 return MISCREG_TLBI_VAE2IS_Xt
;
1174 return MISCREG_TLBI_ALLE1IS
;
1176 return MISCREG_TLBI_VALE2IS_Xt
;
1178 return MISCREG_TLBI_VMALLS12E1IS
;
1184 return MISCREG_TLBI_IPAS2E1_Xt
;
1186 return MISCREG_TLBI_IPAS2LE1_Xt
;
1192 return MISCREG_TLBI_ALLE2
;
1194 return MISCREG_TLBI_VAE2_Xt
;
1196 return MISCREG_TLBI_ALLE1
;
1198 return MISCREG_TLBI_VALE2_Xt
;
1200 return MISCREG_TLBI_VMALLS12E1
;
1210 return MISCREG_TLBI_ALLE3IS
;
1212 return MISCREG_TLBI_VAE3IS_Xt
;
1214 return MISCREG_TLBI_VALE3IS_Xt
;
1220 return MISCREG_TLBI_ALLE3
;
1222 return MISCREG_TLBI_VAE3_Xt
;
1224 return MISCREG_TLBI_VALE3_Xt
;
1233 // SYS Instruction with CRn = { 11, 15 }
1234 // (Trappable by HCR_EL2.TIDCP)
1235 return MISCREG_IMPDEF_UNIMPL
;
1247 return MISCREG_OSDTRRX_EL1
;
1249 return MISCREG_DBGBVR0_EL1
;
1251 return MISCREG_DBGBCR0_EL1
;
1253 return MISCREG_DBGWVR0_EL1
;
1255 return MISCREG_DBGWCR0_EL1
;
1261 return MISCREG_DBGBVR1_EL1
;
1263 return MISCREG_DBGBCR1_EL1
;
1265 return MISCREG_DBGWVR1_EL1
;
1267 return MISCREG_DBGWCR1_EL1
;
1273 return MISCREG_MDCCINT_EL1
;
1275 return MISCREG_MDSCR_EL1
;
1277 return MISCREG_DBGBVR2_EL1
;
1279 return MISCREG_DBGBCR2_EL1
;
1281 return MISCREG_DBGWVR2_EL1
;
1283 return MISCREG_DBGWCR2_EL1
;
1289 return MISCREG_OSDTRTX_EL1
;
1291 return MISCREG_DBGBVR3_EL1
;
1293 return MISCREG_DBGBCR3_EL1
;
1295 return MISCREG_DBGWVR3_EL1
;
1297 return MISCREG_DBGWCR3_EL1
;
1303 return MISCREG_DBGBVR4_EL1
;
1305 return MISCREG_DBGBCR4_EL1
;
1311 return MISCREG_DBGBVR5_EL1
;
1313 return MISCREG_DBGBCR5_EL1
;
1319 return MISCREG_OSECCR_EL1
;
1329 return MISCREG_TEECR32_EL1
;
1339 return MISCREG_MDCCSR_EL0
;
1345 return MISCREG_MDDTR_EL0
;
1351 return MISCREG_MDDTRRX_EL0
;
1361 return MISCREG_DBGVCR32_EL2
;
1375 return MISCREG_MDRAR_EL1
;
1377 return MISCREG_OSLAR_EL1
;
1383 return MISCREG_OSLSR_EL1
;
1389 return MISCREG_OSDLR_EL1
;
1395 return MISCREG_DBGPRCR_EL1
;
1405 return MISCREG_TEEHBR32_EL1
;
1419 return MISCREG_DBGCLAIMSET_EL1
;
1425 return MISCREG_DBGCLAIMCLR_EL1
;
1431 return MISCREG_DBGAUTHSTATUS_EL1
;
1449 return MISCREG_MIDR_EL1
;
1451 return MISCREG_MPIDR_EL1
;
1453 return MISCREG_REVIDR_EL1
;
1459 return MISCREG_ID_PFR0_EL1
;
1461 return MISCREG_ID_PFR1_EL1
;
1463 return MISCREG_ID_DFR0_EL1
;
1465 return MISCREG_ID_AFR0_EL1
;
1467 return MISCREG_ID_MMFR0_EL1
;
1469 return MISCREG_ID_MMFR1_EL1
;
1471 return MISCREG_ID_MMFR2_EL1
;
1473 return MISCREG_ID_MMFR3_EL1
;
1479 return MISCREG_ID_ISAR0_EL1
;
1481 return MISCREG_ID_ISAR1_EL1
;
1483 return MISCREG_ID_ISAR2_EL1
;
1485 return MISCREG_ID_ISAR3_EL1
;
1487 return MISCREG_ID_ISAR4_EL1
;
1489 return MISCREG_ID_ISAR5_EL1
;
1495 return MISCREG_MVFR0_EL1
;
1497 return MISCREG_MVFR1_EL1
;
1499 return MISCREG_MVFR2_EL1
;
1507 return MISCREG_ID_AA64PFR0_EL1
;
1509 return MISCREG_ID_AA64PFR1_EL1
;
1517 return MISCREG_ID_AA64DFR0_EL1
;
1519 return MISCREG_ID_AA64DFR1_EL1
;
1521 return MISCREG_ID_AA64AFR0_EL1
;
1523 return MISCREG_ID_AA64AFR1_EL1
;
1534 return MISCREG_ID_AA64ISAR0_EL1
;
1536 return MISCREG_ID_AA64ISAR1_EL1
;
1544 return MISCREG_ID_AA64MMFR0_EL1
;
1546 return MISCREG_ID_AA64MMFR1_EL1
;
1548 return MISCREG_ID_AA64MMFR2_EL1
;
1560 return MISCREG_CCSIDR_EL1
;
1562 return MISCREG_CLIDR_EL1
;
1564 return MISCREG_AIDR_EL1
;
1574 return MISCREG_CSSELR_EL1
;
1584 return MISCREG_CTR_EL0
;
1586 return MISCREG_DCZID_EL0
;
1596 return MISCREG_VPIDR_EL2
;
1598 return MISCREG_VMPIDR_EL2
;
1612 return MISCREG_SCTLR_EL1
;
1614 return MISCREG_ACTLR_EL1
;
1616 return MISCREG_CPACR_EL1
;
1626 return MISCREG_SCTLR_EL2
;
1628 return MISCREG_ACTLR_EL2
;
1634 return MISCREG_HCR_EL2
;
1636 return MISCREG_MDCR_EL2
;
1638 return MISCREG_CPTR_EL2
;
1640 return MISCREG_HSTR_EL2
;
1642 return MISCREG_HACR_EL2
;
1652 return MISCREG_SCTLR_EL3
;
1654 return MISCREG_ACTLR_EL3
;
1660 return MISCREG_SCR_EL3
;
1662 return MISCREG_SDER32_EL3
;
1664 return MISCREG_CPTR_EL3
;
1670 return MISCREG_MDCR_EL3
;
1684 return MISCREG_TTBR0_EL1
;
1686 return MISCREG_TTBR1_EL1
;
1688 return MISCREG_TCR_EL1
;
1698 return MISCREG_TTBR0_EL2
;
1700 return MISCREG_TTBR1_EL2
;
1702 return MISCREG_TCR_EL2
;
1708 return MISCREG_VTTBR_EL2
;
1710 return MISCREG_VTCR_EL2
;
1720 return MISCREG_TTBR0_EL3
;
1722 return MISCREG_TCR_EL3
;
1736 return MISCREG_DACR32_EL2
;
1750 return MISCREG_SPSR_EL1
;
1752 return MISCREG_ELR_EL1
;
1758 return MISCREG_SP_EL0
;
1764 return MISCREG_SPSEL
;
1766 return MISCREG_CURRENTEL
;
1776 return MISCREG_NZCV
;
1778 return MISCREG_DAIF
;
1784 return MISCREG_FPCR
;
1786 return MISCREG_FPSR
;
1792 return MISCREG_DSPSR_EL0
;
1794 return MISCREG_DLR_EL0
;
1804 return MISCREG_SPSR_EL2
;
1806 return MISCREG_ELR_EL2
;
1812 return MISCREG_SP_EL1
;
1818 return MISCREG_SPSR_IRQ_AA64
;
1820 return MISCREG_SPSR_ABT_AA64
;
1822 return MISCREG_SPSR_UND_AA64
;
1824 return MISCREG_SPSR_FIQ_AA64
;
1834 return MISCREG_SPSR_EL3
;
1836 return MISCREG_ELR_EL3
;
1842 return MISCREG_SP_EL2
;
1856 return MISCREG_AFSR0_EL1
;
1858 return MISCREG_AFSR1_EL1
;
1864 return MISCREG_ESR_EL1
;
1870 return MISCREG_ERRIDR_EL1
;
1872 return MISCREG_ERRSELR_EL1
;
1878 return MISCREG_ERXFR_EL1
;
1880 return MISCREG_ERXCTLR_EL1
;
1882 return MISCREG_ERXSTATUS_EL1
;
1884 return MISCREG_ERXADDR_EL1
;
1890 return MISCREG_ERXMISC0_EL1
;
1892 return MISCREG_ERXMISC1_EL1
;
1902 return MISCREG_IFSR32_EL2
;
1908 return MISCREG_AFSR0_EL2
;
1910 return MISCREG_AFSR1_EL2
;
1916 return MISCREG_ESR_EL2
;
1918 return MISCREG_VSESR_EL2
;
1924 return MISCREG_FPEXC32_EL2
;
1934 return MISCREG_AFSR0_EL3
;
1936 return MISCREG_AFSR1_EL3
;
1942 return MISCREG_ESR_EL3
;
1956 return MISCREG_FAR_EL1
;
1966 return MISCREG_FAR_EL2
;
1968 return MISCREG_HPFAR_EL2
;
1978 return MISCREG_FAR_EL3
;
1992 return MISCREG_PAR_EL1
;
2006 return MISCREG_PMINTENSET_EL1
;
2008 return MISCREG_PMINTENCLR_EL1
;
2018 return MISCREG_PMCR_EL0
;
2020 return MISCREG_PMCNTENSET_EL0
;
2022 return MISCREG_PMCNTENCLR_EL0
;
2024 return MISCREG_PMOVSCLR_EL0
;
2026 return MISCREG_PMSWINC_EL0
;
2028 return MISCREG_PMSELR_EL0
;
2030 return MISCREG_PMCEID0_EL0
;
2032 return MISCREG_PMCEID1_EL0
;
2038 return MISCREG_PMCCNTR_EL0
;
2040 return MISCREG_PMXEVTYPER_EL0
;
2042 return MISCREG_PMXEVCNTR_EL0
;
2048 return MISCREG_PMUSERENR_EL0
;
2050 return MISCREG_PMOVSSET_EL0
;
2064 return MISCREG_MAIR_EL1
;
2070 return MISCREG_AMAIR_EL1
;
2080 return MISCREG_MAIR_EL2
;
2086 return MISCREG_AMAIR_EL2
;
2096 return MISCREG_MAIR_EL3
;
2102 return MISCREG_AMAIR_EL3
;
2116 return MISCREG_L2CTLR_EL1
;
2118 return MISCREG_L2ECTLR_EL1
;
2124 // S3_<op1>_11_<Cm>_<op2>
2125 return MISCREG_IMPDEF_UNIMPL
;
2135 return MISCREG_VBAR_EL1
;
2137 return MISCREG_RVBAR_EL1
;
2143 return MISCREG_ISR_EL1
;
2145 return MISCREG_DISR_EL1
;
2155 return MISCREG_VBAR_EL2
;
2157 return MISCREG_RVBAR_EL2
;
2163 return MISCREG_VDISR_EL2
;
2173 return MISCREG_VBAR_EL3
;
2175 return MISCREG_RVBAR_EL3
;
2177 return MISCREG_RMR_EL3
;
2191 return MISCREG_CONTEXTIDR_EL1
;
2193 return MISCREG_TPIDR_EL1
;
2203 return MISCREG_TPIDR_EL0
;
2205 return MISCREG_TPIDRRO_EL0
;
2215 return MISCREG_CONTEXTIDR_EL2
;
2217 return MISCREG_TPIDR_EL2
;
2227 return MISCREG_TPIDR_EL3
;
2241 return MISCREG_CNTKCTL_EL1
;
2251 return MISCREG_CNTFRQ_EL0
;
2253 return MISCREG_CNTPCT_EL0
;
2255 return MISCREG_CNTVCT_EL0
;
2261 return MISCREG_CNTP_TVAL_EL0
;
2263 return MISCREG_CNTP_CTL_EL0
;
2265 return MISCREG_CNTP_CVAL_EL0
;
2271 return MISCREG_CNTV_TVAL_EL0
;
2273 return MISCREG_CNTV_CTL_EL0
;
2275 return MISCREG_CNTV_CVAL_EL0
;
2281 return MISCREG_PMEVCNTR0_EL0
;
2283 return MISCREG_PMEVCNTR1_EL0
;
2285 return MISCREG_PMEVCNTR2_EL0
;
2287 return MISCREG_PMEVCNTR3_EL0
;
2289 return MISCREG_PMEVCNTR4_EL0
;
2291 return MISCREG_PMEVCNTR5_EL0
;
2297 return MISCREG_PMEVTYPER0_EL0
;
2299 return MISCREG_PMEVTYPER1_EL0
;
2301 return MISCREG_PMEVTYPER2_EL0
;
2303 return MISCREG_PMEVTYPER3_EL0
;
2305 return MISCREG_PMEVTYPER4_EL0
;
2307 return MISCREG_PMEVTYPER5_EL0
;
2313 return MISCREG_PMCCFILTR_EL0
;
2322 return MISCREG_CNTVOFF_EL2
;
2328 return MISCREG_CNTHCTL_EL2
;
2334 return MISCREG_CNTHP_TVAL_EL2
;
2336 return MISCREG_CNTHP_CTL_EL2
;
2338 return MISCREG_CNTHP_CVAL_EL2
;
2344 return MISCREG_CNTHV_TVAL_EL2
;
2346 return MISCREG_CNTHV_CTL_EL2
;
2348 return MISCREG_CNTHV_CVAL_EL2
;
2358 return MISCREG_CNTPS_TVAL_EL1
;
2360 return MISCREG_CNTPS_CTL_EL1
;
2362 return MISCREG_CNTPS_CVAL_EL1
;
2376 return MISCREG_IL1DATA0_EL1
;
2378 return MISCREG_IL1DATA1_EL1
;
2380 return MISCREG_IL1DATA2_EL1
;
2382 return MISCREG_IL1DATA3_EL1
;
2388 return MISCREG_DL1DATA0_EL1
;
2390 return MISCREG_DL1DATA1_EL1
;
2392 return MISCREG_DL1DATA2_EL1
;
2394 return MISCREG_DL1DATA3_EL1
;
2396 return MISCREG_DL1DATA4_EL1
;
2406 return MISCREG_L2ACTLR_EL1
;
2412 return MISCREG_CPUACTLR_EL1
;
2414 return MISCREG_CPUECTLR_EL1
;
2416 return MISCREG_CPUMERRSR_EL1
;
2418 return MISCREG_L2MERRSR_EL1
;
2424 return MISCREG_CBAR_EL1
;
2431 // S3_<op1>_15_<Cm>_<op2>
2432 return MISCREG_IMPDEF_UNIMPL
;
2437 return MISCREG_UNKNOWN
;
2440 bitset
<NUM_MISCREG_INFOS
> miscRegInfo
[NUM_MISCREGS
]; // initialized below
2443 ISA::initializeMiscRegMetadata()
2445 // the MiscReg metadata tables are shared across all instances of the
2446 // ISA object, so there's no need to initialize them multiple times.
2447 static bool completed
= false;
2451 // This boolean variable specifies if the system is running in aarch32 at
2452 // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
2453 // is running in aarch64 (aarch32EL3 = false)
2454 bool aarch32EL3
= haveSecurity
&& !highestELIs64
;
2457 * Some registers alias with others, and therefore need to be translated.
2458 * When two mapping registers are given, they are the 32b lower and
2459 * upper halves, respectively, of the 64b register being mapped.
2460 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
2462 * NAM = "not architecturally mandated",
2463 * from ARM DDI 0487A.i, template text
2464 * "AArch64 System register ___ can be mapped to
2465 * AArch32 System register ___, but this is not
2466 * architecturally mandated."
2469 InitReg(MISCREG_CPSR
)
2471 InitReg(MISCREG_SPSR
)
2473 InitReg(MISCREG_SPSR_FIQ
)
2475 InitReg(MISCREG_SPSR_IRQ
)
2477 InitReg(MISCREG_SPSR_SVC
)
2479 InitReg(MISCREG_SPSR_MON
)
2481 InitReg(MISCREG_SPSR_ABT
)
2483 InitReg(MISCREG_SPSR_HYP
)
2485 InitReg(MISCREG_SPSR_UND
)
2487 InitReg(MISCREG_ELR_HYP
)
2489 InitReg(MISCREG_FPSID
)
2491 InitReg(MISCREG_FPSCR
)
2493 InitReg(MISCREG_MVFR1
)
2495 InitReg(MISCREG_MVFR0
)
2497 InitReg(MISCREG_FPEXC
)
2501 InitReg(MISCREG_CPSR_MODE
)
2503 InitReg(MISCREG_CPSR_Q
)
2505 InitReg(MISCREG_FPSCR_EXC
)
2507 InitReg(MISCREG_FPSCR_QC
)
2509 InitReg(MISCREG_LOCKADDR
)
2511 InitReg(MISCREG_LOCKFLAG
)
2513 InitReg(MISCREG_PRRR_MAIR0
)
2516 InitReg(MISCREG_PRRR_MAIR0_NS
)
2518 .privSecure(!aarch32EL3
)
2520 InitReg(MISCREG_PRRR_MAIR0_S
)
2523 InitReg(MISCREG_NMRR_MAIR1
)
2526 InitReg(MISCREG_NMRR_MAIR1_NS
)
2528 .privSecure(!aarch32EL3
)
2530 InitReg(MISCREG_NMRR_MAIR1_S
)
2533 InitReg(MISCREG_PMXEVTYPER_PMCCFILTR
)
2535 InitReg(MISCREG_SCTLR_RST
)
2537 InitReg(MISCREG_SEV_MAILBOX
)
2540 // AArch32 CP14 registers
2541 InitReg(MISCREG_DBGDIDR
)
2542 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2543 InitReg(MISCREG_DBGDSCRint
)
2544 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2545 InitReg(MISCREG_DBGDCCINT
)
2548 InitReg(MISCREG_DBGDTRTXint
)
2551 InitReg(MISCREG_DBGDTRRXint
)
2554 InitReg(MISCREG_DBGWFAR
)
2557 InitReg(MISCREG_DBGVCR
)
2560 InitReg(MISCREG_DBGDTRRXext
)
2563 InitReg(MISCREG_DBGDSCRext
)
2567 InitReg(MISCREG_DBGDTRTXext
)
2570 InitReg(MISCREG_DBGOSECCR
)
2573 InitReg(MISCREG_DBGBVR0
)
2576 InitReg(MISCREG_DBGBVR1
)
2579 InitReg(MISCREG_DBGBVR2
)
2582 InitReg(MISCREG_DBGBVR3
)
2585 InitReg(MISCREG_DBGBVR4
)
2588 InitReg(MISCREG_DBGBVR5
)
2591 InitReg(MISCREG_DBGBCR0
)
2594 InitReg(MISCREG_DBGBCR1
)
2597 InitReg(MISCREG_DBGBCR2
)
2600 InitReg(MISCREG_DBGBCR3
)
2603 InitReg(MISCREG_DBGBCR4
)
2606 InitReg(MISCREG_DBGBCR5
)
2609 InitReg(MISCREG_DBGWVR0
)
2612 InitReg(MISCREG_DBGWVR1
)
2615 InitReg(MISCREG_DBGWVR2
)
2618 InitReg(MISCREG_DBGWVR3
)
2621 InitReg(MISCREG_DBGWCR0
)
2624 InitReg(MISCREG_DBGWCR1
)
2627 InitReg(MISCREG_DBGWCR2
)
2630 InitReg(MISCREG_DBGWCR3
)
2633 InitReg(MISCREG_DBGDRAR
)
2635 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2636 InitReg(MISCREG_DBGBXVR4
)
2639 InitReg(MISCREG_DBGBXVR5
)
2642 InitReg(MISCREG_DBGOSLAR
)
2644 .allPrivileges().monSecureRead(0).monNonSecureRead(0);
2645 InitReg(MISCREG_DBGOSLSR
)
2647 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2648 InitReg(MISCREG_DBGOSDLR
)
2651 InitReg(MISCREG_DBGPRCR
)
2654 InitReg(MISCREG_DBGDSAR
)
2656 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2657 InitReg(MISCREG_DBGCLAIMSET
)
2660 InitReg(MISCREG_DBGCLAIMCLR
)
2663 InitReg(MISCREG_DBGAUTHSTATUS
)
2665 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2666 InitReg(MISCREG_DBGDEVID2
)
2668 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2669 InitReg(MISCREG_DBGDEVID1
)
2671 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2672 InitReg(MISCREG_DBGDEVID0
)
2674 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2675 InitReg(MISCREG_TEECR
)
2678 InitReg(MISCREG_JIDR
)
2680 InitReg(MISCREG_TEEHBR
)
2682 InitReg(MISCREG_JOSCR
)
2684 InitReg(MISCREG_JMCR
)
2687 // AArch32 CP15 registers
2688 InitReg(MISCREG_MIDR
)
2689 .allPrivileges().exceptUserMode().writes(0);
2690 InitReg(MISCREG_CTR
)
2691 .allPrivileges().exceptUserMode().writes(0);
2692 InitReg(MISCREG_TCMTR
)
2693 .allPrivileges().exceptUserMode().writes(0);
2694 InitReg(MISCREG_TLBTR
)
2695 .allPrivileges().exceptUserMode().writes(0);
2696 InitReg(MISCREG_MPIDR
)
2697 .allPrivileges().exceptUserMode().writes(0);
2698 InitReg(MISCREG_REVIDR
)
2701 .allPrivileges().exceptUserMode().writes(0);
2702 InitReg(MISCREG_ID_PFR0
)
2703 .allPrivileges().exceptUserMode().writes(0);
2704 InitReg(MISCREG_ID_PFR1
)
2705 .allPrivileges().exceptUserMode().writes(0);
2706 InitReg(MISCREG_ID_DFR0
)
2707 .allPrivileges().exceptUserMode().writes(0);
2708 InitReg(MISCREG_ID_AFR0
)
2709 .allPrivileges().exceptUserMode().writes(0);
2710 InitReg(MISCREG_ID_MMFR0
)
2711 .allPrivileges().exceptUserMode().writes(0);
2712 InitReg(MISCREG_ID_MMFR1
)
2713 .allPrivileges().exceptUserMode().writes(0);
2714 InitReg(MISCREG_ID_MMFR2
)
2715 .allPrivileges().exceptUserMode().writes(0);
2716 InitReg(MISCREG_ID_MMFR3
)
2717 .allPrivileges().exceptUserMode().writes(0);
2718 InitReg(MISCREG_ID_ISAR0
)
2719 .allPrivileges().exceptUserMode().writes(0);
2720 InitReg(MISCREG_ID_ISAR1
)
2721 .allPrivileges().exceptUserMode().writes(0);
2722 InitReg(MISCREG_ID_ISAR2
)
2723 .allPrivileges().exceptUserMode().writes(0);
2724 InitReg(MISCREG_ID_ISAR3
)
2725 .allPrivileges().exceptUserMode().writes(0);
2726 InitReg(MISCREG_ID_ISAR4
)
2727 .allPrivileges().exceptUserMode().writes(0);
2728 InitReg(MISCREG_ID_ISAR5
)
2729 .allPrivileges().exceptUserMode().writes(0);
2730 InitReg(MISCREG_CCSIDR
)
2731 .allPrivileges().exceptUserMode().writes(0);
2732 InitReg(MISCREG_CLIDR
)
2733 .allPrivileges().exceptUserMode().writes(0);
2734 InitReg(MISCREG_AIDR
)
2735 .allPrivileges().exceptUserMode().writes(0);
2736 InitReg(MISCREG_CSSELR
)
2738 InitReg(MISCREG_CSSELR_NS
)
2740 .privSecure(!aarch32EL3
)
2741 .nonSecure().exceptUserMode();
2742 InitReg(MISCREG_CSSELR_S
)
2744 .secure().exceptUserMode();
2745 InitReg(MISCREG_VPIDR
)
2746 .hyp().monNonSecure();
2747 InitReg(MISCREG_VMPIDR
)
2748 .hyp().monNonSecure();
2749 InitReg(MISCREG_SCTLR
)
2751 InitReg(MISCREG_SCTLR_NS
)
2753 .privSecure(!aarch32EL3
)
2754 .nonSecure().exceptUserMode();
2755 InitReg(MISCREG_SCTLR_S
)
2757 .secure().exceptUserMode();
2758 InitReg(MISCREG_ACTLR
)
2760 InitReg(MISCREG_ACTLR_NS
)
2762 .privSecure(!aarch32EL3
)
2763 .nonSecure().exceptUserMode();
2764 InitReg(MISCREG_ACTLR_S
)
2766 .secure().exceptUserMode();
2767 InitReg(MISCREG_CPACR
)
2768 .allPrivileges().exceptUserMode();
2769 InitReg(MISCREG_SCR
)
2770 .mon().secure().exceptUserMode()
2771 .res0(0xff40) // [31:16], [6]
2772 .res1(0x0030); // [5:4]
2773 InitReg(MISCREG_SDER
)
2775 InitReg(MISCREG_NSACR
)
2776 .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
2777 InitReg(MISCREG_HSCTLR
)
2778 .hyp().monNonSecure();
2779 InitReg(MISCREG_HACTLR
)
2780 .hyp().monNonSecure();
2781 InitReg(MISCREG_HCR
)
2782 .hyp().monNonSecure();
2783 InitReg(MISCREG_HDCR
)
2784 .hyp().monNonSecure();
2785 InitReg(MISCREG_HCPTR
)
2786 .hyp().monNonSecure();
2787 InitReg(MISCREG_HSTR
)
2788 .hyp().monNonSecure();
2789 InitReg(MISCREG_HACR
)
2792 .hyp().monNonSecure();
2793 InitReg(MISCREG_TTBR0
)
2795 InitReg(MISCREG_TTBR0_NS
)
2797 .privSecure(!aarch32EL3
)
2798 .nonSecure().exceptUserMode();
2799 InitReg(MISCREG_TTBR0_S
)
2801 .secure().exceptUserMode();
2802 InitReg(MISCREG_TTBR1
)
2804 InitReg(MISCREG_TTBR1_NS
)
2806 .privSecure(!aarch32EL3
)
2807 .nonSecure().exceptUserMode();
2808 InitReg(MISCREG_TTBR1_S
)
2810 .secure().exceptUserMode();
2811 InitReg(MISCREG_TTBCR
)
2813 InitReg(MISCREG_TTBCR_NS
)
2815 .privSecure(!aarch32EL3
)
2816 .nonSecure().exceptUserMode();
2817 InitReg(MISCREG_TTBCR_S
)
2819 .secure().exceptUserMode();
2820 InitReg(MISCREG_HTCR
)
2821 .hyp().monNonSecure();
2822 InitReg(MISCREG_VTCR
)
2823 .hyp().monNonSecure();
2824 InitReg(MISCREG_DACR
)
2826 InitReg(MISCREG_DACR_NS
)
2828 .privSecure(!aarch32EL3
)
2829 .nonSecure().exceptUserMode();
2830 InitReg(MISCREG_DACR_S
)
2832 .secure().exceptUserMode();
2833 InitReg(MISCREG_DFSR
)
2835 InitReg(MISCREG_DFSR_NS
)
2837 .privSecure(!aarch32EL3
)
2838 .nonSecure().exceptUserMode();
2839 InitReg(MISCREG_DFSR_S
)
2841 .secure().exceptUserMode();
2842 InitReg(MISCREG_IFSR
)
2844 InitReg(MISCREG_IFSR_NS
)
2846 .privSecure(!aarch32EL3
)
2847 .nonSecure().exceptUserMode();
2848 InitReg(MISCREG_IFSR_S
)
2850 .secure().exceptUserMode();
2851 InitReg(MISCREG_ADFSR
)
2855 InitReg(MISCREG_ADFSR_NS
)
2859 .privSecure(!aarch32EL3
)
2860 .nonSecure().exceptUserMode();
2861 InitReg(MISCREG_ADFSR_S
)
2865 .secure().exceptUserMode();
2866 InitReg(MISCREG_AIFSR
)
2870 InitReg(MISCREG_AIFSR_NS
)
2874 .privSecure(!aarch32EL3
)
2875 .nonSecure().exceptUserMode();
2876 InitReg(MISCREG_AIFSR_S
)
2880 .secure().exceptUserMode();
2881 InitReg(MISCREG_HADFSR
)
2882 .hyp().monNonSecure();
2883 InitReg(MISCREG_HAIFSR
)
2884 .hyp().monNonSecure();
2885 InitReg(MISCREG_HSR
)
2886 .hyp().monNonSecure();
2887 InitReg(MISCREG_DFAR
)
2889 InitReg(MISCREG_DFAR_NS
)
2891 .privSecure(!aarch32EL3
)
2892 .nonSecure().exceptUserMode();
2893 InitReg(MISCREG_DFAR_S
)
2895 .secure().exceptUserMode();
2896 InitReg(MISCREG_IFAR
)
2898 InitReg(MISCREG_IFAR_NS
)
2900 .privSecure(!aarch32EL3
)
2901 .nonSecure().exceptUserMode();
2902 InitReg(MISCREG_IFAR_S
)
2904 .secure().exceptUserMode();
2905 InitReg(MISCREG_HDFAR
)
2906 .hyp().monNonSecure();
2907 InitReg(MISCREG_HIFAR
)
2908 .hyp().monNonSecure();
2909 InitReg(MISCREG_HPFAR
)
2910 .hyp().monNonSecure();
2911 InitReg(MISCREG_ICIALLUIS
)
2914 .writes(1).exceptUserMode();
2915 InitReg(MISCREG_BPIALLIS
)
2918 .writes(1).exceptUserMode();
2919 InitReg(MISCREG_PAR
)
2921 InitReg(MISCREG_PAR_NS
)
2923 .privSecure(!aarch32EL3
)
2924 .nonSecure().exceptUserMode();
2925 InitReg(MISCREG_PAR_S
)
2927 .secure().exceptUserMode();
2928 InitReg(MISCREG_ICIALLU
)
2929 .writes(1).exceptUserMode();
2930 InitReg(MISCREG_ICIMVAU
)
2933 .writes(1).exceptUserMode();
2934 InitReg(MISCREG_CP15ISB
)
2936 InitReg(MISCREG_BPIALL
)
2939 .writes(1).exceptUserMode();
2940 InitReg(MISCREG_BPIMVA
)
2943 .writes(1).exceptUserMode();
2944 InitReg(MISCREG_DCIMVAC
)
2947 .writes(1).exceptUserMode();
2948 InitReg(MISCREG_DCISW
)
2951 .writes(1).exceptUserMode();
2952 InitReg(MISCREG_ATS1CPR
)
2953 .writes(1).exceptUserMode();
2954 InitReg(MISCREG_ATS1CPW
)
2955 .writes(1).exceptUserMode();
2956 InitReg(MISCREG_ATS1CUR
)
2957 .writes(1).exceptUserMode();
2958 InitReg(MISCREG_ATS1CUW
)
2959 .writes(1).exceptUserMode();
2960 InitReg(MISCREG_ATS12NSOPR
)
2961 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2962 InitReg(MISCREG_ATS12NSOPW
)
2963 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2964 InitReg(MISCREG_ATS12NSOUR
)
2965 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2966 InitReg(MISCREG_ATS12NSOUW
)
2967 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2968 InitReg(MISCREG_DCCMVAC
)
2969 .writes(1).exceptUserMode();
2970 InitReg(MISCREG_DCCSW
)
2973 .writes(1).exceptUserMode();
2974 InitReg(MISCREG_CP15DSB
)
2976 InitReg(MISCREG_CP15DMB
)
2978 InitReg(MISCREG_DCCMVAU
)
2981 .writes(1).exceptUserMode();
2982 InitReg(MISCREG_DCCIMVAC
)
2985 .writes(1).exceptUserMode();
2986 InitReg(MISCREG_DCCISW
)
2989 .writes(1).exceptUserMode();
2990 InitReg(MISCREG_ATS1HR
)
2991 .monNonSecureWrite().hypWrite();
2992 InitReg(MISCREG_ATS1HW
)
2993 .monNonSecureWrite().hypWrite();
2994 InitReg(MISCREG_TLBIALLIS
)
2995 .writes(1).exceptUserMode();
2996 InitReg(MISCREG_TLBIMVAIS
)
2997 .writes(1).exceptUserMode();
2998 InitReg(MISCREG_TLBIASIDIS
)
2999 .writes(1).exceptUserMode();
3000 InitReg(MISCREG_TLBIMVAAIS
)
3001 .writes(1).exceptUserMode();
3002 InitReg(MISCREG_TLBIMVALIS
)
3003 .writes(1).exceptUserMode();
3004 InitReg(MISCREG_TLBIMVAALIS
)
3005 .writes(1).exceptUserMode();
3006 InitReg(MISCREG_ITLBIALL
)
3007 .writes(1).exceptUserMode();
3008 InitReg(MISCREG_ITLBIMVA
)
3009 .writes(1).exceptUserMode();
3010 InitReg(MISCREG_ITLBIASID
)
3011 .writes(1).exceptUserMode();
3012 InitReg(MISCREG_DTLBIALL
)
3013 .writes(1).exceptUserMode();
3014 InitReg(MISCREG_DTLBIMVA
)
3015 .writes(1).exceptUserMode();
3016 InitReg(MISCREG_DTLBIASID
)
3017 .writes(1).exceptUserMode();
3018 InitReg(MISCREG_TLBIALL
)
3019 .writes(1).exceptUserMode();
3020 InitReg(MISCREG_TLBIMVA
)
3021 .writes(1).exceptUserMode();
3022 InitReg(MISCREG_TLBIASID
)
3023 .writes(1).exceptUserMode();
3024 InitReg(MISCREG_TLBIMVAA
)
3025 .writes(1).exceptUserMode();
3026 InitReg(MISCREG_TLBIMVAL
)
3027 .writes(1).exceptUserMode();
3028 InitReg(MISCREG_TLBIMVAAL
)
3029 .writes(1).exceptUserMode();
3030 InitReg(MISCREG_TLBIIPAS2IS
)
3031 .monNonSecureWrite().hypWrite();
3032 InitReg(MISCREG_TLBIIPAS2LIS
)
3033 .monNonSecureWrite().hypWrite();
3034 InitReg(MISCREG_TLBIALLHIS
)
3035 .monNonSecureWrite().hypWrite();
3036 InitReg(MISCREG_TLBIMVAHIS
)
3037 .monNonSecureWrite().hypWrite();
3038 InitReg(MISCREG_TLBIALLNSNHIS
)
3039 .monNonSecureWrite().hypWrite();
3040 InitReg(MISCREG_TLBIMVALHIS
)
3041 .monNonSecureWrite().hypWrite();
3042 InitReg(MISCREG_TLBIIPAS2
)
3043 .monNonSecureWrite().hypWrite();
3044 InitReg(MISCREG_TLBIIPAS2L
)
3045 .monNonSecureWrite().hypWrite();
3046 InitReg(MISCREG_TLBIALLH
)
3047 .monNonSecureWrite().hypWrite();
3048 InitReg(MISCREG_TLBIMVAH
)
3049 .monNonSecureWrite().hypWrite();
3050 InitReg(MISCREG_TLBIALLNSNH
)
3051 .monNonSecureWrite().hypWrite();
3052 InitReg(MISCREG_TLBIMVALH
)
3053 .monNonSecureWrite().hypWrite();
3054 InitReg(MISCREG_PMCR
)
3056 InitReg(MISCREG_PMCNTENSET
)
3058 InitReg(MISCREG_PMCNTENCLR
)
3060 InitReg(MISCREG_PMOVSR
)
3062 InitReg(MISCREG_PMSWINC
)
3064 InitReg(MISCREG_PMSELR
)
3066 InitReg(MISCREG_PMCEID0
)
3068 InitReg(MISCREG_PMCEID1
)
3070 InitReg(MISCREG_PMCCNTR
)
3072 InitReg(MISCREG_PMXEVTYPER
)
3074 InitReg(MISCREG_PMCCFILTR
)
3076 InitReg(MISCREG_PMXEVCNTR
)
3078 InitReg(MISCREG_PMUSERENR
)
3079 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
3080 InitReg(MISCREG_PMINTENSET
)
3081 .allPrivileges().exceptUserMode();
3082 InitReg(MISCREG_PMINTENCLR
)
3083 .allPrivileges().exceptUserMode();
3084 InitReg(MISCREG_PMOVSSET
)
3087 InitReg(MISCREG_L2CTLR
)
3088 .allPrivileges().exceptUserMode();
3089 InitReg(MISCREG_L2ECTLR
)
3091 .allPrivileges().exceptUserMode();
3092 InitReg(MISCREG_PRRR
)
3094 InitReg(MISCREG_PRRR_NS
)
3096 .privSecure(!aarch32EL3
)
3097 .nonSecure().exceptUserMode();
3098 InitReg(MISCREG_PRRR_S
)
3100 .secure().exceptUserMode();
3101 InitReg(MISCREG_MAIR0
)
3103 InitReg(MISCREG_MAIR0_NS
)
3105 .privSecure(!aarch32EL3
)
3106 .nonSecure().exceptUserMode();
3107 InitReg(MISCREG_MAIR0_S
)
3109 .secure().exceptUserMode();
3110 InitReg(MISCREG_NMRR
)
3112 InitReg(MISCREG_NMRR_NS
)
3114 .privSecure(!aarch32EL3
)
3115 .nonSecure().exceptUserMode();
3116 InitReg(MISCREG_NMRR_S
)
3118 .secure().exceptUserMode();
3119 InitReg(MISCREG_MAIR1
)
3121 InitReg(MISCREG_MAIR1_NS
)
3123 .privSecure(!aarch32EL3
)
3124 .nonSecure().exceptUserMode();
3125 InitReg(MISCREG_MAIR1_S
)
3127 .secure().exceptUserMode();
3128 InitReg(MISCREG_AMAIR0
)
3130 InitReg(MISCREG_AMAIR0_NS
)
3132 .privSecure(!aarch32EL3
)
3133 .nonSecure().exceptUserMode();
3134 InitReg(MISCREG_AMAIR0_S
)
3136 .secure().exceptUserMode();
3137 InitReg(MISCREG_AMAIR1
)
3139 InitReg(MISCREG_AMAIR1_NS
)
3141 .privSecure(!aarch32EL3
)
3142 .nonSecure().exceptUserMode();
3143 InitReg(MISCREG_AMAIR1_S
)
3145 .secure().exceptUserMode();
3146 InitReg(MISCREG_HMAIR0
)
3147 .hyp().monNonSecure();
3148 InitReg(MISCREG_HMAIR1
)
3149 .hyp().monNonSecure();
3150 InitReg(MISCREG_HAMAIR0
)
3153 .hyp().monNonSecure();
3154 InitReg(MISCREG_HAMAIR1
)
3157 .hyp().monNonSecure();
3158 InitReg(MISCREG_VBAR
)
3160 InitReg(MISCREG_VBAR_NS
)
3162 .privSecure(!aarch32EL3
)
3163 .nonSecure().exceptUserMode();
3164 InitReg(MISCREG_VBAR_S
)
3166 .secure().exceptUserMode();
3167 InitReg(MISCREG_MVBAR
)
3168 .mon().secure().exceptUserMode();
3169 InitReg(MISCREG_RMR
)
3171 .mon().secure().exceptUserMode();
3172 InitReg(MISCREG_ISR
)
3173 .allPrivileges().exceptUserMode().writes(0);
3174 InitReg(MISCREG_HVBAR
)
3175 .hyp().monNonSecure();
3176 InitReg(MISCREG_FCSEIDR
)
3179 .allPrivileges().exceptUserMode();
3180 InitReg(MISCREG_CONTEXTIDR
)
3182 InitReg(MISCREG_CONTEXTIDR_NS
)
3184 .privSecure(!aarch32EL3
)
3185 .nonSecure().exceptUserMode();
3186 InitReg(MISCREG_CONTEXTIDR_S
)
3188 .secure().exceptUserMode();
3189 InitReg(MISCREG_TPIDRURW
)
3191 InitReg(MISCREG_TPIDRURW_NS
)
3194 .privSecure(!aarch32EL3
)
3196 InitReg(MISCREG_TPIDRURW_S
)
3199 InitReg(MISCREG_TPIDRURO
)
3201 InitReg(MISCREG_TPIDRURO_NS
)
3204 .userNonSecureWrite(0).userSecureRead(1)
3205 .privSecure(!aarch32EL3
)
3207 InitReg(MISCREG_TPIDRURO_S
)
3209 .secure().userSecureWrite(0);
3210 InitReg(MISCREG_TPIDRPRW
)
3212 InitReg(MISCREG_TPIDRPRW_NS
)
3214 .nonSecure().exceptUserMode()
3215 .privSecure(!aarch32EL3
);
3216 InitReg(MISCREG_TPIDRPRW_S
)
3218 .secure().exceptUserMode();
3219 InitReg(MISCREG_HTPIDR
)
3220 .hyp().monNonSecure();
3221 InitReg(MISCREG_CNTFRQ
)
3224 InitReg(MISCREG_CNTKCTL
)
3225 .allPrivileges().exceptUserMode();
3226 InitReg(MISCREG_CNTP_TVAL
)
3228 InitReg(MISCREG_CNTP_TVAL_NS
)
3231 .privSecure(!aarch32EL3
)
3233 InitReg(MISCREG_CNTP_TVAL_S
)
3236 InitReg(MISCREG_CNTP_CTL
)
3238 InitReg(MISCREG_CNTP_CTL_NS
)
3241 .privSecure(!aarch32EL3
)
3243 InitReg(MISCREG_CNTP_CTL_S
)
3246 InitReg(MISCREG_CNTV_TVAL
)
3248 InitReg(MISCREG_CNTV_CTL
)
3250 InitReg(MISCREG_CNTHCTL
)
3251 .hypWrite().monNonSecureRead();
3252 InitReg(MISCREG_CNTHP_TVAL
)
3253 .hypWrite().monNonSecureRead();
3254 InitReg(MISCREG_CNTHP_CTL
)
3255 .hypWrite().monNonSecureRead();
3256 InitReg(MISCREG_IL1DATA0
)
3258 .allPrivileges().exceptUserMode();
3259 InitReg(MISCREG_IL1DATA1
)
3261 .allPrivileges().exceptUserMode();
3262 InitReg(MISCREG_IL1DATA2
)
3264 .allPrivileges().exceptUserMode();
3265 InitReg(MISCREG_IL1DATA3
)
3267 .allPrivileges().exceptUserMode();
3268 InitReg(MISCREG_DL1DATA0
)
3270 .allPrivileges().exceptUserMode();
3271 InitReg(MISCREG_DL1DATA1
)
3273 .allPrivileges().exceptUserMode();
3274 InitReg(MISCREG_DL1DATA2
)
3276 .allPrivileges().exceptUserMode();
3277 InitReg(MISCREG_DL1DATA3
)
3279 .allPrivileges().exceptUserMode();
3280 InitReg(MISCREG_DL1DATA4
)
3282 .allPrivileges().exceptUserMode();
3283 InitReg(MISCREG_RAMINDEX
)
3285 .writes(1).exceptUserMode();
3286 InitReg(MISCREG_L2ACTLR
)
3288 .allPrivileges().exceptUserMode();
3289 InitReg(MISCREG_CBAR
)
3291 .allPrivileges().exceptUserMode().writes(0);
3292 InitReg(MISCREG_HTTBR
)
3293 .hyp().monNonSecure();
3294 InitReg(MISCREG_VTTBR
)
3295 .hyp().monNonSecure();
3296 InitReg(MISCREG_CNTPCT
)
3298 InitReg(MISCREG_CNTVCT
)
3301 InitReg(MISCREG_CNTP_CVAL
)
3303 InitReg(MISCREG_CNTP_CVAL_NS
)
3306 .privSecure(!aarch32EL3
)
3308 InitReg(MISCREG_CNTP_CVAL_S
)
3311 InitReg(MISCREG_CNTV_CVAL
)
3313 InitReg(MISCREG_CNTVOFF
)
3314 .hyp().monNonSecure();
3315 InitReg(MISCREG_CNTHP_CVAL
)
3316 .hypWrite().monNonSecureRead();
3317 InitReg(MISCREG_CPUMERRSR
)
3319 .allPrivileges().exceptUserMode();
3320 InitReg(MISCREG_L2MERRSR
)
3323 .allPrivileges().exceptUserMode();
3325 // AArch64 registers (Op0=2);
3326 InitReg(MISCREG_MDCCINT_EL1
)
3328 InitReg(MISCREG_OSDTRRX_EL1
)
3330 .mapsTo(MISCREG_DBGDTRRXext
);
3331 InitReg(MISCREG_MDSCR_EL1
)
3333 .mapsTo(MISCREG_DBGDSCRext
);
3334 InitReg(MISCREG_OSDTRTX_EL1
)
3336 .mapsTo(MISCREG_DBGDTRTXext
);
3337 InitReg(MISCREG_OSECCR_EL1
)
3339 .mapsTo(MISCREG_DBGOSECCR
);
3340 InitReg(MISCREG_DBGBVR0_EL1
)
3342 .mapsTo(MISCREG_DBGBVR0
/*, MISCREG_DBGBXVR0 */);
3343 InitReg(MISCREG_DBGBVR1_EL1
)
3345 .mapsTo(MISCREG_DBGBVR1
/*, MISCREG_DBGBXVR1 */);
3346 InitReg(MISCREG_DBGBVR2_EL1
)
3348 .mapsTo(MISCREG_DBGBVR2
/*, MISCREG_DBGBXVR2 */);
3349 InitReg(MISCREG_DBGBVR3_EL1
)
3351 .mapsTo(MISCREG_DBGBVR3
/*, MISCREG_DBGBXVR3 */);
3352 InitReg(MISCREG_DBGBVR4_EL1
)
3354 .mapsTo(MISCREG_DBGBVR4
/*, MISCREG_DBGBXVR4 */);
3355 InitReg(MISCREG_DBGBVR5_EL1
)
3357 .mapsTo(MISCREG_DBGBVR5
/*, MISCREG_DBGBXVR5 */);
3358 InitReg(MISCREG_DBGBCR0_EL1
)
3360 .mapsTo(MISCREG_DBGBCR0
);
3361 InitReg(MISCREG_DBGBCR1_EL1
)
3363 .mapsTo(MISCREG_DBGBCR1
);
3364 InitReg(MISCREG_DBGBCR2_EL1
)
3366 .mapsTo(MISCREG_DBGBCR2
);
3367 InitReg(MISCREG_DBGBCR3_EL1
)
3369 .mapsTo(MISCREG_DBGBCR3
);
3370 InitReg(MISCREG_DBGBCR4_EL1
)
3372 .mapsTo(MISCREG_DBGBCR4
);
3373 InitReg(MISCREG_DBGBCR5_EL1
)
3375 .mapsTo(MISCREG_DBGBCR5
);
3376 InitReg(MISCREG_DBGWVR0_EL1
)
3378 .mapsTo(MISCREG_DBGWVR0
);
3379 InitReg(MISCREG_DBGWVR1_EL1
)
3381 .mapsTo(MISCREG_DBGWVR1
);
3382 InitReg(MISCREG_DBGWVR2_EL1
)
3384 .mapsTo(MISCREG_DBGWVR2
);
3385 InitReg(MISCREG_DBGWVR3_EL1
)
3387 .mapsTo(MISCREG_DBGWVR3
);
3388 InitReg(MISCREG_DBGWCR0_EL1
)
3390 .mapsTo(MISCREG_DBGWCR0
);
3391 InitReg(MISCREG_DBGWCR1_EL1
)
3393 .mapsTo(MISCREG_DBGWCR1
);
3394 InitReg(MISCREG_DBGWCR2_EL1
)
3396 .mapsTo(MISCREG_DBGWCR2
);
3397 InitReg(MISCREG_DBGWCR3_EL1
)
3399 .mapsTo(MISCREG_DBGWCR3
);
3400 InitReg(MISCREG_MDCCSR_EL0
)
3401 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3402 .mapsTo(MISCREG_DBGDSCRint
);
3403 InitReg(MISCREG_MDDTR_EL0
)
3405 InitReg(MISCREG_MDDTRTX_EL0
)
3407 InitReg(MISCREG_MDDTRRX_EL0
)
3409 InitReg(MISCREG_DBGVCR32_EL2
)
3411 .mapsTo(MISCREG_DBGVCR
);
3412 InitReg(MISCREG_MDRAR_EL1
)
3413 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3414 .mapsTo(MISCREG_DBGDRAR
);
3415 InitReg(MISCREG_OSLAR_EL1
)
3416 .allPrivileges().monSecureRead(0).monNonSecureRead(0)
3417 .mapsTo(MISCREG_DBGOSLAR
);
3418 InitReg(MISCREG_OSLSR_EL1
)
3419 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3420 .mapsTo(MISCREG_DBGOSLSR
);
3421 InitReg(MISCREG_OSDLR_EL1
)
3423 .mapsTo(MISCREG_DBGOSDLR
);
3424 InitReg(MISCREG_DBGPRCR_EL1
)
3426 .mapsTo(MISCREG_DBGPRCR
);
3427 InitReg(MISCREG_DBGCLAIMSET_EL1
)
3429 .mapsTo(MISCREG_DBGCLAIMSET
);
3430 InitReg(MISCREG_DBGCLAIMCLR_EL1
)
3432 .mapsTo(MISCREG_DBGCLAIMCLR
);
3433 InitReg(MISCREG_DBGAUTHSTATUS_EL1
)
3434 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3435 .mapsTo(MISCREG_DBGAUTHSTATUS
);
3436 InitReg(MISCREG_TEECR32_EL1
);
3437 InitReg(MISCREG_TEEHBR32_EL1
);
3439 // AArch64 registers (Op0=1,3);
3440 InitReg(MISCREG_MIDR_EL1
)
3441 .allPrivileges().exceptUserMode().writes(0);
3442 InitReg(MISCREG_MPIDR_EL1
)
3443 .allPrivileges().exceptUserMode().writes(0);
3444 InitReg(MISCREG_REVIDR_EL1
)
3445 .allPrivileges().exceptUserMode().writes(0);
3446 InitReg(MISCREG_ID_PFR0_EL1
)
3447 .allPrivileges().exceptUserMode().writes(0)
3448 .mapsTo(MISCREG_ID_PFR0
);
3449 InitReg(MISCREG_ID_PFR1_EL1
)
3450 .allPrivileges().exceptUserMode().writes(0)
3451 .mapsTo(MISCREG_ID_PFR1
);
3452 InitReg(MISCREG_ID_DFR0_EL1
)
3453 .allPrivileges().exceptUserMode().writes(0)
3454 .mapsTo(MISCREG_ID_DFR0
);
3455 InitReg(MISCREG_ID_AFR0_EL1
)
3456 .allPrivileges().exceptUserMode().writes(0)
3457 .mapsTo(MISCREG_ID_AFR0
);
3458 InitReg(MISCREG_ID_MMFR0_EL1
)
3459 .allPrivileges().exceptUserMode().writes(0)
3460 .mapsTo(MISCREG_ID_MMFR0
);
3461 InitReg(MISCREG_ID_MMFR1_EL1
)
3462 .allPrivileges().exceptUserMode().writes(0)
3463 .mapsTo(MISCREG_ID_MMFR1
);
3464 InitReg(MISCREG_ID_MMFR2_EL1
)
3465 .allPrivileges().exceptUserMode().writes(0)
3466 .mapsTo(MISCREG_ID_MMFR2
);
3467 InitReg(MISCREG_ID_MMFR3_EL1
)
3468 .allPrivileges().exceptUserMode().writes(0)
3469 .mapsTo(MISCREG_ID_MMFR3
);
3470 InitReg(MISCREG_ID_ISAR0_EL1
)
3471 .allPrivileges().exceptUserMode().writes(0)
3472 .mapsTo(MISCREG_ID_ISAR0
);
3473 InitReg(MISCREG_ID_ISAR1_EL1
)
3474 .allPrivileges().exceptUserMode().writes(0)
3475 .mapsTo(MISCREG_ID_ISAR1
);
3476 InitReg(MISCREG_ID_ISAR2_EL1
)
3477 .allPrivileges().exceptUserMode().writes(0)
3478 .mapsTo(MISCREG_ID_ISAR2
);
3479 InitReg(MISCREG_ID_ISAR3_EL1
)
3480 .allPrivileges().exceptUserMode().writes(0)
3481 .mapsTo(MISCREG_ID_ISAR3
);
3482 InitReg(MISCREG_ID_ISAR4_EL1
)
3483 .allPrivileges().exceptUserMode().writes(0)
3484 .mapsTo(MISCREG_ID_ISAR4
);
3485 InitReg(MISCREG_ID_ISAR5_EL1
)
3486 .allPrivileges().exceptUserMode().writes(0)
3487 .mapsTo(MISCREG_ID_ISAR5
);
3488 InitReg(MISCREG_MVFR0_EL1
)
3489 .allPrivileges().exceptUserMode().writes(0);
3490 InitReg(MISCREG_MVFR1_EL1
)
3491 .allPrivileges().exceptUserMode().writes(0);
3492 InitReg(MISCREG_MVFR2_EL1
)
3493 .allPrivileges().exceptUserMode().writes(0);
3494 InitReg(MISCREG_ID_AA64PFR0_EL1
)
3495 .allPrivileges().exceptUserMode().writes(0);
3496 InitReg(MISCREG_ID_AA64PFR1_EL1
)
3497 .allPrivileges().exceptUserMode().writes(0);
3498 InitReg(MISCREG_ID_AA64DFR0_EL1
)
3499 .allPrivileges().exceptUserMode().writes(0);
3500 InitReg(MISCREG_ID_AA64DFR1_EL1
)
3501 .allPrivileges().exceptUserMode().writes(0);
3502 InitReg(MISCREG_ID_AA64AFR0_EL1
)
3503 .allPrivileges().exceptUserMode().writes(0);
3504 InitReg(MISCREG_ID_AA64AFR1_EL1
)
3505 .allPrivileges().exceptUserMode().writes(0);
3506 InitReg(MISCREG_ID_AA64ISAR0_EL1
)
3507 .allPrivileges().exceptUserMode().writes(0);
3508 InitReg(MISCREG_ID_AA64ISAR1_EL1
)
3509 .allPrivileges().exceptUserMode().writes(0);
3510 InitReg(MISCREG_ID_AA64MMFR0_EL1
)
3511 .allPrivileges().exceptUserMode().writes(0);
3512 InitReg(MISCREG_ID_AA64MMFR1_EL1
)
3513 .allPrivileges().exceptUserMode().writes(0);
3514 InitReg(MISCREG_ID_AA64MMFR2_EL1
)
3515 .allPrivileges().exceptUserMode().writes(0);
3516 InitReg(MISCREG_CCSIDR_EL1
)
3517 .allPrivileges().exceptUserMode().writes(0);
3518 InitReg(MISCREG_CLIDR_EL1
)
3519 .allPrivileges().exceptUserMode().writes(0);
3520 InitReg(MISCREG_AIDR_EL1
)
3521 .allPrivileges().exceptUserMode().writes(0);
3522 InitReg(MISCREG_CSSELR_EL1
)
3523 .allPrivileges().exceptUserMode()
3524 .mapsTo(MISCREG_CSSELR_NS
);
3525 InitReg(MISCREG_CTR_EL0
)
3527 InitReg(MISCREG_DCZID_EL0
)
3529 InitReg(MISCREG_VPIDR_EL2
)
3531 .mapsTo(MISCREG_VPIDR
);
3532 InitReg(MISCREG_VMPIDR_EL2
)
3534 .mapsTo(MISCREG_VMPIDR
);
3535 InitReg(MISCREG_SCTLR_EL1
)
3536 .allPrivileges().exceptUserMode()
3537 .mapsTo(MISCREG_SCTLR_NS
);
3538 InitReg(MISCREG_ACTLR_EL1
)
3539 .allPrivileges().exceptUserMode()
3540 .mapsTo(MISCREG_ACTLR_NS
);
3541 InitReg(MISCREG_CPACR_EL1
)
3542 .allPrivileges().exceptUserMode()
3543 .mapsTo(MISCREG_CPACR
);
3544 InitReg(MISCREG_SCTLR_EL2
)
3546 .mapsTo(MISCREG_HSCTLR
);
3547 InitReg(MISCREG_ACTLR_EL2
)
3549 .mapsTo(MISCREG_HACTLR
);
3550 InitReg(MISCREG_HCR_EL2
)
3552 .mapsTo(MISCREG_HCR
/*, MISCREG_HCR2*/);
3553 InitReg(MISCREG_MDCR_EL2
)
3555 .mapsTo(MISCREG_HDCR
);
3556 InitReg(MISCREG_CPTR_EL2
)
3558 .mapsTo(MISCREG_HCPTR
);
3559 InitReg(MISCREG_HSTR_EL2
)
3561 .mapsTo(MISCREG_HSTR
);
3562 InitReg(MISCREG_HACR_EL2
)
3564 .mapsTo(MISCREG_HACR
);
3565 InitReg(MISCREG_SCTLR_EL3
)
3567 InitReg(MISCREG_ACTLR_EL3
)
3569 InitReg(MISCREG_SCR_EL3
)
3571 .mapsTo(MISCREG_SCR
); // NAM D7-2005
3572 InitReg(MISCREG_SDER32_EL3
)
3574 .mapsTo(MISCREG_SDER
);
3575 InitReg(MISCREG_CPTR_EL3
)
3577 InitReg(MISCREG_MDCR_EL3
)
3579 InitReg(MISCREG_TTBR0_EL1
)
3580 .allPrivileges().exceptUserMode()
3581 .mapsTo(MISCREG_TTBR0_NS
);
3582 InitReg(MISCREG_TTBR1_EL1
)
3583 .allPrivileges().exceptUserMode()
3584 .mapsTo(MISCREG_TTBR1_NS
);
3585 InitReg(MISCREG_TCR_EL1
)
3586 .allPrivileges().exceptUserMode()
3587 .mapsTo(MISCREG_TTBCR_NS
);
3588 InitReg(MISCREG_TTBR0_EL2
)
3590 .mapsTo(MISCREG_HTTBR
);
3591 InitReg(MISCREG_TTBR1_EL2
)
3593 InitReg(MISCREG_TCR_EL2
)
3595 .mapsTo(MISCREG_HTCR
);
3596 InitReg(MISCREG_VTTBR_EL2
)
3598 .mapsTo(MISCREG_VTTBR
);
3599 InitReg(MISCREG_VTCR_EL2
)
3601 .mapsTo(MISCREG_VTCR
);
3602 InitReg(MISCREG_TTBR0_EL3
)
3604 InitReg(MISCREG_TCR_EL3
)
3606 InitReg(MISCREG_DACR32_EL2
)
3608 .mapsTo(MISCREG_DACR_NS
);
3609 InitReg(MISCREG_SPSR_EL1
)
3610 .allPrivileges().exceptUserMode()
3611 .mapsTo(MISCREG_SPSR_SVC
); // NAM C5.2.17 SPSR_EL1
3612 InitReg(MISCREG_ELR_EL1
)
3613 .allPrivileges().exceptUserMode();
3614 InitReg(MISCREG_SP_EL0
)
3615 .allPrivileges().exceptUserMode();
3616 InitReg(MISCREG_SPSEL
)
3617 .allPrivileges().exceptUserMode();
3618 InitReg(MISCREG_CURRENTEL
)
3619 .allPrivileges().exceptUserMode().writes(0);
3620 InitReg(MISCREG_NZCV
)
3622 InitReg(MISCREG_DAIF
)
3624 InitReg(MISCREG_FPCR
)
3626 InitReg(MISCREG_FPSR
)
3628 InitReg(MISCREG_DSPSR_EL0
)
3630 InitReg(MISCREG_DLR_EL0
)
3632 InitReg(MISCREG_SPSR_EL2
)
3634 .mapsTo(MISCREG_SPSR_HYP
); // NAM C5.2.18 SPSR_EL2
3635 InitReg(MISCREG_ELR_EL2
)
3637 InitReg(MISCREG_SP_EL1
)
3639 InitReg(MISCREG_SPSR_IRQ_AA64
)
3641 InitReg(MISCREG_SPSR_ABT_AA64
)
3643 InitReg(MISCREG_SPSR_UND_AA64
)
3645 InitReg(MISCREG_SPSR_FIQ_AA64
)
3647 InitReg(MISCREG_SPSR_EL3
)
3649 .mapsTo(MISCREG_SPSR_MON
); // NAM C5.2.19 SPSR_EL3
3650 InitReg(MISCREG_ELR_EL3
)
3652 InitReg(MISCREG_SP_EL2
)
3654 InitReg(MISCREG_AFSR0_EL1
)
3655 .allPrivileges().exceptUserMode()
3656 .mapsTo(MISCREG_ADFSR_NS
);
3657 InitReg(MISCREG_AFSR1_EL1
)
3658 .allPrivileges().exceptUserMode()
3659 .mapsTo(MISCREG_AIFSR_NS
);
3660 InitReg(MISCREG_ESR_EL1
)
3661 .allPrivileges().exceptUserMode();
3662 InitReg(MISCREG_IFSR32_EL2
)
3664 .mapsTo(MISCREG_IFSR_NS
);
3665 InitReg(MISCREG_AFSR0_EL2
)
3667 .mapsTo(MISCREG_HADFSR
);
3668 InitReg(MISCREG_AFSR1_EL2
)
3670 .mapsTo(MISCREG_HAIFSR
);
3671 InitReg(MISCREG_ESR_EL2
)
3673 .mapsTo(MISCREG_HSR
);
3674 InitReg(MISCREG_FPEXC32_EL2
)
3675 .hyp().mon().mapsTo(MISCREG_FPEXC
);
3676 InitReg(MISCREG_AFSR0_EL3
)
3678 InitReg(MISCREG_AFSR1_EL3
)
3680 InitReg(MISCREG_ESR_EL3
)
3682 InitReg(MISCREG_FAR_EL1
)
3683 .allPrivileges().exceptUserMode()
3684 .mapsTo(MISCREG_DFAR_NS
, MISCREG_IFAR_NS
);
3685 InitReg(MISCREG_FAR_EL2
)
3687 .mapsTo(MISCREG_HDFAR
, MISCREG_HIFAR
);
3688 InitReg(MISCREG_HPFAR_EL2
)
3690 .mapsTo(MISCREG_HPFAR
);
3691 InitReg(MISCREG_FAR_EL3
)
3693 InitReg(MISCREG_IC_IALLUIS
)
3695 .writes(1).exceptUserMode();
3696 InitReg(MISCREG_PAR_EL1
)
3697 .allPrivileges().exceptUserMode()
3698 .mapsTo(MISCREG_PAR_NS
);
3699 InitReg(MISCREG_IC_IALLU
)
3701 .writes(1).exceptUserMode();
3702 InitReg(MISCREG_DC_IVAC_Xt
)
3704 .writes(1).exceptUserMode();
3705 InitReg(MISCREG_DC_ISW_Xt
)
3707 .writes(1).exceptUserMode();
3708 InitReg(MISCREG_AT_S1E1R_Xt
)
3709 .writes(1).exceptUserMode();
3710 InitReg(MISCREG_AT_S1E1W_Xt
)
3711 .writes(1).exceptUserMode();
3712 InitReg(MISCREG_AT_S1E0R_Xt
)
3713 .writes(1).exceptUserMode();
3714 InitReg(MISCREG_AT_S1E0W_Xt
)
3715 .writes(1).exceptUserMode();
3716 InitReg(MISCREG_DC_CSW_Xt
)
3718 .writes(1).exceptUserMode();
3719 InitReg(MISCREG_DC_CISW_Xt
)
3721 .writes(1).exceptUserMode();
3722 InitReg(MISCREG_DC_ZVA_Xt
)
3724 .writes(1).userSecureWrite(0);
3725 InitReg(MISCREG_IC_IVAU_Xt
)
3727 InitReg(MISCREG_DC_CVAC_Xt
)
3730 InitReg(MISCREG_DC_CVAU_Xt
)
3733 InitReg(MISCREG_DC_CIVAC_Xt
)
3736 InitReg(MISCREG_AT_S1E2R_Xt
)
3737 .monNonSecureWrite().hypWrite();
3738 InitReg(MISCREG_AT_S1E2W_Xt
)
3739 .monNonSecureWrite().hypWrite();
3740 InitReg(MISCREG_AT_S12E1R_Xt
)
3741 .hypWrite().monSecureWrite().monNonSecureWrite();
3742 InitReg(MISCREG_AT_S12E1W_Xt
)
3743 .hypWrite().monSecureWrite().monNonSecureWrite();
3744 InitReg(MISCREG_AT_S12E0R_Xt
)
3745 .hypWrite().monSecureWrite().monNonSecureWrite();
3746 InitReg(MISCREG_AT_S12E0W_Xt
)
3747 .hypWrite().monSecureWrite().monNonSecureWrite();
3748 InitReg(MISCREG_AT_S1E3R_Xt
)
3749 .monSecureWrite().monNonSecureWrite();
3750 InitReg(MISCREG_AT_S1E3W_Xt
)
3751 .monSecureWrite().monNonSecureWrite();
3752 InitReg(MISCREG_TLBI_VMALLE1IS
)
3753 .writes(1).exceptUserMode();
3754 InitReg(MISCREG_TLBI_VAE1IS_Xt
)
3755 .writes(1).exceptUserMode();
3756 InitReg(MISCREG_TLBI_ASIDE1IS_Xt
)
3757 .writes(1).exceptUserMode();
3758 InitReg(MISCREG_TLBI_VAAE1IS_Xt
)
3759 .writes(1).exceptUserMode();
3760 InitReg(MISCREG_TLBI_VALE1IS_Xt
)
3761 .writes(1).exceptUserMode();
3762 InitReg(MISCREG_TLBI_VAALE1IS_Xt
)
3763 .writes(1).exceptUserMode();
3764 InitReg(MISCREG_TLBI_VMALLE1
)
3765 .writes(1).exceptUserMode();
3766 InitReg(MISCREG_TLBI_VAE1_Xt
)
3767 .writes(1).exceptUserMode();
3768 InitReg(MISCREG_TLBI_ASIDE1_Xt
)
3769 .writes(1).exceptUserMode();
3770 InitReg(MISCREG_TLBI_VAAE1_Xt
)
3771 .writes(1).exceptUserMode();
3772 InitReg(MISCREG_TLBI_VALE1_Xt
)
3773 .writes(1).exceptUserMode();
3774 InitReg(MISCREG_TLBI_VAALE1_Xt
)
3775 .writes(1).exceptUserMode();
3776 InitReg(MISCREG_TLBI_IPAS2E1IS_Xt
)
3777 .hypWrite().monSecureWrite().monNonSecureWrite();
3778 InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt
)
3779 .hypWrite().monSecureWrite().monNonSecureWrite();
3780 InitReg(MISCREG_TLBI_ALLE2IS
)
3781 .monNonSecureWrite().hypWrite();
3782 InitReg(MISCREG_TLBI_VAE2IS_Xt
)
3783 .monNonSecureWrite().hypWrite();
3784 InitReg(MISCREG_TLBI_ALLE1IS
)
3785 .hypWrite().monSecureWrite().monNonSecureWrite();
3786 InitReg(MISCREG_TLBI_VALE2IS_Xt
)
3787 .monNonSecureWrite().hypWrite();
3788 InitReg(MISCREG_TLBI_VMALLS12E1IS
)
3789 .hypWrite().monSecureWrite().monNonSecureWrite();
3790 InitReg(MISCREG_TLBI_IPAS2E1_Xt
)
3791 .hypWrite().monSecureWrite().monNonSecureWrite();
3792 InitReg(MISCREG_TLBI_IPAS2LE1_Xt
)
3793 .hypWrite().monSecureWrite().monNonSecureWrite();
3794 InitReg(MISCREG_TLBI_ALLE2
)
3795 .monNonSecureWrite().hypWrite();
3796 InitReg(MISCREG_TLBI_VAE2_Xt
)
3797 .monNonSecureWrite().hypWrite();
3798 InitReg(MISCREG_TLBI_ALLE1
)
3799 .hypWrite().monSecureWrite().monNonSecureWrite();
3800 InitReg(MISCREG_TLBI_VALE2_Xt
)
3801 .monNonSecureWrite().hypWrite();
3802 InitReg(MISCREG_TLBI_VMALLS12E1
)
3803 .hypWrite().monSecureWrite().monNonSecureWrite();
3804 InitReg(MISCREG_TLBI_ALLE3IS
)
3805 .monSecureWrite().monNonSecureWrite();
3806 InitReg(MISCREG_TLBI_VAE3IS_Xt
)
3807 .monSecureWrite().monNonSecureWrite();
3808 InitReg(MISCREG_TLBI_VALE3IS_Xt
)
3809 .monSecureWrite().monNonSecureWrite();
3810 InitReg(MISCREG_TLBI_ALLE3
)
3811 .monSecureWrite().monNonSecureWrite();
3812 InitReg(MISCREG_TLBI_VAE3_Xt
)
3813 .monSecureWrite().monNonSecureWrite();
3814 InitReg(MISCREG_TLBI_VALE3_Xt
)
3815 .monSecureWrite().monNonSecureWrite();
3816 InitReg(MISCREG_PMINTENSET_EL1
)
3817 .allPrivileges().exceptUserMode()
3818 .mapsTo(MISCREG_PMINTENSET
);
3819 InitReg(MISCREG_PMINTENCLR_EL1
)
3820 .allPrivileges().exceptUserMode()
3821 .mapsTo(MISCREG_PMINTENCLR
);
3822 InitReg(MISCREG_PMCR_EL0
)
3824 .mapsTo(MISCREG_PMCR
);
3825 InitReg(MISCREG_PMCNTENSET_EL0
)
3827 .mapsTo(MISCREG_PMCNTENSET
);
3828 InitReg(MISCREG_PMCNTENCLR_EL0
)
3830 .mapsTo(MISCREG_PMCNTENCLR
);
3831 InitReg(MISCREG_PMOVSCLR_EL0
)
3833 // .mapsTo(MISCREG_PMOVSCLR);
3834 InitReg(MISCREG_PMSWINC_EL0
)
3836 .mapsTo(MISCREG_PMSWINC
);
3837 InitReg(MISCREG_PMSELR_EL0
)
3839 .mapsTo(MISCREG_PMSELR
);
3840 InitReg(MISCREG_PMCEID0_EL0
)
3842 .mapsTo(MISCREG_PMCEID0
);
3843 InitReg(MISCREG_PMCEID1_EL0
)
3845 .mapsTo(MISCREG_PMCEID1
);
3846 InitReg(MISCREG_PMCCNTR_EL0
)
3848 .mapsTo(MISCREG_PMCCNTR
);
3849 InitReg(MISCREG_PMXEVTYPER_EL0
)
3851 .mapsTo(MISCREG_PMXEVTYPER
);
3852 InitReg(MISCREG_PMCCFILTR_EL0
)
3854 InitReg(MISCREG_PMXEVCNTR_EL0
)
3856 .mapsTo(MISCREG_PMXEVCNTR
);
3857 InitReg(MISCREG_PMUSERENR_EL0
)
3858 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
3859 .mapsTo(MISCREG_PMUSERENR
);
3860 InitReg(MISCREG_PMOVSSET_EL0
)
3862 .mapsTo(MISCREG_PMOVSSET
);
3863 InitReg(MISCREG_MAIR_EL1
)
3864 .allPrivileges().exceptUserMode()
3865 .mapsTo(MISCREG_PRRR_NS
, MISCREG_NMRR_NS
);
3866 InitReg(MISCREG_AMAIR_EL1
)
3867 .allPrivileges().exceptUserMode()
3868 .mapsTo(MISCREG_AMAIR0_NS
, MISCREG_AMAIR1_NS
);
3869 InitReg(MISCREG_MAIR_EL2
)
3871 .mapsTo(MISCREG_HMAIR0
, MISCREG_HMAIR1
);
3872 InitReg(MISCREG_AMAIR_EL2
)
3874 .mapsTo(MISCREG_HAMAIR0
, MISCREG_HAMAIR1
);
3875 InitReg(MISCREG_MAIR_EL3
)
3877 InitReg(MISCREG_AMAIR_EL3
)
3879 InitReg(MISCREG_L2CTLR_EL1
)
3880 .allPrivileges().exceptUserMode();
3881 InitReg(MISCREG_L2ECTLR_EL1
)
3882 .allPrivileges().exceptUserMode();
3883 InitReg(MISCREG_VBAR_EL1
)
3884 .allPrivileges().exceptUserMode()
3885 .mapsTo(MISCREG_VBAR_NS
);
3886 InitReg(MISCREG_RVBAR_EL1
)
3887 .allPrivileges().exceptUserMode().writes(0);
3888 InitReg(MISCREG_ISR_EL1
)
3889 .allPrivileges().exceptUserMode().writes(0);
3890 InitReg(MISCREG_VBAR_EL2
)
3892 .mapsTo(MISCREG_HVBAR
);
3893 InitReg(MISCREG_RVBAR_EL2
)
3894 .mon().hyp().writes(0);
3895 InitReg(MISCREG_VBAR_EL3
)
3897 InitReg(MISCREG_RVBAR_EL3
)
3899 InitReg(MISCREG_RMR_EL3
)
3901 InitReg(MISCREG_CONTEXTIDR_EL1
)
3902 .allPrivileges().exceptUserMode()
3903 .mapsTo(MISCREG_CONTEXTIDR_NS
);
3904 InitReg(MISCREG_TPIDR_EL1
)
3905 .allPrivileges().exceptUserMode()
3906 .mapsTo(MISCREG_TPIDRPRW_NS
);
3907 InitReg(MISCREG_TPIDR_EL0
)
3909 .mapsTo(MISCREG_TPIDRURW_NS
);
3910 InitReg(MISCREG_TPIDRRO_EL0
)
3911 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
3912 .mapsTo(MISCREG_TPIDRURO_NS
);
3913 InitReg(MISCREG_TPIDR_EL2
)
3915 .mapsTo(MISCREG_HTPIDR
);
3916 InitReg(MISCREG_TPIDR_EL3
)
3918 InitReg(MISCREG_CNTKCTL_EL1
)
3919 .allPrivileges().exceptUserMode()
3920 .mapsTo(MISCREG_CNTKCTL
);
3921 InitReg(MISCREG_CNTFRQ_EL0
)
3923 .mapsTo(MISCREG_CNTFRQ
);
3924 InitReg(MISCREG_CNTPCT_EL0
)
3926 .mapsTo(MISCREG_CNTPCT
); /* 64b */
3927 InitReg(MISCREG_CNTVCT_EL0
)
3930 .mapsTo(MISCREG_CNTVCT
); /* 64b */
3931 InitReg(MISCREG_CNTP_TVAL_EL0
)
3933 .mapsTo(MISCREG_CNTP_TVAL_NS
);
3934 InitReg(MISCREG_CNTP_CTL_EL0
)
3936 .mapsTo(MISCREG_CNTP_CTL_NS
);
3937 InitReg(MISCREG_CNTP_CVAL_EL0
)
3939 .mapsTo(MISCREG_CNTP_CVAL_NS
); /* 64b */
3940 InitReg(MISCREG_CNTV_TVAL_EL0
)
3942 .mapsTo(MISCREG_CNTV_TVAL
);
3943 InitReg(MISCREG_CNTV_CTL_EL0
)
3945 .mapsTo(MISCREG_CNTV_CTL
);
3946 InitReg(MISCREG_CNTV_CVAL_EL0
)
3948 .mapsTo(MISCREG_CNTV_CVAL
); /* 64b */
3949 InitReg(MISCREG_PMEVCNTR0_EL0
)
3951 // .mapsTo(MISCREG_PMEVCNTR0);
3952 InitReg(MISCREG_PMEVCNTR1_EL0
)
3954 // .mapsTo(MISCREG_PMEVCNTR1);
3955 InitReg(MISCREG_PMEVCNTR2_EL0
)
3957 // .mapsTo(MISCREG_PMEVCNTR2);
3958 InitReg(MISCREG_PMEVCNTR3_EL0
)
3960 // .mapsTo(MISCREG_PMEVCNTR3);
3961 InitReg(MISCREG_PMEVCNTR4_EL0
)
3963 // .mapsTo(MISCREG_PMEVCNTR4);
3964 InitReg(MISCREG_PMEVCNTR5_EL0
)
3966 // .mapsTo(MISCREG_PMEVCNTR5);
3967 InitReg(MISCREG_PMEVTYPER0_EL0
)
3969 // .mapsTo(MISCREG_PMEVTYPER0);
3970 InitReg(MISCREG_PMEVTYPER1_EL0
)
3972 // .mapsTo(MISCREG_PMEVTYPER1);
3973 InitReg(MISCREG_PMEVTYPER2_EL0
)
3975 // .mapsTo(MISCREG_PMEVTYPER2);
3976 InitReg(MISCREG_PMEVTYPER3_EL0
)
3978 // .mapsTo(MISCREG_PMEVTYPER3);
3979 InitReg(MISCREG_PMEVTYPER4_EL0
)
3981 // .mapsTo(MISCREG_PMEVTYPER4);
3982 InitReg(MISCREG_PMEVTYPER5_EL0
)
3984 // .mapsTo(MISCREG_PMEVTYPER5);
3985 InitReg(MISCREG_CNTVOFF_EL2
)
3987 .mapsTo(MISCREG_CNTVOFF
); /* 64b */
3988 InitReg(MISCREG_CNTHCTL_EL2
)
3990 .mapsTo(MISCREG_CNTHCTL
);
3991 InitReg(MISCREG_CNTHP_TVAL_EL2
)
3993 .mapsTo(MISCREG_CNTHP_TVAL
);
3994 InitReg(MISCREG_CNTHP_CTL_EL2
)
3996 .mapsTo(MISCREG_CNTHP_CTL
);
3997 InitReg(MISCREG_CNTHP_CVAL_EL2
)
3999 .mapsTo(MISCREG_CNTHP_CVAL
); /* 64b */
4000 InitReg(MISCREG_CNTPS_TVAL_EL1
)
4001 .mon().privSecure();
4002 InitReg(MISCREG_CNTPS_CTL_EL1
)
4003 .mon().privSecure();
4004 InitReg(MISCREG_CNTPS_CVAL_EL1
)
4005 .mon().privSecure();
4006 InitReg(MISCREG_IL1DATA0_EL1
)
4007 .allPrivileges().exceptUserMode();
4008 InitReg(MISCREG_IL1DATA1_EL1
)
4009 .allPrivileges().exceptUserMode();
4010 InitReg(MISCREG_IL1DATA2_EL1
)
4011 .allPrivileges().exceptUserMode();
4012 InitReg(MISCREG_IL1DATA3_EL1
)
4013 .allPrivileges().exceptUserMode();
4014 InitReg(MISCREG_DL1DATA0_EL1
)
4015 .allPrivileges().exceptUserMode();
4016 InitReg(MISCREG_DL1DATA1_EL1
)
4017 .allPrivileges().exceptUserMode();
4018 InitReg(MISCREG_DL1DATA2_EL1
)
4019 .allPrivileges().exceptUserMode();
4020 InitReg(MISCREG_DL1DATA3_EL1
)
4021 .allPrivileges().exceptUserMode();
4022 InitReg(MISCREG_DL1DATA4_EL1
)
4023 .allPrivileges().exceptUserMode();
4024 InitReg(MISCREG_L2ACTLR_EL1
)
4025 .allPrivileges().exceptUserMode();
4026 InitReg(MISCREG_CPUACTLR_EL1
)
4027 .allPrivileges().exceptUserMode();
4028 InitReg(MISCREG_CPUECTLR_EL1
)
4029 .allPrivileges().exceptUserMode();
4030 InitReg(MISCREG_CPUMERRSR_EL1
)
4031 .allPrivileges().exceptUserMode();
4032 InitReg(MISCREG_L2MERRSR_EL1
)
4035 .allPrivileges().exceptUserMode();
4036 InitReg(MISCREG_CBAR_EL1
)
4037 .allPrivileges().exceptUserMode().writes(0);
4038 InitReg(MISCREG_CONTEXTIDR_EL2
)
4040 InitReg(MISCREG_CNTHV_CTL_EL2
)
4042 InitReg(MISCREG_CNTHV_CVAL_EL2
)
4044 InitReg(MISCREG_CNTHV_TVAL_EL2
)
4048 InitReg(MISCREG_NOP
)
4050 InitReg(MISCREG_RAZ
)
4051 .allPrivileges().exceptUserMode().writes(0);
4052 InitReg(MISCREG_CP14_UNIMPL
)
4055 InitReg(MISCREG_CP15_UNIMPL
)
4058 InitReg(MISCREG_UNKNOWN
);
4059 InitReg(MISCREG_IMPDEF_UNIMPL
)
4061 .warnNotFail(impdefAsNop
);
4063 // RAS extension (unimplemented)
4064 InitReg(MISCREG_ERRIDR_EL1
)
4067 InitReg(MISCREG_ERRSELR_EL1
)
4070 InitReg(MISCREG_ERXFR_EL1
)
4073 InitReg(MISCREG_ERXCTLR_EL1
)
4076 InitReg(MISCREG_ERXSTATUS_EL1
)
4079 InitReg(MISCREG_ERXADDR_EL1
)
4082 InitReg(MISCREG_ERXMISC0_EL1
)
4085 InitReg(MISCREG_ERXMISC1_EL1
)
4088 InitReg(MISCREG_DISR_EL1
)
4091 InitReg(MISCREG_VSESR_EL2
)
4094 InitReg(MISCREG_VDISR_EL2
)
4098 // Register mappings for some unimplemented registers:
4102 // DBGDTR_EL0 -> DBGDTR{R or T}Xint
4103 // DBGDTRRX_EL0 -> DBGDTRRXint
4104 // DBGDTRTX_EL0 -> DBGDTRRXint
4105 // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
4110 } // namespace ArmISA