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arch-arm: Introduce ARMv8.1 Virtual Timer System Registers
[gem5.git] / src / arch / arm / miscregs.cc
1 /*
2 * Copyright (c) 2010-2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 * Giacomo Gabrielli
40 */
41
42 #include "arch/arm/miscregs.hh"
43
44 #include <tuple>
45
46 #include "arch/arm/isa.hh"
47 #include "base/logging.hh"
48 #include "cpu/thread_context.hh"
49 #include "sim/full_system.hh"
50
51 namespace ArmISA
52 {
53
54 MiscRegIndex
55 decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
56 {
57 switch(crn) {
58 case 0:
59 switch (opc1) {
60 case 0:
61 switch (opc2) {
62 case 0:
63 switch (crm) {
64 case 0:
65 return MISCREG_DBGDIDR;
66 case 1:
67 return MISCREG_DBGDSCRint;
68 }
69 break;
70 }
71 break;
72 case 7:
73 switch (opc2) {
74 case 0:
75 switch (crm) {
76 case 0:
77 return MISCREG_JIDR;
78 }
79 break;
80 }
81 break;
82 }
83 break;
84 case 1:
85 switch (opc1) {
86 case 6:
87 switch (crm) {
88 case 0:
89 switch (opc2) {
90 case 0:
91 return MISCREG_TEEHBR;
92 }
93 break;
94 }
95 break;
96 case 7:
97 switch (crm) {
98 case 0:
99 switch (opc2) {
100 case 0:
101 return MISCREG_JOSCR;
102 }
103 break;
104 }
105 break;
106 }
107 break;
108 case 2:
109 switch (opc1) {
110 case 7:
111 switch (crm) {
112 case 0:
113 switch (opc2) {
114 case 0:
115 return MISCREG_JMCR;
116 }
117 break;
118 }
119 break;
120 }
121 break;
122 }
123 // If we get here then it must be a register that we haven't implemented
124 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
125 crn, opc1, crm, opc2);
126 return MISCREG_CP14_UNIMPL;
127 }
128
129 using namespace std;
130
131 MiscRegIndex
132 decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
133 {
134 switch (crn) {
135 case 0:
136 switch (opc1) {
137 case 0:
138 switch (crm) {
139 case 0:
140 switch (opc2) {
141 case 1:
142 return MISCREG_CTR;
143 case 2:
144 return MISCREG_TCMTR;
145 case 3:
146 return MISCREG_TLBTR;
147 case 5:
148 return MISCREG_MPIDR;
149 case 6:
150 return MISCREG_REVIDR;
151 default:
152 return MISCREG_MIDR;
153 }
154 break;
155 case 1:
156 switch (opc2) {
157 case 0:
158 return MISCREG_ID_PFR0;
159 case 1:
160 return MISCREG_ID_PFR1;
161 case 2:
162 return MISCREG_ID_DFR0;
163 case 3:
164 return MISCREG_ID_AFR0;
165 case 4:
166 return MISCREG_ID_MMFR0;
167 case 5:
168 return MISCREG_ID_MMFR1;
169 case 6:
170 return MISCREG_ID_MMFR2;
171 case 7:
172 return MISCREG_ID_MMFR3;
173 }
174 break;
175 case 2:
176 switch (opc2) {
177 case 0:
178 return MISCREG_ID_ISAR0;
179 case 1:
180 return MISCREG_ID_ISAR1;
181 case 2:
182 return MISCREG_ID_ISAR2;
183 case 3:
184 return MISCREG_ID_ISAR3;
185 case 4:
186 return MISCREG_ID_ISAR4;
187 case 5:
188 return MISCREG_ID_ISAR5;
189 case 6:
190 case 7:
191 return MISCREG_RAZ; // read as zero
192 }
193 break;
194 default:
195 return MISCREG_RAZ; // read as zero
196 }
197 break;
198 case 1:
199 if (crm == 0) {
200 switch (opc2) {
201 case 0:
202 return MISCREG_CCSIDR;
203 case 1:
204 return MISCREG_CLIDR;
205 case 7:
206 return MISCREG_AIDR;
207 }
208 }
209 break;
210 case 2:
211 if (crm == 0 && opc2 == 0) {
212 return MISCREG_CSSELR;
213 }
214 break;
215 case 4:
216 if (crm == 0) {
217 if (opc2 == 0)
218 return MISCREG_VPIDR;
219 else if (opc2 == 5)
220 return MISCREG_VMPIDR;
221 }
222 break;
223 }
224 break;
225 case 1:
226 if (opc1 == 0) {
227 if (crm == 0) {
228 switch (opc2) {
229 case 0:
230 return MISCREG_SCTLR;
231 case 1:
232 return MISCREG_ACTLR;
233 case 0x2:
234 return MISCREG_CPACR;
235 }
236 } else if (crm == 1) {
237 switch (opc2) {
238 case 0:
239 return MISCREG_SCR;
240 case 1:
241 return MISCREG_SDER;
242 case 2:
243 return MISCREG_NSACR;
244 }
245 }
246 } else if (opc1 == 4) {
247 if (crm == 0) {
248 if (opc2 == 0)
249 return MISCREG_HSCTLR;
250 else if (opc2 == 1)
251 return MISCREG_HACTLR;
252 } else if (crm == 1) {
253 switch (opc2) {
254 case 0:
255 return MISCREG_HCR;
256 case 1:
257 return MISCREG_HDCR;
258 case 2:
259 return MISCREG_HCPTR;
260 case 3:
261 return MISCREG_HSTR;
262 case 7:
263 return MISCREG_HACR;
264 }
265 }
266 }
267 break;
268 case 2:
269 if (opc1 == 0 && crm == 0) {
270 switch (opc2) {
271 case 0:
272 return MISCREG_TTBR0;
273 case 1:
274 return MISCREG_TTBR1;
275 case 2:
276 return MISCREG_TTBCR;
277 }
278 } else if (opc1 == 4) {
279 if (crm == 0 && opc2 == 2)
280 return MISCREG_HTCR;
281 else if (crm == 1 && opc2 == 2)
282 return MISCREG_VTCR;
283 }
284 break;
285 case 3:
286 if (opc1 == 0 && crm == 0 && opc2 == 0) {
287 return MISCREG_DACR;
288 }
289 break;
290 case 5:
291 if (opc1 == 0) {
292 if (crm == 0) {
293 if (opc2 == 0) {
294 return MISCREG_DFSR;
295 } else if (opc2 == 1) {
296 return MISCREG_IFSR;
297 }
298 } else if (crm == 1) {
299 if (opc2 == 0) {
300 return MISCREG_ADFSR;
301 } else if (opc2 == 1) {
302 return MISCREG_AIFSR;
303 }
304 }
305 } else if (opc1 == 4) {
306 if (crm == 1) {
307 if (opc2 == 0)
308 return MISCREG_HADFSR;
309 else if (opc2 == 1)
310 return MISCREG_HAIFSR;
311 } else if (crm == 2 && opc2 == 0) {
312 return MISCREG_HSR;
313 }
314 }
315 break;
316 case 6:
317 if (opc1 == 0 && crm == 0) {
318 switch (opc2) {
319 case 0:
320 return MISCREG_DFAR;
321 case 2:
322 return MISCREG_IFAR;
323 }
324 } else if (opc1 == 4 && crm == 0) {
325 switch (opc2) {
326 case 0:
327 return MISCREG_HDFAR;
328 case 2:
329 return MISCREG_HIFAR;
330 case 4:
331 return MISCREG_HPFAR;
332 }
333 }
334 break;
335 case 7:
336 if (opc1 == 0) {
337 switch (crm) {
338 case 0:
339 if (opc2 == 4) {
340 return MISCREG_NOP;
341 }
342 break;
343 case 1:
344 switch (opc2) {
345 case 0:
346 return MISCREG_ICIALLUIS;
347 case 6:
348 return MISCREG_BPIALLIS;
349 }
350 break;
351 case 4:
352 if (opc2 == 0) {
353 return MISCREG_PAR;
354 }
355 break;
356 case 5:
357 switch (opc2) {
358 case 0:
359 return MISCREG_ICIALLU;
360 case 1:
361 return MISCREG_ICIMVAU;
362 case 4:
363 return MISCREG_CP15ISB;
364 case 6:
365 return MISCREG_BPIALL;
366 case 7:
367 return MISCREG_BPIMVA;
368 }
369 break;
370 case 6:
371 if (opc2 == 1) {
372 return MISCREG_DCIMVAC;
373 } else if (opc2 == 2) {
374 return MISCREG_DCISW;
375 }
376 break;
377 case 8:
378 switch (opc2) {
379 case 0:
380 return MISCREG_ATS1CPR;
381 case 1:
382 return MISCREG_ATS1CPW;
383 case 2:
384 return MISCREG_ATS1CUR;
385 case 3:
386 return MISCREG_ATS1CUW;
387 case 4:
388 return MISCREG_ATS12NSOPR;
389 case 5:
390 return MISCREG_ATS12NSOPW;
391 case 6:
392 return MISCREG_ATS12NSOUR;
393 case 7:
394 return MISCREG_ATS12NSOUW;
395 }
396 break;
397 case 10:
398 switch (opc2) {
399 case 1:
400 return MISCREG_DCCMVAC;
401 case 2:
402 return MISCREG_DCCSW;
403 case 4:
404 return MISCREG_CP15DSB;
405 case 5:
406 return MISCREG_CP15DMB;
407 }
408 break;
409 case 11:
410 if (opc2 == 1) {
411 return MISCREG_DCCMVAU;
412 }
413 break;
414 case 13:
415 if (opc2 == 1) {
416 return MISCREG_NOP;
417 }
418 break;
419 case 14:
420 if (opc2 == 1) {
421 return MISCREG_DCCIMVAC;
422 } else if (opc2 == 2) {
423 return MISCREG_DCCISW;
424 }
425 break;
426 }
427 } else if (opc1 == 4 && crm == 8) {
428 if (opc2 == 0)
429 return MISCREG_ATS1HR;
430 else if (opc2 == 1)
431 return MISCREG_ATS1HW;
432 }
433 break;
434 case 8:
435 if (opc1 == 0) {
436 switch (crm) {
437 case 3:
438 switch (opc2) {
439 case 0:
440 return MISCREG_TLBIALLIS;
441 case 1:
442 return MISCREG_TLBIMVAIS;
443 case 2:
444 return MISCREG_TLBIASIDIS;
445 case 3:
446 return MISCREG_TLBIMVAAIS;
447 case 5:
448 return MISCREG_TLBIMVALIS;
449 case 7:
450 return MISCREG_TLBIMVAALIS;
451 }
452 break;
453 case 5:
454 switch (opc2) {
455 case 0:
456 return MISCREG_ITLBIALL;
457 case 1:
458 return MISCREG_ITLBIMVA;
459 case 2:
460 return MISCREG_ITLBIASID;
461 }
462 break;
463 case 6:
464 switch (opc2) {
465 case 0:
466 return MISCREG_DTLBIALL;
467 case 1:
468 return MISCREG_DTLBIMVA;
469 case 2:
470 return MISCREG_DTLBIASID;
471 }
472 break;
473 case 7:
474 switch (opc2) {
475 case 0:
476 return MISCREG_TLBIALL;
477 case 1:
478 return MISCREG_TLBIMVA;
479 case 2:
480 return MISCREG_TLBIASID;
481 case 3:
482 return MISCREG_TLBIMVAA;
483 case 5:
484 return MISCREG_TLBIMVAL;
485 case 7:
486 return MISCREG_TLBIMVAAL;
487 }
488 break;
489 }
490 } else if (opc1 == 4) {
491 if (crm == 0) {
492 switch (opc2) {
493 case 1:
494 return MISCREG_TLBIIPAS2IS;
495 case 5:
496 return MISCREG_TLBIIPAS2LIS;
497 }
498 } else if (crm == 3) {
499 switch (opc2) {
500 case 0:
501 return MISCREG_TLBIALLHIS;
502 case 1:
503 return MISCREG_TLBIMVAHIS;
504 case 4:
505 return MISCREG_TLBIALLNSNHIS;
506 case 5:
507 return MISCREG_TLBIMVALHIS;
508 }
509 } else if (crm == 4) {
510 switch (opc2) {
511 case 1:
512 return MISCREG_TLBIIPAS2;
513 case 5:
514 return MISCREG_TLBIIPAS2L;
515 }
516 } else if (crm == 7) {
517 switch (opc2) {
518 case 0:
519 return MISCREG_TLBIALLH;
520 case 1:
521 return MISCREG_TLBIMVAH;
522 case 4:
523 return MISCREG_TLBIALLNSNH;
524 case 5:
525 return MISCREG_TLBIMVALH;
526 }
527 }
528 }
529 break;
530 case 9:
531 // Every cop register with CRn = 9 and CRm in
532 // {0-2}, {5-8} is implementation defined regardless
533 // of opc1 and opc2.
534 switch (crm) {
535 case 0:
536 case 1:
537 case 2:
538 case 5:
539 case 6:
540 case 7:
541 case 8:
542 return MISCREG_IMPDEF_UNIMPL;
543 }
544 if (opc1 == 0) {
545 switch (crm) {
546 case 12:
547 switch (opc2) {
548 case 0:
549 return MISCREG_PMCR;
550 case 1:
551 return MISCREG_PMCNTENSET;
552 case 2:
553 return MISCREG_PMCNTENCLR;
554 case 3:
555 return MISCREG_PMOVSR;
556 case 4:
557 return MISCREG_PMSWINC;
558 case 5:
559 return MISCREG_PMSELR;
560 case 6:
561 return MISCREG_PMCEID0;
562 case 7:
563 return MISCREG_PMCEID1;
564 }
565 break;
566 case 13:
567 switch (opc2) {
568 case 0:
569 return MISCREG_PMCCNTR;
570 case 1:
571 // Selector is PMSELR.SEL
572 return MISCREG_PMXEVTYPER_PMCCFILTR;
573 case 2:
574 return MISCREG_PMXEVCNTR;
575 }
576 break;
577 case 14:
578 switch (opc2) {
579 case 0:
580 return MISCREG_PMUSERENR;
581 case 1:
582 return MISCREG_PMINTENSET;
583 case 2:
584 return MISCREG_PMINTENCLR;
585 case 3:
586 return MISCREG_PMOVSSET;
587 }
588 break;
589 }
590 } else if (opc1 == 1) {
591 switch (crm) {
592 case 0:
593 switch (opc2) {
594 case 2: // L2CTLR, L2 Control Register
595 return MISCREG_L2CTLR;
596 case 3:
597 return MISCREG_L2ECTLR;
598 }
599 break;
600 break;
601 }
602 }
603 break;
604 case 10:
605 if (opc1 == 0) {
606 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
607 if (crm < 2) {
608 return MISCREG_IMPDEF_UNIMPL;
609 } else if (crm == 2) { // TEX Remap Registers
610 if (opc2 == 0) {
611 // Selector is TTBCR.EAE
612 return MISCREG_PRRR_MAIR0;
613 } else if (opc2 == 1) {
614 // Selector is TTBCR.EAE
615 return MISCREG_NMRR_MAIR1;
616 }
617 } else if (crm == 3) {
618 if (opc2 == 0) {
619 return MISCREG_AMAIR0;
620 } else if (opc2 == 1) {
621 return MISCREG_AMAIR1;
622 }
623 }
624 } else if (opc1 == 4) {
625 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
626 if (crm == 2) {
627 if (opc2 == 0)
628 return MISCREG_HMAIR0;
629 else if (opc2 == 1)
630 return MISCREG_HMAIR1;
631 } else if (crm == 3) {
632 if (opc2 == 0)
633 return MISCREG_HAMAIR0;
634 else if (opc2 == 1)
635 return MISCREG_HAMAIR1;
636 }
637 }
638 break;
639 case 11:
640 if (opc1 <=7) {
641 switch (crm) {
642 case 0:
643 case 1:
644 case 2:
645 case 3:
646 case 4:
647 case 5:
648 case 6:
649 case 7:
650 case 8:
651 case 15:
652 // Reserved for DMA operations for TCM access
653 return MISCREG_IMPDEF_UNIMPL;
654 default:
655 break;
656 }
657 }
658 break;
659 case 12:
660 if (opc1 == 0) {
661 if (crm == 0) {
662 if (opc2 == 0) {
663 return MISCREG_VBAR;
664 } else if (opc2 == 1) {
665 return MISCREG_MVBAR;
666 }
667 } else if (crm == 1) {
668 if (opc2 == 0) {
669 return MISCREG_ISR;
670 }
671 }
672 } else if (opc1 == 4) {
673 if (crm == 0 && opc2 == 0)
674 return MISCREG_HVBAR;
675 }
676 break;
677 case 13:
678 if (opc1 == 0) {
679 if (crm == 0) {
680 switch (opc2) {
681 case 0:
682 return MISCREG_FCSEIDR;
683 case 1:
684 return MISCREG_CONTEXTIDR;
685 case 2:
686 return MISCREG_TPIDRURW;
687 case 3:
688 return MISCREG_TPIDRURO;
689 case 4:
690 return MISCREG_TPIDRPRW;
691 }
692 }
693 } else if (opc1 == 4) {
694 if (crm == 0 && opc2 == 2)
695 return MISCREG_HTPIDR;
696 }
697 break;
698 case 14:
699 if (opc1 == 0) {
700 switch (crm) {
701 case 0:
702 if (opc2 == 0)
703 return MISCREG_CNTFRQ;
704 break;
705 case 1:
706 if (opc2 == 0)
707 return MISCREG_CNTKCTL;
708 break;
709 case 2:
710 if (opc2 == 0)
711 return MISCREG_CNTP_TVAL;
712 else if (opc2 == 1)
713 return MISCREG_CNTP_CTL;
714 break;
715 case 3:
716 if (opc2 == 0)
717 return MISCREG_CNTV_TVAL;
718 else if (opc2 == 1)
719 return MISCREG_CNTV_CTL;
720 break;
721 }
722 } else if (opc1 == 4) {
723 if (crm == 1 && opc2 == 0) {
724 return MISCREG_CNTHCTL;
725 } else if (crm == 2) {
726 if (opc2 == 0)
727 return MISCREG_CNTHP_TVAL;
728 else if (opc2 == 1)
729 return MISCREG_CNTHP_CTL;
730 }
731 }
732 break;
733 case 15:
734 // Implementation defined
735 return MISCREG_IMPDEF_UNIMPL;
736 }
737 // Unrecognized register
738 return MISCREG_CP15_UNIMPL;
739 }
740
741 MiscRegIndex
742 decodeCP15Reg64(unsigned crm, unsigned opc1)
743 {
744 switch (crm) {
745 case 2:
746 switch (opc1) {
747 case 0:
748 return MISCREG_TTBR0;
749 case 1:
750 return MISCREG_TTBR1;
751 case 4:
752 return MISCREG_HTTBR;
753 case 6:
754 return MISCREG_VTTBR;
755 }
756 break;
757 case 7:
758 if (opc1 == 0)
759 return MISCREG_PAR;
760 break;
761 case 14:
762 switch (opc1) {
763 case 0:
764 return MISCREG_CNTPCT;
765 case 1:
766 return MISCREG_CNTVCT;
767 case 2:
768 return MISCREG_CNTP_CVAL;
769 case 3:
770 return MISCREG_CNTV_CVAL;
771 case 4:
772 return MISCREG_CNTVOFF;
773 case 6:
774 return MISCREG_CNTHP_CVAL;
775 }
776 break;
777 case 15:
778 if (opc1 == 0)
779 return MISCREG_CPUMERRSR;
780 else if (opc1 == 1)
781 return MISCREG_L2MERRSR;
782 break;
783 }
784 // Unrecognized register
785 return MISCREG_CP15_UNIMPL;
786 }
787
788 std::tuple<bool, bool>
789 canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
790 {
791 bool secure = !scr.ns;
792 bool canRead = false;
793 bool undefined = false;
794
795 switch (cpsr.mode) {
796 case MODE_USER:
797 canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
798 miscRegInfo[reg][MISCREG_USR_NS_RD];
799 break;
800 case MODE_FIQ:
801 case MODE_IRQ:
802 case MODE_SVC:
803 case MODE_ABORT:
804 case MODE_UNDEFINED:
805 case MODE_SYSTEM:
806 canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
807 miscRegInfo[reg][MISCREG_PRI_NS_RD];
808 break;
809 case MODE_MON:
810 canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
811 miscRegInfo[reg][MISCREG_MON_NS1_RD];
812 break;
813 case MODE_HYP:
814 canRead = miscRegInfo[reg][MISCREG_HYP_RD];
815 break;
816 default:
817 undefined = true;
818 }
819 // can't do permissions checkes on the root of a banked pair of regs
820 assert(!miscRegInfo[reg][MISCREG_BANKED]);
821 return std::make_tuple(canRead, undefined);
822 }
823
824 std::tuple<bool, bool>
825 canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
826 {
827 bool secure = !scr.ns;
828 bool canWrite = false;
829 bool undefined = false;
830
831 switch (cpsr.mode) {
832 case MODE_USER:
833 canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
834 miscRegInfo[reg][MISCREG_USR_NS_WR];
835 break;
836 case MODE_FIQ:
837 case MODE_IRQ:
838 case MODE_SVC:
839 case MODE_ABORT:
840 case MODE_UNDEFINED:
841 case MODE_SYSTEM:
842 canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
843 miscRegInfo[reg][MISCREG_PRI_NS_WR];
844 break;
845 case MODE_MON:
846 canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
847 miscRegInfo[reg][MISCREG_MON_NS1_WR];
848 break;
849 case MODE_HYP:
850 canWrite = miscRegInfo[reg][MISCREG_HYP_WR];
851 break;
852 default:
853 undefined = true;
854 }
855 // can't do permissions checkes on the root of a banked pair of regs
856 assert(!miscRegInfo[reg][MISCREG_BANKED]);
857 return std::make_tuple(canWrite, undefined);
858 }
859
860 int
861 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
862 {
863 SCR scr = tc->readMiscReg(MISCREG_SCR);
864 return snsBankedIndex(reg, tc, scr.ns);
865 }
866
867 int
868 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
869 {
870 int reg_as_int = static_cast<int>(reg);
871 if (miscRegInfo[reg][MISCREG_BANKED]) {
872 reg_as_int += (ArmSystem::haveSecurity(tc) &&
873 !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
874 }
875 return reg_as_int;
876 }
877
878
879 /**
880 * If the reg is a child reg of a banked set, then the parent is the last
881 * banked one in the list. This is messy, and the wish is to eventually have
882 * the bitmap replaced with a better data structure. the preUnflatten function
883 * initializes a lookup table to speed up the search for these banked
884 * registers.
885 */
886
887 int unflattenResultMiscReg[NUM_MISCREGS];
888
889 void
890 preUnflattenMiscReg()
891 {
892 int reg = -1;
893 for (int i = 0 ; i < NUM_MISCREGS; i++){
894 if (miscRegInfo[i][MISCREG_BANKED])
895 reg = i;
896 if (miscRegInfo[i][MISCREG_BANKED_CHILD])
897 unflattenResultMiscReg[i] = reg;
898 else
899 unflattenResultMiscReg[i] = i;
900 // if this assert fails, no parent was found, and something is broken
901 assert(unflattenResultMiscReg[i] > -1);
902 }
903 }
904
905 int
906 unflattenMiscReg(int reg)
907 {
908 return unflattenResultMiscReg[reg];
909 }
910
911 bool
912 canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
913 {
914 // Check for SP_EL0 access while SPSEL == 0
915 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
916 return false;
917
918 // Check for RVBAR access
919 if (reg == MISCREG_RVBAR_EL1) {
920 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
921 if (highest_el == EL2 || highest_el == EL3)
922 return false;
923 }
924 if (reg == MISCREG_RVBAR_EL2) {
925 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
926 if (highest_el == EL3)
927 return false;
928 }
929
930 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
931
932 switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) {
933 case EL0:
934 return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
935 miscRegInfo[reg][MISCREG_USR_NS_RD];
936 case EL1:
937 return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
938 miscRegInfo[reg][MISCREG_PRI_NS_RD];
939 case EL2:
940 return miscRegInfo[reg][MISCREG_HYP_RD];
941 case EL3:
942 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
943 miscRegInfo[reg][MISCREG_MON_NS1_RD];
944 default:
945 panic("Invalid exception level");
946 }
947 }
948
949 bool
950 canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
951 {
952 // Check for SP_EL0 access while SPSEL == 0
953 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
954 return false;
955 ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
956 if (reg == MISCREG_DAIF) {
957 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
958 if (el == EL0 && !sctlr.uma)
959 return false;
960 }
961 if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
962 // In syscall-emulation mode, this test is skipped and DCZVA is always
963 // allowed at EL0
964 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
965 if (el == EL0 && !sctlr.dze)
966 return false;
967 }
968 if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
969 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
970 if (el == EL0 && !sctlr.uci)
971 return false;
972 }
973
974 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
975
976 switch (el) {
977 case EL0:
978 return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
979 miscRegInfo[reg][MISCREG_USR_NS_WR];
980 case EL1:
981 return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
982 miscRegInfo[reg][MISCREG_PRI_NS_WR];
983 case EL2:
984 return miscRegInfo[reg][MISCREG_HYP_WR];
985 case EL3:
986 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
987 miscRegInfo[reg][MISCREG_MON_NS1_WR];
988 default:
989 panic("Invalid exception level");
990 }
991 }
992
993 MiscRegIndex
994 decodeAArch64SysReg(unsigned op0, unsigned op1,
995 unsigned crn, unsigned crm,
996 unsigned op2)
997 {
998 switch (op0) {
999 case 1:
1000 switch (crn) {
1001 case 7:
1002 switch (op1) {
1003 case 0:
1004 switch (crm) {
1005 case 1:
1006 switch (op2) {
1007 case 0:
1008 return MISCREG_IC_IALLUIS;
1009 }
1010 break;
1011 case 5:
1012 switch (op2) {
1013 case 0:
1014 return MISCREG_IC_IALLU;
1015 }
1016 break;
1017 case 6:
1018 switch (op2) {
1019 case 1:
1020 return MISCREG_DC_IVAC_Xt;
1021 case 2:
1022 return MISCREG_DC_ISW_Xt;
1023 }
1024 break;
1025 case 8:
1026 switch (op2) {
1027 case 0:
1028 return MISCREG_AT_S1E1R_Xt;
1029 case 1:
1030 return MISCREG_AT_S1E1W_Xt;
1031 case 2:
1032 return MISCREG_AT_S1E0R_Xt;
1033 case 3:
1034 return MISCREG_AT_S1E0W_Xt;
1035 }
1036 break;
1037 case 10:
1038 switch (op2) {
1039 case 2:
1040 return MISCREG_DC_CSW_Xt;
1041 }
1042 break;
1043 case 14:
1044 switch (op2) {
1045 case 2:
1046 return MISCREG_DC_CISW_Xt;
1047 }
1048 break;
1049 }
1050 break;
1051 case 3:
1052 switch (crm) {
1053 case 4:
1054 switch (op2) {
1055 case 1:
1056 return MISCREG_DC_ZVA_Xt;
1057 }
1058 break;
1059 case 5:
1060 switch (op2) {
1061 case 1:
1062 return MISCREG_IC_IVAU_Xt;
1063 }
1064 break;
1065 case 10:
1066 switch (op2) {
1067 case 1:
1068 return MISCREG_DC_CVAC_Xt;
1069 }
1070 break;
1071 case 11:
1072 switch (op2) {
1073 case 1:
1074 return MISCREG_DC_CVAU_Xt;
1075 }
1076 break;
1077 case 14:
1078 switch (op2) {
1079 case 1:
1080 return MISCREG_DC_CIVAC_Xt;
1081 }
1082 break;
1083 }
1084 break;
1085 case 4:
1086 switch (crm) {
1087 case 8:
1088 switch (op2) {
1089 case 0:
1090 return MISCREG_AT_S1E2R_Xt;
1091 case 1:
1092 return MISCREG_AT_S1E2W_Xt;
1093 case 4:
1094 return MISCREG_AT_S12E1R_Xt;
1095 case 5:
1096 return MISCREG_AT_S12E1W_Xt;
1097 case 6:
1098 return MISCREG_AT_S12E0R_Xt;
1099 case 7:
1100 return MISCREG_AT_S12E0W_Xt;
1101 }
1102 break;
1103 }
1104 break;
1105 case 6:
1106 switch (crm) {
1107 case 8:
1108 switch (op2) {
1109 case 0:
1110 return MISCREG_AT_S1E3R_Xt;
1111 case 1:
1112 return MISCREG_AT_S1E3W_Xt;
1113 }
1114 break;
1115 }
1116 break;
1117 }
1118 break;
1119 case 8:
1120 switch (op1) {
1121 case 0:
1122 switch (crm) {
1123 case 3:
1124 switch (op2) {
1125 case 0:
1126 return MISCREG_TLBI_VMALLE1IS;
1127 case 1:
1128 return MISCREG_TLBI_VAE1IS_Xt;
1129 case 2:
1130 return MISCREG_TLBI_ASIDE1IS_Xt;
1131 case 3:
1132 return MISCREG_TLBI_VAAE1IS_Xt;
1133 case 5:
1134 return MISCREG_TLBI_VALE1IS_Xt;
1135 case 7:
1136 return MISCREG_TLBI_VAALE1IS_Xt;
1137 }
1138 break;
1139 case 7:
1140 switch (op2) {
1141 case 0:
1142 return MISCREG_TLBI_VMALLE1;
1143 case 1:
1144 return MISCREG_TLBI_VAE1_Xt;
1145 case 2:
1146 return MISCREG_TLBI_ASIDE1_Xt;
1147 case 3:
1148 return MISCREG_TLBI_VAAE1_Xt;
1149 case 5:
1150 return MISCREG_TLBI_VALE1_Xt;
1151 case 7:
1152 return MISCREG_TLBI_VAALE1_Xt;
1153 }
1154 break;
1155 }
1156 break;
1157 case 4:
1158 switch (crm) {
1159 case 0:
1160 switch (op2) {
1161 case 1:
1162 return MISCREG_TLBI_IPAS2E1IS_Xt;
1163 case 5:
1164 return MISCREG_TLBI_IPAS2LE1IS_Xt;
1165 }
1166 break;
1167 case 3:
1168 switch (op2) {
1169 case 0:
1170 return MISCREG_TLBI_ALLE2IS;
1171 case 1:
1172 return MISCREG_TLBI_VAE2IS_Xt;
1173 case 4:
1174 return MISCREG_TLBI_ALLE1IS;
1175 case 5:
1176 return MISCREG_TLBI_VALE2IS_Xt;
1177 case 6:
1178 return MISCREG_TLBI_VMALLS12E1IS;
1179 }
1180 break;
1181 case 4:
1182 switch (op2) {
1183 case 1:
1184 return MISCREG_TLBI_IPAS2E1_Xt;
1185 case 5:
1186 return MISCREG_TLBI_IPAS2LE1_Xt;
1187 }
1188 break;
1189 case 7:
1190 switch (op2) {
1191 case 0:
1192 return MISCREG_TLBI_ALLE2;
1193 case 1:
1194 return MISCREG_TLBI_VAE2_Xt;
1195 case 4:
1196 return MISCREG_TLBI_ALLE1;
1197 case 5:
1198 return MISCREG_TLBI_VALE2_Xt;
1199 case 6:
1200 return MISCREG_TLBI_VMALLS12E1;
1201 }
1202 break;
1203 }
1204 break;
1205 case 6:
1206 switch (crm) {
1207 case 3:
1208 switch (op2) {
1209 case 0:
1210 return MISCREG_TLBI_ALLE3IS;
1211 case 1:
1212 return MISCREG_TLBI_VAE3IS_Xt;
1213 case 5:
1214 return MISCREG_TLBI_VALE3IS_Xt;
1215 }
1216 break;
1217 case 7:
1218 switch (op2) {
1219 case 0:
1220 return MISCREG_TLBI_ALLE3;
1221 case 1:
1222 return MISCREG_TLBI_VAE3_Xt;
1223 case 5:
1224 return MISCREG_TLBI_VALE3_Xt;
1225 }
1226 break;
1227 }
1228 break;
1229 }
1230 break;
1231 }
1232 break;
1233 case 2:
1234 switch (crn) {
1235 case 0:
1236 switch (op1) {
1237 case 0:
1238 switch (crm) {
1239 case 0:
1240 switch (op2) {
1241 case 2:
1242 return MISCREG_OSDTRRX_EL1;
1243 case 4:
1244 return MISCREG_DBGBVR0_EL1;
1245 case 5:
1246 return MISCREG_DBGBCR0_EL1;
1247 case 6:
1248 return MISCREG_DBGWVR0_EL1;
1249 case 7:
1250 return MISCREG_DBGWCR0_EL1;
1251 }
1252 break;
1253 case 1:
1254 switch (op2) {
1255 case 4:
1256 return MISCREG_DBGBVR1_EL1;
1257 case 5:
1258 return MISCREG_DBGBCR1_EL1;
1259 case 6:
1260 return MISCREG_DBGWVR1_EL1;
1261 case 7:
1262 return MISCREG_DBGWCR1_EL1;
1263 }
1264 break;
1265 case 2:
1266 switch (op2) {
1267 case 0:
1268 return MISCREG_MDCCINT_EL1;
1269 case 2:
1270 return MISCREG_MDSCR_EL1;
1271 case 4:
1272 return MISCREG_DBGBVR2_EL1;
1273 case 5:
1274 return MISCREG_DBGBCR2_EL1;
1275 case 6:
1276 return MISCREG_DBGWVR2_EL1;
1277 case 7:
1278 return MISCREG_DBGWCR2_EL1;
1279 }
1280 break;
1281 case 3:
1282 switch (op2) {
1283 case 2:
1284 return MISCREG_OSDTRTX_EL1;
1285 case 4:
1286 return MISCREG_DBGBVR3_EL1;
1287 case 5:
1288 return MISCREG_DBGBCR3_EL1;
1289 case 6:
1290 return MISCREG_DBGWVR3_EL1;
1291 case 7:
1292 return MISCREG_DBGWCR3_EL1;
1293 }
1294 break;
1295 case 4:
1296 switch (op2) {
1297 case 4:
1298 return MISCREG_DBGBVR4_EL1;
1299 case 5:
1300 return MISCREG_DBGBCR4_EL1;
1301 }
1302 break;
1303 case 5:
1304 switch (op2) {
1305 case 4:
1306 return MISCREG_DBGBVR5_EL1;
1307 case 5:
1308 return MISCREG_DBGBCR5_EL1;
1309 }
1310 break;
1311 case 6:
1312 switch (op2) {
1313 case 2:
1314 return MISCREG_OSECCR_EL1;
1315 }
1316 break;
1317 }
1318 break;
1319 case 2:
1320 switch (crm) {
1321 case 0:
1322 switch (op2) {
1323 case 0:
1324 return MISCREG_TEECR32_EL1;
1325 }
1326 break;
1327 }
1328 break;
1329 case 3:
1330 switch (crm) {
1331 case 1:
1332 switch (op2) {
1333 case 0:
1334 return MISCREG_MDCCSR_EL0;
1335 }
1336 break;
1337 case 4:
1338 switch (op2) {
1339 case 0:
1340 return MISCREG_MDDTR_EL0;
1341 }
1342 break;
1343 case 5:
1344 switch (op2) {
1345 case 0:
1346 return MISCREG_MDDTRRX_EL0;
1347 }
1348 break;
1349 }
1350 break;
1351 case 4:
1352 switch (crm) {
1353 case 7:
1354 switch (op2) {
1355 case 0:
1356 return MISCREG_DBGVCR32_EL2;
1357 }
1358 break;
1359 }
1360 break;
1361 }
1362 break;
1363 case 1:
1364 switch (op1) {
1365 case 0:
1366 switch (crm) {
1367 case 0:
1368 switch (op2) {
1369 case 0:
1370 return MISCREG_MDRAR_EL1;
1371 case 4:
1372 return MISCREG_OSLAR_EL1;
1373 }
1374 break;
1375 case 1:
1376 switch (op2) {
1377 case 4:
1378 return MISCREG_OSLSR_EL1;
1379 }
1380 break;
1381 case 3:
1382 switch (op2) {
1383 case 4:
1384 return MISCREG_OSDLR_EL1;
1385 }
1386 break;
1387 case 4:
1388 switch (op2) {
1389 case 4:
1390 return MISCREG_DBGPRCR_EL1;
1391 }
1392 break;
1393 }
1394 break;
1395 case 2:
1396 switch (crm) {
1397 case 0:
1398 switch (op2) {
1399 case 0:
1400 return MISCREG_TEEHBR32_EL1;
1401 }
1402 break;
1403 }
1404 break;
1405 }
1406 break;
1407 case 7:
1408 switch (op1) {
1409 case 0:
1410 switch (crm) {
1411 case 8:
1412 switch (op2) {
1413 case 6:
1414 return MISCREG_DBGCLAIMSET_EL1;
1415 }
1416 break;
1417 case 9:
1418 switch (op2) {
1419 case 6:
1420 return MISCREG_DBGCLAIMCLR_EL1;
1421 }
1422 break;
1423 case 14:
1424 switch (op2) {
1425 case 6:
1426 return MISCREG_DBGAUTHSTATUS_EL1;
1427 }
1428 break;
1429 }
1430 break;
1431 }
1432 break;
1433 }
1434 break;
1435 case 3:
1436 switch (crn) {
1437 case 0:
1438 switch (op1) {
1439 case 0:
1440 switch (crm) {
1441 case 0:
1442 switch (op2) {
1443 case 0:
1444 return MISCREG_MIDR_EL1;
1445 case 5:
1446 return MISCREG_MPIDR_EL1;
1447 case 6:
1448 return MISCREG_REVIDR_EL1;
1449 }
1450 break;
1451 case 1:
1452 switch (op2) {
1453 case 0:
1454 return MISCREG_ID_PFR0_EL1;
1455 case 1:
1456 return MISCREG_ID_PFR1_EL1;
1457 case 2:
1458 return MISCREG_ID_DFR0_EL1;
1459 case 3:
1460 return MISCREG_ID_AFR0_EL1;
1461 case 4:
1462 return MISCREG_ID_MMFR0_EL1;
1463 case 5:
1464 return MISCREG_ID_MMFR1_EL1;
1465 case 6:
1466 return MISCREG_ID_MMFR2_EL1;
1467 case 7:
1468 return MISCREG_ID_MMFR3_EL1;
1469 }
1470 break;
1471 case 2:
1472 switch (op2) {
1473 case 0:
1474 return MISCREG_ID_ISAR0_EL1;
1475 case 1:
1476 return MISCREG_ID_ISAR1_EL1;
1477 case 2:
1478 return MISCREG_ID_ISAR2_EL1;
1479 case 3:
1480 return MISCREG_ID_ISAR3_EL1;
1481 case 4:
1482 return MISCREG_ID_ISAR4_EL1;
1483 case 5:
1484 return MISCREG_ID_ISAR5_EL1;
1485 }
1486 break;
1487 case 3:
1488 switch (op2) {
1489 case 0:
1490 return MISCREG_MVFR0_EL1;
1491 case 1:
1492 return MISCREG_MVFR1_EL1;
1493 case 2:
1494 return MISCREG_MVFR2_EL1;
1495 case 3 ... 7:
1496 return MISCREG_RAZ;
1497 }
1498 break;
1499 case 4:
1500 switch (op2) {
1501 case 0:
1502 return MISCREG_ID_AA64PFR0_EL1;
1503 case 1:
1504 return MISCREG_ID_AA64PFR1_EL1;
1505 case 2 ... 7:
1506 return MISCREG_RAZ;
1507 }
1508 break;
1509 case 5:
1510 switch (op2) {
1511 case 0:
1512 return MISCREG_ID_AA64DFR0_EL1;
1513 case 1:
1514 return MISCREG_ID_AA64DFR1_EL1;
1515 case 4:
1516 return MISCREG_ID_AA64AFR0_EL1;
1517 case 5:
1518 return MISCREG_ID_AA64AFR1_EL1;
1519 case 2:
1520 case 3:
1521 case 6:
1522 case 7:
1523 return MISCREG_RAZ;
1524 }
1525 break;
1526 case 6:
1527 switch (op2) {
1528 case 0:
1529 return MISCREG_ID_AA64ISAR0_EL1;
1530 case 1:
1531 return MISCREG_ID_AA64ISAR1_EL1;
1532 case 2 ... 7:
1533 return MISCREG_RAZ;
1534 }
1535 break;
1536 case 7:
1537 switch (op2) {
1538 case 0:
1539 return MISCREG_ID_AA64MMFR0_EL1;
1540 case 1:
1541 return MISCREG_ID_AA64MMFR1_EL1;
1542 case 2 ... 7:
1543 return MISCREG_RAZ;
1544 }
1545 break;
1546 }
1547 break;
1548 case 1:
1549 switch (crm) {
1550 case 0:
1551 switch (op2) {
1552 case 0:
1553 return MISCREG_CCSIDR_EL1;
1554 case 1:
1555 return MISCREG_CLIDR_EL1;
1556 case 7:
1557 return MISCREG_AIDR_EL1;
1558 }
1559 break;
1560 }
1561 break;
1562 case 2:
1563 switch (crm) {
1564 case 0:
1565 switch (op2) {
1566 case 0:
1567 return MISCREG_CSSELR_EL1;
1568 }
1569 break;
1570 }
1571 break;
1572 case 3:
1573 switch (crm) {
1574 case 0:
1575 switch (op2) {
1576 case 1:
1577 return MISCREG_CTR_EL0;
1578 case 7:
1579 return MISCREG_DCZID_EL0;
1580 }
1581 break;
1582 }
1583 break;
1584 case 4:
1585 switch (crm) {
1586 case 0:
1587 switch (op2) {
1588 case 0:
1589 return MISCREG_VPIDR_EL2;
1590 case 5:
1591 return MISCREG_VMPIDR_EL2;
1592 }
1593 break;
1594 }
1595 break;
1596 }
1597 break;
1598 case 1:
1599 switch (op1) {
1600 case 0:
1601 switch (crm) {
1602 case 0:
1603 switch (op2) {
1604 case 0:
1605 return MISCREG_SCTLR_EL1;
1606 case 1:
1607 return MISCREG_ACTLR_EL1;
1608 case 2:
1609 return MISCREG_CPACR_EL1;
1610 }
1611 break;
1612 }
1613 break;
1614 case 4:
1615 switch (crm) {
1616 case 0:
1617 switch (op2) {
1618 case 0:
1619 return MISCREG_SCTLR_EL2;
1620 case 1:
1621 return MISCREG_ACTLR_EL2;
1622 }
1623 break;
1624 case 1:
1625 switch (op2) {
1626 case 0:
1627 return MISCREG_HCR_EL2;
1628 case 1:
1629 return MISCREG_MDCR_EL2;
1630 case 2:
1631 return MISCREG_CPTR_EL2;
1632 case 3:
1633 return MISCREG_HSTR_EL2;
1634 case 7:
1635 return MISCREG_HACR_EL2;
1636 }
1637 break;
1638 }
1639 break;
1640 case 6:
1641 switch (crm) {
1642 case 0:
1643 switch (op2) {
1644 case 0:
1645 return MISCREG_SCTLR_EL3;
1646 case 1:
1647 return MISCREG_ACTLR_EL3;
1648 }
1649 break;
1650 case 1:
1651 switch (op2) {
1652 case 0:
1653 return MISCREG_SCR_EL3;
1654 case 1:
1655 return MISCREG_SDER32_EL3;
1656 case 2:
1657 return MISCREG_CPTR_EL3;
1658 }
1659 break;
1660 case 3:
1661 switch (op2) {
1662 case 1:
1663 return MISCREG_MDCR_EL3;
1664 }
1665 break;
1666 }
1667 break;
1668 }
1669 break;
1670 case 2:
1671 switch (op1) {
1672 case 0:
1673 switch (crm) {
1674 case 0:
1675 switch (op2) {
1676 case 0:
1677 return MISCREG_TTBR0_EL1;
1678 case 1:
1679 return MISCREG_TTBR1_EL1;
1680 case 2:
1681 return MISCREG_TCR_EL1;
1682 }
1683 break;
1684 }
1685 break;
1686 case 4:
1687 switch (crm) {
1688 case 0:
1689 switch (op2) {
1690 case 0:
1691 return MISCREG_TTBR0_EL2;
1692 case 1:
1693 return MISCREG_TTBR1_EL2;
1694 case 2:
1695 return MISCREG_TCR_EL2;
1696 }
1697 break;
1698 case 1:
1699 switch (op2) {
1700 case 0:
1701 return MISCREG_VTTBR_EL2;
1702 case 2:
1703 return MISCREG_VTCR_EL2;
1704 }
1705 break;
1706 }
1707 break;
1708 case 6:
1709 switch (crm) {
1710 case 0:
1711 switch (op2) {
1712 case 0:
1713 return MISCREG_TTBR0_EL3;
1714 case 2:
1715 return MISCREG_TCR_EL3;
1716 }
1717 break;
1718 }
1719 break;
1720 }
1721 break;
1722 case 3:
1723 switch (op1) {
1724 case 4:
1725 switch (crm) {
1726 case 0:
1727 switch (op2) {
1728 case 0:
1729 return MISCREG_DACR32_EL2;
1730 }
1731 break;
1732 }
1733 break;
1734 }
1735 break;
1736 case 4:
1737 switch (op1) {
1738 case 0:
1739 switch (crm) {
1740 case 0:
1741 switch (op2) {
1742 case 0:
1743 return MISCREG_SPSR_EL1;
1744 case 1:
1745 return MISCREG_ELR_EL1;
1746 }
1747 break;
1748 case 1:
1749 switch (op2) {
1750 case 0:
1751 return MISCREG_SP_EL0;
1752 }
1753 break;
1754 case 2:
1755 switch (op2) {
1756 case 0:
1757 return MISCREG_SPSEL;
1758 case 2:
1759 return MISCREG_CURRENTEL;
1760 }
1761 break;
1762 }
1763 break;
1764 case 3:
1765 switch (crm) {
1766 case 2:
1767 switch (op2) {
1768 case 0:
1769 return MISCREG_NZCV;
1770 case 1:
1771 return MISCREG_DAIF;
1772 }
1773 break;
1774 case 4:
1775 switch (op2) {
1776 case 0:
1777 return MISCREG_FPCR;
1778 case 1:
1779 return MISCREG_FPSR;
1780 }
1781 break;
1782 case 5:
1783 switch (op2) {
1784 case 0:
1785 return MISCREG_DSPSR_EL0;
1786 case 1:
1787 return MISCREG_DLR_EL0;
1788 }
1789 break;
1790 }
1791 break;
1792 case 4:
1793 switch (crm) {
1794 case 0:
1795 switch (op2) {
1796 case 0:
1797 return MISCREG_SPSR_EL2;
1798 case 1:
1799 return MISCREG_ELR_EL2;
1800 }
1801 break;
1802 case 1:
1803 switch (op2) {
1804 case 0:
1805 return MISCREG_SP_EL1;
1806 }
1807 break;
1808 case 3:
1809 switch (op2) {
1810 case 0:
1811 return MISCREG_SPSR_IRQ_AA64;
1812 case 1:
1813 return MISCREG_SPSR_ABT_AA64;
1814 case 2:
1815 return MISCREG_SPSR_UND_AA64;
1816 case 3:
1817 return MISCREG_SPSR_FIQ_AA64;
1818 }
1819 break;
1820 }
1821 break;
1822 case 6:
1823 switch (crm) {
1824 case 0:
1825 switch (op2) {
1826 case 0:
1827 return MISCREG_SPSR_EL3;
1828 case 1:
1829 return MISCREG_ELR_EL3;
1830 }
1831 break;
1832 case 1:
1833 switch (op2) {
1834 case 0:
1835 return MISCREG_SP_EL2;
1836 }
1837 break;
1838 }
1839 break;
1840 }
1841 break;
1842 case 5:
1843 switch (op1) {
1844 case 0:
1845 switch (crm) {
1846 case 1:
1847 switch (op2) {
1848 case 0:
1849 return MISCREG_AFSR0_EL1;
1850 case 1:
1851 return MISCREG_AFSR1_EL1;
1852 }
1853 break;
1854 case 2:
1855 switch (op2) {
1856 case 0:
1857 return MISCREG_ESR_EL1;
1858 }
1859 break;
1860 case 3:
1861 switch (op2) {
1862 case 0:
1863 return MISCREG_ERRIDR_EL1;
1864 case 1:
1865 return MISCREG_ERRSELR_EL1;
1866 }
1867 break;
1868 case 4:
1869 switch (op2) {
1870 case 0:
1871 return MISCREG_ERXFR_EL1;
1872 case 1:
1873 return MISCREG_ERXCTLR_EL1;
1874 case 2:
1875 return MISCREG_ERXSTATUS_EL1;
1876 case 3:
1877 return MISCREG_ERXADDR_EL1;
1878 }
1879 break;
1880 case 5:
1881 switch (op2) {
1882 case 0:
1883 return MISCREG_ERXMISC0_EL1;
1884 case 1:
1885 return MISCREG_ERXMISC1_EL1;
1886 }
1887 break;
1888 }
1889 break;
1890 case 4:
1891 switch (crm) {
1892 case 0:
1893 switch (op2) {
1894 case 1:
1895 return MISCREG_IFSR32_EL2;
1896 }
1897 break;
1898 case 1:
1899 switch (op2) {
1900 case 0:
1901 return MISCREG_AFSR0_EL2;
1902 case 1:
1903 return MISCREG_AFSR1_EL2;
1904 }
1905 break;
1906 case 2:
1907 switch (op2) {
1908 case 0:
1909 return MISCREG_ESR_EL2;
1910 case 3:
1911 return MISCREG_VSESR_EL2;
1912 }
1913 break;
1914 case 3:
1915 switch (op2) {
1916 case 0:
1917 return MISCREG_FPEXC32_EL2;
1918 }
1919 break;
1920 }
1921 break;
1922 case 6:
1923 switch (crm) {
1924 case 1:
1925 switch (op2) {
1926 case 0:
1927 return MISCREG_AFSR0_EL3;
1928 case 1:
1929 return MISCREG_AFSR1_EL3;
1930 }
1931 break;
1932 case 2:
1933 switch (op2) {
1934 case 0:
1935 return MISCREG_ESR_EL3;
1936 }
1937 break;
1938 }
1939 break;
1940 }
1941 break;
1942 case 6:
1943 switch (op1) {
1944 case 0:
1945 switch (crm) {
1946 case 0:
1947 switch (op2) {
1948 case 0:
1949 return MISCREG_FAR_EL1;
1950 }
1951 break;
1952 }
1953 break;
1954 case 4:
1955 switch (crm) {
1956 case 0:
1957 switch (op2) {
1958 case 0:
1959 return MISCREG_FAR_EL2;
1960 case 4:
1961 return MISCREG_HPFAR_EL2;
1962 }
1963 break;
1964 }
1965 break;
1966 case 6:
1967 switch (crm) {
1968 case 0:
1969 switch (op2) {
1970 case 0:
1971 return MISCREG_FAR_EL3;
1972 }
1973 break;
1974 }
1975 break;
1976 }
1977 break;
1978 case 7:
1979 switch (op1) {
1980 case 0:
1981 switch (crm) {
1982 case 4:
1983 switch (op2) {
1984 case 0:
1985 return MISCREG_PAR_EL1;
1986 }
1987 break;
1988 }
1989 break;
1990 }
1991 break;
1992 case 9:
1993 switch (op1) {
1994 case 0:
1995 switch (crm) {
1996 case 14:
1997 switch (op2) {
1998 case 1:
1999 return MISCREG_PMINTENSET_EL1;
2000 case 2:
2001 return MISCREG_PMINTENCLR_EL1;
2002 }
2003 break;
2004 }
2005 break;
2006 case 3:
2007 switch (crm) {
2008 case 12:
2009 switch (op2) {
2010 case 0:
2011 return MISCREG_PMCR_EL0;
2012 case 1:
2013 return MISCREG_PMCNTENSET_EL0;
2014 case 2:
2015 return MISCREG_PMCNTENCLR_EL0;
2016 case 3:
2017 return MISCREG_PMOVSCLR_EL0;
2018 case 4:
2019 return MISCREG_PMSWINC_EL0;
2020 case 5:
2021 return MISCREG_PMSELR_EL0;
2022 case 6:
2023 return MISCREG_PMCEID0_EL0;
2024 case 7:
2025 return MISCREG_PMCEID1_EL0;
2026 }
2027 break;
2028 case 13:
2029 switch (op2) {
2030 case 0:
2031 return MISCREG_PMCCNTR_EL0;
2032 case 1:
2033 return MISCREG_PMXEVTYPER_EL0;
2034 case 2:
2035 return MISCREG_PMXEVCNTR_EL0;
2036 }
2037 break;
2038 case 14:
2039 switch (op2) {
2040 case 0:
2041 return MISCREG_PMUSERENR_EL0;
2042 case 3:
2043 return MISCREG_PMOVSSET_EL0;
2044 }
2045 break;
2046 }
2047 break;
2048 }
2049 break;
2050 case 10:
2051 switch (op1) {
2052 case 0:
2053 switch (crm) {
2054 case 2:
2055 switch (op2) {
2056 case 0:
2057 return MISCREG_MAIR_EL1;
2058 }
2059 break;
2060 case 3:
2061 switch (op2) {
2062 case 0:
2063 return MISCREG_AMAIR_EL1;
2064 }
2065 break;
2066 }
2067 break;
2068 case 4:
2069 switch (crm) {
2070 case 2:
2071 switch (op2) {
2072 case 0:
2073 return MISCREG_MAIR_EL2;
2074 }
2075 break;
2076 case 3:
2077 switch (op2) {
2078 case 0:
2079 return MISCREG_AMAIR_EL2;
2080 }
2081 break;
2082 }
2083 break;
2084 case 6:
2085 switch (crm) {
2086 case 2:
2087 switch (op2) {
2088 case 0:
2089 return MISCREG_MAIR_EL3;
2090 }
2091 break;
2092 case 3:
2093 switch (op2) {
2094 case 0:
2095 return MISCREG_AMAIR_EL3;
2096 }
2097 break;
2098 }
2099 break;
2100 }
2101 break;
2102 case 11:
2103 switch (op1) {
2104 case 1:
2105 switch (crm) {
2106 case 0:
2107 switch (op2) {
2108 case 2:
2109 return MISCREG_L2CTLR_EL1;
2110 case 3:
2111 return MISCREG_L2ECTLR_EL1;
2112 }
2113 break;
2114 }
2115 M5_FALLTHROUGH;
2116 default:
2117 // S3_<op1>_11_<Cm>_<op2>
2118 return MISCREG_IMPDEF_UNIMPL;
2119 }
2120 M5_UNREACHABLE;
2121 case 12:
2122 switch (op1) {
2123 case 0:
2124 switch (crm) {
2125 case 0:
2126 switch (op2) {
2127 case 0:
2128 return MISCREG_VBAR_EL1;
2129 case 1:
2130 return MISCREG_RVBAR_EL1;
2131 }
2132 break;
2133 case 1:
2134 switch (op2) {
2135 case 0:
2136 return MISCREG_ISR_EL1;
2137 case 1:
2138 return MISCREG_DISR_EL1;
2139 }
2140 break;
2141 }
2142 break;
2143 case 4:
2144 switch (crm) {
2145 case 0:
2146 switch (op2) {
2147 case 0:
2148 return MISCREG_VBAR_EL2;
2149 case 1:
2150 return MISCREG_RVBAR_EL2;
2151 }
2152 break;
2153 case 1:
2154 switch (op2) {
2155 case 1:
2156 return MISCREG_VDISR_EL2;
2157 }
2158 break;
2159 }
2160 break;
2161 case 6:
2162 switch (crm) {
2163 case 0:
2164 switch (op2) {
2165 case 0:
2166 return MISCREG_VBAR_EL3;
2167 case 1:
2168 return MISCREG_RVBAR_EL3;
2169 case 2:
2170 return MISCREG_RMR_EL3;
2171 }
2172 break;
2173 }
2174 break;
2175 }
2176 break;
2177 case 13:
2178 switch (op1) {
2179 case 0:
2180 switch (crm) {
2181 case 0:
2182 switch (op2) {
2183 case 1:
2184 return MISCREG_CONTEXTIDR_EL1;
2185 case 4:
2186 return MISCREG_TPIDR_EL1;
2187 }
2188 break;
2189 }
2190 break;
2191 case 3:
2192 switch (crm) {
2193 case 0:
2194 switch (op2) {
2195 case 2:
2196 return MISCREG_TPIDR_EL0;
2197 case 3:
2198 return MISCREG_TPIDRRO_EL0;
2199 }
2200 break;
2201 }
2202 break;
2203 case 4:
2204 switch (crm) {
2205 case 0:
2206 switch (op2) {
2207 case 1:
2208 return MISCREG_CONTEXTIDR_EL2;
2209 case 2:
2210 return MISCREG_TPIDR_EL2;
2211 }
2212 break;
2213 }
2214 break;
2215 case 6:
2216 switch (crm) {
2217 case 0:
2218 switch (op2) {
2219 case 2:
2220 return MISCREG_TPIDR_EL3;
2221 }
2222 break;
2223 }
2224 break;
2225 }
2226 break;
2227 case 14:
2228 switch (op1) {
2229 case 0:
2230 switch (crm) {
2231 case 1:
2232 switch (op2) {
2233 case 0:
2234 return MISCREG_CNTKCTL_EL1;
2235 }
2236 break;
2237 }
2238 break;
2239 case 3:
2240 switch (crm) {
2241 case 0:
2242 switch (op2) {
2243 case 0:
2244 return MISCREG_CNTFRQ_EL0;
2245 case 1:
2246 return MISCREG_CNTPCT_EL0;
2247 case 2:
2248 return MISCREG_CNTVCT_EL0;
2249 }
2250 break;
2251 case 2:
2252 switch (op2) {
2253 case 0:
2254 return MISCREG_CNTP_TVAL_EL0;
2255 case 1:
2256 return MISCREG_CNTP_CTL_EL0;
2257 case 2:
2258 return MISCREG_CNTP_CVAL_EL0;
2259 }
2260 break;
2261 case 3:
2262 switch (op2) {
2263 case 0:
2264 return MISCREG_CNTV_TVAL_EL0;
2265 case 1:
2266 return MISCREG_CNTV_CTL_EL0;
2267 case 2:
2268 return MISCREG_CNTV_CVAL_EL0;
2269 }
2270 break;
2271 case 8:
2272 switch (op2) {
2273 case 0:
2274 return MISCREG_PMEVCNTR0_EL0;
2275 case 1:
2276 return MISCREG_PMEVCNTR1_EL0;
2277 case 2:
2278 return MISCREG_PMEVCNTR2_EL0;
2279 case 3:
2280 return MISCREG_PMEVCNTR3_EL0;
2281 case 4:
2282 return MISCREG_PMEVCNTR4_EL0;
2283 case 5:
2284 return MISCREG_PMEVCNTR5_EL0;
2285 }
2286 break;
2287 case 12:
2288 switch (op2) {
2289 case 0:
2290 return MISCREG_PMEVTYPER0_EL0;
2291 case 1:
2292 return MISCREG_PMEVTYPER1_EL0;
2293 case 2:
2294 return MISCREG_PMEVTYPER2_EL0;
2295 case 3:
2296 return MISCREG_PMEVTYPER3_EL0;
2297 case 4:
2298 return MISCREG_PMEVTYPER4_EL0;
2299 case 5:
2300 return MISCREG_PMEVTYPER5_EL0;
2301 }
2302 break;
2303 case 15:
2304 switch (op2) {
2305 case 7:
2306 return MISCREG_PMCCFILTR_EL0;
2307 }
2308 }
2309 break;
2310 case 4:
2311 switch (crm) {
2312 case 0:
2313 switch (op2) {
2314 case 3:
2315 return MISCREG_CNTVOFF_EL2;
2316 }
2317 break;
2318 case 1:
2319 switch (op2) {
2320 case 0:
2321 return MISCREG_CNTHCTL_EL2;
2322 }
2323 break;
2324 case 2:
2325 switch (op2) {
2326 case 0:
2327 return MISCREG_CNTHP_TVAL_EL2;
2328 case 1:
2329 return MISCREG_CNTHP_CTL_EL2;
2330 case 2:
2331 return MISCREG_CNTHP_CVAL_EL2;
2332 }
2333 break;
2334 case 3:
2335 switch (op2) {
2336 case 0:
2337 return MISCREG_CNTHV_TVAL_EL2;
2338 case 1:
2339 return MISCREG_CNTHV_CTL_EL2;
2340 case 2:
2341 return MISCREG_CNTHV_CVAL_EL2;
2342 }
2343 break;
2344 }
2345 break;
2346 case 7:
2347 switch (crm) {
2348 case 2:
2349 switch (op2) {
2350 case 0:
2351 return MISCREG_CNTPS_TVAL_EL1;
2352 case 1:
2353 return MISCREG_CNTPS_CTL_EL1;
2354 case 2:
2355 return MISCREG_CNTPS_CVAL_EL1;
2356 }
2357 break;
2358 }
2359 break;
2360 }
2361 break;
2362 case 15:
2363 switch (op1) {
2364 case 0:
2365 switch (crm) {
2366 case 0:
2367 switch (op2) {
2368 case 0:
2369 return MISCREG_IL1DATA0_EL1;
2370 case 1:
2371 return MISCREG_IL1DATA1_EL1;
2372 case 2:
2373 return MISCREG_IL1DATA2_EL1;
2374 case 3:
2375 return MISCREG_IL1DATA3_EL1;
2376 }
2377 break;
2378 case 1:
2379 switch (op2) {
2380 case 0:
2381 return MISCREG_DL1DATA0_EL1;
2382 case 1:
2383 return MISCREG_DL1DATA1_EL1;
2384 case 2:
2385 return MISCREG_DL1DATA2_EL1;
2386 case 3:
2387 return MISCREG_DL1DATA3_EL1;
2388 case 4:
2389 return MISCREG_DL1DATA4_EL1;
2390 }
2391 break;
2392 }
2393 break;
2394 case 1:
2395 switch (crm) {
2396 case 0:
2397 switch (op2) {
2398 case 0:
2399 return MISCREG_L2ACTLR_EL1;
2400 }
2401 break;
2402 case 2:
2403 switch (op2) {
2404 case 0:
2405 return MISCREG_CPUACTLR_EL1;
2406 case 1:
2407 return MISCREG_CPUECTLR_EL1;
2408 case 2:
2409 return MISCREG_CPUMERRSR_EL1;
2410 case 3:
2411 return MISCREG_L2MERRSR_EL1;
2412 }
2413 break;
2414 case 3:
2415 switch (op2) {
2416 case 0:
2417 return MISCREG_CBAR_EL1;
2418
2419 }
2420 break;
2421 }
2422 break;
2423 }
2424 // S3_<op1>_15_<Cm>_<op2>
2425 return MISCREG_IMPDEF_UNIMPL;
2426 }
2427 break;
2428 }
2429
2430 return MISCREG_UNKNOWN;
2431 }
2432
2433 bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below
2434
2435 void
2436 ISA::initializeMiscRegMetadata()
2437 {
2438 // the MiscReg metadata tables are shared across all instances of the
2439 // ISA object, so there's no need to initialize them multiple times.
2440 static bool completed = false;
2441 if (completed)
2442 return;
2443
2444 // This boolean variable specifies if the system is running in aarch32 at
2445 // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
2446 // is running in aarch64 (aarch32EL3 = false)
2447 bool aarch32EL3 = haveSecurity && !highestELIs64;
2448
2449 /**
2450 * Some registers alias with others, and therefore need to be translated.
2451 * When two mapping registers are given, they are the 32b lower and
2452 * upper halves, respectively, of the 64b register being mapped.
2453 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
2454 *
2455 * NAM = "not architecturally mandated",
2456 * from ARM DDI 0487A.i, template text
2457 * "AArch64 System register ___ can be mapped to
2458 * AArch32 System register ___, but this is not
2459 * architecturally mandated."
2460 */
2461
2462 InitReg(MISCREG_CPSR)
2463 .allPrivileges();
2464 InitReg(MISCREG_SPSR)
2465 .allPrivileges();
2466 InitReg(MISCREG_SPSR_FIQ)
2467 .allPrivileges();
2468 InitReg(MISCREG_SPSR_IRQ)
2469 .allPrivileges();
2470 InitReg(MISCREG_SPSR_SVC)
2471 .allPrivileges();
2472 InitReg(MISCREG_SPSR_MON)
2473 .allPrivileges();
2474 InitReg(MISCREG_SPSR_ABT)
2475 .allPrivileges();
2476 InitReg(MISCREG_SPSR_HYP)
2477 .allPrivileges();
2478 InitReg(MISCREG_SPSR_UND)
2479 .allPrivileges();
2480 InitReg(MISCREG_ELR_HYP)
2481 .allPrivileges();
2482 InitReg(MISCREG_FPSID)
2483 .allPrivileges();
2484 InitReg(MISCREG_FPSCR)
2485 .allPrivileges();
2486 InitReg(MISCREG_MVFR1)
2487 .allPrivileges();
2488 InitReg(MISCREG_MVFR0)
2489 .allPrivileges();
2490 InitReg(MISCREG_FPEXC)
2491 .allPrivileges();
2492
2493 // Helper registers
2494 InitReg(MISCREG_CPSR_MODE)
2495 .allPrivileges();
2496 InitReg(MISCREG_CPSR_Q)
2497 .allPrivileges();
2498 InitReg(MISCREG_FPSCR_EXC)
2499 .allPrivileges();
2500 InitReg(MISCREG_FPSCR_QC)
2501 .allPrivileges();
2502 InitReg(MISCREG_LOCKADDR)
2503 .allPrivileges();
2504 InitReg(MISCREG_LOCKFLAG)
2505 .allPrivileges();
2506 InitReg(MISCREG_PRRR_MAIR0)
2507 .mutex()
2508 .banked();
2509 InitReg(MISCREG_PRRR_MAIR0_NS)
2510 .mutex()
2511 .privSecure(!aarch32EL3)
2512 .bankedChild();
2513 InitReg(MISCREG_PRRR_MAIR0_S)
2514 .mutex()
2515 .bankedChild();
2516 InitReg(MISCREG_NMRR_MAIR1)
2517 .mutex()
2518 .banked();
2519 InitReg(MISCREG_NMRR_MAIR1_NS)
2520 .mutex()
2521 .privSecure(!aarch32EL3)
2522 .bankedChild();
2523 InitReg(MISCREG_NMRR_MAIR1_S)
2524 .mutex()
2525 .bankedChild();
2526 InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
2527 .mutex();
2528 InitReg(MISCREG_SCTLR_RST)
2529 .allPrivileges();
2530 InitReg(MISCREG_SEV_MAILBOX)
2531 .allPrivileges();
2532
2533 // AArch32 CP14 registers
2534 InitReg(MISCREG_DBGDIDR)
2535 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2536 InitReg(MISCREG_DBGDSCRint)
2537 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2538 InitReg(MISCREG_DBGDCCINT)
2539 .unimplemented()
2540 .allPrivileges();
2541 InitReg(MISCREG_DBGDTRTXint)
2542 .unimplemented()
2543 .allPrivileges();
2544 InitReg(MISCREG_DBGDTRRXint)
2545 .unimplemented()
2546 .allPrivileges();
2547 InitReg(MISCREG_DBGWFAR)
2548 .unimplemented()
2549 .allPrivileges();
2550 InitReg(MISCREG_DBGVCR)
2551 .unimplemented()
2552 .allPrivileges();
2553 InitReg(MISCREG_DBGDTRRXext)
2554 .unimplemented()
2555 .allPrivileges();
2556 InitReg(MISCREG_DBGDSCRext)
2557 .unimplemented()
2558 .warnNotFail()
2559 .allPrivileges();
2560 InitReg(MISCREG_DBGDTRTXext)
2561 .unimplemented()
2562 .allPrivileges();
2563 InitReg(MISCREG_DBGOSECCR)
2564 .unimplemented()
2565 .allPrivileges();
2566 InitReg(MISCREG_DBGBVR0)
2567 .unimplemented()
2568 .allPrivileges();
2569 InitReg(MISCREG_DBGBVR1)
2570 .unimplemented()
2571 .allPrivileges();
2572 InitReg(MISCREG_DBGBVR2)
2573 .unimplemented()
2574 .allPrivileges();
2575 InitReg(MISCREG_DBGBVR3)
2576 .unimplemented()
2577 .allPrivileges();
2578 InitReg(MISCREG_DBGBVR4)
2579 .unimplemented()
2580 .allPrivileges();
2581 InitReg(MISCREG_DBGBVR5)
2582 .unimplemented()
2583 .allPrivileges();
2584 InitReg(MISCREG_DBGBCR0)
2585 .unimplemented()
2586 .allPrivileges();
2587 InitReg(MISCREG_DBGBCR1)
2588 .unimplemented()
2589 .allPrivileges();
2590 InitReg(MISCREG_DBGBCR2)
2591 .unimplemented()
2592 .allPrivileges();
2593 InitReg(MISCREG_DBGBCR3)
2594 .unimplemented()
2595 .allPrivileges();
2596 InitReg(MISCREG_DBGBCR4)
2597 .unimplemented()
2598 .allPrivileges();
2599 InitReg(MISCREG_DBGBCR5)
2600 .unimplemented()
2601 .allPrivileges();
2602 InitReg(MISCREG_DBGWVR0)
2603 .unimplemented()
2604 .allPrivileges();
2605 InitReg(MISCREG_DBGWVR1)
2606 .unimplemented()
2607 .allPrivileges();
2608 InitReg(MISCREG_DBGWVR2)
2609 .unimplemented()
2610 .allPrivileges();
2611 InitReg(MISCREG_DBGWVR3)
2612 .unimplemented()
2613 .allPrivileges();
2614 InitReg(MISCREG_DBGWCR0)
2615 .unimplemented()
2616 .allPrivileges();
2617 InitReg(MISCREG_DBGWCR1)
2618 .unimplemented()
2619 .allPrivileges();
2620 InitReg(MISCREG_DBGWCR2)
2621 .unimplemented()
2622 .allPrivileges();
2623 InitReg(MISCREG_DBGWCR3)
2624 .unimplemented()
2625 .allPrivileges();
2626 InitReg(MISCREG_DBGDRAR)
2627 .unimplemented()
2628 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2629 InitReg(MISCREG_DBGBXVR4)
2630 .unimplemented()
2631 .allPrivileges();
2632 InitReg(MISCREG_DBGBXVR5)
2633 .unimplemented()
2634 .allPrivileges();
2635 InitReg(MISCREG_DBGOSLAR)
2636 .unimplemented()
2637 .allPrivileges().monSecureRead(0).monNonSecureRead(0);
2638 InitReg(MISCREG_DBGOSLSR)
2639 .unimplemented()
2640 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2641 InitReg(MISCREG_DBGOSDLR)
2642 .unimplemented()
2643 .allPrivileges();
2644 InitReg(MISCREG_DBGPRCR)
2645 .unimplemented()
2646 .allPrivileges();
2647 InitReg(MISCREG_DBGDSAR)
2648 .unimplemented()
2649 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2650 InitReg(MISCREG_DBGCLAIMSET)
2651 .unimplemented()
2652 .allPrivileges();
2653 InitReg(MISCREG_DBGCLAIMCLR)
2654 .unimplemented()
2655 .allPrivileges();
2656 InitReg(MISCREG_DBGAUTHSTATUS)
2657 .unimplemented()
2658 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2659 InitReg(MISCREG_DBGDEVID2)
2660 .unimplemented()
2661 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2662 InitReg(MISCREG_DBGDEVID1)
2663 .unimplemented()
2664 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2665 InitReg(MISCREG_DBGDEVID0)
2666 .unimplemented()
2667 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2668 InitReg(MISCREG_TEECR)
2669 .unimplemented()
2670 .allPrivileges();
2671 InitReg(MISCREG_JIDR)
2672 .allPrivileges();
2673 InitReg(MISCREG_TEEHBR)
2674 .allPrivileges();
2675 InitReg(MISCREG_JOSCR)
2676 .allPrivileges();
2677 InitReg(MISCREG_JMCR)
2678 .allPrivileges();
2679
2680 // AArch32 CP15 registers
2681 InitReg(MISCREG_MIDR)
2682 .allPrivileges().exceptUserMode().writes(0);
2683 InitReg(MISCREG_CTR)
2684 .allPrivileges().exceptUserMode().writes(0);
2685 InitReg(MISCREG_TCMTR)
2686 .allPrivileges().exceptUserMode().writes(0);
2687 InitReg(MISCREG_TLBTR)
2688 .allPrivileges().exceptUserMode().writes(0);
2689 InitReg(MISCREG_MPIDR)
2690 .allPrivileges().exceptUserMode().writes(0);
2691 InitReg(MISCREG_REVIDR)
2692 .unimplemented()
2693 .warnNotFail()
2694 .allPrivileges().exceptUserMode().writes(0);
2695 InitReg(MISCREG_ID_PFR0)
2696 .allPrivileges().exceptUserMode().writes(0);
2697 InitReg(MISCREG_ID_PFR1)
2698 .allPrivileges().exceptUserMode().writes(0);
2699 InitReg(MISCREG_ID_DFR0)
2700 .allPrivileges().exceptUserMode().writes(0);
2701 InitReg(MISCREG_ID_AFR0)
2702 .allPrivileges().exceptUserMode().writes(0);
2703 InitReg(MISCREG_ID_MMFR0)
2704 .allPrivileges().exceptUserMode().writes(0);
2705 InitReg(MISCREG_ID_MMFR1)
2706 .allPrivileges().exceptUserMode().writes(0);
2707 InitReg(MISCREG_ID_MMFR2)
2708 .allPrivileges().exceptUserMode().writes(0);
2709 InitReg(MISCREG_ID_MMFR3)
2710 .allPrivileges().exceptUserMode().writes(0);
2711 InitReg(MISCREG_ID_ISAR0)
2712 .allPrivileges().exceptUserMode().writes(0);
2713 InitReg(MISCREG_ID_ISAR1)
2714 .allPrivileges().exceptUserMode().writes(0);
2715 InitReg(MISCREG_ID_ISAR2)
2716 .allPrivileges().exceptUserMode().writes(0);
2717 InitReg(MISCREG_ID_ISAR3)
2718 .allPrivileges().exceptUserMode().writes(0);
2719 InitReg(MISCREG_ID_ISAR4)
2720 .allPrivileges().exceptUserMode().writes(0);
2721 InitReg(MISCREG_ID_ISAR5)
2722 .allPrivileges().exceptUserMode().writes(0);
2723 InitReg(MISCREG_CCSIDR)
2724 .allPrivileges().exceptUserMode().writes(0);
2725 InitReg(MISCREG_CLIDR)
2726 .allPrivileges().exceptUserMode().writes(0);
2727 InitReg(MISCREG_AIDR)
2728 .allPrivileges().exceptUserMode().writes(0);
2729 InitReg(MISCREG_CSSELR)
2730 .banked();
2731 InitReg(MISCREG_CSSELR_NS)
2732 .bankedChild()
2733 .privSecure(!aarch32EL3)
2734 .nonSecure().exceptUserMode();
2735 InitReg(MISCREG_CSSELR_S)
2736 .bankedChild()
2737 .secure().exceptUserMode();
2738 InitReg(MISCREG_VPIDR)
2739 .hyp().monNonSecure();
2740 InitReg(MISCREG_VMPIDR)
2741 .hyp().monNonSecure();
2742 InitReg(MISCREG_SCTLR)
2743 .banked();
2744 InitReg(MISCREG_SCTLR_NS)
2745 .bankedChild()
2746 .privSecure(!aarch32EL3)
2747 .nonSecure().exceptUserMode();
2748 InitReg(MISCREG_SCTLR_S)
2749 .bankedChild()
2750 .secure().exceptUserMode();
2751 InitReg(MISCREG_ACTLR)
2752 .banked();
2753 InitReg(MISCREG_ACTLR_NS)
2754 .bankedChild()
2755 .privSecure(!aarch32EL3)
2756 .nonSecure().exceptUserMode();
2757 InitReg(MISCREG_ACTLR_S)
2758 .bankedChild()
2759 .secure().exceptUserMode();
2760 InitReg(MISCREG_CPACR)
2761 .allPrivileges().exceptUserMode();
2762 InitReg(MISCREG_SCR)
2763 .mon().secure().exceptUserMode()
2764 .res0(0xff40) // [31:16], [6]
2765 .res1(0x0030); // [5:4]
2766 InitReg(MISCREG_SDER)
2767 .mon();
2768 InitReg(MISCREG_NSACR)
2769 .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
2770 InitReg(MISCREG_HSCTLR)
2771 .hyp().monNonSecure();
2772 InitReg(MISCREG_HACTLR)
2773 .hyp().monNonSecure();
2774 InitReg(MISCREG_HCR)
2775 .hyp().monNonSecure();
2776 InitReg(MISCREG_HDCR)
2777 .hyp().monNonSecure();
2778 InitReg(MISCREG_HCPTR)
2779 .hyp().monNonSecure();
2780 InitReg(MISCREG_HSTR)
2781 .hyp().monNonSecure();
2782 InitReg(MISCREG_HACR)
2783 .unimplemented()
2784 .warnNotFail()
2785 .hyp().monNonSecure();
2786 InitReg(MISCREG_TTBR0)
2787 .banked();
2788 InitReg(MISCREG_TTBR0_NS)
2789 .bankedChild()
2790 .privSecure(!aarch32EL3)
2791 .nonSecure().exceptUserMode();
2792 InitReg(MISCREG_TTBR0_S)
2793 .bankedChild()
2794 .secure().exceptUserMode();
2795 InitReg(MISCREG_TTBR1)
2796 .banked();
2797 InitReg(MISCREG_TTBR1_NS)
2798 .bankedChild()
2799 .privSecure(!aarch32EL3)
2800 .nonSecure().exceptUserMode();
2801 InitReg(MISCREG_TTBR1_S)
2802 .bankedChild()
2803 .secure().exceptUserMode();
2804 InitReg(MISCREG_TTBCR)
2805 .banked();
2806 InitReg(MISCREG_TTBCR_NS)
2807 .bankedChild()
2808 .privSecure(!aarch32EL3)
2809 .nonSecure().exceptUserMode();
2810 InitReg(MISCREG_TTBCR_S)
2811 .bankedChild()
2812 .secure().exceptUserMode();
2813 InitReg(MISCREG_HTCR)
2814 .hyp().monNonSecure();
2815 InitReg(MISCREG_VTCR)
2816 .hyp().monNonSecure();
2817 InitReg(MISCREG_DACR)
2818 .banked();
2819 InitReg(MISCREG_DACR_NS)
2820 .bankedChild()
2821 .privSecure(!aarch32EL3)
2822 .nonSecure().exceptUserMode();
2823 InitReg(MISCREG_DACR_S)
2824 .bankedChild()
2825 .secure().exceptUserMode();
2826 InitReg(MISCREG_DFSR)
2827 .banked();
2828 InitReg(MISCREG_DFSR_NS)
2829 .bankedChild()
2830 .privSecure(!aarch32EL3)
2831 .nonSecure().exceptUserMode();
2832 InitReg(MISCREG_DFSR_S)
2833 .bankedChild()
2834 .secure().exceptUserMode();
2835 InitReg(MISCREG_IFSR)
2836 .banked();
2837 InitReg(MISCREG_IFSR_NS)
2838 .bankedChild()
2839 .privSecure(!aarch32EL3)
2840 .nonSecure().exceptUserMode();
2841 InitReg(MISCREG_IFSR_S)
2842 .bankedChild()
2843 .secure().exceptUserMode();
2844 InitReg(MISCREG_ADFSR)
2845 .unimplemented()
2846 .warnNotFail()
2847 .banked();
2848 InitReg(MISCREG_ADFSR_NS)
2849 .unimplemented()
2850 .warnNotFail()
2851 .bankedChild()
2852 .privSecure(!aarch32EL3)
2853 .nonSecure().exceptUserMode();
2854 InitReg(MISCREG_ADFSR_S)
2855 .unimplemented()
2856 .warnNotFail()
2857 .bankedChild()
2858 .secure().exceptUserMode();
2859 InitReg(MISCREG_AIFSR)
2860 .unimplemented()
2861 .warnNotFail()
2862 .banked();
2863 InitReg(MISCREG_AIFSR_NS)
2864 .unimplemented()
2865 .warnNotFail()
2866 .bankedChild()
2867 .privSecure(!aarch32EL3)
2868 .nonSecure().exceptUserMode();
2869 InitReg(MISCREG_AIFSR_S)
2870 .unimplemented()
2871 .warnNotFail()
2872 .bankedChild()
2873 .secure().exceptUserMode();
2874 InitReg(MISCREG_HADFSR)
2875 .hyp().monNonSecure();
2876 InitReg(MISCREG_HAIFSR)
2877 .hyp().monNonSecure();
2878 InitReg(MISCREG_HSR)
2879 .hyp().monNonSecure();
2880 InitReg(MISCREG_DFAR)
2881 .banked();
2882 InitReg(MISCREG_DFAR_NS)
2883 .bankedChild()
2884 .privSecure(!aarch32EL3)
2885 .nonSecure().exceptUserMode();
2886 InitReg(MISCREG_DFAR_S)
2887 .bankedChild()
2888 .secure().exceptUserMode();
2889 InitReg(MISCREG_IFAR)
2890 .banked();
2891 InitReg(MISCREG_IFAR_NS)
2892 .bankedChild()
2893 .privSecure(!aarch32EL3)
2894 .nonSecure().exceptUserMode();
2895 InitReg(MISCREG_IFAR_S)
2896 .bankedChild()
2897 .secure().exceptUserMode();
2898 InitReg(MISCREG_HDFAR)
2899 .hyp().monNonSecure();
2900 InitReg(MISCREG_HIFAR)
2901 .hyp().monNonSecure();
2902 InitReg(MISCREG_HPFAR)
2903 .hyp().monNonSecure();
2904 InitReg(MISCREG_ICIALLUIS)
2905 .unimplemented()
2906 .warnNotFail()
2907 .writes(1).exceptUserMode();
2908 InitReg(MISCREG_BPIALLIS)
2909 .unimplemented()
2910 .warnNotFail()
2911 .writes(1).exceptUserMode();
2912 InitReg(MISCREG_PAR)
2913 .banked();
2914 InitReg(MISCREG_PAR_NS)
2915 .bankedChild()
2916 .privSecure(!aarch32EL3)
2917 .nonSecure().exceptUserMode();
2918 InitReg(MISCREG_PAR_S)
2919 .bankedChild()
2920 .secure().exceptUserMode();
2921 InitReg(MISCREG_ICIALLU)
2922 .writes(1).exceptUserMode();
2923 InitReg(MISCREG_ICIMVAU)
2924 .unimplemented()
2925 .warnNotFail()
2926 .writes(1).exceptUserMode();
2927 InitReg(MISCREG_CP15ISB)
2928 .writes(1);
2929 InitReg(MISCREG_BPIALL)
2930 .unimplemented()
2931 .warnNotFail()
2932 .writes(1).exceptUserMode();
2933 InitReg(MISCREG_BPIMVA)
2934 .unimplemented()
2935 .warnNotFail()
2936 .writes(1).exceptUserMode();
2937 InitReg(MISCREG_DCIMVAC)
2938 .unimplemented()
2939 .warnNotFail()
2940 .writes(1).exceptUserMode();
2941 InitReg(MISCREG_DCISW)
2942 .unimplemented()
2943 .warnNotFail()
2944 .writes(1).exceptUserMode();
2945 InitReg(MISCREG_ATS1CPR)
2946 .writes(1).exceptUserMode();
2947 InitReg(MISCREG_ATS1CPW)
2948 .writes(1).exceptUserMode();
2949 InitReg(MISCREG_ATS1CUR)
2950 .writes(1).exceptUserMode();
2951 InitReg(MISCREG_ATS1CUW)
2952 .writes(1).exceptUserMode();
2953 InitReg(MISCREG_ATS12NSOPR)
2954 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2955 InitReg(MISCREG_ATS12NSOPW)
2956 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2957 InitReg(MISCREG_ATS12NSOUR)
2958 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2959 InitReg(MISCREG_ATS12NSOUW)
2960 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2961 InitReg(MISCREG_DCCMVAC)
2962 .writes(1).exceptUserMode();
2963 InitReg(MISCREG_DCCSW)
2964 .unimplemented()
2965 .warnNotFail()
2966 .writes(1).exceptUserMode();
2967 InitReg(MISCREG_CP15DSB)
2968 .writes(1);
2969 InitReg(MISCREG_CP15DMB)
2970 .writes(1);
2971 InitReg(MISCREG_DCCMVAU)
2972 .unimplemented()
2973 .warnNotFail()
2974 .writes(1).exceptUserMode();
2975 InitReg(MISCREG_DCCIMVAC)
2976 .unimplemented()
2977 .warnNotFail()
2978 .writes(1).exceptUserMode();
2979 InitReg(MISCREG_DCCISW)
2980 .unimplemented()
2981 .warnNotFail()
2982 .writes(1).exceptUserMode();
2983 InitReg(MISCREG_ATS1HR)
2984 .monNonSecureWrite().hypWrite();
2985 InitReg(MISCREG_ATS1HW)
2986 .monNonSecureWrite().hypWrite();
2987 InitReg(MISCREG_TLBIALLIS)
2988 .writes(1).exceptUserMode();
2989 InitReg(MISCREG_TLBIMVAIS)
2990 .writes(1).exceptUserMode();
2991 InitReg(MISCREG_TLBIASIDIS)
2992 .writes(1).exceptUserMode();
2993 InitReg(MISCREG_TLBIMVAAIS)
2994 .writes(1).exceptUserMode();
2995 InitReg(MISCREG_TLBIMVALIS)
2996 .writes(1).exceptUserMode();
2997 InitReg(MISCREG_TLBIMVAALIS)
2998 .writes(1).exceptUserMode();
2999 InitReg(MISCREG_ITLBIALL)
3000 .writes(1).exceptUserMode();
3001 InitReg(MISCREG_ITLBIMVA)
3002 .writes(1).exceptUserMode();
3003 InitReg(MISCREG_ITLBIASID)
3004 .writes(1).exceptUserMode();
3005 InitReg(MISCREG_DTLBIALL)
3006 .writes(1).exceptUserMode();
3007 InitReg(MISCREG_DTLBIMVA)
3008 .writes(1).exceptUserMode();
3009 InitReg(MISCREG_DTLBIASID)
3010 .writes(1).exceptUserMode();
3011 InitReg(MISCREG_TLBIALL)
3012 .writes(1).exceptUserMode();
3013 InitReg(MISCREG_TLBIMVA)
3014 .writes(1).exceptUserMode();
3015 InitReg(MISCREG_TLBIASID)
3016 .writes(1).exceptUserMode();
3017 InitReg(MISCREG_TLBIMVAA)
3018 .writes(1).exceptUserMode();
3019 InitReg(MISCREG_TLBIMVAL)
3020 .writes(1).exceptUserMode();
3021 InitReg(MISCREG_TLBIMVAAL)
3022 .writes(1).exceptUserMode();
3023 InitReg(MISCREG_TLBIIPAS2IS)
3024 .monNonSecureWrite().hypWrite();
3025 InitReg(MISCREG_TLBIIPAS2LIS)
3026 .monNonSecureWrite().hypWrite();
3027 InitReg(MISCREG_TLBIALLHIS)
3028 .monNonSecureWrite().hypWrite();
3029 InitReg(MISCREG_TLBIMVAHIS)
3030 .monNonSecureWrite().hypWrite();
3031 InitReg(MISCREG_TLBIALLNSNHIS)
3032 .monNonSecureWrite().hypWrite();
3033 InitReg(MISCREG_TLBIMVALHIS)
3034 .monNonSecureWrite().hypWrite();
3035 InitReg(MISCREG_TLBIIPAS2)
3036 .monNonSecureWrite().hypWrite();
3037 InitReg(MISCREG_TLBIIPAS2L)
3038 .monNonSecureWrite().hypWrite();
3039 InitReg(MISCREG_TLBIALLH)
3040 .monNonSecureWrite().hypWrite();
3041 InitReg(MISCREG_TLBIMVAH)
3042 .monNonSecureWrite().hypWrite();
3043 InitReg(MISCREG_TLBIALLNSNH)
3044 .monNonSecureWrite().hypWrite();
3045 InitReg(MISCREG_TLBIMVALH)
3046 .monNonSecureWrite().hypWrite();
3047 InitReg(MISCREG_PMCR)
3048 .allPrivileges();
3049 InitReg(MISCREG_PMCNTENSET)
3050 .allPrivileges();
3051 InitReg(MISCREG_PMCNTENCLR)
3052 .allPrivileges();
3053 InitReg(MISCREG_PMOVSR)
3054 .allPrivileges();
3055 InitReg(MISCREG_PMSWINC)
3056 .allPrivileges();
3057 InitReg(MISCREG_PMSELR)
3058 .allPrivileges();
3059 InitReg(MISCREG_PMCEID0)
3060 .allPrivileges();
3061 InitReg(MISCREG_PMCEID1)
3062 .allPrivileges();
3063 InitReg(MISCREG_PMCCNTR)
3064 .allPrivileges();
3065 InitReg(MISCREG_PMXEVTYPER)
3066 .allPrivileges();
3067 InitReg(MISCREG_PMCCFILTR)
3068 .allPrivileges();
3069 InitReg(MISCREG_PMXEVCNTR)
3070 .allPrivileges();
3071 InitReg(MISCREG_PMUSERENR)
3072 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
3073 InitReg(MISCREG_PMINTENSET)
3074 .allPrivileges().exceptUserMode();
3075 InitReg(MISCREG_PMINTENCLR)
3076 .allPrivileges().exceptUserMode();
3077 InitReg(MISCREG_PMOVSSET)
3078 .unimplemented()
3079 .allPrivileges();
3080 InitReg(MISCREG_L2CTLR)
3081 .allPrivileges().exceptUserMode();
3082 InitReg(MISCREG_L2ECTLR)
3083 .unimplemented()
3084 .allPrivileges().exceptUserMode();
3085 InitReg(MISCREG_PRRR)
3086 .banked();
3087 InitReg(MISCREG_PRRR_NS)
3088 .bankedChild()
3089 .privSecure(!aarch32EL3)
3090 .nonSecure().exceptUserMode();
3091 InitReg(MISCREG_PRRR_S)
3092 .bankedChild()
3093 .secure().exceptUserMode();
3094 InitReg(MISCREG_MAIR0)
3095 .banked();
3096 InitReg(MISCREG_MAIR0_NS)
3097 .bankedChild()
3098 .privSecure(!aarch32EL3)
3099 .nonSecure().exceptUserMode();
3100 InitReg(MISCREG_MAIR0_S)
3101 .bankedChild()
3102 .secure().exceptUserMode();
3103 InitReg(MISCREG_NMRR)
3104 .banked();
3105 InitReg(MISCREG_NMRR_NS)
3106 .bankedChild()
3107 .privSecure(!aarch32EL3)
3108 .nonSecure().exceptUserMode();
3109 InitReg(MISCREG_NMRR_S)
3110 .bankedChild()
3111 .secure().exceptUserMode();
3112 InitReg(MISCREG_MAIR1)
3113 .banked();
3114 InitReg(MISCREG_MAIR1_NS)
3115 .bankedChild()
3116 .privSecure(!aarch32EL3)
3117 .nonSecure().exceptUserMode();
3118 InitReg(MISCREG_MAIR1_S)
3119 .bankedChild()
3120 .secure().exceptUserMode();
3121 InitReg(MISCREG_AMAIR0)
3122 .banked();
3123 InitReg(MISCREG_AMAIR0_NS)
3124 .bankedChild()
3125 .privSecure(!aarch32EL3)
3126 .nonSecure().exceptUserMode();
3127 InitReg(MISCREG_AMAIR0_S)
3128 .bankedChild()
3129 .secure().exceptUserMode();
3130 InitReg(MISCREG_AMAIR1)
3131 .banked();
3132 InitReg(MISCREG_AMAIR1_NS)
3133 .bankedChild()
3134 .privSecure(!aarch32EL3)
3135 .nonSecure().exceptUserMode();
3136 InitReg(MISCREG_AMAIR1_S)
3137 .bankedChild()
3138 .secure().exceptUserMode();
3139 InitReg(MISCREG_HMAIR0)
3140 .hyp().monNonSecure();
3141 InitReg(MISCREG_HMAIR1)
3142 .hyp().monNonSecure();
3143 InitReg(MISCREG_HAMAIR0)
3144 .unimplemented()
3145 .warnNotFail()
3146 .hyp().monNonSecure();
3147 InitReg(MISCREG_HAMAIR1)
3148 .unimplemented()
3149 .warnNotFail()
3150 .hyp().monNonSecure();
3151 InitReg(MISCREG_VBAR)
3152 .banked();
3153 InitReg(MISCREG_VBAR_NS)
3154 .bankedChild()
3155 .privSecure(!aarch32EL3)
3156 .nonSecure().exceptUserMode();
3157 InitReg(MISCREG_VBAR_S)
3158 .bankedChild()
3159 .secure().exceptUserMode();
3160 InitReg(MISCREG_MVBAR)
3161 .mon().secure().exceptUserMode();
3162 InitReg(MISCREG_RMR)
3163 .unimplemented()
3164 .mon().secure().exceptUserMode();
3165 InitReg(MISCREG_ISR)
3166 .allPrivileges().exceptUserMode().writes(0);
3167 InitReg(MISCREG_HVBAR)
3168 .hyp().monNonSecure();
3169 InitReg(MISCREG_FCSEIDR)
3170 .unimplemented()
3171 .warnNotFail()
3172 .allPrivileges().exceptUserMode();
3173 InitReg(MISCREG_CONTEXTIDR)
3174 .banked();
3175 InitReg(MISCREG_CONTEXTIDR_NS)
3176 .bankedChild()
3177 .privSecure(!aarch32EL3)
3178 .nonSecure().exceptUserMode();
3179 InitReg(MISCREG_CONTEXTIDR_S)
3180 .bankedChild()
3181 .secure().exceptUserMode();
3182 InitReg(MISCREG_TPIDRURW)
3183 .banked();
3184 InitReg(MISCREG_TPIDRURW_NS)
3185 .bankedChild()
3186 .allPrivileges()
3187 .privSecure(!aarch32EL3)
3188 .monSecure(0);
3189 InitReg(MISCREG_TPIDRURW_S)
3190 .bankedChild()
3191 .secure();
3192 InitReg(MISCREG_TPIDRURO)
3193 .banked();
3194 InitReg(MISCREG_TPIDRURO_NS)
3195 .bankedChild()
3196 .allPrivileges()
3197 .userNonSecureWrite(0).userSecureRead(1)
3198 .privSecure(!aarch32EL3)
3199 .monSecure(0);
3200 InitReg(MISCREG_TPIDRURO_S)
3201 .bankedChild()
3202 .secure().userSecureWrite(0);
3203 InitReg(MISCREG_TPIDRPRW)
3204 .banked();
3205 InitReg(MISCREG_TPIDRPRW_NS)
3206 .bankedChild()
3207 .nonSecure().exceptUserMode()
3208 .privSecure(!aarch32EL3);
3209 InitReg(MISCREG_TPIDRPRW_S)
3210 .bankedChild()
3211 .secure().exceptUserMode();
3212 InitReg(MISCREG_HTPIDR)
3213 .hyp().monNonSecure();
3214 InitReg(MISCREG_CNTFRQ)
3215 .unverifiable()
3216 .reads(1).mon();
3217 InitReg(MISCREG_CNTKCTL)
3218 .allPrivileges().exceptUserMode();
3219 InitReg(MISCREG_CNTP_TVAL)
3220 .banked();
3221 InitReg(MISCREG_CNTP_TVAL_NS)
3222 .bankedChild()
3223 .allPrivileges()
3224 .privSecure(!aarch32EL3)
3225 .monSecure(0);
3226 InitReg(MISCREG_CNTP_TVAL_S)
3227 .bankedChild()
3228 .secure().user(1);
3229 InitReg(MISCREG_CNTP_CTL)
3230 .banked();
3231 InitReg(MISCREG_CNTP_CTL_NS)
3232 .bankedChild()
3233 .allPrivileges()
3234 .privSecure(!aarch32EL3)
3235 .monSecure(0);
3236 InitReg(MISCREG_CNTP_CTL_S)
3237 .bankedChild()
3238 .secure().user(1);
3239 InitReg(MISCREG_CNTV_TVAL)
3240 .allPrivileges();
3241 InitReg(MISCREG_CNTV_CTL)
3242 .allPrivileges();
3243 InitReg(MISCREG_CNTHCTL)
3244 .hypWrite().monNonSecureRead();
3245 InitReg(MISCREG_CNTHP_TVAL)
3246 .hypWrite().monNonSecureRead();
3247 InitReg(MISCREG_CNTHP_CTL)
3248 .hypWrite().monNonSecureRead();
3249 InitReg(MISCREG_IL1DATA0)
3250 .unimplemented()
3251 .allPrivileges().exceptUserMode();
3252 InitReg(MISCREG_IL1DATA1)
3253 .unimplemented()
3254 .allPrivileges().exceptUserMode();
3255 InitReg(MISCREG_IL1DATA2)
3256 .unimplemented()
3257 .allPrivileges().exceptUserMode();
3258 InitReg(MISCREG_IL1DATA3)
3259 .unimplemented()
3260 .allPrivileges().exceptUserMode();
3261 InitReg(MISCREG_DL1DATA0)
3262 .unimplemented()
3263 .allPrivileges().exceptUserMode();
3264 InitReg(MISCREG_DL1DATA1)
3265 .unimplemented()
3266 .allPrivileges().exceptUserMode();
3267 InitReg(MISCREG_DL1DATA2)
3268 .unimplemented()
3269 .allPrivileges().exceptUserMode();
3270 InitReg(MISCREG_DL1DATA3)
3271 .unimplemented()
3272 .allPrivileges().exceptUserMode();
3273 InitReg(MISCREG_DL1DATA4)
3274 .unimplemented()
3275 .allPrivileges().exceptUserMode();
3276 InitReg(MISCREG_RAMINDEX)
3277 .unimplemented()
3278 .writes(1).exceptUserMode();
3279 InitReg(MISCREG_L2ACTLR)
3280 .unimplemented()
3281 .allPrivileges().exceptUserMode();
3282 InitReg(MISCREG_CBAR)
3283 .unimplemented()
3284 .allPrivileges().exceptUserMode().writes(0);
3285 InitReg(MISCREG_HTTBR)
3286 .hyp().monNonSecure();
3287 InitReg(MISCREG_VTTBR)
3288 .hyp().monNonSecure();
3289 InitReg(MISCREG_CNTPCT)
3290 .reads(1);
3291 InitReg(MISCREG_CNTVCT)
3292 .unverifiable()
3293 .reads(1);
3294 InitReg(MISCREG_CNTP_CVAL)
3295 .banked();
3296 InitReg(MISCREG_CNTP_CVAL_NS)
3297 .bankedChild()
3298 .allPrivileges()
3299 .privSecure(!aarch32EL3)
3300 .monSecure(0);
3301 InitReg(MISCREG_CNTP_CVAL_S)
3302 .bankedChild()
3303 .secure().user(1);
3304 InitReg(MISCREG_CNTV_CVAL)
3305 .allPrivileges();
3306 InitReg(MISCREG_CNTVOFF)
3307 .hyp().monNonSecure();
3308 InitReg(MISCREG_CNTHP_CVAL)
3309 .hypWrite().monNonSecureRead();
3310 InitReg(MISCREG_CPUMERRSR)
3311 .unimplemented()
3312 .allPrivileges().exceptUserMode();
3313 InitReg(MISCREG_L2MERRSR)
3314 .unimplemented()
3315 .warnNotFail()
3316 .allPrivileges().exceptUserMode();
3317
3318 // AArch64 registers (Op0=2);
3319 InitReg(MISCREG_MDCCINT_EL1)
3320 .allPrivileges();
3321 InitReg(MISCREG_OSDTRRX_EL1)
3322 .allPrivileges()
3323 .mapsTo(MISCREG_DBGDTRRXext);
3324 InitReg(MISCREG_MDSCR_EL1)
3325 .allPrivileges()
3326 .mapsTo(MISCREG_DBGDSCRext);
3327 InitReg(MISCREG_OSDTRTX_EL1)
3328 .allPrivileges()
3329 .mapsTo(MISCREG_DBGDTRTXext);
3330 InitReg(MISCREG_OSECCR_EL1)
3331 .allPrivileges()
3332 .mapsTo(MISCREG_DBGOSECCR);
3333 InitReg(MISCREG_DBGBVR0_EL1)
3334 .allPrivileges()
3335 .mapsTo(MISCREG_DBGBVR0 /*, MISCREG_DBGBXVR0 */);
3336 InitReg(MISCREG_DBGBVR1_EL1)
3337 .allPrivileges()
3338 .mapsTo(MISCREG_DBGBVR1 /*, MISCREG_DBGBXVR1 */);
3339 InitReg(MISCREG_DBGBVR2_EL1)
3340 .allPrivileges()
3341 .mapsTo(MISCREG_DBGBVR2 /*, MISCREG_DBGBXVR2 */);
3342 InitReg(MISCREG_DBGBVR3_EL1)
3343 .allPrivileges()
3344 .mapsTo(MISCREG_DBGBVR3 /*, MISCREG_DBGBXVR3 */);
3345 InitReg(MISCREG_DBGBVR4_EL1)
3346 .allPrivileges()
3347 .mapsTo(MISCREG_DBGBVR4 /*, MISCREG_DBGBXVR4 */);
3348 InitReg(MISCREG_DBGBVR5_EL1)
3349 .allPrivileges()
3350 .mapsTo(MISCREG_DBGBVR5 /*, MISCREG_DBGBXVR5 */);
3351 InitReg(MISCREG_DBGBCR0_EL1)
3352 .allPrivileges()
3353 .mapsTo(MISCREG_DBGBCR0);
3354 InitReg(MISCREG_DBGBCR1_EL1)
3355 .allPrivileges()
3356 .mapsTo(MISCREG_DBGBCR1);
3357 InitReg(MISCREG_DBGBCR2_EL1)
3358 .allPrivileges()
3359 .mapsTo(MISCREG_DBGBCR2);
3360 InitReg(MISCREG_DBGBCR3_EL1)
3361 .allPrivileges()
3362 .mapsTo(MISCREG_DBGBCR3);
3363 InitReg(MISCREG_DBGBCR4_EL1)
3364 .allPrivileges()
3365 .mapsTo(MISCREG_DBGBCR4);
3366 InitReg(MISCREG_DBGBCR5_EL1)
3367 .allPrivileges()
3368 .mapsTo(MISCREG_DBGBCR5);
3369 InitReg(MISCREG_DBGWVR0_EL1)
3370 .allPrivileges()
3371 .mapsTo(MISCREG_DBGWVR0);
3372 InitReg(MISCREG_DBGWVR1_EL1)
3373 .allPrivileges()
3374 .mapsTo(MISCREG_DBGWVR1);
3375 InitReg(MISCREG_DBGWVR2_EL1)
3376 .allPrivileges()
3377 .mapsTo(MISCREG_DBGWVR2);
3378 InitReg(MISCREG_DBGWVR3_EL1)
3379 .allPrivileges()
3380 .mapsTo(MISCREG_DBGWVR3);
3381 InitReg(MISCREG_DBGWCR0_EL1)
3382 .allPrivileges()
3383 .mapsTo(MISCREG_DBGWCR0);
3384 InitReg(MISCREG_DBGWCR1_EL1)
3385 .allPrivileges()
3386 .mapsTo(MISCREG_DBGWCR1);
3387 InitReg(MISCREG_DBGWCR2_EL1)
3388 .allPrivileges()
3389 .mapsTo(MISCREG_DBGWCR2);
3390 InitReg(MISCREG_DBGWCR3_EL1)
3391 .allPrivileges()
3392 .mapsTo(MISCREG_DBGWCR3);
3393 InitReg(MISCREG_MDCCSR_EL0)
3394 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3395 .mapsTo(MISCREG_DBGDSCRint);
3396 InitReg(MISCREG_MDDTR_EL0)
3397 .allPrivileges();
3398 InitReg(MISCREG_MDDTRTX_EL0)
3399 .allPrivileges();
3400 InitReg(MISCREG_MDDTRRX_EL0)
3401 .allPrivileges();
3402 InitReg(MISCREG_DBGVCR32_EL2)
3403 .allPrivileges()
3404 .mapsTo(MISCREG_DBGVCR);
3405 InitReg(MISCREG_MDRAR_EL1)
3406 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3407 .mapsTo(MISCREG_DBGDRAR);
3408 InitReg(MISCREG_OSLAR_EL1)
3409 .allPrivileges().monSecureRead(0).monNonSecureRead(0)
3410 .mapsTo(MISCREG_DBGOSLAR);
3411 InitReg(MISCREG_OSLSR_EL1)
3412 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3413 .mapsTo(MISCREG_DBGOSLSR);
3414 InitReg(MISCREG_OSDLR_EL1)
3415 .allPrivileges()
3416 .mapsTo(MISCREG_DBGOSDLR);
3417 InitReg(MISCREG_DBGPRCR_EL1)
3418 .allPrivileges()
3419 .mapsTo(MISCREG_DBGPRCR);
3420 InitReg(MISCREG_DBGCLAIMSET_EL1)
3421 .allPrivileges()
3422 .mapsTo(MISCREG_DBGCLAIMSET);
3423 InitReg(MISCREG_DBGCLAIMCLR_EL1)
3424 .allPrivileges()
3425 .mapsTo(MISCREG_DBGCLAIMCLR);
3426 InitReg(MISCREG_DBGAUTHSTATUS_EL1)
3427 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3428 .mapsTo(MISCREG_DBGAUTHSTATUS);
3429 InitReg(MISCREG_TEECR32_EL1);
3430 InitReg(MISCREG_TEEHBR32_EL1);
3431
3432 // AArch64 registers (Op0=1,3);
3433 InitReg(MISCREG_MIDR_EL1)
3434 .allPrivileges().exceptUserMode().writes(0);
3435 InitReg(MISCREG_MPIDR_EL1)
3436 .allPrivileges().exceptUserMode().writes(0);
3437 InitReg(MISCREG_REVIDR_EL1)
3438 .allPrivileges().exceptUserMode().writes(0);
3439 InitReg(MISCREG_ID_PFR0_EL1)
3440 .allPrivileges().exceptUserMode().writes(0)
3441 .mapsTo(MISCREG_ID_PFR0);
3442 InitReg(MISCREG_ID_PFR1_EL1)
3443 .allPrivileges().exceptUserMode().writes(0)
3444 .mapsTo(MISCREG_ID_PFR1);
3445 InitReg(MISCREG_ID_DFR0_EL1)
3446 .allPrivileges().exceptUserMode().writes(0)
3447 .mapsTo(MISCREG_ID_DFR0);
3448 InitReg(MISCREG_ID_AFR0_EL1)
3449 .allPrivileges().exceptUserMode().writes(0)
3450 .mapsTo(MISCREG_ID_AFR0);
3451 InitReg(MISCREG_ID_MMFR0_EL1)
3452 .allPrivileges().exceptUserMode().writes(0)
3453 .mapsTo(MISCREG_ID_MMFR0);
3454 InitReg(MISCREG_ID_MMFR1_EL1)
3455 .allPrivileges().exceptUserMode().writes(0)
3456 .mapsTo(MISCREG_ID_MMFR1);
3457 InitReg(MISCREG_ID_MMFR2_EL1)
3458 .allPrivileges().exceptUserMode().writes(0)
3459 .mapsTo(MISCREG_ID_MMFR2);
3460 InitReg(MISCREG_ID_MMFR3_EL1)
3461 .allPrivileges().exceptUserMode().writes(0)
3462 .mapsTo(MISCREG_ID_MMFR3);
3463 InitReg(MISCREG_ID_ISAR0_EL1)
3464 .allPrivileges().exceptUserMode().writes(0)
3465 .mapsTo(MISCREG_ID_ISAR0);
3466 InitReg(MISCREG_ID_ISAR1_EL1)
3467 .allPrivileges().exceptUserMode().writes(0)
3468 .mapsTo(MISCREG_ID_ISAR1);
3469 InitReg(MISCREG_ID_ISAR2_EL1)
3470 .allPrivileges().exceptUserMode().writes(0)
3471 .mapsTo(MISCREG_ID_ISAR2);
3472 InitReg(MISCREG_ID_ISAR3_EL1)
3473 .allPrivileges().exceptUserMode().writes(0)
3474 .mapsTo(MISCREG_ID_ISAR3);
3475 InitReg(MISCREG_ID_ISAR4_EL1)
3476 .allPrivileges().exceptUserMode().writes(0)
3477 .mapsTo(MISCREG_ID_ISAR4);
3478 InitReg(MISCREG_ID_ISAR5_EL1)
3479 .allPrivileges().exceptUserMode().writes(0)
3480 .mapsTo(MISCREG_ID_ISAR5);
3481 InitReg(MISCREG_MVFR0_EL1)
3482 .allPrivileges().exceptUserMode().writes(0);
3483 InitReg(MISCREG_MVFR1_EL1)
3484 .allPrivileges().exceptUserMode().writes(0);
3485 InitReg(MISCREG_MVFR2_EL1)
3486 .allPrivileges().exceptUserMode().writes(0);
3487 InitReg(MISCREG_ID_AA64PFR0_EL1)
3488 .allPrivileges().exceptUserMode().writes(0);
3489 InitReg(MISCREG_ID_AA64PFR1_EL1)
3490 .allPrivileges().exceptUserMode().writes(0);
3491 InitReg(MISCREG_ID_AA64DFR0_EL1)
3492 .allPrivileges().exceptUserMode().writes(0);
3493 InitReg(MISCREG_ID_AA64DFR1_EL1)
3494 .allPrivileges().exceptUserMode().writes(0);
3495 InitReg(MISCREG_ID_AA64AFR0_EL1)
3496 .allPrivileges().exceptUserMode().writes(0);
3497 InitReg(MISCREG_ID_AA64AFR1_EL1)
3498 .allPrivileges().exceptUserMode().writes(0);
3499 InitReg(MISCREG_ID_AA64ISAR0_EL1)
3500 .allPrivileges().exceptUserMode().writes(0);
3501 InitReg(MISCREG_ID_AA64ISAR1_EL1)
3502 .allPrivileges().exceptUserMode().writes(0);
3503 InitReg(MISCREG_ID_AA64MMFR0_EL1)
3504 .allPrivileges().exceptUserMode().writes(0);
3505 InitReg(MISCREG_ID_AA64MMFR1_EL1)
3506 .allPrivileges().exceptUserMode().writes(0);
3507 InitReg(MISCREG_CCSIDR_EL1)
3508 .allPrivileges().exceptUserMode().writes(0);
3509 InitReg(MISCREG_CLIDR_EL1)
3510 .allPrivileges().exceptUserMode().writes(0);
3511 InitReg(MISCREG_AIDR_EL1)
3512 .allPrivileges().exceptUserMode().writes(0);
3513 InitReg(MISCREG_CSSELR_EL1)
3514 .allPrivileges().exceptUserMode()
3515 .mapsTo(MISCREG_CSSELR_NS);
3516 InitReg(MISCREG_CTR_EL0)
3517 .reads(1);
3518 InitReg(MISCREG_DCZID_EL0)
3519 .reads(1);
3520 InitReg(MISCREG_VPIDR_EL2)
3521 .hyp().mon()
3522 .mapsTo(MISCREG_VPIDR);
3523 InitReg(MISCREG_VMPIDR_EL2)
3524 .hyp().mon()
3525 .mapsTo(MISCREG_VMPIDR);
3526 InitReg(MISCREG_SCTLR_EL1)
3527 .allPrivileges().exceptUserMode()
3528 .mapsTo(MISCREG_SCTLR_NS);
3529 InitReg(MISCREG_ACTLR_EL1)
3530 .allPrivileges().exceptUserMode()
3531 .mapsTo(MISCREG_ACTLR_NS);
3532 InitReg(MISCREG_CPACR_EL1)
3533 .allPrivileges().exceptUserMode()
3534 .mapsTo(MISCREG_CPACR);
3535 InitReg(MISCREG_SCTLR_EL2)
3536 .hyp().mon()
3537 .mapsTo(MISCREG_HSCTLR);
3538 InitReg(MISCREG_ACTLR_EL2)
3539 .hyp().mon()
3540 .mapsTo(MISCREG_HACTLR);
3541 InitReg(MISCREG_HCR_EL2)
3542 .hyp().mon()
3543 .mapsTo(MISCREG_HCR /*, MISCREG_HCR2*/);
3544 InitReg(MISCREG_MDCR_EL2)
3545 .hyp().mon()
3546 .mapsTo(MISCREG_HDCR);
3547 InitReg(MISCREG_CPTR_EL2)
3548 .hyp().mon()
3549 .mapsTo(MISCREG_HCPTR);
3550 InitReg(MISCREG_HSTR_EL2)
3551 .hyp().mon()
3552 .mapsTo(MISCREG_HSTR);
3553 InitReg(MISCREG_HACR_EL2)
3554 .hyp().mon()
3555 .mapsTo(MISCREG_HACR);
3556 InitReg(MISCREG_SCTLR_EL3)
3557 .mon();
3558 InitReg(MISCREG_ACTLR_EL3)
3559 .mon();
3560 InitReg(MISCREG_SCR_EL3)
3561 .mon()
3562 .mapsTo(MISCREG_SCR); // NAM D7-2005
3563 InitReg(MISCREG_SDER32_EL3)
3564 .mon()
3565 .mapsTo(MISCREG_SDER);
3566 InitReg(MISCREG_CPTR_EL3)
3567 .mon();
3568 InitReg(MISCREG_MDCR_EL3)
3569 .mon();
3570 InitReg(MISCREG_TTBR0_EL1)
3571 .allPrivileges().exceptUserMode()
3572 .mapsTo(MISCREG_TTBR0_NS);
3573 InitReg(MISCREG_TTBR1_EL1)
3574 .allPrivileges().exceptUserMode()
3575 .mapsTo(MISCREG_TTBR1_NS);
3576 InitReg(MISCREG_TCR_EL1)
3577 .allPrivileges().exceptUserMode()
3578 .mapsTo(MISCREG_TTBCR_NS);
3579 InitReg(MISCREG_TTBR0_EL2)
3580 .hyp().mon()
3581 .mapsTo(MISCREG_HTTBR);
3582 InitReg(MISCREG_TTBR1_EL2)
3583 .hyp().mon();
3584 InitReg(MISCREG_TCR_EL2)
3585 .hyp().mon()
3586 .mapsTo(MISCREG_HTCR);
3587 InitReg(MISCREG_VTTBR_EL2)
3588 .hyp().mon()
3589 .mapsTo(MISCREG_VTTBR);
3590 InitReg(MISCREG_VTCR_EL2)
3591 .hyp().mon()
3592 .mapsTo(MISCREG_VTCR);
3593 InitReg(MISCREG_TTBR0_EL3)
3594 .mon();
3595 InitReg(MISCREG_TCR_EL3)
3596 .mon();
3597 InitReg(MISCREG_DACR32_EL2)
3598 .hyp().mon()
3599 .mapsTo(MISCREG_DACR_NS);
3600 InitReg(MISCREG_SPSR_EL1)
3601 .allPrivileges().exceptUserMode()
3602 .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
3603 InitReg(MISCREG_ELR_EL1)
3604 .allPrivileges().exceptUserMode();
3605 InitReg(MISCREG_SP_EL0)
3606 .allPrivileges().exceptUserMode();
3607 InitReg(MISCREG_SPSEL)
3608 .allPrivileges().exceptUserMode();
3609 InitReg(MISCREG_CURRENTEL)
3610 .allPrivileges().exceptUserMode().writes(0);
3611 InitReg(MISCREG_NZCV)
3612 .allPrivileges();
3613 InitReg(MISCREG_DAIF)
3614 .allPrivileges();
3615 InitReg(MISCREG_FPCR)
3616 .allPrivileges();
3617 InitReg(MISCREG_FPSR)
3618 .allPrivileges();
3619 InitReg(MISCREG_DSPSR_EL0)
3620 .allPrivileges();
3621 InitReg(MISCREG_DLR_EL0)
3622 .allPrivileges();
3623 InitReg(MISCREG_SPSR_EL2)
3624 .hyp().mon()
3625 .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2
3626 InitReg(MISCREG_ELR_EL2)
3627 .hyp().mon();
3628 InitReg(MISCREG_SP_EL1)
3629 .hyp().mon();
3630 InitReg(MISCREG_SPSR_IRQ_AA64)
3631 .hyp().mon();
3632 InitReg(MISCREG_SPSR_ABT_AA64)
3633 .hyp().mon();
3634 InitReg(MISCREG_SPSR_UND_AA64)
3635 .hyp().mon();
3636 InitReg(MISCREG_SPSR_FIQ_AA64)
3637 .hyp().mon();
3638 InitReg(MISCREG_SPSR_EL3)
3639 .mon()
3640 .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3
3641 InitReg(MISCREG_ELR_EL3)
3642 .mon();
3643 InitReg(MISCREG_SP_EL2)
3644 .mon();
3645 InitReg(MISCREG_AFSR0_EL1)
3646 .allPrivileges().exceptUserMode()
3647 .mapsTo(MISCREG_ADFSR_NS);
3648 InitReg(MISCREG_AFSR1_EL1)
3649 .allPrivileges().exceptUserMode()
3650 .mapsTo(MISCREG_AIFSR_NS);
3651 InitReg(MISCREG_ESR_EL1)
3652 .allPrivileges().exceptUserMode();
3653 InitReg(MISCREG_IFSR32_EL2)
3654 .hyp().mon()
3655 .mapsTo(MISCREG_IFSR_NS);
3656 InitReg(MISCREG_AFSR0_EL2)
3657 .hyp().mon()
3658 .mapsTo(MISCREG_HADFSR);
3659 InitReg(MISCREG_AFSR1_EL2)
3660 .hyp().mon()
3661 .mapsTo(MISCREG_HAIFSR);
3662 InitReg(MISCREG_ESR_EL2)
3663 .hyp().mon()
3664 .mapsTo(MISCREG_HSR);
3665 InitReg(MISCREG_FPEXC32_EL2)
3666 .hyp().mon().mapsTo(MISCREG_FPEXC);
3667 InitReg(MISCREG_AFSR0_EL3)
3668 .mon();
3669 InitReg(MISCREG_AFSR1_EL3)
3670 .mon();
3671 InitReg(MISCREG_ESR_EL3)
3672 .mon();
3673 InitReg(MISCREG_FAR_EL1)
3674 .allPrivileges().exceptUserMode()
3675 .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
3676 InitReg(MISCREG_FAR_EL2)
3677 .hyp().mon()
3678 .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR);
3679 InitReg(MISCREG_HPFAR_EL2)
3680 .hyp().mon()
3681 .mapsTo(MISCREG_HPFAR);
3682 InitReg(MISCREG_FAR_EL3)
3683 .mon();
3684 InitReg(MISCREG_IC_IALLUIS)
3685 .warnNotFail()
3686 .writes(1).exceptUserMode();
3687 InitReg(MISCREG_PAR_EL1)
3688 .allPrivileges().exceptUserMode()
3689 .mapsTo(MISCREG_PAR_NS);
3690 InitReg(MISCREG_IC_IALLU)
3691 .warnNotFail()
3692 .writes(1).exceptUserMode();
3693 InitReg(MISCREG_DC_IVAC_Xt)
3694 .warnNotFail()
3695 .writes(1).exceptUserMode();
3696 InitReg(MISCREG_DC_ISW_Xt)
3697 .warnNotFail()
3698 .writes(1).exceptUserMode();
3699 InitReg(MISCREG_AT_S1E1R_Xt)
3700 .writes(1).exceptUserMode();
3701 InitReg(MISCREG_AT_S1E1W_Xt)
3702 .writes(1).exceptUserMode();
3703 InitReg(MISCREG_AT_S1E0R_Xt)
3704 .writes(1).exceptUserMode();
3705 InitReg(MISCREG_AT_S1E0W_Xt)
3706 .writes(1).exceptUserMode();
3707 InitReg(MISCREG_DC_CSW_Xt)
3708 .warnNotFail()
3709 .writes(1).exceptUserMode();
3710 InitReg(MISCREG_DC_CISW_Xt)
3711 .warnNotFail()
3712 .writes(1).exceptUserMode();
3713 InitReg(MISCREG_DC_ZVA_Xt)
3714 .warnNotFail()
3715 .writes(1).userSecureWrite(0);
3716 InitReg(MISCREG_IC_IVAU_Xt)
3717 .writes(1);
3718 InitReg(MISCREG_DC_CVAC_Xt)
3719 .warnNotFail()
3720 .writes(1);
3721 InitReg(MISCREG_DC_CVAU_Xt)
3722 .warnNotFail()
3723 .writes(1);
3724 InitReg(MISCREG_DC_CIVAC_Xt)
3725 .warnNotFail()
3726 .writes(1);
3727 InitReg(MISCREG_AT_S1E2R_Xt)
3728 .monNonSecureWrite().hypWrite();
3729 InitReg(MISCREG_AT_S1E2W_Xt)
3730 .monNonSecureWrite().hypWrite();
3731 InitReg(MISCREG_AT_S12E1R_Xt)
3732 .hypWrite().monSecureWrite().monNonSecureWrite();
3733 InitReg(MISCREG_AT_S12E1W_Xt)
3734 .hypWrite().monSecureWrite().monNonSecureWrite();
3735 InitReg(MISCREG_AT_S12E0R_Xt)
3736 .hypWrite().monSecureWrite().monNonSecureWrite();
3737 InitReg(MISCREG_AT_S12E0W_Xt)
3738 .hypWrite().monSecureWrite().monNonSecureWrite();
3739 InitReg(MISCREG_AT_S1E3R_Xt)
3740 .monSecureWrite().monNonSecureWrite();
3741 InitReg(MISCREG_AT_S1E3W_Xt)
3742 .monSecureWrite().monNonSecureWrite();
3743 InitReg(MISCREG_TLBI_VMALLE1IS)
3744 .writes(1).exceptUserMode();
3745 InitReg(MISCREG_TLBI_VAE1IS_Xt)
3746 .writes(1).exceptUserMode();
3747 InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
3748 .writes(1).exceptUserMode();
3749 InitReg(MISCREG_TLBI_VAAE1IS_Xt)
3750 .writes(1).exceptUserMode();
3751 InitReg(MISCREG_TLBI_VALE1IS_Xt)
3752 .writes(1).exceptUserMode();
3753 InitReg(MISCREG_TLBI_VAALE1IS_Xt)
3754 .writes(1).exceptUserMode();
3755 InitReg(MISCREG_TLBI_VMALLE1)
3756 .writes(1).exceptUserMode();
3757 InitReg(MISCREG_TLBI_VAE1_Xt)
3758 .writes(1).exceptUserMode();
3759 InitReg(MISCREG_TLBI_ASIDE1_Xt)
3760 .writes(1).exceptUserMode();
3761 InitReg(MISCREG_TLBI_VAAE1_Xt)
3762 .writes(1).exceptUserMode();
3763 InitReg(MISCREG_TLBI_VALE1_Xt)
3764 .writes(1).exceptUserMode();
3765 InitReg(MISCREG_TLBI_VAALE1_Xt)
3766 .writes(1).exceptUserMode();
3767 InitReg(MISCREG_TLBI_IPAS2E1IS_Xt)
3768 .hypWrite().monSecureWrite().monNonSecureWrite();
3769 InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt)
3770 .hypWrite().monSecureWrite().monNonSecureWrite();
3771 InitReg(MISCREG_TLBI_ALLE2IS)
3772 .monNonSecureWrite().hypWrite();
3773 InitReg(MISCREG_TLBI_VAE2IS_Xt)
3774 .monNonSecureWrite().hypWrite();
3775 InitReg(MISCREG_TLBI_ALLE1IS)
3776 .hypWrite().monSecureWrite().monNonSecureWrite();
3777 InitReg(MISCREG_TLBI_VALE2IS_Xt)
3778 .monNonSecureWrite().hypWrite();
3779 InitReg(MISCREG_TLBI_VMALLS12E1IS)
3780 .hypWrite().monSecureWrite().monNonSecureWrite();
3781 InitReg(MISCREG_TLBI_IPAS2E1_Xt)
3782 .hypWrite().monSecureWrite().monNonSecureWrite();
3783 InitReg(MISCREG_TLBI_IPAS2LE1_Xt)
3784 .hypWrite().monSecureWrite().monNonSecureWrite();
3785 InitReg(MISCREG_TLBI_ALLE2)
3786 .monNonSecureWrite().hypWrite();
3787 InitReg(MISCREG_TLBI_VAE2_Xt)
3788 .monNonSecureWrite().hypWrite();
3789 InitReg(MISCREG_TLBI_ALLE1)
3790 .hypWrite().monSecureWrite().monNonSecureWrite();
3791 InitReg(MISCREG_TLBI_VALE2_Xt)
3792 .monNonSecureWrite().hypWrite();
3793 InitReg(MISCREG_TLBI_VMALLS12E1)
3794 .hypWrite().monSecureWrite().monNonSecureWrite();
3795 InitReg(MISCREG_TLBI_ALLE3IS)
3796 .monSecureWrite().monNonSecureWrite();
3797 InitReg(MISCREG_TLBI_VAE3IS_Xt)
3798 .monSecureWrite().monNonSecureWrite();
3799 InitReg(MISCREG_TLBI_VALE3IS_Xt)
3800 .monSecureWrite().monNonSecureWrite();
3801 InitReg(MISCREG_TLBI_ALLE3)
3802 .monSecureWrite().monNonSecureWrite();
3803 InitReg(MISCREG_TLBI_VAE3_Xt)
3804 .monSecureWrite().monNonSecureWrite();
3805 InitReg(MISCREG_TLBI_VALE3_Xt)
3806 .monSecureWrite().monNonSecureWrite();
3807 InitReg(MISCREG_PMINTENSET_EL1)
3808 .allPrivileges().exceptUserMode()
3809 .mapsTo(MISCREG_PMINTENSET);
3810 InitReg(MISCREG_PMINTENCLR_EL1)
3811 .allPrivileges().exceptUserMode()
3812 .mapsTo(MISCREG_PMINTENCLR);
3813 InitReg(MISCREG_PMCR_EL0)
3814 .allPrivileges()
3815 .mapsTo(MISCREG_PMCR);
3816 InitReg(MISCREG_PMCNTENSET_EL0)
3817 .allPrivileges()
3818 .mapsTo(MISCREG_PMCNTENSET);
3819 InitReg(MISCREG_PMCNTENCLR_EL0)
3820 .allPrivileges()
3821 .mapsTo(MISCREG_PMCNTENCLR);
3822 InitReg(MISCREG_PMOVSCLR_EL0)
3823 .allPrivileges();
3824 // .mapsTo(MISCREG_PMOVSCLR);
3825 InitReg(MISCREG_PMSWINC_EL0)
3826 .writes(1).user()
3827 .mapsTo(MISCREG_PMSWINC);
3828 InitReg(MISCREG_PMSELR_EL0)
3829 .allPrivileges()
3830 .mapsTo(MISCREG_PMSELR);
3831 InitReg(MISCREG_PMCEID0_EL0)
3832 .reads(1).user()
3833 .mapsTo(MISCREG_PMCEID0);
3834 InitReg(MISCREG_PMCEID1_EL0)
3835 .reads(1).user()
3836 .mapsTo(MISCREG_PMCEID1);
3837 InitReg(MISCREG_PMCCNTR_EL0)
3838 .allPrivileges()
3839 .mapsTo(MISCREG_PMCCNTR);
3840 InitReg(MISCREG_PMXEVTYPER_EL0)
3841 .allPrivileges()
3842 .mapsTo(MISCREG_PMXEVTYPER);
3843 InitReg(MISCREG_PMCCFILTR_EL0)
3844 .allPrivileges();
3845 InitReg(MISCREG_PMXEVCNTR_EL0)
3846 .allPrivileges()
3847 .mapsTo(MISCREG_PMXEVCNTR);
3848 InitReg(MISCREG_PMUSERENR_EL0)
3849 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
3850 .mapsTo(MISCREG_PMUSERENR);
3851 InitReg(MISCREG_PMOVSSET_EL0)
3852 .allPrivileges()
3853 .mapsTo(MISCREG_PMOVSSET);
3854 InitReg(MISCREG_MAIR_EL1)
3855 .allPrivileges().exceptUserMode()
3856 .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
3857 InitReg(MISCREG_AMAIR_EL1)
3858 .allPrivileges().exceptUserMode()
3859 .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
3860 InitReg(MISCREG_MAIR_EL2)
3861 .hyp().mon()
3862 .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1);
3863 InitReg(MISCREG_AMAIR_EL2)
3864 .hyp().mon()
3865 .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1);
3866 InitReg(MISCREG_MAIR_EL3)
3867 .mon();
3868 InitReg(MISCREG_AMAIR_EL3)
3869 .mon();
3870 InitReg(MISCREG_L2CTLR_EL1)
3871 .allPrivileges().exceptUserMode();
3872 InitReg(MISCREG_L2ECTLR_EL1)
3873 .allPrivileges().exceptUserMode();
3874 InitReg(MISCREG_VBAR_EL1)
3875 .allPrivileges().exceptUserMode()
3876 .mapsTo(MISCREG_VBAR_NS);
3877 InitReg(MISCREG_RVBAR_EL1)
3878 .allPrivileges().exceptUserMode().writes(0);
3879 InitReg(MISCREG_ISR_EL1)
3880 .allPrivileges().exceptUserMode().writes(0);
3881 InitReg(MISCREG_VBAR_EL2)
3882 .hyp().mon()
3883 .mapsTo(MISCREG_HVBAR);
3884 InitReg(MISCREG_RVBAR_EL2)
3885 .mon().hyp().writes(0);
3886 InitReg(MISCREG_VBAR_EL3)
3887 .mon();
3888 InitReg(MISCREG_RVBAR_EL3)
3889 .mon().writes(0);
3890 InitReg(MISCREG_RMR_EL3)
3891 .mon();
3892 InitReg(MISCREG_CONTEXTIDR_EL1)
3893 .allPrivileges().exceptUserMode()
3894 .mapsTo(MISCREG_CONTEXTIDR_NS);
3895 InitReg(MISCREG_TPIDR_EL1)
3896 .allPrivileges().exceptUserMode()
3897 .mapsTo(MISCREG_TPIDRPRW_NS);
3898 InitReg(MISCREG_TPIDR_EL0)
3899 .allPrivileges()
3900 .mapsTo(MISCREG_TPIDRURW_NS);
3901 InitReg(MISCREG_TPIDRRO_EL0)
3902 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
3903 .mapsTo(MISCREG_TPIDRURO_NS);
3904 InitReg(MISCREG_TPIDR_EL2)
3905 .hyp().mon()
3906 .mapsTo(MISCREG_HTPIDR);
3907 InitReg(MISCREG_TPIDR_EL3)
3908 .mon();
3909 InitReg(MISCREG_CNTKCTL_EL1)
3910 .allPrivileges().exceptUserMode()
3911 .mapsTo(MISCREG_CNTKCTL);
3912 InitReg(MISCREG_CNTFRQ_EL0)
3913 .reads(1).mon()
3914 .mapsTo(MISCREG_CNTFRQ);
3915 InitReg(MISCREG_CNTPCT_EL0)
3916 .reads(1)
3917 .mapsTo(MISCREG_CNTPCT); /* 64b */
3918 InitReg(MISCREG_CNTVCT_EL0)
3919 .unverifiable()
3920 .reads(1)
3921 .mapsTo(MISCREG_CNTVCT); /* 64b */
3922 InitReg(MISCREG_CNTP_TVAL_EL0)
3923 .allPrivileges()
3924 .mapsTo(MISCREG_CNTP_TVAL_NS);
3925 InitReg(MISCREG_CNTP_CTL_EL0)
3926 .allPrivileges()
3927 .mapsTo(MISCREG_CNTP_CTL_NS);
3928 InitReg(MISCREG_CNTP_CVAL_EL0)
3929 .allPrivileges()
3930 .mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b */
3931 InitReg(MISCREG_CNTV_TVAL_EL0)
3932 .allPrivileges()
3933 .mapsTo(MISCREG_CNTV_TVAL);
3934 InitReg(MISCREG_CNTV_CTL_EL0)
3935 .allPrivileges()
3936 .mapsTo(MISCREG_CNTV_CTL);
3937 InitReg(MISCREG_CNTV_CVAL_EL0)
3938 .allPrivileges()
3939 .mapsTo(MISCREG_CNTV_CVAL); /* 64b */
3940 InitReg(MISCREG_PMEVCNTR0_EL0)
3941 .allPrivileges();
3942 // .mapsTo(MISCREG_PMEVCNTR0);
3943 InitReg(MISCREG_PMEVCNTR1_EL0)
3944 .allPrivileges();
3945 // .mapsTo(MISCREG_PMEVCNTR1);
3946 InitReg(MISCREG_PMEVCNTR2_EL0)
3947 .allPrivileges();
3948 // .mapsTo(MISCREG_PMEVCNTR2);
3949 InitReg(MISCREG_PMEVCNTR3_EL0)
3950 .allPrivileges();
3951 // .mapsTo(MISCREG_PMEVCNTR3);
3952 InitReg(MISCREG_PMEVCNTR4_EL0)
3953 .allPrivileges();
3954 // .mapsTo(MISCREG_PMEVCNTR4);
3955 InitReg(MISCREG_PMEVCNTR5_EL0)
3956 .allPrivileges();
3957 // .mapsTo(MISCREG_PMEVCNTR5);
3958 InitReg(MISCREG_PMEVTYPER0_EL0)
3959 .allPrivileges();
3960 // .mapsTo(MISCREG_PMEVTYPER0);
3961 InitReg(MISCREG_PMEVTYPER1_EL0)
3962 .allPrivileges();
3963 // .mapsTo(MISCREG_PMEVTYPER1);
3964 InitReg(MISCREG_PMEVTYPER2_EL0)
3965 .allPrivileges();
3966 // .mapsTo(MISCREG_PMEVTYPER2);
3967 InitReg(MISCREG_PMEVTYPER3_EL0)
3968 .allPrivileges();
3969 // .mapsTo(MISCREG_PMEVTYPER3);
3970 InitReg(MISCREG_PMEVTYPER4_EL0)
3971 .allPrivileges();
3972 // .mapsTo(MISCREG_PMEVTYPER4);
3973 InitReg(MISCREG_PMEVTYPER5_EL0)
3974 .allPrivileges();
3975 // .mapsTo(MISCREG_PMEVTYPER5);
3976 InitReg(MISCREG_CNTVOFF_EL2)
3977 .hyp().mon()
3978 .mapsTo(MISCREG_CNTVOFF); /* 64b */
3979 InitReg(MISCREG_CNTHCTL_EL2)
3980 .mon().hyp()
3981 .mapsTo(MISCREG_CNTHCTL);
3982 InitReg(MISCREG_CNTHP_TVAL_EL2)
3983 .mon().hyp()
3984 .mapsTo(MISCREG_CNTHP_TVAL);
3985 InitReg(MISCREG_CNTHP_CTL_EL2)
3986 .mon().hyp()
3987 .mapsTo(MISCREG_CNTHP_CTL);
3988 InitReg(MISCREG_CNTHP_CVAL_EL2)
3989 .mon().hyp()
3990 .mapsTo(MISCREG_CNTHP_CVAL); /* 64b */
3991 InitReg(MISCREG_CNTPS_TVAL_EL1)
3992 .mon().privSecure();
3993 InitReg(MISCREG_CNTPS_CTL_EL1)
3994 .mon().privSecure();
3995 InitReg(MISCREG_CNTPS_CVAL_EL1)
3996 .mon().privSecure();
3997 InitReg(MISCREG_IL1DATA0_EL1)
3998 .allPrivileges().exceptUserMode();
3999 InitReg(MISCREG_IL1DATA1_EL1)
4000 .allPrivileges().exceptUserMode();
4001 InitReg(MISCREG_IL1DATA2_EL1)
4002 .allPrivileges().exceptUserMode();
4003 InitReg(MISCREG_IL1DATA3_EL1)
4004 .allPrivileges().exceptUserMode();
4005 InitReg(MISCREG_DL1DATA0_EL1)
4006 .allPrivileges().exceptUserMode();
4007 InitReg(MISCREG_DL1DATA1_EL1)
4008 .allPrivileges().exceptUserMode();
4009 InitReg(MISCREG_DL1DATA2_EL1)
4010 .allPrivileges().exceptUserMode();
4011 InitReg(MISCREG_DL1DATA3_EL1)
4012 .allPrivileges().exceptUserMode();
4013 InitReg(MISCREG_DL1DATA4_EL1)
4014 .allPrivileges().exceptUserMode();
4015 InitReg(MISCREG_L2ACTLR_EL1)
4016 .allPrivileges().exceptUserMode();
4017 InitReg(MISCREG_CPUACTLR_EL1)
4018 .allPrivileges().exceptUserMode();
4019 InitReg(MISCREG_CPUECTLR_EL1)
4020 .allPrivileges().exceptUserMode();
4021 InitReg(MISCREG_CPUMERRSR_EL1)
4022 .allPrivileges().exceptUserMode();
4023 InitReg(MISCREG_L2MERRSR_EL1)
4024 .unimplemented()
4025 .warnNotFail()
4026 .allPrivileges().exceptUserMode();
4027 InitReg(MISCREG_CBAR_EL1)
4028 .allPrivileges().exceptUserMode().writes(0);
4029 InitReg(MISCREG_CONTEXTIDR_EL2)
4030 .mon().hyp();
4031 InitReg(MISCREG_CNTHV_CTL_EL2)
4032 .mon().hyp();
4033 InitReg(MISCREG_CNTHV_CVAL_EL2)
4034 .mon().hyp();
4035 InitReg(MISCREG_CNTHV_TVAL_EL2)
4036 .mon().hyp();
4037
4038 // Dummy registers
4039 InitReg(MISCREG_NOP)
4040 .allPrivileges();
4041 InitReg(MISCREG_RAZ)
4042 .allPrivileges().exceptUserMode().writes(0);
4043 InitReg(MISCREG_CP14_UNIMPL)
4044 .unimplemented()
4045 .warnNotFail();
4046 InitReg(MISCREG_CP15_UNIMPL)
4047 .unimplemented()
4048 .warnNotFail();
4049 InitReg(MISCREG_UNKNOWN);
4050 InitReg(MISCREG_IMPDEF_UNIMPL)
4051 .unimplemented()
4052 .warnNotFail(impdefAsNop);
4053
4054 // RAS extension (unimplemented)
4055 InitReg(MISCREG_ERRIDR_EL1)
4056 .unimplemented()
4057 .warnNotFail();
4058 InitReg(MISCREG_ERRSELR_EL1)
4059 .unimplemented()
4060 .warnNotFail();
4061 InitReg(MISCREG_ERXFR_EL1)
4062 .unimplemented()
4063 .warnNotFail();
4064 InitReg(MISCREG_ERXCTLR_EL1)
4065 .unimplemented()
4066 .warnNotFail();
4067 InitReg(MISCREG_ERXSTATUS_EL1)
4068 .unimplemented()
4069 .warnNotFail();
4070 InitReg(MISCREG_ERXADDR_EL1)
4071 .unimplemented()
4072 .warnNotFail();
4073 InitReg(MISCREG_ERXMISC0_EL1)
4074 .unimplemented()
4075 .warnNotFail();
4076 InitReg(MISCREG_ERXMISC1_EL1)
4077 .unimplemented()
4078 .warnNotFail();
4079 InitReg(MISCREG_DISR_EL1)
4080 .unimplemented()
4081 .warnNotFail();
4082 InitReg(MISCREG_VSESR_EL2)
4083 .unimplemented()
4084 .warnNotFail();
4085 InitReg(MISCREG_VDISR_EL2)
4086 .unimplemented()
4087 .warnNotFail();
4088
4089 // Register mappings for some unimplemented registers:
4090 // ESR_EL1 -> DFSR
4091 // RMR_EL1 -> RMR
4092 // RMR_EL2 -> HRMR
4093 // DBGDTR_EL0 -> DBGDTR{R or T}Xint
4094 // DBGDTRRX_EL0 -> DBGDTRRXint
4095 // DBGDTRTX_EL0 -> DBGDTRRXint
4096 // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
4097
4098 completed = true;
4099 }
4100
4101 } // namespace ArmISA