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42 #ifndef __ARCH_ARM_MISCREGS_HH__
43 #define __ARCH_ARM_MISCREGS_HH__
45 #include "base/bitunion.hh"
46 #include "base/compiler.hh"
82 MISCREG_FPSCR_QC, // Cumulative saturation flag
83 MISCREG_FPSCR_EXC, // Cumulative FP exception flags
92 MISCREG_DBGDIDR = MISCREG_CP14_START,
101 MISCREG_DBGDTRRX_EXT,
103 MISCREG_DBGDTRTX_EXT,
120 MISCREG_DBGAUTHSTATUS,
127 MISCREG_SCTLR = MISCREG_CP15_START,
216 MISCREG_CP15_UNIMP_START,
217 MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
240 MISCREG_NOP = MISCREG_CP15_END,
246 MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1,
247 unsigned crm, unsigned opc2);
249 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
250 unsigned crm, unsigned opc2);
253 const char * const miscRegName[] = {
254 "cpsr", "cpsr_q", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
255 "spsr_mon", "spsr_und", "spsr_abt",
256 "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc",
258 "sctlr_rst", "sev_mailbox",
291 "sctlr", "dccisw", "dccimvac", "dccmvac",
292 "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
293 "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
294 "clidr", "ccsidr", "csselr",
295 "icialluis", "iciallu", "icimvau",
296 "bpimva", "bpiallis", "bpiall",
297 "midr", "ttbr0", "ttbr1", "tlbtr", "dacr",
298 "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais",
299 "itlbiall", "itlbimva", "itlbiasid",
300 "dtlbiall", "dtlbimva", "dtlbiasid",
301 "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
302 "dfsr", "ifsr", "dfar", "ifar", "mpidr",
303 "prrr", "nmrr", "ttbcr", "id_pfr0", "ctr",
304 "scr", "sder", "par",
305 "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
306 "v2powpr", "v2powpw", "v2powur", "v2powuw",
307 "id_mmfr0", "id_mmfr2", "id_mmfr3", "actlr", "pmcr", "pmccntr",
308 "pmcntenset", "pmcntenclr", "pmovsr",
309 "pmswinc", "pmselr", "pmceid0",
310 "pmceid1", "pmc_other", "pmxevcntr",
311 "pmuserenr", "pmintenset", "pmintenclr",
312 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
313 "lockflag", "lockaddr", "id_pfr1",
315 // Unimplemented below
317 "id_dfr0", "id_afr0",
319 "aidr", "adfsr", "aifsr",
320 "dcimvac", "dcisw", "mccsw",
323 "vbar", "mvbar", "isr", "fceidr", "l2latency",
328 static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
329 "The miscRegName array and NUM_MISCREGS are inconsistent.");
348 // This mask selects bits of the CPSR that actually go in the CondCodes
349 // integer register to allow renaming.
350 static const uint32_t CondCodesMask = 0xF00F0000;
351 static const uint32_t CpsrMaskQ = 0x08000000;
354 Bitfield<31> ie; // Instruction endianness
355 Bitfield<30> te; // Thumb Exception Enable
356 Bitfield<29> afe; // Access flag enable
357 Bitfield<28> tre; // TEX Remap bit
358 Bitfield<27> nmfi;// Non-maskable fast interrupts enable
359 Bitfield<25> ee; // Exception Endianness bit
360 Bitfield<24> ve; // Interrupt vectors enable
361 Bitfield<23> xp; // Extended page table enable bit
362 Bitfield<22> u; // Alignment (now unused)
363 Bitfield<21> fi; // Fast interrupts configuration enable
364 Bitfield<19> dz; // Divide by Zero fault enable bit
365 Bitfield<18> rao2;// Read as one
366 Bitfield<17> br; // Background region bit
367 Bitfield<16> rao3;// Read as one
368 Bitfield<14> rr; // Round robin cache replacement
369 Bitfield<13> v; // Base address for exception vectors
370 Bitfield<12> i; // instruction cache enable
371 Bitfield<11> z; // branch prediction enable bit
372 Bitfield<10> sw; // Enable swp/swpb
373 Bitfield<9,8> rs; // deprecated protection bits
374 Bitfield<6,3> rao4;// Read as one
375 Bitfield<7> b; // Endianness support (unused)
376 Bitfield<2> c; // Cache enable bit
377 Bitfield<1> a; // Alignment fault checking
378 Bitfield<0> m; // MMU enable bit
387 Bitfield<11, 10> cp5;
388 Bitfield<13, 12> cp6;
389 Bitfield<15, 14> cp7;
390 Bitfield<17, 16> cp8;
391 Bitfield<19, 18> cp9;
392 Bitfield<21, 20> cp10;
393 Bitfield<23, 22> cp11;
394 Bitfield<25, 24> cp12;
395 Bitfield<27, 26> cp13;
396 Bitfield<29, 28> rsvd;
402 Bitfield<3, 0> fsLow;
403 Bitfield<7, 4> domain;
422 Bitfield<18, 16> len;
423 Bitfield<21, 20> stride;
424 Bitfield<23, 22> rMode;
435 // This mask selects bits of the FPSCR that actually go in the FpCondCodes
436 // integer register to allow renaming.
437 static const uint32_t FpCondCodesMask = 0xF0000000;
438 // This mask selects the cumulative FP exception flags of the FPSCR.
439 static const uint32_t FpscrExcMask = 0x0000009F;
440 // This mask selects the cumulative saturation flag of the FPSCR.
441 static const uint32_t FpscrQcMask = 0x08000000;
446 Bitfield<29, 0> subArchDefined;
450 Bitfield<3, 0> advSimdRegisters;
451 Bitfield<7, 4> singlePrecision;
452 Bitfield<11, 8> doublePrecision;
453 Bitfield<15, 12> vfpExceptionTrapping;
454 Bitfield<19, 16> divide;
455 Bitfield<23, 20> squareRoot;
456 Bitfield<27, 24> shortVectors;
457 Bitfield<31, 28> roundingModes;
461 Bitfield<3, 0> flushToZero;
462 Bitfield<7, 4> defaultNaN;
463 Bitfield<11, 8> advSimdLoadStore;
464 Bitfield<15, 12> advSimdInteger;
465 Bitfield<19, 16> advSimdSinglePrecision;
466 Bitfield<23, 20> advSimdHalfPrecision;
467 Bitfield<27, 24> vfpHalfPrecision;
468 Bitfield<31, 28> raz;
513 BitUnion32(CONTEXTIDR)
515 Bitfield<31,8> procid;
516 EndBitUnion(CONTEXTIDR)
519 Bitfield<2,0> sataRAMLatency;
520 Bitfield<4,3> reserved_4_3;
521 Bitfield<5> dataRAMSetup;
522 Bitfield<8,6> tagRAMLatency;
523 Bitfield<9> tagRAMSetup;
524 Bitfield<11,10> dataRAMSlice;
525 Bitfield<12> tagRAMSlice;
526 Bitfield<20,13> reserved_20_13;
527 Bitfield<21> eccandParityEnable;
528 Bitfield<22> reserved_22;
529 Bitfield<23> interptCtrlPresent;
530 Bitfield<25,24> numCPUs;
531 Bitfield<30,26> reserved_30_26;
532 Bitfield<31> l2rstDISABLE_monitor;
536 Bitfield<3,0> iCacheLineSize;
537 Bitfield<13,4> raz_13_4;
538 Bitfield<15,14> l1IndexPolicy;
539 Bitfield<19,16> dCacheLineSize;
543 Bitfield<31,29> format;
547 #endif // __ARCH_ARM_MISCREGS_HH__