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42 #ifndef __ARCH_ARM_MISCREGS_HH__
43 #define __ARCH_ARM_MISCREGS_HH__
45 #include "base/bitunion.hh"
81 MISCREG_FPSCR_QC, // Cumulative saturation flag
82 MISCREG_FPSCR_EXC, // Cumulative FP exception flags
91 MISCREG_SCTLR = MISCREG_CP15_START,
181 MISCREG_CP15_UNIMP_START,
182 MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
205 MISCREG_NOP = MISCREG_CP15_END,
211 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
212 unsigned crm, unsigned opc2);
214 const char * const miscRegName[NUM_MISCREGS] = {
215 "cpsr", "cpsr_q", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
216 "spsr_mon", "spsr_und", "spsr_abt",
217 "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc",
219 "sctlr_rst", "sev_mailbox",
220 "sctlr", "dccisw", "dccimvac", "dccmvac",
221 "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
222 "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
223 "clidr", "ccsidr", "csselr",
224 "icialluis", "iciallu", "icimvau",
225 "bpimva", "bpiallis", "bpiall",
226 "midr", "ttbr0", "ttbr1", "tlbtr", "dacr",
227 "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais",
228 "itlbiall", "itlbimva", "itlbiasid",
229 "dtlbiall", "dtlbimva", "dtlbiasid",
230 "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
231 "dfsr", "ifsr", "dfar", "ifar", "mpidr",
232 "prrr", "nmrr", "ttbcr", "id_pfr0", "ctr",
233 "scr", "sder", "par",
234 "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
235 "v2powpr", "v2powpw", "v2powur", "v2powuw",
236 "id_mmfr0", "id_mmfr2", "id_mmfr3", "actlr", "pmcr", "pmccntr",
237 "pmcntenset", "pmcntenclr", "pmovsr",
238 "pmswinc", "pmselr", "pmceid0",
239 "pmceid1", "pmc_other", "pmxevcntr",
240 "pmuserenr", "pmintenset", "pmintenclr",
241 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
242 "cpsr_mode", "lockflag", "lockaddr", "id_pfr1",
244 // Unimplemented below
246 "id_dfr0", "id_afr0",
248 "aidr", "adfsr", "aifsr",
249 "dcimvac", "dcisw", "mccsw",
252 "vbar", "mvbar", "isr", "fceidr", "l2latency",
274 // This mask selects bits of the CPSR that actually go in the CondCodes
275 // integer register to allow renaming.
276 static const uint32_t CondCodesMask = 0xF00F0000;
277 static const uint32_t CpsrMaskQ = 0x08000000;
280 Bitfield<31> ie; // Instruction endianness
281 Bitfield<30> te; // Thumb Exception Enable
282 Bitfield<29> afe; // Access flag enable
283 Bitfield<28> tre; // TEX Remap bit
284 Bitfield<27> nmfi;// Non-maskable fast interrupts enable
285 Bitfield<25> ee; // Exception Endianness bit
286 Bitfield<24> ve; // Interrupt vectors enable
287 Bitfield<23> xp; // Extended page table enable bit
288 Bitfield<22> u; // Alignment (now unused)
289 Bitfield<21> fi; // Fast interrupts configuration enable
290 Bitfield<19> dz; // Divide by Zero fault enable bit
291 Bitfield<18> rao2;// Read as one
292 Bitfield<17> br; // Background region bit
293 Bitfield<16> rao3;// Read as one
294 Bitfield<14> rr; // Round robin cache replacement
295 Bitfield<13> v; // Base address for exception vectors
296 Bitfield<12> i; // instruction cache enable
297 Bitfield<11> z; // branch prediction enable bit
298 Bitfield<10> sw; // Enable swp/swpb
299 Bitfield<9,8> rs; // deprecated protection bits
300 Bitfield<6,3> rao4;// Read as one
301 Bitfield<7> b; // Endianness support (unused)
302 Bitfield<2> c; // Cache enable bit
303 Bitfield<1> a; // Alignment fault checking
304 Bitfield<0> m; // MMU enable bit
313 Bitfield<11, 10> cp5;
314 Bitfield<13, 12> cp6;
315 Bitfield<15, 14> cp7;
316 Bitfield<17, 16> cp8;
317 Bitfield<19, 18> cp9;
318 Bitfield<21, 20> cp10;
319 Bitfield<23, 22> cp11;
320 Bitfield<25, 24> cp12;
321 Bitfield<27, 26> cp13;
322 Bitfield<29, 28> rsvd;
328 Bitfield<3, 0> fsLow;
329 Bitfield<7, 4> domain;
348 Bitfield<18, 16> len;
349 Bitfield<21, 20> stride;
350 Bitfield<23, 22> rMode;
361 // This mask selects bits of the FPSCR that actually go in the FpCondCodes
362 // integer register to allow renaming.
363 static const uint32_t FpCondCodesMask = 0xF0000000;
364 // This mask selects the cumulative FP exception flags of the FPSCR.
365 static const uint32_t FpscrExcMask = 0x0000009F;
366 // This mask selects the cumulative saturation flag of the FPSCR.
367 static const uint32_t FpscrQcMask = 0x08000000;
372 Bitfield<29, 0> subArchDefined;
376 Bitfield<3, 0> advSimdRegisters;
377 Bitfield<7, 4> singlePrecision;
378 Bitfield<11, 8> doublePrecision;
379 Bitfield<15, 12> vfpExceptionTrapping;
380 Bitfield<19, 16> divide;
381 Bitfield<23, 20> squareRoot;
382 Bitfield<27, 24> shortVectors;
383 Bitfield<31, 28> roundingModes;
387 Bitfield<3, 0> flushToZero;
388 Bitfield<7, 4> defaultNaN;
389 Bitfield<11, 8> advSimdLoadStore;
390 Bitfield<15, 12> advSimdInteger;
391 Bitfield<19, 16> advSimdSinglePrecision;
392 Bitfield<23, 20> advSimdHalfPrecision;
393 Bitfield<27, 24> vfpHalfPrecision;
394 Bitfield<31, 28> raz;
439 BitUnion32(CONTEXTIDR)
441 Bitfield<31,8> procid;
442 EndBitUnion(CONTEXTIDR)
445 Bitfield<2,0> sataRAMLatency;
446 Bitfield<4,3> reserved_4_3;
447 Bitfield<5> dataRAMSetup;
448 Bitfield<8,6> tagRAMLatency;
449 Bitfield<9> tagRAMSetup;
450 Bitfield<11,10> dataRAMSlice;
451 Bitfield<12> tagRAMSlice;
452 Bitfield<20,13> reserved_20_13;
453 Bitfield<21> eccandParityEnable;
454 Bitfield<22> reserved_22;
455 Bitfield<23> interptCtrlPresent;
456 Bitfield<25,24> numCPUs;
457 Bitfield<30,26> reserved_30_26;
458 Bitfield<31> l2rstDISABLE_monitor;
463 #endif // __ARCH_ARM_MISCREGS_HH__