src/arch/arm/miscregs.hh

   1 /*
   2  * Copyright (c) 2010-2020 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2009 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
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  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #ifndef __ARCH_ARM_MISCREGS_HH__
  42 #define __ARCH_ARM_MISCREGS_HH__
  43
  44 #include <bitset>
  45 #include <tuple>
  46
  47 #include "arch/arm/miscregs_types.hh"
  48 #include "base/compiler.hh"
  49 #include "dev/arm/generic_timer_miscregs_types.hh"
  50
  51 class ThreadContext;
  52
  53
  54 namespace ArmISA
  55 {
  56     enum MiscRegIndex {
  57         MISCREG_CPSR = 0,
  58         MISCREG_SPSR,
  59         MISCREG_SPSR_FIQ,
  60         MISCREG_SPSR_IRQ,
  61         MISCREG_SPSR_SVC,
  62         MISCREG_SPSR_MON,
  63         MISCREG_SPSR_ABT,
  64         MISCREG_SPSR_HYP,
  65         MISCREG_SPSR_UND,
  66         MISCREG_ELR_HYP,
  67         MISCREG_FPSID,
  68         MISCREG_FPSCR,
  69         MISCREG_MVFR1,
  70         MISCREG_MVFR0,
  71         MISCREG_FPEXC,
  72
  73         // Helper registers
  74         MISCREG_CPSR_MODE,
  75         MISCREG_CPSR_Q,
  76         MISCREG_FPSCR_EXC,
  77         MISCREG_FPSCR_QC,
  78         MISCREG_LOCKADDR,
  79         MISCREG_LOCKFLAG,
  80         MISCREG_PRRR_MAIR0,
  81         MISCREG_PRRR_MAIR0_NS,
  82         MISCREG_PRRR_MAIR0_S,
  83         MISCREG_NMRR_MAIR1,
  84         MISCREG_NMRR_MAIR1_NS,
  85         MISCREG_NMRR_MAIR1_S,
  86         MISCREG_PMXEVTYPER_PMCCFILTR,
  87         MISCREG_SCTLR_RST,
  88         MISCREG_SEV_MAILBOX,
  89
  90         // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control)
  91         MISCREG_DBGDIDR,
  92         MISCREG_DBGDSCRint,
  93         MISCREG_DBGDCCINT,
  94         MISCREG_DBGDTRTXint,
  95         MISCREG_DBGDTRRXint,
  96         MISCREG_DBGWFAR,
  97         MISCREG_DBGVCR,
  98         MISCREG_DBGDTRRXext,
  99         MISCREG_DBGDSCRext,
 100         MISCREG_DBGDTRTXext,
 101         MISCREG_DBGOSECCR,
 102         MISCREG_DBGBVR0,
 103         MISCREG_DBGBVR1,
 104         MISCREG_DBGBVR2,
 105         MISCREG_DBGBVR3,
 106         MISCREG_DBGBVR4,
 107         MISCREG_DBGBVR5,
 108         MISCREG_DBGBCR0,
 109         MISCREG_DBGBCR1,
 110         MISCREG_DBGBCR2,
 111         MISCREG_DBGBCR3,
 112         MISCREG_DBGBCR4,
 113         MISCREG_DBGBCR5,
 114         MISCREG_DBGWVR0,
 115         MISCREG_DBGWVR1,
 116         MISCREG_DBGWVR2,
 117         MISCREG_DBGWVR3,
 118         MISCREG_DBGWCR0,
 119         MISCREG_DBGWCR1,
 120         MISCREG_DBGWCR2,
 121         MISCREG_DBGWCR3,
 122         MISCREG_DBGDRAR,
 123         MISCREG_DBGBXVR4,
 124         MISCREG_DBGBXVR5,
 125         MISCREG_DBGOSLAR,
 126         MISCREG_DBGOSLSR,
 127         MISCREG_DBGOSDLR,
 128         MISCREG_DBGPRCR,
 129         MISCREG_DBGDSAR,
 130         MISCREG_DBGCLAIMSET,
 131         MISCREG_DBGCLAIMCLR,
 132         MISCREG_DBGAUTHSTATUS,
 133         MISCREG_DBGDEVID2,
 134         MISCREG_DBGDEVID1,
 135         MISCREG_DBGDEVID0,
 136         MISCREG_TEECR,  // not in ARM DDI 0487A.b+
 137         MISCREG_JIDR,
 138         MISCREG_TEEHBR, // not in ARM DDI 0487A.b+
 139         MISCREG_JOSCR,
 140         MISCREG_JMCR,
 141
 142         // AArch32 CP15 registers (system control)
 143         MISCREG_MIDR,
 144         MISCREG_CTR,
 145         MISCREG_TCMTR,
 146         MISCREG_TLBTR,
 147         MISCREG_MPIDR,
 148         MISCREG_REVIDR,
 149         MISCREG_ID_PFR0,
 150         MISCREG_ID_PFR1,
 151         MISCREG_ID_DFR0,
 152         MISCREG_ID_AFR0,
 153         MISCREG_ID_MMFR0,
 154         MISCREG_ID_MMFR1,
 155         MISCREG_ID_MMFR2,
 156         MISCREG_ID_MMFR3,
 157         MISCREG_ID_ISAR0,
 158         MISCREG_ID_ISAR1,
 159         MISCREG_ID_ISAR2,
 160         MISCREG_ID_ISAR3,
 161         MISCREG_ID_ISAR4,
 162         MISCREG_ID_ISAR5,
 163         MISCREG_CCSIDR,
 164         MISCREG_CLIDR,
 165         MISCREG_AIDR,
 166         MISCREG_CSSELR,
 167         MISCREG_CSSELR_NS,
 168         MISCREG_CSSELR_S,
 169         MISCREG_VPIDR,
 170         MISCREG_VMPIDR,
 171         MISCREG_SCTLR,
 172         MISCREG_SCTLR_NS,
 173         MISCREG_SCTLR_S,
 174         MISCREG_ACTLR,
 175         MISCREG_ACTLR_NS,
 176         MISCREG_ACTLR_S,
 177         MISCREG_CPACR,
 178         MISCREG_SCR,
 179         MISCREG_SDER,
 180         MISCREG_NSACR,
 181         MISCREG_HSCTLR,
 182         MISCREG_HACTLR,
 183         MISCREG_HCR,
 184         MISCREG_HCR2,
 185         MISCREG_HDCR,
 186         MISCREG_HCPTR,
 187         MISCREG_HSTR,
 188         MISCREG_HACR,
 189         MISCREG_TTBR0,
 190         MISCREG_TTBR0_NS,
 191         MISCREG_TTBR0_S,
 192         MISCREG_TTBR1,
 193         MISCREG_TTBR1_NS,
 194         MISCREG_TTBR1_S,
 195         MISCREG_TTBCR,
 196         MISCREG_TTBCR_NS,
 197         MISCREG_TTBCR_S,
 198         MISCREG_HTCR,
 199         MISCREG_VTCR,
 200         MISCREG_DACR,
 201         MISCREG_DACR_NS,
 202         MISCREG_DACR_S,
 203         MISCREG_DFSR,
 204         MISCREG_DFSR_NS,
 205         MISCREG_DFSR_S,
 206         MISCREG_IFSR,
 207         MISCREG_IFSR_NS,
 208         MISCREG_IFSR_S,
 209         MISCREG_ADFSR,
 210         MISCREG_ADFSR_NS,
 211         MISCREG_ADFSR_S,
 212         MISCREG_AIFSR,
 213         MISCREG_AIFSR_NS,
 214         MISCREG_AIFSR_S,
 215         MISCREG_HADFSR,
 216         MISCREG_HAIFSR,
 217         MISCREG_HSR,
 218         MISCREG_DFAR,
 219         MISCREG_DFAR_NS,
 220         MISCREG_DFAR_S,
 221         MISCREG_IFAR,
 222         MISCREG_IFAR_NS,
 223         MISCREG_IFAR_S,
 224         MISCREG_HDFAR,
 225         MISCREG_HIFAR,
 226         MISCREG_HPFAR,
 227         MISCREG_ICIALLUIS,
 228         MISCREG_BPIALLIS,
 229         MISCREG_PAR,
 230         MISCREG_PAR_NS,
 231         MISCREG_PAR_S,
 232         MISCREG_ICIALLU,
 233         MISCREG_ICIMVAU,
 234         MISCREG_CP15ISB,
 235         MISCREG_BPIALL,
 236         MISCREG_BPIMVA,
 237         MISCREG_DCIMVAC,
 238         MISCREG_DCISW,
 239         MISCREG_ATS1CPR,
 240         MISCREG_ATS1CPW,
 241         MISCREG_ATS1CUR,
 242         MISCREG_ATS1CUW,
 243         MISCREG_ATS12NSOPR,
 244         MISCREG_ATS12NSOPW,
 245         MISCREG_ATS12NSOUR,
 246         MISCREG_ATS12NSOUW,
 247         MISCREG_DCCMVAC,
 248         MISCREG_DCCSW,
 249         MISCREG_CP15DSB,
 250         MISCREG_CP15DMB,
 251         MISCREG_DCCMVAU,
 252         MISCREG_DCCIMVAC,
 253         MISCREG_DCCISW,
 254         MISCREG_ATS1HR,
 255         MISCREG_ATS1HW,
 256         MISCREG_TLBIALLIS,
 257         MISCREG_TLBIMVAIS,
 258         MISCREG_TLBIASIDIS,
 259         MISCREG_TLBIMVAAIS,
 260         MISCREG_TLBIMVALIS,
 261         MISCREG_TLBIMVAALIS,
 262         MISCREG_ITLBIALL,
 263         MISCREG_ITLBIMVA,
 264         MISCREG_ITLBIASID,
 265         MISCREG_DTLBIALL,
 266         MISCREG_DTLBIMVA,
 267         MISCREG_DTLBIASID,
 268         MISCREG_TLBIALL,
 269         MISCREG_TLBIMVA,
 270         MISCREG_TLBIASID,
 271         MISCREG_TLBIMVAA,
 272         MISCREG_TLBIMVAL,
 273         MISCREG_TLBIMVAAL,
 274         MISCREG_TLBIIPAS2IS,
 275         MISCREG_TLBIIPAS2LIS,
 276         MISCREG_TLBIALLHIS,
 277         MISCREG_TLBIMVAHIS,
 278         MISCREG_TLBIALLNSNHIS,
 279         MISCREG_TLBIMVALHIS,
 280         MISCREG_TLBIIPAS2,
 281         MISCREG_TLBIIPAS2L,
 282         MISCREG_TLBIALLH,
 283         MISCREG_TLBIMVAH,
 284         MISCREG_TLBIALLNSNH,
 285         MISCREG_TLBIMVALH,
 286         MISCREG_PMCR,
 287         MISCREG_PMCNTENSET,
 288         MISCREG_PMCNTENCLR,
 289         MISCREG_PMOVSR,
 290         MISCREG_PMSWINC,
 291         MISCREG_PMSELR,
 292         MISCREG_PMCEID0,
 293         MISCREG_PMCEID1,
 294         MISCREG_PMCCNTR,
 295         MISCREG_PMXEVTYPER,
 296         MISCREG_PMCCFILTR,
 297         MISCREG_PMXEVCNTR,
 298         MISCREG_PMUSERENR,
 299         MISCREG_PMINTENSET,
 300         MISCREG_PMINTENCLR,
 301         MISCREG_PMOVSSET,
 302         MISCREG_L2CTLR,
 303         MISCREG_L2ECTLR,
 304         MISCREG_PRRR,
 305         MISCREG_PRRR_NS,
 306         MISCREG_PRRR_S,
 307         MISCREG_MAIR0,
 308         MISCREG_MAIR0_NS,
 309         MISCREG_MAIR0_S,
 310         MISCREG_NMRR,
 311         MISCREG_NMRR_NS,
 312         MISCREG_NMRR_S,
 313         MISCREG_MAIR1,
 314         MISCREG_MAIR1_NS,
 315         MISCREG_MAIR1_S,
 316         MISCREG_AMAIR0,
 317         MISCREG_AMAIR0_NS,
 318         MISCREG_AMAIR0_S,
 319         MISCREG_AMAIR1,
 320         MISCREG_AMAIR1_NS,
 321         MISCREG_AMAIR1_S,
 322         MISCREG_HMAIR0,
 323         MISCREG_HMAIR1,
 324         MISCREG_HAMAIR0,
 325         MISCREG_HAMAIR1,
 326         MISCREG_VBAR,
 327         MISCREG_VBAR_NS,
 328         MISCREG_VBAR_S,
 329         MISCREG_MVBAR,
 330         MISCREG_RMR,
 331         MISCREG_ISR,
 332         MISCREG_HVBAR,
 333         MISCREG_FCSEIDR,
 334         MISCREG_CONTEXTIDR,
 335         MISCREG_CONTEXTIDR_NS,
 336         MISCREG_CONTEXTIDR_S,
 337         MISCREG_TPIDRURW,
 338         MISCREG_TPIDRURW_NS,
 339         MISCREG_TPIDRURW_S,
 340         MISCREG_TPIDRURO,
 341         MISCREG_TPIDRURO_NS,
 342         MISCREG_TPIDRURO_S,
 343         MISCREG_TPIDRPRW,
 344         MISCREG_TPIDRPRW_NS,
 345         MISCREG_TPIDRPRW_S,
 346         MISCREG_HTPIDR,
 347         // BEGIN Generic Timer (AArch32)
 348         MISCREG_CNTFRQ,
 349         MISCREG_CNTPCT,
 350         MISCREG_CNTVCT,
 351         MISCREG_CNTP_CTL,
 352         MISCREG_CNTP_CTL_NS,
 353         MISCREG_CNTP_CTL_S,
 354         MISCREG_CNTP_CVAL,
 355         MISCREG_CNTP_CVAL_NS,
 356         MISCREG_CNTP_CVAL_S,
 357         MISCREG_CNTP_TVAL,
 358         MISCREG_CNTP_TVAL_NS,
 359         MISCREG_CNTP_TVAL_S,
 360         MISCREG_CNTV_CTL,
 361         MISCREG_CNTV_CVAL,
 362         MISCREG_CNTV_TVAL,
 363         MISCREG_CNTKCTL,
 364         MISCREG_CNTHCTL,
 365         MISCREG_CNTHP_CTL,
 366         MISCREG_CNTHP_CVAL,
 367         MISCREG_CNTHP_TVAL,
 368         MISCREG_CNTVOFF,
 369         // END Generic Timer (AArch32)
 370         MISCREG_IL1DATA0,
 371         MISCREG_IL1DATA1,
 372         MISCREG_IL1DATA2,
 373         MISCREG_IL1DATA3,
 374         MISCREG_DL1DATA0,
 375         MISCREG_DL1DATA1,
 376         MISCREG_DL1DATA2,
 377         MISCREG_DL1DATA3,
 378         MISCREG_DL1DATA4,
 379         MISCREG_RAMINDEX,
 380         MISCREG_L2ACTLR,
 381         MISCREG_CBAR,
 382         MISCREG_HTTBR,
 383         MISCREG_VTTBR,
 384         MISCREG_CPUMERRSR,
 385         MISCREG_L2MERRSR,
 386
 387         // AArch64 registers (Op0=2)
 388         MISCREG_MDCCINT_EL1,
 389         MISCREG_OSDTRRX_EL1,
 390         MISCREG_MDSCR_EL1,
 391         MISCREG_OSDTRTX_EL1,
 392         MISCREG_OSECCR_EL1,
 393         MISCREG_DBGBVR0_EL1,
 394         MISCREG_DBGBVR1_EL1,
 395         MISCREG_DBGBVR2_EL1,
 396         MISCREG_DBGBVR3_EL1,
 397         MISCREG_DBGBVR4_EL1,
 398         MISCREG_DBGBVR5_EL1,
 399         MISCREG_DBGBCR0_EL1,
 400         MISCREG_DBGBCR1_EL1,
 401         MISCREG_DBGBCR2_EL1,
 402         MISCREG_DBGBCR3_EL1,
 403         MISCREG_DBGBCR4_EL1,
 404         MISCREG_DBGBCR5_EL1,
 405         MISCREG_DBGWVR0_EL1,
 406         MISCREG_DBGWVR1_EL1,
 407         MISCREG_DBGWVR2_EL1,
 408         MISCREG_DBGWVR3_EL1,
 409         MISCREG_DBGWCR0_EL1,
 410         MISCREG_DBGWCR1_EL1,
 411         MISCREG_DBGWCR2_EL1,
 412         MISCREG_DBGWCR3_EL1,
 413         MISCREG_MDCCSR_EL0,
 414         MISCREG_MDDTR_EL0,
 415         MISCREG_MDDTRTX_EL0,
 416         MISCREG_MDDTRRX_EL0,
 417         MISCREG_DBGVCR32_EL2,
 418         MISCREG_MDRAR_EL1,
 419         MISCREG_OSLAR_EL1,
 420         MISCREG_OSLSR_EL1,
 421         MISCREG_OSDLR_EL1,
 422         MISCREG_DBGPRCR_EL1,
 423         MISCREG_DBGCLAIMSET_EL1,
 424         MISCREG_DBGCLAIMCLR_EL1,
 425         MISCREG_DBGAUTHSTATUS_EL1,
 426         MISCREG_TEECR32_EL1, // not in ARM DDI 0487A.b+
 427         MISCREG_TEEHBR32_EL1, // not in ARM DDI 0487A.b+
 428
 429         // AArch64 registers (Op0=1,3)
 430         MISCREG_MIDR_EL1,
 431         MISCREG_MPIDR_EL1,
 432         MISCREG_REVIDR_EL1,
 433         MISCREG_ID_PFR0_EL1,
 434         MISCREG_ID_PFR1_EL1,
 435         MISCREG_ID_DFR0_EL1,
 436         MISCREG_ID_AFR0_EL1,
 437         MISCREG_ID_MMFR0_EL1,
 438         MISCREG_ID_MMFR1_EL1,
 439         MISCREG_ID_MMFR2_EL1,
 440         MISCREG_ID_MMFR3_EL1,
 441         MISCREG_ID_ISAR0_EL1,
 442         MISCREG_ID_ISAR1_EL1,
 443         MISCREG_ID_ISAR2_EL1,
 444         MISCREG_ID_ISAR3_EL1,
 445         MISCREG_ID_ISAR4_EL1,
 446         MISCREG_ID_ISAR5_EL1,
 447         MISCREG_MVFR0_EL1,
 448         MISCREG_MVFR1_EL1,
 449         MISCREG_MVFR2_EL1,
 450         MISCREG_ID_AA64PFR0_EL1,
 451         MISCREG_ID_AA64PFR1_EL1,
 452         MISCREG_ID_AA64DFR0_EL1,
 453         MISCREG_ID_AA64DFR1_EL1,
 454         MISCREG_ID_AA64AFR0_EL1,
 455         MISCREG_ID_AA64AFR1_EL1,
 456         MISCREG_ID_AA64ISAR0_EL1,
 457         MISCREG_ID_AA64ISAR1_EL1,
 458         MISCREG_ID_AA64MMFR0_EL1,
 459         MISCREG_ID_AA64MMFR1_EL1,
 460         MISCREG_CCSIDR_EL1,
 461         MISCREG_CLIDR_EL1,
 462         MISCREG_AIDR_EL1,
 463         MISCREG_CSSELR_EL1,
 464         MISCREG_CTR_EL0,
 465         MISCREG_DCZID_EL0,
 466         MISCREG_VPIDR_EL2,
 467         MISCREG_VMPIDR_EL2,
 468         MISCREG_SCTLR_EL1,
 469         MISCREG_ACTLR_EL1,
 470         MISCREG_CPACR_EL1,
 471         MISCREG_SCTLR_EL2,
 472         MISCREG_ACTLR_EL2,
 473         MISCREG_HCR_EL2,
 474         MISCREG_MDCR_EL2,
 475         MISCREG_CPTR_EL2,
 476         MISCREG_HSTR_EL2,
 477         MISCREG_HACR_EL2,
 478         MISCREG_SCTLR_EL3,
 479         MISCREG_ACTLR_EL3,
 480         MISCREG_SCR_EL3,
 481         MISCREG_SDER32_EL3,
 482         MISCREG_CPTR_EL3,
 483         MISCREG_MDCR_EL3,
 484         MISCREG_TTBR0_EL1,
 485         MISCREG_TTBR1_EL1,
 486         MISCREG_TCR_EL1,
 487         MISCREG_TTBR0_EL2,
 488         MISCREG_TCR_EL2,
 489         MISCREG_VTTBR_EL2,
 490         MISCREG_VTCR_EL2,
 491         MISCREG_TTBR0_EL3,
 492         MISCREG_TCR_EL3,
 493         MISCREG_DACR32_EL2,
 494         MISCREG_SPSR_EL1,
 495         MISCREG_ELR_EL1,
 496         MISCREG_SP_EL0,
 497         MISCREG_SPSEL,
 498         MISCREG_CURRENTEL,
 499         MISCREG_NZCV,
 500         MISCREG_DAIF,
 501         MISCREG_FPCR,
 502         MISCREG_FPSR,
 503         MISCREG_DSPSR_EL0,
 504         MISCREG_DLR_EL0,
 505         MISCREG_SPSR_EL2,
 506         MISCREG_ELR_EL2,
 507         MISCREG_SP_EL1,
 508         MISCREG_SPSR_IRQ_AA64,
 509         MISCREG_SPSR_ABT_AA64,
 510         MISCREG_SPSR_UND_AA64,
 511         MISCREG_SPSR_FIQ_AA64,
 512         MISCREG_SPSR_EL3,
 513         MISCREG_ELR_EL3,
 514         MISCREG_SP_EL2,
 515         MISCREG_AFSR0_EL1,
 516         MISCREG_AFSR1_EL1,
 517         MISCREG_ESR_EL1,
 518         MISCREG_IFSR32_EL2,
 519         MISCREG_AFSR0_EL2,
 520         MISCREG_AFSR1_EL2,
 521         MISCREG_ESR_EL2,
 522         MISCREG_FPEXC32_EL2,
 523         MISCREG_AFSR0_EL3,
 524         MISCREG_AFSR1_EL3,
 525         MISCREG_ESR_EL3,
 526         MISCREG_FAR_EL1,
 527         MISCREG_FAR_EL2,
 528         MISCREG_HPFAR_EL2,
 529         MISCREG_FAR_EL3,
 530         MISCREG_IC_IALLUIS,
 531         MISCREG_PAR_EL1,
 532         MISCREG_IC_IALLU,
 533         MISCREG_DC_IVAC_Xt,
 534         MISCREG_DC_ISW_Xt,
 535         MISCREG_AT_S1E1R_Xt,
 536         MISCREG_AT_S1E1W_Xt,
 537         MISCREG_AT_S1E0R_Xt,
 538         MISCREG_AT_S1E0W_Xt,
 539         MISCREG_DC_CSW_Xt,
 540         MISCREG_DC_CISW_Xt,
 541         MISCREG_DC_ZVA_Xt,
 542         MISCREG_IC_IVAU_Xt,
 543         MISCREG_DC_CVAC_Xt,
 544         MISCREG_DC_CVAU_Xt,
 545         MISCREG_DC_CIVAC_Xt,
 546         MISCREG_AT_S1E2R_Xt,
 547         MISCREG_AT_S1E2W_Xt,
 548         MISCREG_AT_S12E1R_Xt,
 549         MISCREG_AT_S12E1W_Xt,
 550         MISCREG_AT_S12E0R_Xt,
 551         MISCREG_AT_S12E0W_Xt,
 552         MISCREG_AT_S1E3R_Xt,
 553         MISCREG_AT_S1E3W_Xt,
 554         MISCREG_TLBI_VMALLE1IS,
 555         MISCREG_TLBI_VAE1IS_Xt,
 556         MISCREG_TLBI_ASIDE1IS_Xt,
 557         MISCREG_TLBI_VAAE1IS_Xt,
 558         MISCREG_TLBI_VALE1IS_Xt,
 559         MISCREG_TLBI_VAALE1IS_Xt,
 560         MISCREG_TLBI_VMALLE1,
 561         MISCREG_TLBI_VAE1_Xt,
 562         MISCREG_TLBI_ASIDE1_Xt,
 563         MISCREG_TLBI_VAAE1_Xt,
 564         MISCREG_TLBI_VALE1_Xt,
 565         MISCREG_TLBI_VAALE1_Xt,
 566         MISCREG_TLBI_IPAS2E1IS_Xt,
 567         MISCREG_TLBI_IPAS2LE1IS_Xt,
 568         MISCREG_TLBI_ALLE2IS,
 569         MISCREG_TLBI_VAE2IS_Xt,
 570         MISCREG_TLBI_ALLE1IS,
 571         MISCREG_TLBI_VALE2IS_Xt,
 572         MISCREG_TLBI_VMALLS12E1IS,
 573         MISCREG_TLBI_IPAS2E1_Xt,
 574         MISCREG_TLBI_IPAS2LE1_Xt,
 575         MISCREG_TLBI_ALLE2,
 576         MISCREG_TLBI_VAE2_Xt,
 577         MISCREG_TLBI_ALLE1,
 578         MISCREG_TLBI_VALE2_Xt,
 579         MISCREG_TLBI_VMALLS12E1,
 580         MISCREG_TLBI_ALLE3IS,
 581         MISCREG_TLBI_VAE3IS_Xt,
 582         MISCREG_TLBI_VALE3IS_Xt,
 583         MISCREG_TLBI_ALLE3,
 584         MISCREG_TLBI_VAE3_Xt,
 585         MISCREG_TLBI_VALE3_Xt,
 586         MISCREG_PMINTENSET_EL1,
 587         MISCREG_PMINTENCLR_EL1,
 588         MISCREG_PMCR_EL0,
 589         MISCREG_PMCNTENSET_EL0,
 590         MISCREG_PMCNTENCLR_EL0,
 591         MISCREG_PMOVSCLR_EL0,
 592         MISCREG_PMSWINC_EL0,
 593         MISCREG_PMSELR_EL0,
 594         MISCREG_PMCEID0_EL0,
 595         MISCREG_PMCEID1_EL0,
 596         MISCREG_PMCCNTR_EL0,
 597         MISCREG_PMXEVTYPER_EL0,
 598         MISCREG_PMCCFILTR_EL0,
 599         MISCREG_PMXEVCNTR_EL0,
 600         MISCREG_PMUSERENR_EL0,
 601         MISCREG_PMOVSSET_EL0,
 602         MISCREG_MAIR_EL1,
 603         MISCREG_AMAIR_EL1,
 604         MISCREG_MAIR_EL2,
 605         MISCREG_AMAIR_EL2,
 606         MISCREG_MAIR_EL3,
 607         MISCREG_AMAIR_EL3,
 608         MISCREG_L2CTLR_EL1,
 609         MISCREG_L2ECTLR_EL1,
 610         MISCREG_VBAR_EL1,
 611         MISCREG_RVBAR_EL1,
 612         MISCREG_ISR_EL1,
 613         MISCREG_VBAR_EL2,
 614         MISCREG_RVBAR_EL2,
 615         MISCREG_VBAR_EL3,
 616         MISCREG_RVBAR_EL3,
 617         MISCREG_RMR_EL3,
 618         MISCREG_CONTEXTIDR_EL1,
 619         MISCREG_TPIDR_EL1,
 620         MISCREG_TPIDR_EL0,
 621         MISCREG_TPIDRRO_EL0,
 622         MISCREG_TPIDR_EL2,
 623         MISCREG_TPIDR_EL3,
 624         // BEGIN Generic Timer (AArch64)
 625         MISCREG_CNTFRQ_EL0,
 626         MISCREG_CNTPCT_EL0,
 627         MISCREG_CNTVCT_EL0,
 628         MISCREG_CNTP_CTL_EL0,
 629         MISCREG_CNTP_CVAL_EL0,
 630         MISCREG_CNTP_TVAL_EL0,
 631         MISCREG_CNTV_CTL_EL0,
 632         MISCREG_CNTV_CVAL_EL0,
 633         MISCREG_CNTV_TVAL_EL0,
 634         MISCREG_CNTP_CTL_EL02,
 635         MISCREG_CNTP_CVAL_EL02,
 636         MISCREG_CNTP_TVAL_EL02,
 637         MISCREG_CNTV_CTL_EL02,
 638         MISCREG_CNTV_CVAL_EL02,
 639         MISCREG_CNTV_TVAL_EL02,
 640         MISCREG_CNTKCTL_EL1,
 641         MISCREG_CNTKCTL_EL12,
 642         MISCREG_CNTPS_CTL_EL1,
 643         MISCREG_CNTPS_CVAL_EL1,
 644         MISCREG_CNTPS_TVAL_EL1,
 645         MISCREG_CNTHCTL_EL2,
 646         MISCREG_CNTHP_CTL_EL2,
 647         MISCREG_CNTHP_CVAL_EL2,
 648         MISCREG_CNTHP_TVAL_EL2,
 649         // IF Armv8.1-VHE
 650         MISCREG_CNTHV_CTL_EL2,
 651         MISCREG_CNTHV_CVAL_EL2,
 652         MISCREG_CNTHV_TVAL_EL2,
 653         // ENDIF Armv8.1-VHE
 654         MISCREG_CNTVOFF_EL2,
 655         // END Generic Timer (AArch64)
 656         MISCREG_PMEVCNTR0_EL0,
 657         MISCREG_PMEVCNTR1_EL0,
 658         MISCREG_PMEVCNTR2_EL0,
 659         MISCREG_PMEVCNTR3_EL0,
 660         MISCREG_PMEVCNTR4_EL0,
 661         MISCREG_PMEVCNTR5_EL0,
 662         MISCREG_PMEVTYPER0_EL0,
 663         MISCREG_PMEVTYPER1_EL0,
 664         MISCREG_PMEVTYPER2_EL0,
 665         MISCREG_PMEVTYPER3_EL0,
 666         MISCREG_PMEVTYPER4_EL0,
 667         MISCREG_PMEVTYPER5_EL0,
 668         MISCREG_IL1DATA0_EL1,
 669         MISCREG_IL1DATA1_EL1,
 670         MISCREG_IL1DATA2_EL1,
 671         MISCREG_IL1DATA3_EL1,
 672         MISCREG_DL1DATA0_EL1,
 673         MISCREG_DL1DATA1_EL1,
 674         MISCREG_DL1DATA2_EL1,
 675         MISCREG_DL1DATA3_EL1,
 676         MISCREG_DL1DATA4_EL1,
 677         MISCREG_L2ACTLR_EL1,
 678         MISCREG_CPUACTLR_EL1,
 679         MISCREG_CPUECTLR_EL1,
 680         MISCREG_CPUMERRSR_EL1,
 681         MISCREG_L2MERRSR_EL1,
 682         MISCREG_CBAR_EL1,
 683         MISCREG_CONTEXTIDR_EL2,
 684
 685         // Introduced in ARMv8.1
 686         MISCREG_TTBR1_EL2,
 687
 688         MISCREG_ID_AA64MMFR2_EL1,
 689
 690         //PAuth Key Regsiters
 691         MISCREG_APDAKeyHi_EL1,
 692         MISCREG_APDAKeyLo_EL1,
 693         MISCREG_APDBKeyHi_EL1,
 694         MISCREG_APDBKeyLo_EL1,
 695         MISCREG_APGAKeyHi_EL1,
 696         MISCREG_APGAKeyLo_EL1,
 697         MISCREG_APIAKeyHi_EL1,
 698         MISCREG_APIAKeyLo_EL1,
 699         MISCREG_APIBKeyHi_EL1,
 700         MISCREG_APIBKeyLo_EL1,
 701
 702         // GICv3, CPU interface
 703         MISCREG_ICC_PMR_EL1,
 704         MISCREG_ICC_IAR0_EL1,
 705         MISCREG_ICC_EOIR0_EL1,
 706         MISCREG_ICC_HPPIR0_EL1,
 707         MISCREG_ICC_BPR0_EL1,
 708         MISCREG_ICC_AP0R0_EL1,
 709         MISCREG_ICC_AP0R1_EL1,
 710         MISCREG_ICC_AP0R2_EL1,
 711         MISCREG_ICC_AP0R3_EL1,
 712         MISCREG_ICC_AP1R0_EL1,
 713         MISCREG_ICC_AP1R0_EL1_NS,
 714         MISCREG_ICC_AP1R0_EL1_S,
 715         MISCREG_ICC_AP1R1_EL1,
 716         MISCREG_ICC_AP1R1_EL1_NS,
 717         MISCREG_ICC_AP1R1_EL1_S,
 718         MISCREG_ICC_AP1R2_EL1,
 719         MISCREG_ICC_AP1R2_EL1_NS,
 720         MISCREG_ICC_AP1R2_EL1_S,
 721         MISCREG_ICC_AP1R3_EL1,
 722         MISCREG_ICC_AP1R3_EL1_NS,
 723         MISCREG_ICC_AP1R3_EL1_S,
 724         MISCREG_ICC_DIR_EL1,
 725         MISCREG_ICC_RPR_EL1,
 726         MISCREG_ICC_SGI1R_EL1,
 727         MISCREG_ICC_ASGI1R_EL1,
 728         MISCREG_ICC_SGI0R_EL1,
 729         MISCREG_ICC_IAR1_EL1,
 730         MISCREG_ICC_EOIR1_EL1,
 731         MISCREG_ICC_HPPIR1_EL1,
 732         MISCREG_ICC_BPR1_EL1,
 733         MISCREG_ICC_BPR1_EL1_NS,
 734         MISCREG_ICC_BPR1_EL1_S,
 735         MISCREG_ICC_CTLR_EL1,
 736         MISCREG_ICC_CTLR_EL1_NS,
 737         MISCREG_ICC_CTLR_EL1_S,
 738         MISCREG_ICC_SRE_EL1,
 739         MISCREG_ICC_SRE_EL1_NS,
 740         MISCREG_ICC_SRE_EL1_S,
 741         MISCREG_ICC_IGRPEN0_EL1,
 742         MISCREG_ICC_IGRPEN1_EL1,
 743         MISCREG_ICC_IGRPEN1_EL1_NS,
 744         MISCREG_ICC_IGRPEN1_EL1_S,
 745         MISCREG_ICC_SRE_EL2,
 746         MISCREG_ICC_CTLR_EL3,
 747         MISCREG_ICC_SRE_EL3,
 748         MISCREG_ICC_IGRPEN1_EL3,
 749
 750         // GICv3, CPU interface, virtualization
 751         MISCREG_ICH_AP0R0_EL2,
 752         MISCREG_ICH_AP0R1_EL2,
 753         MISCREG_ICH_AP0R2_EL2,
 754         MISCREG_ICH_AP0R3_EL2,
 755         MISCREG_ICH_AP1R0_EL2,
 756         MISCREG_ICH_AP1R1_EL2,
 757         MISCREG_ICH_AP1R2_EL2,
 758         MISCREG_ICH_AP1R3_EL2,
 759         MISCREG_ICH_HCR_EL2,
 760         MISCREG_ICH_VTR_EL2,
 761         MISCREG_ICH_MISR_EL2,
 762         MISCREG_ICH_EISR_EL2,
 763         MISCREG_ICH_ELRSR_EL2,
 764         MISCREG_ICH_VMCR_EL2,
 765         MISCREG_ICH_LR0_EL2,
 766         MISCREG_ICH_LR1_EL2,
 767         MISCREG_ICH_LR2_EL2,
 768         MISCREG_ICH_LR3_EL2,
 769         MISCREG_ICH_LR4_EL2,
 770         MISCREG_ICH_LR5_EL2,
 771         MISCREG_ICH_LR6_EL2,
 772         MISCREG_ICH_LR7_EL2,
 773         MISCREG_ICH_LR8_EL2,
 774         MISCREG_ICH_LR9_EL2,
 775         MISCREG_ICH_LR10_EL2,
 776         MISCREG_ICH_LR11_EL2,
 777         MISCREG_ICH_LR12_EL2,
 778         MISCREG_ICH_LR13_EL2,
 779         MISCREG_ICH_LR14_EL2,
 780         MISCREG_ICH_LR15_EL2,
 781
 782         MISCREG_ICV_PMR_EL1,
 783         MISCREG_ICV_IAR0_EL1,
 784         MISCREG_ICV_EOIR0_EL1,
 785         MISCREG_ICV_HPPIR0_EL1,
 786         MISCREG_ICV_BPR0_EL1,
 787         MISCREG_ICV_AP0R0_EL1,
 788         MISCREG_ICV_AP0R1_EL1,
 789         MISCREG_ICV_AP0R2_EL1,
 790         MISCREG_ICV_AP0R3_EL1,
 791         MISCREG_ICV_AP1R0_EL1,
 792         MISCREG_ICV_AP1R0_EL1_NS,
 793         MISCREG_ICV_AP1R0_EL1_S,
 794         MISCREG_ICV_AP1R1_EL1,
 795         MISCREG_ICV_AP1R1_EL1_NS,
 796         MISCREG_ICV_AP1R1_EL1_S,
 797         MISCREG_ICV_AP1R2_EL1,
 798         MISCREG_ICV_AP1R2_EL1_NS,
 799         MISCREG_ICV_AP1R2_EL1_S,
 800         MISCREG_ICV_AP1R3_EL1,
 801         MISCREG_ICV_AP1R3_EL1_NS,
 802         MISCREG_ICV_AP1R3_EL1_S,
 803         MISCREG_ICV_DIR_EL1,
 804         MISCREG_ICV_RPR_EL1,
 805         MISCREG_ICV_SGI1R_EL1,
 806         MISCREG_ICV_ASGI1R_EL1,
 807         MISCREG_ICV_SGI0R_EL1,
 808         MISCREG_ICV_IAR1_EL1,
 809         MISCREG_ICV_EOIR1_EL1,
 810         MISCREG_ICV_HPPIR1_EL1,
 811         MISCREG_ICV_BPR1_EL1,
 812         MISCREG_ICV_BPR1_EL1_NS,
 813         MISCREG_ICV_BPR1_EL1_S,
 814         MISCREG_ICV_CTLR_EL1,
 815         MISCREG_ICV_CTLR_EL1_NS,
 816         MISCREG_ICV_CTLR_EL1_S,
 817         MISCREG_ICV_SRE_EL1,
 818         MISCREG_ICV_SRE_EL1_NS,
 819         MISCREG_ICV_SRE_EL1_S,
 820         MISCREG_ICV_IGRPEN0_EL1,
 821         MISCREG_ICV_IGRPEN1_EL1,
 822         MISCREG_ICV_IGRPEN1_EL1_NS,
 823         MISCREG_ICV_IGRPEN1_EL1_S,
 824
 825         MISCREG_ICC_AP0R0,
 826         MISCREG_ICC_AP0R1,
 827         MISCREG_ICC_AP0R2,
 828         MISCREG_ICC_AP0R3,
 829         MISCREG_ICC_AP1R0,
 830         MISCREG_ICC_AP1R0_NS,
 831         MISCREG_ICC_AP1R0_S,
 832         MISCREG_ICC_AP1R1,
 833         MISCREG_ICC_AP1R1_NS,
 834         MISCREG_ICC_AP1R1_S,
 835         MISCREG_ICC_AP1R2,
 836         MISCREG_ICC_AP1R2_NS,
 837         MISCREG_ICC_AP1R2_S,
 838         MISCREG_ICC_AP1R3,
 839         MISCREG_ICC_AP1R3_NS,
 840         MISCREG_ICC_AP1R3_S,
 841         MISCREG_ICC_ASGI1R,
 842         MISCREG_ICC_BPR0,
 843         MISCREG_ICC_BPR1,
 844         MISCREG_ICC_BPR1_NS,
 845         MISCREG_ICC_BPR1_S,
 846         MISCREG_ICC_CTLR,
 847         MISCREG_ICC_CTLR_NS,
 848         MISCREG_ICC_CTLR_S,
 849         MISCREG_ICC_DIR,
 850         MISCREG_ICC_EOIR0,
 851         MISCREG_ICC_EOIR1,
 852         MISCREG_ICC_HPPIR0,
 853         MISCREG_ICC_HPPIR1,
 854         MISCREG_ICC_HSRE,
 855         MISCREG_ICC_IAR0,
 856         MISCREG_ICC_IAR1,
 857         MISCREG_ICC_IGRPEN0,
 858         MISCREG_ICC_IGRPEN1,
 859         MISCREG_ICC_IGRPEN1_NS,
 860         MISCREG_ICC_IGRPEN1_S,
 861         MISCREG_ICC_MCTLR,
 862         MISCREG_ICC_MGRPEN1,
 863         MISCREG_ICC_MSRE,
 864         MISCREG_ICC_PMR,
 865         MISCREG_ICC_RPR,
 866         MISCREG_ICC_SGI0R,
 867         MISCREG_ICC_SGI1R,
 868         MISCREG_ICC_SRE,
 869         MISCREG_ICC_SRE_NS,
 870         MISCREG_ICC_SRE_S,
 871
 872         MISCREG_ICH_AP0R0,
 873         MISCREG_ICH_AP0R1,
 874         MISCREG_ICH_AP0R2,
 875         MISCREG_ICH_AP0R3,
 876         MISCREG_ICH_AP1R0,
 877         MISCREG_ICH_AP1R1,
 878         MISCREG_ICH_AP1R2,
 879         MISCREG_ICH_AP1R3,
 880         MISCREG_ICH_HCR,
 881         MISCREG_ICH_VTR,
 882         MISCREG_ICH_MISR,
 883         MISCREG_ICH_EISR,
 884         MISCREG_ICH_ELRSR,
 885         MISCREG_ICH_VMCR,
 886         MISCREG_ICH_LR0,
 887         MISCREG_ICH_LR1,
 888         MISCREG_ICH_LR2,
 889         MISCREG_ICH_LR3,
 890         MISCREG_ICH_LR4,
 891         MISCREG_ICH_LR5,
 892         MISCREG_ICH_LR6,
 893         MISCREG_ICH_LR7,
 894         MISCREG_ICH_LR8,
 895         MISCREG_ICH_LR9,
 896         MISCREG_ICH_LR10,
 897         MISCREG_ICH_LR11,
 898         MISCREG_ICH_LR12,
 899         MISCREG_ICH_LR13,
 900         MISCREG_ICH_LR14,
 901         MISCREG_ICH_LR15,
 902         MISCREG_ICH_LRC0,
 903         MISCREG_ICH_LRC1,
 904         MISCREG_ICH_LRC2,
 905         MISCREG_ICH_LRC3,
 906         MISCREG_ICH_LRC4,
 907         MISCREG_ICH_LRC5,
 908         MISCREG_ICH_LRC6,
 909         MISCREG_ICH_LRC7,
 910         MISCREG_ICH_LRC8,
 911         MISCREG_ICH_LRC9,
 912         MISCREG_ICH_LRC10,
 913         MISCREG_ICH_LRC11,
 914         MISCREG_ICH_LRC12,
 915         MISCREG_ICH_LRC13,
 916         MISCREG_ICH_LRC14,
 917         MISCREG_ICH_LRC15,
 918
 919         // SVE
 920         MISCREG_ID_AA64ZFR0_EL1,
 921         MISCREG_ZCR_EL3,
 922         MISCREG_ZCR_EL2,
 923         MISCREG_ZCR_EL12,
 924         MISCREG_ZCR_EL1,
 925
 926         // NUM_PHYS_MISCREGS specifies the number of actual physical
 927         // registers, not considering the following pseudo-registers
 928         // (dummy registers), like UNKNOWN, CP15_UNIMPL, MISCREG_IMPDEF_UNIMPL.
 929         // Checkpointing should use this physical index when
 930         // saving/restoring register values.
 931         NUM_PHYS_MISCREGS,
 932
 933         // Dummy registers
 934         MISCREG_NOP,
 935         MISCREG_RAZ,
 936         MISCREG_CP14_UNIMPL,
 937         MISCREG_CP15_UNIMPL,
 938         MISCREG_UNKNOWN,
 939
 940         // Implementation defined register: this represent
 941         // a pool of unimplemented registers whose access can throw
 942         // either UNDEFINED or hypervisor trap exception.
 943         MISCREG_IMPDEF_UNIMPL,
 944
 945         // RAS extension (unimplemented)
 946         MISCREG_ERRIDR_EL1,
 947         MISCREG_ERRSELR_EL1,
 948         MISCREG_ERXFR_EL1,
 949         MISCREG_ERXCTLR_EL1,
 950         MISCREG_ERXSTATUS_EL1,
 951         MISCREG_ERXADDR_EL1,
 952         MISCREG_ERXMISC0_EL1,
 953         MISCREG_ERXMISC1_EL1,
 954         MISCREG_DISR_EL1,
 955         MISCREG_VSESR_EL2,
 956         MISCREG_VDISR_EL2,
 957
 958         // PSTATE
 959         MISCREG_PAN,
 960
 961         // Total number of Misc Registers: Physical + Dummy
 962         NUM_MISCREGS
 963     };
 964
 965     enum MiscRegInfo {
 966         MISCREG_IMPLEMENTED,
 967         MISCREG_UNVERIFIABLE,   // Does the value change on every read (e.g. a
 968                                 // arch generic counter)
 969         MISCREG_WARN_NOT_FAIL,  // If MISCREG_IMPLEMENTED is deasserted, it
 970                                 // tells whether the instruction should raise a
 971                                 // warning or fail
 972         MISCREG_MUTEX,  // True if the register corresponds to a pair of
 973                         // mutually exclusive registers
 974         MISCREG_BANKED,  // True if the register is banked between the two
 975                          // security states, and this is the parent node of the
 976                          // two banked registers
 977         MISCREG_BANKED64, // True if the register is banked between the two
 978                           // security states, and this is the parent node of
 979                           // the two banked registers. Used in AA64 only.
 980         MISCREG_BANKED_CHILD, // The entry is one of the child registers that
 981                               // forms a banked set of regs (along with the
 982                               // other child regs)
 983
 984         // Access permissions
 985         // User mode
 986         MISCREG_USR_NS_RD,
 987         MISCREG_USR_NS_WR,
 988         MISCREG_USR_S_RD,
 989         MISCREG_USR_S_WR,
 990         // Privileged modes other than hypervisor or monitor
 991         MISCREG_PRI_NS_RD,
 992         MISCREG_PRI_NS_WR,
 993         MISCREG_PRI_S_RD,
 994         MISCREG_PRI_S_WR,
 995         // Hypervisor mode
 996         MISCREG_HYP_RD,
 997         MISCREG_HYP_WR,
 998         // Hypervisor mode, HCR_EL2.E2H == 1
 999         MISCREG_HYP_E2H_RD,
1000         MISCREG_HYP_E2H_WR,
1001         // Monitor mode, SCR.NS == 0
1002         MISCREG_MON_NS0_RD,
1003         MISCREG_MON_NS0_WR,
1004         // Monitor mode, SCR.NS == 1
1005         MISCREG_MON_NS1_RD,
1006         MISCREG_MON_NS1_WR,
1007         // Monitor mode, HCR_EL2.E2H == 1
1008         MISCREG_MON_E2H_RD,
1009         MISCREG_MON_E2H_WR,
1010
1011         NUM_MISCREG_INFOS
1012     };
1013
1014     extern std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS];
1015
1016     // Decodes 32-bit CP14 registers accessible through MCR/MRC instructions
1017     MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1,
1018                                unsigned crm, unsigned opc2);
1019     MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1,
1020                                      unsigned crn, unsigned crm,
1021                                      unsigned op2);
1022     // Whether a particular AArch64 system register is -always- read only.
1023     bool aarch64SysRegReadOnly(MiscRegIndex miscReg);
1024
1025     // Decodes 32-bit CP15 registers accessible through MCR/MRC instructions
1026     MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
1027                                unsigned crm, unsigned opc2);
1028
1029     // Decodes 64-bit CP15 registers accessible through MCRR/MRRC instructions
1030     MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1);
1031
1032
1033     const char * const miscRegName[] = {
1034         "cpsr",
1035         "spsr",
1036         "spsr_fiq",
1037         "spsr_irq",
1038         "spsr_svc",
1039         "spsr_mon",
1040         "spsr_abt",
1041         "spsr_hyp",
1042         "spsr_und",
1043         "elr_hyp",
1044         "fpsid",
1045         "fpscr",
1046         "mvfr1",
1047         "mvfr0",
1048         "fpexc",
1049
1050         // Helper registers
1051         "cpsr_mode",
1052         "cpsr_q",
1053         "fpscr_exc",
1054         "fpscr_qc",
1055         "lockaddr",
1056         "lockflag",
1057         "prrr_mair0",
1058         "prrr_mair0_ns",
1059         "prrr_mair0_s",
1060         "nmrr_mair1",
1061         "nmrr_mair1_ns",
1062         "nmrr_mair1_s",
1063         "pmxevtyper_pmccfiltr",
1064         "sctlr_rst",
1065         "sev_mailbox",
1066
1067         // AArch32 CP14 registers
1068         "dbgdidr",
1069         "dbgdscrint",
1070         "dbgdccint",
1071         "dbgdtrtxint",
1072         "dbgdtrrxint",
1073         "dbgwfar",
1074         "dbgvcr",
1075         "dbgdtrrxext",
1076         "dbgdscrext",
1077         "dbgdtrtxext",
1078         "dbgoseccr",
1079         "dbgbvr0",
1080         "dbgbvr1",
1081         "dbgbvr2",
1082         "dbgbvr3",
1083         "dbgbvr4",
1084         "dbgbvr5",
1085         "dbgbcr0",
1086         "dbgbcr1",
1087         "dbgbcr2",
1088         "dbgbcr3",
1089         "dbgbcr4",
1090         "dbgbcr5",
1091         "dbgwvr0",
1092         "dbgwvr1",
1093         "dbgwvr2",
1094         "dbgwvr3",
1095         "dbgwcr0",
1096         "dbgwcr1",
1097         "dbgwcr2",
1098         "dbgwcr3",
1099         "dbgdrar",
1100         "dbgbxvr4",
1101         "dbgbxvr5",
1102         "dbgoslar",
1103         "dbgoslsr",
1104         "dbgosdlr",
1105         "dbgprcr",
1106         "dbgdsar",
1107         "dbgclaimset",
1108         "dbgclaimclr",
1109         "dbgauthstatus",
1110         "dbgdevid2",
1111         "dbgdevid1",
1112         "dbgdevid0",
1113         "teecr",
1114         "jidr",
1115         "teehbr",
1116         "joscr",
1117         "jmcr",
1118
1119         // AArch32 CP15 registers
1120         "midr",
1121         "ctr",
1122         "tcmtr",
1123         "tlbtr",
1124         "mpidr",
1125         "revidr",
1126         "id_pfr0",
1127         "id_pfr1",
1128         "id_dfr0",
1129         "id_afr0",
1130         "id_mmfr0",
1131         "id_mmfr1",
1132         "id_mmfr2",
1133         "id_mmfr3",
1134         "id_isar0",
1135         "id_isar1",
1136         "id_isar2",
1137         "id_isar3",
1138         "id_isar4",
1139         "id_isar5",
1140         "ccsidr",
1141         "clidr",
1142         "aidr",
1143         "csselr",
1144         "csselr_ns",
1145         "csselr_s",
1146         "vpidr",
1147         "vmpidr",
1148         "sctlr",
1149         "sctlr_ns",
1150         "sctlr_s",
1151         "actlr",
1152         "actlr_ns",
1153         "actlr_s",
1154         "cpacr",
1155         "scr",
1156         "sder",
1157         "nsacr",
1158         "hsctlr",
1159         "hactlr",
1160         "hcr",
1161         "hcr2",
1162         "hdcr",
1163         "hcptr",
1164         "hstr",
1165         "hacr",
1166         "ttbr0",
1167         "ttbr0_ns",
1168         "ttbr0_s",
1169         "ttbr1",
1170         "ttbr1_ns",
1171         "ttbr1_s",
1172         "ttbcr",
1173         "ttbcr_ns",
1174         "ttbcr_s",
1175         "htcr",
1176         "vtcr",
1177         "dacr",
1178         "dacr_ns",
1179         "dacr_s",
1180         "dfsr",
1181         "dfsr_ns",
1182         "dfsr_s",
1183         "ifsr",
1184         "ifsr_ns",
1185         "ifsr_s",
1186         "adfsr",
1187         "adfsr_ns",
1188         "adfsr_s",
1189         "aifsr",
1190         "aifsr_ns",
1191         "aifsr_s",
1192         "hadfsr",
1193         "haifsr",
1194         "hsr",
1195         "dfar",
1196         "dfar_ns",
1197         "dfar_s",
1198         "ifar",
1199         "ifar_ns",
1200         "ifar_s",
1201         "hdfar",
1202         "hifar",
1203         "hpfar",
1204         "icialluis",
1205         "bpiallis",
1206         "par",
1207         "par_ns",
1208         "par_s",
1209         "iciallu",
1210         "icimvau",
1211         "cp15isb",
1212         "bpiall",
1213         "bpimva",
1214         "dcimvac",
1215         "dcisw",
1216         "ats1cpr",
1217         "ats1cpw",
1218         "ats1cur",
1219         "ats1cuw",
1220         "ats12nsopr",
1221         "ats12nsopw",
1222         "ats12nsour",
1223         "ats12nsouw",
1224         "dccmvac",
1225         "dccsw",
1226         "cp15dsb",
1227         "cp15dmb",
1228         "dccmvau",
1229         "dccimvac",
1230         "dccisw",
1231         "ats1hr",
1232         "ats1hw",
1233         "tlbiallis",
1234         "tlbimvais",
1235         "tlbiasidis",
1236         "tlbimvaais",
1237         "tlbimvalis",
1238         "tlbimvaalis",
1239         "itlbiall",
1240         "itlbimva",
1241         "itlbiasid",
1242         "dtlbiall",
1243         "dtlbimva",
1244         "dtlbiasid",
1245         "tlbiall",
1246         "tlbimva",
1247         "tlbiasid",
1248         "tlbimvaa",
1249         "tlbimval",
1250         "tlbimvaal",
1251         "tlbiipas2is",
1252         "tlbiipas2lis",
1253         "tlbiallhis",
1254         "tlbimvahis",
1255         "tlbiallnsnhis",
1256         "tlbimvalhis",
1257         "tlbiipas2",
1258         "tlbiipas2l",
1259         "tlbiallh",
1260         "tlbimvah",
1261         "tlbiallnsnh",
1262         "tlbimvalh",
1263         "pmcr",
1264         "pmcntenset",
1265         "pmcntenclr",
1266         "pmovsr",
1267         "pmswinc",
1268         "pmselr",
1269         "pmceid0",
1270         "pmceid1",
1271         "pmccntr",
1272         "pmxevtyper",
1273         "pmccfiltr",
1274         "pmxevcntr",
1275         "pmuserenr",
1276         "pmintenset",
1277         "pmintenclr",
1278         "pmovsset",
1279         "l2ctlr",
1280         "l2ectlr",
1281         "prrr",
1282         "prrr_ns",
1283         "prrr_s",
1284         "mair0",
1285         "mair0_ns",
1286         "mair0_s",
1287         "nmrr",
1288         "nmrr_ns",
1289         "nmrr_s",
1290         "mair1",
1291         "mair1_ns",
1292         "mair1_s",
1293         "amair0",
1294         "amair0_ns",
1295         "amair0_s",
1296         "amair1",
1297         "amair1_ns",
1298         "amair1_s",
1299         "hmair0",
1300         "hmair1",
1301         "hamair0",
1302         "hamair1",
1303         "vbar",
1304         "vbar_ns",
1305         "vbar_s",
1306         "mvbar",
1307         "rmr",
1308         "isr",
1309         "hvbar",
1310         "fcseidr",
1311         "contextidr",
1312         "contextidr_ns",
1313         "contextidr_s",
1314         "tpidrurw",
1315         "tpidrurw_ns",
1316         "tpidrurw_s",
1317         "tpidruro",
1318         "tpidruro_ns",
1319         "tpidruro_s",
1320         "tpidrprw",
1321         "tpidrprw_ns",
1322         "tpidrprw_s",
1323         "htpidr",
1324         "cntfrq",
1325         "cntpct",
1326         "cntvct",
1327         "cntp_ctl",
1328         "cntp_ctl_ns",
1329         "cntp_ctl_s",
1330         "cntp_cval",
1331         "cntp_cval_ns",
1332         "cntp_cval_s",
1333         "cntp_tval",
1334         "cntp_tval_ns",
1335         "cntp_tval_s",
1336         "cntv_ctl",
1337         "cntv_cval",
1338         "cntv_tval",
1339         "cntkctl",
1340         "cnthctl",
1341         "cnthp_ctl",
1342         "cnthp_cval",
1343         "cnthp_tval",
1344         "cntvoff",
1345         "il1data0",
1346         "il1data1",
1347         "il1data2",
1348         "il1data3",
1349         "dl1data0",
1350         "dl1data1",
1351         "dl1data2",
1352         "dl1data3",
1353         "dl1data4",
1354         "ramindex",
1355         "l2actlr",
1356         "cbar",
1357         "httbr",
1358         "vttbr",
1359         "cpumerrsr",
1360         "l2merrsr",
1361
1362         // AArch64 registers (Op0=2)
1363         "mdccint_el1",
1364         "osdtrrx_el1",
1365         "mdscr_el1",
1366         "osdtrtx_el1",
1367         "oseccr_el1",
1368         "dbgbvr0_el1",
1369         "dbgbvr1_el1",
1370         "dbgbvr2_el1",
1371         "dbgbvr3_el1",
1372         "dbgbvr4_el1",
1373         "dbgbvr5_el1",
1374         "dbgbcr0_el1",
1375         "dbgbcr1_el1",
1376         "dbgbcr2_el1",
1377         "dbgbcr3_el1",
1378         "dbgbcr4_el1",
1379         "dbgbcr5_el1",
1380         "dbgwvr0_el1",
1381         "dbgwvr1_el1",
1382         "dbgwvr2_el1",
1383         "dbgwvr3_el1",
1384         "dbgwcr0_el1",
1385         "dbgwcr1_el1",
1386         "dbgwcr2_el1",
1387         "dbgwcr3_el1",
1388         "mdccsr_el0",
1389         "mddtr_el0",
1390         "mddtrtx_el0",
1391         "mddtrrx_el0",
1392         "dbgvcr32_el2",
1393         "mdrar_el1",
1394         "oslar_el1",
1395         "oslsr_el1",
1396         "osdlr_el1",
1397         "dbgprcr_el1",
1398         "dbgclaimset_el1",
1399         "dbgclaimclr_el1",
1400         "dbgauthstatus_el1",
1401         "teecr32_el1",
1402         "teehbr32_el1",
1403
1404         // AArch64 registers (Op0=1,3)
1405         "midr_el1",
1406         "mpidr_el1",
1407         "revidr_el1",
1408         "id_pfr0_el1",
1409         "id_pfr1_el1",
1410         "id_dfr0_el1",
1411         "id_afr0_el1",
1412         "id_mmfr0_el1",
1413         "id_mmfr1_el1",
1414         "id_mmfr2_el1",
1415         "id_mmfr3_el1",
1416         "id_isar0_el1",
1417         "id_isar1_el1",
1418         "id_isar2_el1",
1419         "id_isar3_el1",
1420         "id_isar4_el1",
1421         "id_isar5_el1",
1422         "mvfr0_el1",
1423         "mvfr1_el1",
1424         "mvfr2_el1",
1425         "id_aa64pfr0_el1",
1426         "id_aa64pfr1_el1",
1427         "id_aa64dfr0_el1",
1428         "id_aa64dfr1_el1",
1429         "id_aa64afr0_el1",
1430         "id_aa64afr1_el1",
1431         "id_aa64isar0_el1",
1432         "id_aa64isar1_el1",
1433         "id_aa64mmfr0_el1",
1434         "id_aa64mmfr1_el1",
1435         "ccsidr_el1",
1436         "clidr_el1",
1437         "aidr_el1",
1438         "csselr_el1",
1439         "ctr_el0",
1440         "dczid_el0",
1441         "vpidr_el2",
1442         "vmpidr_el2",
1443         "sctlr_el1",
1444         "actlr_el1",
1445         "cpacr_el1",
1446         "sctlr_el2",
1447         "actlr_el2",
1448         "hcr_el2",
1449         "mdcr_el2",
1450         "cptr_el2",
1451         "hstr_el2",
1452         "hacr_el2",
1453         "sctlr_el3",
1454         "actlr_el3",
1455         "scr_el3",
1456         "sder32_el3",
1457         "cptr_el3",
1458         "mdcr_el3",
1459         "ttbr0_el1",
1460         "ttbr1_el1",
1461         "tcr_el1",
1462         "ttbr0_el2",
1463         "tcr_el2",
1464         "vttbr_el2",
1465         "vtcr_el2",
1466         "ttbr0_el3",
1467         "tcr_el3",
1468         "dacr32_el2",
1469         "spsr_el1",
1470         "elr_el1",
1471         "sp_el0",
1472         "spsel",
1473         "currentel",
1474         "nzcv",
1475         "daif",
1476         "fpcr",
1477         "fpsr",
1478         "dspsr_el0",
1479         "dlr_el0",
1480         "spsr_el2",
1481         "elr_el2",
1482         "sp_el1",
1483         "spsr_irq_aa64",
1484         "spsr_abt_aa64",
1485         "spsr_und_aa64",
1486         "spsr_fiq_aa64",
1487         "spsr_el3",
1488         "elr_el3",
1489         "sp_el2",
1490         "afsr0_el1",
1491         "afsr1_el1",
1492         "esr_el1",
1493         "ifsr32_el2",
1494         "afsr0_el2",
1495         "afsr1_el2",
1496         "esr_el2",
1497         "fpexc32_el2",
1498         "afsr0_el3",
1499         "afsr1_el3",
1500         "esr_el3",
1501         "far_el1",
1502         "far_el2",
1503         "hpfar_el2",
1504         "far_el3",
1505         "ic_ialluis",
1506         "par_el1",
1507         "ic_iallu",
1508         "dc_ivac_xt",
1509         "dc_isw_xt",
1510         "at_s1e1r_xt",
1511         "at_s1e1w_xt",
1512         "at_s1e0r_xt",
1513         "at_s1e0w_xt",
1514         "dc_csw_xt",
1515         "dc_cisw_xt",
1516         "dc_zva_xt",
1517         "ic_ivau_xt",
1518         "dc_cvac_xt",
1519         "dc_cvau_xt",
1520         "dc_civac_xt",
1521         "at_s1e2r_xt",
1522         "at_s1e2w_xt",
1523         "at_s12e1r_xt",
1524         "at_s12e1w_xt",
1525         "at_s12e0r_xt",
1526         "at_s12e0w_xt",
1527         "at_s1e3r_xt",
1528         "at_s1e3w_xt",
1529         "tlbi_vmalle1is",
1530         "tlbi_vae1is_xt",
1531         "tlbi_aside1is_xt",
1532         "tlbi_vaae1is_xt",
1533         "tlbi_vale1is_xt",
1534         "tlbi_vaale1is_xt",
1535         "tlbi_vmalle1",
1536         "tlbi_vae1_xt",
1537         "tlbi_aside1_xt",
1538         "tlbi_vaae1_xt",
1539         "tlbi_vale1_xt",
1540         "tlbi_vaale1_xt",
1541         "tlbi_ipas2e1is_xt",
1542         "tlbi_ipas2le1is_xt",
1543         "tlbi_alle2is",
1544         "tlbi_vae2is_xt",
1545         "tlbi_alle1is",
1546         "tlbi_vale2is_xt",
1547         "tlbi_vmalls12e1is",
1548         "tlbi_ipas2e1_xt",
1549         "tlbi_ipas2le1_xt",
1550         "tlbi_alle2",
1551         "tlbi_vae2_xt",
1552         "tlbi_alle1",
1553         "tlbi_vale2_xt",
1554         "tlbi_vmalls12e1",
1555         "tlbi_alle3is",
1556         "tlbi_vae3is_xt",
1557         "tlbi_vale3is_xt",
1558         "tlbi_alle3",
1559         "tlbi_vae3_xt",
1560         "tlbi_vale3_xt",
1561         "pmintenset_el1",
1562         "pmintenclr_el1",
1563         "pmcr_el0",
1564         "pmcntenset_el0",
1565         "pmcntenclr_el0",
1566         "pmovsclr_el0",
1567         "pmswinc_el0",
1568         "pmselr_el0",
1569         "pmceid0_el0",
1570         "pmceid1_el0",
1571         "pmccntr_el0",
1572         "pmxevtyper_el0",
1573         "pmccfiltr_el0",
1574         "pmxevcntr_el0",
1575         "pmuserenr_el0",
1576         "pmovsset_el0",
1577         "mair_el1",
1578         "amair_el1",
1579         "mair_el2",
1580         "amair_el2",
1581         "mair_el3",
1582         "amair_el3",
1583         "l2ctlr_el1",
1584         "l2ectlr_el1",
1585         "vbar_el1",
1586         "rvbar_el1",
1587         "isr_el1",
1588         "vbar_el2",
1589         "rvbar_el2",
1590         "vbar_el3",
1591         "rvbar_el3",
1592         "rmr_el3",
1593         "contextidr_el1",
1594         "tpidr_el1",
1595         "tpidr_el0",
1596         "tpidrro_el0",
1597         "tpidr_el2",
1598         "tpidr_el3",
1599         "cntfrq_el0",
1600         "cntpct_el0",
1601         "cntvct_el0",
1602         "cntp_ctl_el0",
1603         "cntp_cval_el0",
1604         "cntp_tval_el0",
1605         "cntv_ctl_el0",
1606         "cntv_cval_el0",
1607         "cntv_tval_el0",
1608         "cntp_ctl_el02",
1609         "cntp_cval_el02",
1610         "cntp_tval_el02",
1611         "cntv_ctl_el02",
1612         "cntv_cval_el02",
1613         "cntv_tval_el02",
1614         "cntkctl_el1",
1615         "cntkctl_el12",
1616         "cntps_ctl_el1",
1617         "cntps_cval_el1",
1618         "cntps_tval_el1",
1619         "cnthctl_el2",
1620         "cnthp_ctl_el2",
1621         "cnthp_cval_el2",
1622         "cnthp_tval_el2",
1623         "cnthv_ctl_el2",
1624         "cnthv_cval_el2",
1625         "cnthv_tval_el2",
1626         "cntvoff_el2",
1627         "pmevcntr0_el0",
1628         "pmevcntr1_el0",
1629         "pmevcntr2_el0",
1630         "pmevcntr3_el0",
1631         "pmevcntr4_el0",
1632         "pmevcntr5_el0",
1633         "pmevtyper0_el0",
1634         "pmevtyper1_el0",
1635         "pmevtyper2_el0",
1636         "pmevtyper3_el0",
1637         "pmevtyper4_el0",
1638         "pmevtyper5_el0",
1639         "il1data0_el1",
1640         "il1data1_el1",
1641         "il1data2_el1",
1642         "il1data3_el1",
1643         "dl1data0_el1",
1644         "dl1data1_el1",
1645         "dl1data2_el1",
1646         "dl1data3_el1",
1647         "dl1data4_el1",
1648         "l2actlr_el1",
1649         "cpuactlr_el1",
1650         "cpuectlr_el1",
1651         "cpumerrsr_el1",
1652         "l2merrsr_el1",
1653         "cbar_el1",
1654         "contextidr_el2",
1655
1656         "ttbr1_el2",
1657         "id_aa64mmfr2_el1",
1658
1659         "apdakeyhi_el1",
1660         "apdakeylo_el1",
1661         "apdbkeyhi_el1",
1662         "apdbkeylo_el1",
1663         "apgakeyhi_el1",
1664         "apgakeylo_el1",
1665         "apiakeyhi_el1",
1666         "apiakeylo_el1",
1667         "apibkeyhi_el1",
1668         "apibkeylo_el1",
1669         // GICv3, CPU interface
1670         "icc_pmr_el1",
1671         "icc_iar0_el1",
1672         "icc_eoir0_el1",
1673         "icc_hppir0_el1",
1674         "icc_bpr0_el1",
1675         "icc_ap0r0_el1",
1676         "icc_ap0r1_el1",
1677         "icc_ap0r2_el1",
1678         "icc_ap0r3_el1",
1679         "icc_ap1r0_el1",
1680         "icc_ap1r0_el1_ns",
1681         "icc_ap1r0_el1_s",
1682         "icc_ap1r1_el1",
1683         "icc_ap1r1_el1_ns",
1684         "icc_ap1r1_el1_s",
1685         "icc_ap1r2_el1",
1686         "icc_ap1r2_el1_ns",
1687         "icc_ap1r2_el1_s",
1688         "icc_ap1r3_el1",
1689         "icc_ap1r3_el1_ns",
1690         "icc_ap1r3_el1_s",
1691         "icc_dir_el1",
1692         "icc_rpr_el1",
1693         "icc_sgi1r_el1",
1694         "icc_asgi1r_el1",
1695         "icc_sgi0r_el1",
1696         "icc_iar1_el1",
1697         "icc_eoir1_el1",
1698         "icc_hppir1_el1",
1699         "icc_bpr1_el1",
1700         "icc_bpr1_el1_ns",
1701         "icc_bpr1_el1_s",
1702         "icc_ctlr_el1",
1703         "icc_ctlr_el1_ns",
1704         "icc_ctlr_el1_s",
1705         "icc_sre_el1",
1706         "icc_sre_el1_ns",
1707         "icc_sre_el1_s",
1708         "icc_igrpen0_el1",
1709         "icc_igrpen1_el1",
1710         "icc_igrpen1_el1_ns",
1711         "icc_igrpen1_el1_s",
1712         "icc_sre_el2",
1713         "icc_ctlr_el3",
1714         "icc_sre_el3",
1715         "icc_igrpen1_el3",
1716
1717         // GICv3, CPU interface, virtualization
1718         "ich_ap0r0_el2",
1719         "ich_ap0r1_el2",
1720         "ich_ap0r2_el2",
1721         "ich_ap0r3_el2",
1722         "ich_ap1r0_el2",
1723         "ich_ap1r1_el2",
1724         "ich_ap1r2_el2",
1725         "ich_ap1r3_el2",
1726         "ich_hcr_el2",
1727         "ich_vtr_el2",
1728         "ich_misr_el2",
1729         "ich_eisr_el2",
1730         "ich_elrsr_el2",
1731         "ich_vmcr_el2",
1732         "ich_lr0_el2",
1733         "ich_lr1_el2",
1734         "ich_lr2_el2",
1735         "ich_lr3_el2",
1736         "ich_lr4_el2",
1737         "ich_lr5_el2",
1738         "ich_lr6_el2",
1739         "ich_lr7_el2",
1740         "ich_lr8_el2",
1741         "ich_lr9_el2",
1742         "ich_lr10_el2",
1743         "ich_lr11_el2",
1744         "ich_lr12_el2",
1745         "ich_lr13_el2",
1746         "ich_lr14_el2",
1747         "ich_lr15_el2",
1748
1749         "icv_pmr_el1",
1750         "icv_iar0_el1",
1751         "icv_eoir0_el1",
1752         "icv_hppir0_el1",
1753         "icv_bpr0_el1",
1754         "icv_ap0r0_el1",
1755         "icv_ap0r1_el1",
1756         "icv_ap0r2_el1",
1757         "icv_ap0r3_el1",
1758         "icv_ap1r0_el1",
1759         "icv_ap1r0_el1_ns",
1760         "icv_ap1r0_el1_s",
1761         "icv_ap1r1_el1",
1762         "icv_ap1r1_el1_ns",
1763         "icv_ap1r1_el1_s",
1764         "icv_ap1r2_el1",
1765         "icv_ap1r2_el1_ns",
1766         "icv_ap1r2_el1_s",
1767         "icv_ap1r3_el1",
1768         "icv_ap1r3_el1_ns",
1769         "icv_ap1r3_el1_s",
1770         "icv_dir_el1",
1771         "icv_rpr_el1",
1772         "icv_sgi1r_el1",
1773         "icv_asgi1r_el1",
1774         "icv_sgi0r_el1",
1775         "icv_iar1_el1",
1776         "icv_eoir1_el1",
1777         "icv_hppir1_el1",
1778         "icv_bpr1_el1",
1779         "icv_bpr1_el1_ns",
1780         "icv_bpr1_el1_s",
1781         "icv_ctlr_el1",
1782         "icv_ctlr_el1_ns",
1783         "icv_ctlr_el1_s",
1784         "icv_sre_el1",
1785         "icv_sre_el1_ns",
1786         "icv_sre_el1_s",
1787         "icv_igrpen0_el1",
1788         "icv_igrpen1_el1",
1789         "icv_igrpen1_el1_ns",
1790         "icv_igrpen1_el1_s",
1791
1792         "icc_ap0r0",
1793         "icc_ap0r1",
1794         "icc_ap0r2",
1795         "icc_ap0r3",
1796         "icc_ap1r0",
1797         "icc_ap1r0_ns",
1798         "icc_ap1r0_s",
1799         "icc_ap1r1",
1800         "icc_ap1r1_ns",
1801         "icc_ap1r1_s",
1802         "icc_ap1r2",
1803         "icc_ap1r2_ns",
1804         "icc_ap1r2_s",
1805         "icc_ap1r3",
1806         "icc_ap1r3_ns",
1807         "icc_ap1r3_s",
1808         "icc_asgi1r",
1809         "icc_bpr0",
1810         "icc_bpr1",
1811         "icc_bpr1_ns",
1812         "icc_bpr1_s",
1813         "icc_ctlr",
1814         "icc_ctlr_ns",
1815         "icc_ctlr_s",
1816         "icc_dir",
1817         "icc_eoir0",
1818         "icc_eoir1",
1819         "icc_hppir0",
1820         "icc_hppir1",
1821         "icc_hsre",
1822         "icc_iar0",
1823         "icc_iar1",
1824         "icc_igrpen0",
1825         "icc_igrpen1",
1826         "icc_igrpen1_ns",
1827         "icc_igrpen1_s",
1828         "icc_mctlr",
1829         "icc_mgrpen1",
1830         "icc_msre",
1831         "icc_pmr",
1832         "icc_rpr",
1833         "icc_sgi0r",
1834         "icc_sgi1r",
1835         "icc_sre",
1836         "icc_sre_ns",
1837         "icc_sre_s",
1838
1839         "ich_ap0r0",
1840         "ich_ap0r1",
1841         "ich_ap0r2",
1842         "ich_ap0r3",
1843         "ich_ap1r0",
1844         "ich_ap1r1",
1845         "ich_ap1r2",
1846         "ich_ap1r3",
1847         "ich_hcr",
1848         "ich_vtr",
1849         "ich_misr",
1850         "ich_eisr",
1851         "ich_elrsr",
1852         "ich_vmcr",
1853         "ich_lr0",
1854         "ich_lr1",
1855         "ich_lr2",
1856         "ich_lr3",
1857         "ich_lr4",
1858         "ich_lr5",
1859         "ich_lr6",
1860         "ich_lr7",
1861         "ich_lr8",
1862         "ich_lr9",
1863         "ich_lr10",
1864         "ich_lr11",
1865         "ich_lr12",
1866         "ich_lr13",
1867         "ich_lr14",
1868         "ich_lr15",
1869         "ich_lrc0",
1870         "ich_lrc1",
1871         "ich_lrc2",
1872         "ich_lrc3",
1873         "ich_lrc4",
1874         "ich_lrc5",
1875         "ich_lrc6",
1876         "ich_lrc7",
1877         "ich_lrc8",
1878         "ich_lrc9",
1879         "ich_lrc10",
1880         "ich_lrc11",
1881         "ich_lrc12",
1882         "ich_lrc13",
1883         "ich_lrc14",
1884         "ich_lrc15",
1885
1886         "id_aa64zfr0_el1",
1887         "zcr_el3",
1888         "zcr_el2",
1889         "zcr_el12",
1890         "zcr_el1",
1891
1892         "num_phys_regs",
1893
1894         // Dummy registers
1895         "nop",
1896         "raz",
1897         "cp14_unimpl",
1898         "cp15_unimpl",
1899         "unknown",
1900         "impl_defined",
1901         "erridr_el1",
1902         "errselr_el1",
1903         "erxfr_el1",
1904         "erxctlr_el1",
1905         "erxstatus_el1",
1906         "erxaddr_el1",
1907         "erxmisc0_el1",
1908         "erxmisc1_el1",
1909         "disr_el1",
1910         "vsesr_el2",
1911         "vdisr_el2",
1912
1913         // PSTATE
1914         "pan",
1915     };
1916
1917     static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
1918                   "The miscRegName array and NUM_MISCREGS are inconsistent.");
1919
1920     // This mask selects bits of the CPSR that actually go in the CondCodes
1921     // integer register to allow renaming.
1922     static const uint32_t CondCodesMask   = 0xF00F0000;
1923     static const uint32_t CpsrMaskQ       = 0x08000000;
1924
1925     // APSR (Application Program Status Register Mask). It is the user level
1926     // alias for the CPSR. The APSR is a subset of the CPSR. Although
1927     // bits[15:0] are UNKNOWN on reads, it is permitted that, on a read of
1928     // APSR:
1929     // Bit[9] returns the value of CPSR.E.
1930     // Bits[8:6] return the value of CPSR.{A,I, F}, the mask bits.
1931     static const uint32_t ApsrMask = CpsrMaskQ | CondCodesMask | 0x000001D0;
1932
1933     // CPSR (Current Program Status Register Mask).
1934     static const uint32_t CpsrMask = ApsrMask | 0x00F003DF;
1935
1936     // This mask selects bits of the FPSCR that actually go in the FpCondCodes
1937     // integer register to allow renaming.
1938     static const uint32_t FpCondCodesMask = 0xF0000000;
1939     // This mask selects the cumulative FP exception flags of the FPSCR.
1940     static const uint32_t FpscrExcMask = 0x0000009F;
1941     // This mask selects the cumulative saturation flag of the FPSCR.
1942     static const uint32_t FpscrQcMask = 0x08000000;
1943
1944     /**
1945      * Check for permission to read coprocessor registers.
1946      *
1947      * Checks whether an instruction at the current program mode has
1948      * permissions to read the coprocessor registers. This function
1949      * returns whether the check is undefined and if not whether the
1950      * read access is permitted.
1951      *
1952      * @param the misc reg indicating the coprocessor
1953      * @param the SCR
1954      * @param the CPSR
1955      * @param the thread context on the core
1956      * @return a tuple of booleans: can_read, undefined
1957      */
1958     std::tuple<bool, bool> canReadCoprocReg(MiscRegIndex reg, SCR scr,
1959                                             CPSR cpsr, ThreadContext *tc);
1960
1961     /**
1962      * Check for permission to write coprocessor registers.
1963      *
1964      * Checks whether an instruction at the current program mode has
1965      * permissions to write the coprocessor registers. This function
1966      * returns whether the check is undefined and if not whether the
1967      * write access is permitted.
1968      *
1969      * @param the misc reg indicating the coprocessor
1970      * @param the SCR
1971      * @param the CPSR
1972      * @param the thread context on the core
1973      * @return a tuple of booleans: can_write, undefined
1974      */
1975     std::tuple<bool, bool> canWriteCoprocReg(MiscRegIndex reg, SCR scr,
1976                                              CPSR cpsr, ThreadContext *tc);
1977
1978     // Checks for UNDEFINED behaviours when accessing AArch32
1979     // Generic Timer system registers
1980     bool AArch32isUndefinedGenericTimer(MiscRegIndex reg, ThreadContext *tc);
1981
1982     // Checks read access permissions to AArch64 system registers
1983     bool canReadAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
1984                               ThreadContext *tc);
1985
1986     // Checks write access permissions to AArch64 system registers
1987     bool canWriteAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
1988                                ThreadContext *tc);
1989
1990     // Uses just the scr.ns bit to pre flatten the misc regs. This is useful
1991     // for MCR/MRC instructions
1992     int
1993     snsBankedIndex(MiscRegIndex reg, ThreadContext *tc);
1994
1995     // Flattens a misc reg index using the specified security state. This is
1996     // used for opperations (eg address translations) where the security
1997     // state of the register access may differ from the current state of the
1998     // processor
1999     int
2000     snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns);
2001
2002     int
2003     snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc);
2004
2005     // Takes a misc reg index and returns the root reg if its one of a set of
2006     // banked registers
2007     void
2008     preUnflattenMiscReg();
2009
2010     int
2011     unflattenMiscReg(int reg);
2012
2013 }
2014
2015 #endif // __ARCH_ARM_MISCREGS_HH__