src/arch/arm/miscregs.hh

   1 /*
   2  * Copyright (c) 2010-2020 ARM Limited
   3  * All rights reserved
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   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
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  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2009 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
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  20  * notice, this list of conditions and the following disclaimer;
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  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #ifndef __ARCH_ARM_MISCREGS_HH__
  42 #define __ARCH_ARM_MISCREGS_HH__
  43
  44 #include <bitset>
  45 #include <tuple>
  46
  47 #include "arch/arm/miscregs_types.hh"
  48 #include "base/compiler.hh"
  49 #include "dev/arm/generic_timer_miscregs_types.hh"
  50
  51 class ThreadContext;
  52
  53
  54 namespace ArmISA
  55 {
  56     enum MiscRegIndex {
  57         MISCREG_CPSR = 0,
  58         MISCREG_SPSR,
  59         MISCREG_SPSR_FIQ,
  60         MISCREG_SPSR_IRQ,
  61         MISCREG_SPSR_SVC,
  62         MISCREG_SPSR_MON,
  63         MISCREG_SPSR_ABT,
  64         MISCREG_SPSR_HYP,
  65         MISCREG_SPSR_UND,
  66         MISCREG_ELR_HYP,
  67         MISCREG_FPSID,
  68         MISCREG_FPSCR,
  69         MISCREG_MVFR1,
  70         MISCREG_MVFR0,
  71         MISCREG_FPEXC,
  72
  73         // Helper registers
  74         MISCREG_CPSR_MODE,
  75         MISCREG_CPSR_Q,
  76         MISCREG_FPSCR_EXC,
  77         MISCREG_FPSCR_QC,
  78         MISCREG_LOCKADDR,
  79         MISCREG_LOCKFLAG,
  80         MISCREG_PRRR_MAIR0,
  81         MISCREG_PRRR_MAIR0_NS,
  82         MISCREG_PRRR_MAIR0_S,
  83         MISCREG_NMRR_MAIR1,
  84         MISCREG_NMRR_MAIR1_NS,
  85         MISCREG_NMRR_MAIR1_S,
  86         MISCREG_PMXEVTYPER_PMCCFILTR,
  87         MISCREG_SCTLR_RST,
  88         MISCREG_SEV_MAILBOX,
  89
  90         // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control)
  91         MISCREG_DBGDIDR,
  92         MISCREG_DBGDSCRint,
  93         MISCREG_DBGDCCINT,
  94         MISCREG_DBGDTRTXint,
  95         MISCREG_DBGDTRRXint,
  96         MISCREG_DBGWFAR,
  97         MISCREG_DBGVCR,
  98         MISCREG_DBGDTRRXext,
  99         MISCREG_DBGDSCRext,
 100         MISCREG_DBGDTRTXext,
 101         MISCREG_DBGOSECCR,
 102         MISCREG_DBGBVR0,
 103         MISCREG_DBGBVR1,
 104         MISCREG_DBGBVR2,
 105         MISCREG_DBGBVR3,
 106         MISCREG_DBGBVR4,
 107         MISCREG_DBGBVR5,
 108         MISCREG_DBGBVR6,
 109         MISCREG_DBGBVR7,
 110         MISCREG_DBGBVR8,
 111         MISCREG_DBGBVR9,
 112         MISCREG_DBGBVR10,
 113         MISCREG_DBGBVR11,
 114         MISCREG_DBGBVR12,
 115         MISCREG_DBGBVR13,
 116         MISCREG_DBGBVR14,
 117         MISCREG_DBGBVR15,
 118         MISCREG_DBGBCR0,
 119         MISCREG_DBGBCR1,
 120         MISCREG_DBGBCR2,
 121         MISCREG_DBGBCR3,
 122         MISCREG_DBGBCR4,
 123         MISCREG_DBGBCR5,
 124         MISCREG_DBGBCR6,
 125         MISCREG_DBGBCR7,
 126         MISCREG_DBGBCR8,
 127         MISCREG_DBGBCR9,
 128         MISCREG_DBGBCR10,
 129         MISCREG_DBGBCR11,
 130         MISCREG_DBGBCR12,
 131         MISCREG_DBGBCR13,
 132         MISCREG_DBGBCR14,
 133         MISCREG_DBGBCR15,
 134         MISCREG_DBGWVR0,
 135         MISCREG_DBGWVR1,
 136         MISCREG_DBGWVR2,
 137         MISCREG_DBGWVR3,
 138         MISCREG_DBGWVR4,
 139         MISCREG_DBGWVR5,
 140         MISCREG_DBGWVR6,
 141         MISCREG_DBGWVR7,
 142         MISCREG_DBGWVR8,
 143         MISCREG_DBGWVR9,
 144         MISCREG_DBGWVR10,
 145         MISCREG_DBGWVR11,
 146         MISCREG_DBGWVR12,
 147         MISCREG_DBGWVR13,
 148         MISCREG_DBGWVR14,
 149         MISCREG_DBGWVR15,
 150         MISCREG_DBGWCR0,
 151         MISCREG_DBGWCR1,
 152         MISCREG_DBGWCR2,
 153         MISCREG_DBGWCR3,
 154         MISCREG_DBGWCR4,
 155         MISCREG_DBGWCR5,
 156         MISCREG_DBGWCR6,
 157         MISCREG_DBGWCR7,
 158         MISCREG_DBGWCR8,
 159         MISCREG_DBGWCR9,
 160         MISCREG_DBGWCR10,
 161         MISCREG_DBGWCR11,
 162         MISCREG_DBGWCR12,
 163         MISCREG_DBGWCR13,
 164         MISCREG_DBGWCR14,
 165         MISCREG_DBGWCR15,
 166         MISCREG_DBGDRAR,
 167         MISCREG_DBGBXVR0,
 168         MISCREG_DBGBXVR1,
 169         MISCREG_DBGBXVR2,
 170         MISCREG_DBGBXVR3,
 171         MISCREG_DBGBXVR4,
 172         MISCREG_DBGBXVR5,
 173         MISCREG_DBGBXVR6,
 174         MISCREG_DBGBXVR7,
 175         MISCREG_DBGBXVR8,
 176         MISCREG_DBGBXVR9,
 177         MISCREG_DBGBXVR10,
 178         MISCREG_DBGBXVR11,
 179         MISCREG_DBGBXVR12,
 180         MISCREG_DBGBXVR13,
 181         MISCREG_DBGBXVR14,
 182         MISCREG_DBGBXVR15,
 183         MISCREG_DBGOSLAR,
 184         MISCREG_DBGOSLSR,
 185         MISCREG_DBGOSDLR,
 186         MISCREG_DBGPRCR,
 187         MISCREG_DBGDSAR,
 188         MISCREG_DBGCLAIMSET,
 189         MISCREG_DBGCLAIMCLR,
 190         MISCREG_DBGAUTHSTATUS,
 191         MISCREG_DBGDEVID2,
 192         MISCREG_DBGDEVID1,
 193         MISCREG_DBGDEVID0,
 194         MISCREG_TEECR,  // not in ARM DDI 0487A.b+
 195         MISCREG_JIDR,
 196         MISCREG_TEEHBR, // not in ARM DDI 0487A.b+
 197         MISCREG_JOSCR,
 198         MISCREG_JMCR,
 199
 200         // AArch32 CP15 registers (system control)
 201         MISCREG_MIDR,
 202         MISCREG_CTR,
 203         MISCREG_TCMTR,
 204         MISCREG_TLBTR,
 205         MISCREG_MPIDR,
 206         MISCREG_REVIDR,
 207         MISCREG_ID_PFR0,
 208         MISCREG_ID_PFR1,
 209         MISCREG_ID_DFR0,
 210         MISCREG_ID_AFR0,
 211         MISCREG_ID_MMFR0,
 212         MISCREG_ID_MMFR1,
 213         MISCREG_ID_MMFR2,
 214         MISCREG_ID_MMFR3,
 215         MISCREG_ID_ISAR0,
 216         MISCREG_ID_ISAR1,
 217         MISCREG_ID_ISAR2,
 218         MISCREG_ID_ISAR3,
 219         MISCREG_ID_ISAR4,
 220         MISCREG_ID_ISAR5,
 221         MISCREG_CCSIDR,
 222         MISCREG_CLIDR,
 223         MISCREG_AIDR,
 224         MISCREG_CSSELR,
 225         MISCREG_CSSELR_NS,
 226         MISCREG_CSSELR_S,
 227         MISCREG_VPIDR,
 228         MISCREG_VMPIDR,
 229         MISCREG_SCTLR,
 230         MISCREG_SCTLR_NS,
 231         MISCREG_SCTLR_S,
 232         MISCREG_ACTLR,
 233         MISCREG_ACTLR_NS,
 234         MISCREG_ACTLR_S,
 235         MISCREG_CPACR,
 236         MISCREG_SDCR,
 237         MISCREG_SCR,
 238         MISCREG_SDER,
 239         MISCREG_NSACR,
 240         MISCREG_HSCTLR,
 241         MISCREG_HACTLR,
 242         MISCREG_HCR,
 243         MISCREG_HCR2,
 244         MISCREG_HDCR,
 245         MISCREG_HCPTR,
 246         MISCREG_HSTR,
 247         MISCREG_HACR,
 248         MISCREG_TTBR0,
 249         MISCREG_TTBR0_NS,
 250         MISCREG_TTBR0_S,
 251         MISCREG_TTBR1,
 252         MISCREG_TTBR1_NS,
 253         MISCREG_TTBR1_S,
 254         MISCREG_TTBCR,
 255         MISCREG_TTBCR_NS,
 256         MISCREG_TTBCR_S,
 257         MISCREG_HTCR,
 258         MISCREG_VTCR,
 259         MISCREG_DACR,
 260         MISCREG_DACR_NS,
 261         MISCREG_DACR_S,
 262         MISCREG_DFSR,
 263         MISCREG_DFSR_NS,
 264         MISCREG_DFSR_S,
 265         MISCREG_IFSR,
 266         MISCREG_IFSR_NS,
 267         MISCREG_IFSR_S,
 268         MISCREG_ADFSR,
 269         MISCREG_ADFSR_NS,
 270         MISCREG_ADFSR_S,
 271         MISCREG_AIFSR,
 272         MISCREG_AIFSR_NS,
 273         MISCREG_AIFSR_S,
 274         MISCREG_HADFSR,
 275         MISCREG_HAIFSR,
 276         MISCREG_HSR,
 277         MISCREG_DFAR,
 278         MISCREG_DFAR_NS,
 279         MISCREG_DFAR_S,
 280         MISCREG_IFAR,
 281         MISCREG_IFAR_NS,
 282         MISCREG_IFAR_S,
 283         MISCREG_HDFAR,
 284         MISCREG_HIFAR,
 285         MISCREG_HPFAR,
 286         MISCREG_ICIALLUIS,
 287         MISCREG_BPIALLIS,
 288         MISCREG_PAR,
 289         MISCREG_PAR_NS,
 290         MISCREG_PAR_S,
 291         MISCREG_ICIALLU,
 292         MISCREG_ICIMVAU,
 293         MISCREG_CP15ISB,
 294         MISCREG_BPIALL,
 295         MISCREG_BPIMVA,
 296         MISCREG_DCIMVAC,
 297         MISCREG_DCISW,
 298         MISCREG_ATS1CPR,
 299         MISCREG_ATS1CPW,
 300         MISCREG_ATS1CUR,
 301         MISCREG_ATS1CUW,
 302         MISCREG_ATS12NSOPR,
 303         MISCREG_ATS12NSOPW,
 304         MISCREG_ATS12NSOUR,
 305         MISCREG_ATS12NSOUW,
 306         MISCREG_DCCMVAC,
 307         MISCREG_DCCSW,
 308         MISCREG_CP15DSB,
 309         MISCREG_CP15DMB,
 310         MISCREG_DCCMVAU,
 311         MISCREG_DCCIMVAC,
 312         MISCREG_DCCISW,
 313         MISCREG_ATS1HR,
 314         MISCREG_ATS1HW,
 315         MISCREG_TLBIALLIS,
 316         MISCREG_TLBIMVAIS,
 317         MISCREG_TLBIASIDIS,
 318         MISCREG_TLBIMVAAIS,
 319         MISCREG_TLBIMVALIS,
 320         MISCREG_TLBIMVAALIS,
 321         MISCREG_ITLBIALL,
 322         MISCREG_ITLBIMVA,
 323         MISCREG_ITLBIASID,
 324         MISCREG_DTLBIALL,
 325         MISCREG_DTLBIMVA,
 326         MISCREG_DTLBIASID,
 327         MISCREG_TLBIALL,
 328         MISCREG_TLBIMVA,
 329         MISCREG_TLBIASID,
 330         MISCREG_TLBIMVAA,
 331         MISCREG_TLBIMVAL,
 332         MISCREG_TLBIMVAAL,
 333         MISCREG_TLBIIPAS2IS,
 334         MISCREG_TLBIIPAS2LIS,
 335         MISCREG_TLBIALLHIS,
 336         MISCREG_TLBIMVAHIS,
 337         MISCREG_TLBIALLNSNHIS,
 338         MISCREG_TLBIMVALHIS,
 339         MISCREG_TLBIIPAS2,
 340         MISCREG_TLBIIPAS2L,
 341         MISCREG_TLBIALLH,
 342         MISCREG_TLBIMVAH,
 343         MISCREG_TLBIALLNSNH,
 344         MISCREG_TLBIMVALH,
 345         MISCREG_PMCR,
 346         MISCREG_PMCNTENSET,
 347         MISCREG_PMCNTENCLR,
 348         MISCREG_PMOVSR,
 349         MISCREG_PMSWINC,
 350         MISCREG_PMSELR,
 351         MISCREG_PMCEID0,
 352         MISCREG_PMCEID1,
 353         MISCREG_PMCCNTR,
 354         MISCREG_PMXEVTYPER,
 355         MISCREG_PMCCFILTR,
 356         MISCREG_PMXEVCNTR,
 357         MISCREG_PMUSERENR,
 358         MISCREG_PMINTENSET,
 359         MISCREG_PMINTENCLR,
 360         MISCREG_PMOVSSET,
 361         MISCREG_L2CTLR,
 362         MISCREG_L2ECTLR,
 363         MISCREG_PRRR,
 364         MISCREG_PRRR_NS,
 365         MISCREG_PRRR_S,
 366         MISCREG_MAIR0,
 367         MISCREG_MAIR0_NS,
 368         MISCREG_MAIR0_S,
 369         MISCREG_NMRR,
 370         MISCREG_NMRR_NS,
 371         MISCREG_NMRR_S,
 372         MISCREG_MAIR1,
 373         MISCREG_MAIR1_NS,
 374         MISCREG_MAIR1_S,
 375         MISCREG_AMAIR0,
 376         MISCREG_AMAIR0_NS,
 377         MISCREG_AMAIR0_S,
 378         MISCREG_AMAIR1,
 379         MISCREG_AMAIR1_NS,
 380         MISCREG_AMAIR1_S,
 381         MISCREG_HMAIR0,
 382         MISCREG_HMAIR1,
 383         MISCREG_HAMAIR0,
 384         MISCREG_HAMAIR1,
 385         MISCREG_VBAR,
 386         MISCREG_VBAR_NS,
 387         MISCREG_VBAR_S,
 388         MISCREG_MVBAR,
 389         MISCREG_RMR,
 390         MISCREG_ISR,
 391         MISCREG_HVBAR,
 392         MISCREG_FCSEIDR,
 393         MISCREG_CONTEXTIDR,
 394         MISCREG_CONTEXTIDR_NS,
 395         MISCREG_CONTEXTIDR_S,
 396         MISCREG_TPIDRURW,
 397         MISCREG_TPIDRURW_NS,
 398         MISCREG_TPIDRURW_S,
 399         MISCREG_TPIDRURO,
 400         MISCREG_TPIDRURO_NS,
 401         MISCREG_TPIDRURO_S,
 402         MISCREG_TPIDRPRW,
 403         MISCREG_TPIDRPRW_NS,
 404         MISCREG_TPIDRPRW_S,
 405         MISCREG_HTPIDR,
 406         // BEGIN Generic Timer (AArch32)
 407         MISCREG_CNTFRQ,
 408         MISCREG_CNTPCT,
 409         MISCREG_CNTVCT,
 410         MISCREG_CNTP_CTL,
 411         MISCREG_CNTP_CTL_NS,
 412         MISCREG_CNTP_CTL_S,
 413         MISCREG_CNTP_CVAL,
 414         MISCREG_CNTP_CVAL_NS,
 415         MISCREG_CNTP_CVAL_S,
 416         MISCREG_CNTP_TVAL,
 417         MISCREG_CNTP_TVAL_NS,
 418         MISCREG_CNTP_TVAL_S,
 419         MISCREG_CNTV_CTL,
 420         MISCREG_CNTV_CVAL,
 421         MISCREG_CNTV_TVAL,
 422         MISCREG_CNTKCTL,
 423         MISCREG_CNTHCTL,
 424         MISCREG_CNTHP_CTL,
 425         MISCREG_CNTHP_CVAL,
 426         MISCREG_CNTHP_TVAL,
 427         MISCREG_CNTVOFF,
 428         // END Generic Timer (AArch32)
 429         MISCREG_IL1DATA0,
 430         MISCREG_IL1DATA1,
 431         MISCREG_IL1DATA2,
 432         MISCREG_IL1DATA3,
 433         MISCREG_DL1DATA0,
 434         MISCREG_DL1DATA1,
 435         MISCREG_DL1DATA2,
 436         MISCREG_DL1DATA3,
 437         MISCREG_DL1DATA4,
 438         MISCREG_RAMINDEX,
 439         MISCREG_L2ACTLR,
 440         MISCREG_CBAR,
 441         MISCREG_HTTBR,
 442         MISCREG_VTTBR,
 443         MISCREG_CPUMERRSR,
 444         MISCREG_L2MERRSR,
 445
 446         // AArch64 registers (Op0=2)
 447         MISCREG_MDCCINT_EL1,
 448         MISCREG_OSDTRRX_EL1,
 449         MISCREG_MDSCR_EL1,
 450         MISCREG_OSDTRTX_EL1,
 451         MISCREG_OSECCR_EL1,
 452         MISCREG_DBGBVR0_EL1,
 453         MISCREG_DBGBVR1_EL1,
 454         MISCREG_DBGBVR2_EL1,
 455         MISCREG_DBGBVR3_EL1,
 456         MISCREG_DBGBVR4_EL1,
 457         MISCREG_DBGBVR5_EL1,
 458         MISCREG_DBGBVR6_EL1,
 459         MISCREG_DBGBVR7_EL1,
 460         MISCREG_DBGBVR8_EL1,
 461         MISCREG_DBGBVR9_EL1,
 462         MISCREG_DBGBVR10_EL1,
 463         MISCREG_DBGBVR11_EL1,
 464         MISCREG_DBGBVR12_EL1,
 465         MISCREG_DBGBVR13_EL1,
 466         MISCREG_DBGBVR14_EL1,
 467         MISCREG_DBGBVR15_EL1,
 468         MISCREG_DBGBCR0_EL1,
 469         MISCREG_DBGBCR1_EL1,
 470         MISCREG_DBGBCR2_EL1,
 471         MISCREG_DBGBCR3_EL1,
 472         MISCREG_DBGBCR4_EL1,
 473         MISCREG_DBGBCR5_EL1,
 474         MISCREG_DBGBCR6_EL1,
 475         MISCREG_DBGBCR7_EL1,
 476         MISCREG_DBGBCR8_EL1,
 477         MISCREG_DBGBCR9_EL1,
 478         MISCREG_DBGBCR10_EL1,
 479         MISCREG_DBGBCR11_EL1,
 480         MISCREG_DBGBCR12_EL1,
 481         MISCREG_DBGBCR13_EL1,
 482         MISCREG_DBGBCR14_EL1,
 483         MISCREG_DBGBCR15_EL1,
 484         MISCREG_DBGWVR0_EL1,
 485         MISCREG_DBGWVR1_EL1,
 486         MISCREG_DBGWVR2_EL1,
 487         MISCREG_DBGWVR3_EL1,
 488         MISCREG_DBGWVR4_EL1,
 489         MISCREG_DBGWVR5_EL1,
 490         MISCREG_DBGWVR6_EL1,
 491         MISCREG_DBGWVR7_EL1,
 492         MISCREG_DBGWVR8_EL1,
 493         MISCREG_DBGWVR9_EL1,
 494         MISCREG_DBGWVR10_EL1,
 495         MISCREG_DBGWVR11_EL1,
 496         MISCREG_DBGWVR12_EL1,
 497         MISCREG_DBGWVR13_EL1,
 498         MISCREG_DBGWVR14_EL1,
 499         MISCREG_DBGWVR15_EL1,
 500         MISCREG_DBGWCR0_EL1,
 501         MISCREG_DBGWCR1_EL1,
 502         MISCREG_DBGWCR2_EL1,
 503         MISCREG_DBGWCR3_EL1,
 504         MISCREG_DBGWCR4_EL1,
 505         MISCREG_DBGWCR5_EL1,
 506         MISCREG_DBGWCR6_EL1,
 507         MISCREG_DBGWCR7_EL1,
 508         MISCREG_DBGWCR8_EL1,
 509         MISCREG_DBGWCR9_EL1,
 510         MISCREG_DBGWCR10_EL1,
 511         MISCREG_DBGWCR11_EL1,
 512         MISCREG_DBGWCR12_EL1,
 513         MISCREG_DBGWCR13_EL1,
 514         MISCREG_DBGWCR14_EL1,
 515         MISCREG_DBGWCR15_EL1,
 516         MISCREG_MDCCSR_EL0,
 517         MISCREG_MDDTR_EL0,
 518         MISCREG_MDDTRTX_EL0,
 519         MISCREG_MDDTRRX_EL0,
 520         MISCREG_DBGVCR32_EL2,
 521         MISCREG_MDRAR_EL1,
 522         MISCREG_OSLAR_EL1,
 523         MISCREG_OSLSR_EL1,
 524         MISCREG_OSDLR_EL1,
 525         MISCREG_DBGPRCR_EL1,
 526         MISCREG_DBGCLAIMSET_EL1,
 527         MISCREG_DBGCLAIMCLR_EL1,
 528         MISCREG_DBGAUTHSTATUS_EL1,
 529         MISCREG_TEECR32_EL1, // not in ARM DDI 0487A.b+
 530         MISCREG_TEEHBR32_EL1, // not in ARM DDI 0487A.b+
 531
 532         // AArch64 registers (Op0=1,3)
 533         MISCREG_MIDR_EL1,
 534         MISCREG_MPIDR_EL1,
 535         MISCREG_REVIDR_EL1,
 536         MISCREG_ID_PFR0_EL1,
 537         MISCREG_ID_PFR1_EL1,
 538         MISCREG_ID_DFR0_EL1,
 539         MISCREG_ID_AFR0_EL1,
 540         MISCREG_ID_MMFR0_EL1,
 541         MISCREG_ID_MMFR1_EL1,
 542         MISCREG_ID_MMFR2_EL1,
 543         MISCREG_ID_MMFR3_EL1,
 544         MISCREG_ID_ISAR0_EL1,
 545         MISCREG_ID_ISAR1_EL1,
 546         MISCREG_ID_ISAR2_EL1,
 547         MISCREG_ID_ISAR3_EL1,
 548         MISCREG_ID_ISAR4_EL1,
 549         MISCREG_ID_ISAR5_EL1,
 550         MISCREG_MVFR0_EL1,
 551         MISCREG_MVFR1_EL1,
 552         MISCREG_MVFR2_EL1,
 553         MISCREG_ID_AA64PFR0_EL1,
 554         MISCREG_ID_AA64PFR1_EL1,
 555         MISCREG_ID_AA64DFR0_EL1,
 556         MISCREG_ID_AA64DFR1_EL1,
 557         MISCREG_ID_AA64AFR0_EL1,
 558         MISCREG_ID_AA64AFR1_EL1,
 559         MISCREG_ID_AA64ISAR0_EL1,
 560         MISCREG_ID_AA64ISAR1_EL1,
 561         MISCREG_ID_AA64MMFR0_EL1,
 562         MISCREG_ID_AA64MMFR1_EL1,
 563         MISCREG_CCSIDR_EL1,
 564         MISCREG_CLIDR_EL1,
 565         MISCREG_AIDR_EL1,
 566         MISCREG_CSSELR_EL1,
 567         MISCREG_CTR_EL0,
 568         MISCREG_DCZID_EL0,
 569         MISCREG_VPIDR_EL2,
 570         MISCREG_VMPIDR_EL2,
 571         MISCREG_SCTLR_EL1,
 572         MISCREG_SCTLR_EL12,
 573         MISCREG_ACTLR_EL1,
 574         MISCREG_CPACR_EL1,
 575         MISCREG_CPACR_EL12,
 576         MISCREG_SCTLR_EL2,
 577         MISCREG_ACTLR_EL2,
 578         MISCREG_HCR_EL2,
 579         MISCREG_MDCR_EL2,
 580         MISCREG_CPTR_EL2,
 581         MISCREG_HSTR_EL2,
 582         MISCREG_HACR_EL2,
 583         MISCREG_SCTLR_EL3,
 584         MISCREG_ACTLR_EL3,
 585         MISCREG_SCR_EL3,
 586         MISCREG_SDER32_EL3,
 587         MISCREG_CPTR_EL3,
 588         MISCREG_MDCR_EL3,
 589         MISCREG_TTBR0_EL1,
 590         MISCREG_TTBR0_EL12,
 591         MISCREG_TTBR1_EL1,
 592         MISCREG_TTBR1_EL12,
 593         MISCREG_TCR_EL1,
 594         MISCREG_TCR_EL12,
 595         MISCREG_TTBR0_EL2,
 596         MISCREG_TCR_EL2,
 597         MISCREG_VTTBR_EL2,
 598         MISCREG_VTCR_EL2,
 599         MISCREG_TTBR0_EL3,
 600         MISCREG_TCR_EL3,
 601         MISCREG_DACR32_EL2,
 602         MISCREG_SPSR_EL1,
 603         MISCREG_SPSR_EL12,
 604         MISCREG_ELR_EL1,
 605         MISCREG_ELR_EL12,
 606         MISCREG_SP_EL0,
 607         MISCREG_SPSEL,
 608         MISCREG_CURRENTEL,
 609         MISCREG_NZCV,
 610         MISCREG_DAIF,
 611         MISCREG_FPCR,
 612         MISCREG_FPSR,
 613         MISCREG_DSPSR_EL0,
 614         MISCREG_DLR_EL0,
 615         MISCREG_SPSR_EL2,
 616         MISCREG_ELR_EL2,
 617         MISCREG_SP_EL1,
 618         MISCREG_SPSR_IRQ_AA64,
 619         MISCREG_SPSR_ABT_AA64,
 620         MISCREG_SPSR_UND_AA64,
 621         MISCREG_SPSR_FIQ_AA64,
 622         MISCREG_SPSR_EL3,
 623         MISCREG_ELR_EL3,
 624         MISCREG_SP_EL2,
 625         MISCREG_AFSR0_EL1,
 626         MISCREG_AFSR0_EL12,
 627         MISCREG_AFSR1_EL1,
 628         MISCREG_AFSR1_EL12,
 629         MISCREG_ESR_EL1,
 630         MISCREG_ESR_EL12,
 631         MISCREG_IFSR32_EL2,
 632         MISCREG_AFSR0_EL2,
 633         MISCREG_AFSR1_EL2,
 634         MISCREG_ESR_EL2,
 635         MISCREG_FPEXC32_EL2,
 636         MISCREG_AFSR0_EL3,
 637         MISCREG_AFSR1_EL3,
 638         MISCREG_ESR_EL3,
 639         MISCREG_FAR_EL1,
 640         MISCREG_FAR_EL12,
 641         MISCREG_FAR_EL2,
 642         MISCREG_HPFAR_EL2,
 643         MISCREG_FAR_EL3,
 644         MISCREG_IC_IALLUIS,
 645         MISCREG_PAR_EL1,
 646         MISCREG_IC_IALLU,
 647         MISCREG_DC_IVAC_Xt,
 648         MISCREG_DC_ISW_Xt,
 649         MISCREG_AT_S1E1R_Xt,
 650         MISCREG_AT_S1E1W_Xt,
 651         MISCREG_AT_S1E0R_Xt,
 652         MISCREG_AT_S1E0W_Xt,
 653         MISCREG_DC_CSW_Xt,
 654         MISCREG_DC_CISW_Xt,
 655         MISCREG_DC_ZVA_Xt,
 656         MISCREG_IC_IVAU_Xt,
 657         MISCREG_DC_CVAC_Xt,
 658         MISCREG_DC_CVAU_Xt,
 659         MISCREG_DC_CIVAC_Xt,
 660         MISCREG_AT_S1E2R_Xt,
 661         MISCREG_AT_S1E2W_Xt,
 662         MISCREG_AT_S12E1R_Xt,
 663         MISCREG_AT_S12E1W_Xt,
 664         MISCREG_AT_S12E0R_Xt,
 665         MISCREG_AT_S12E0W_Xt,
 666         MISCREG_AT_S1E3R_Xt,
 667         MISCREG_AT_S1E3W_Xt,
 668         MISCREG_TLBI_VMALLE1IS,
 669         MISCREG_TLBI_VAE1IS_Xt,
 670         MISCREG_TLBI_ASIDE1IS_Xt,
 671         MISCREG_TLBI_VAAE1IS_Xt,
 672         MISCREG_TLBI_VALE1IS_Xt,
 673         MISCREG_TLBI_VAALE1IS_Xt,
 674         MISCREG_TLBI_VMALLE1,
 675         MISCREG_TLBI_VAE1_Xt,
 676         MISCREG_TLBI_ASIDE1_Xt,
 677         MISCREG_TLBI_VAAE1_Xt,
 678         MISCREG_TLBI_VALE1_Xt,
 679         MISCREG_TLBI_VAALE1_Xt,
 680         MISCREG_TLBI_IPAS2E1IS_Xt,
 681         MISCREG_TLBI_IPAS2LE1IS_Xt,
 682         MISCREG_TLBI_ALLE2IS,
 683         MISCREG_TLBI_VAE2IS_Xt,
 684         MISCREG_TLBI_ALLE1IS,
 685         MISCREG_TLBI_VALE2IS_Xt,
 686         MISCREG_TLBI_VMALLS12E1IS,
 687         MISCREG_TLBI_IPAS2E1_Xt,
 688         MISCREG_TLBI_IPAS2LE1_Xt,
 689         MISCREG_TLBI_ALLE2,
 690         MISCREG_TLBI_VAE2_Xt,
 691         MISCREG_TLBI_ALLE1,
 692         MISCREG_TLBI_VALE2_Xt,
 693         MISCREG_TLBI_VMALLS12E1,
 694         MISCREG_TLBI_ALLE3IS,
 695         MISCREG_TLBI_VAE3IS_Xt,
 696         MISCREG_TLBI_VALE3IS_Xt,
 697         MISCREG_TLBI_ALLE3,
 698         MISCREG_TLBI_VAE3_Xt,
 699         MISCREG_TLBI_VALE3_Xt,
 700         MISCREG_PMINTENSET_EL1,
 701         MISCREG_PMINTENCLR_EL1,
 702         MISCREG_PMCR_EL0,
 703         MISCREG_PMCNTENSET_EL0,
 704         MISCREG_PMCNTENCLR_EL0,
 705         MISCREG_PMOVSCLR_EL0,
 706         MISCREG_PMSWINC_EL0,
 707         MISCREG_PMSELR_EL0,
 708         MISCREG_PMCEID0_EL0,
 709         MISCREG_PMCEID1_EL0,
 710         MISCREG_PMCCNTR_EL0,
 711         MISCREG_PMXEVTYPER_EL0,
 712         MISCREG_PMCCFILTR_EL0,
 713         MISCREG_PMXEVCNTR_EL0,
 714         MISCREG_PMUSERENR_EL0,
 715         MISCREG_PMOVSSET_EL0,
 716         MISCREG_MAIR_EL1,
 717         MISCREG_MAIR_EL12,
 718         MISCREG_AMAIR_EL1,
 719         MISCREG_AMAIR_EL12,
 720         MISCREG_MAIR_EL2,
 721         MISCREG_AMAIR_EL2,
 722         MISCREG_MAIR_EL3,
 723         MISCREG_AMAIR_EL3,
 724         MISCREG_L2CTLR_EL1,
 725         MISCREG_L2ECTLR_EL1,
 726         MISCREG_VBAR_EL1,
 727         MISCREG_VBAR_EL12,
 728         MISCREG_RVBAR_EL1,
 729         MISCREG_ISR_EL1,
 730         MISCREG_VBAR_EL2,
 731         MISCREG_RVBAR_EL2,
 732         MISCREG_VBAR_EL3,
 733         MISCREG_RVBAR_EL3,
 734         MISCREG_RMR_EL3,
 735         MISCREG_CONTEXTIDR_EL1,
 736         MISCREG_CONTEXTIDR_EL12,
 737         MISCREG_TPIDR_EL1,
 738         MISCREG_TPIDR_EL0,
 739         MISCREG_TPIDRRO_EL0,
 740         MISCREG_TPIDR_EL2,
 741         MISCREG_TPIDR_EL3,
 742         // BEGIN Generic Timer (AArch64)
 743         MISCREG_CNTFRQ_EL0,
 744         MISCREG_CNTPCT_EL0,
 745         MISCREG_CNTVCT_EL0,
 746         MISCREG_CNTP_CTL_EL0,
 747         MISCREG_CNTP_CVAL_EL0,
 748         MISCREG_CNTP_TVAL_EL0,
 749         MISCREG_CNTV_CTL_EL0,
 750         MISCREG_CNTV_CVAL_EL0,
 751         MISCREG_CNTV_TVAL_EL0,
 752         MISCREG_CNTP_CTL_EL02,
 753         MISCREG_CNTP_CVAL_EL02,
 754         MISCREG_CNTP_TVAL_EL02,
 755         MISCREG_CNTV_CTL_EL02,
 756         MISCREG_CNTV_CVAL_EL02,
 757         MISCREG_CNTV_TVAL_EL02,
 758         MISCREG_CNTKCTL_EL1,
 759         MISCREG_CNTKCTL_EL12,
 760         MISCREG_CNTPS_CTL_EL1,
 761         MISCREG_CNTPS_CVAL_EL1,
 762         MISCREG_CNTPS_TVAL_EL1,
 763         MISCREG_CNTHCTL_EL2,
 764         MISCREG_CNTHP_CTL_EL2,
 765         MISCREG_CNTHP_CVAL_EL2,
 766         MISCREG_CNTHP_TVAL_EL2,
 767         MISCREG_CNTHPS_CTL_EL2,
 768         MISCREG_CNTHPS_CVAL_EL2,
 769         MISCREG_CNTHPS_TVAL_EL2,
 770         // IF Armv8.1-VHE
 771         MISCREG_CNTHV_CTL_EL2,
 772         MISCREG_CNTHV_CVAL_EL2,
 773         MISCREG_CNTHV_TVAL_EL2,
 774         MISCREG_CNTHVS_CTL_EL2,
 775         MISCREG_CNTHVS_CVAL_EL2,
 776         MISCREG_CNTHVS_TVAL_EL2,
 777         // ENDIF Armv8.1-VHE
 778         MISCREG_CNTVOFF_EL2,
 779         // END Generic Timer (AArch64)
 780         MISCREG_PMEVCNTR0_EL0,
 781         MISCREG_PMEVCNTR1_EL0,
 782         MISCREG_PMEVCNTR2_EL0,
 783         MISCREG_PMEVCNTR3_EL0,
 784         MISCREG_PMEVCNTR4_EL0,
 785         MISCREG_PMEVCNTR5_EL0,
 786         MISCREG_PMEVTYPER0_EL0,
 787         MISCREG_PMEVTYPER1_EL0,
 788         MISCREG_PMEVTYPER2_EL0,
 789         MISCREG_PMEVTYPER3_EL0,
 790         MISCREG_PMEVTYPER4_EL0,
 791         MISCREG_PMEVTYPER5_EL0,
 792         MISCREG_IL1DATA0_EL1,
 793         MISCREG_IL1DATA1_EL1,
 794         MISCREG_IL1DATA2_EL1,
 795         MISCREG_IL1DATA3_EL1,
 796         MISCREG_DL1DATA0_EL1,
 797         MISCREG_DL1DATA1_EL1,
 798         MISCREG_DL1DATA2_EL1,
 799         MISCREG_DL1DATA3_EL1,
 800         MISCREG_DL1DATA4_EL1,
 801         MISCREG_L2ACTLR_EL1,
 802         MISCREG_CPUACTLR_EL1,
 803         MISCREG_CPUECTLR_EL1,
 804         MISCREG_CPUMERRSR_EL1,
 805         MISCREG_L2MERRSR_EL1,
 806         MISCREG_CBAR_EL1,
 807         MISCREG_CONTEXTIDR_EL2,
 808
 809         // Introduced in ARMv8.1
 810         MISCREG_TTBR1_EL2,
 811
 812         MISCREG_ID_AA64MMFR2_EL1,
 813
 814         //PAuth Key Regsiters
 815         MISCREG_APDAKeyHi_EL1,
 816         MISCREG_APDAKeyLo_EL1,
 817         MISCREG_APDBKeyHi_EL1,
 818         MISCREG_APDBKeyLo_EL1,
 819         MISCREG_APGAKeyHi_EL1,
 820         MISCREG_APGAKeyLo_EL1,
 821         MISCREG_APIAKeyHi_EL1,
 822         MISCREG_APIAKeyLo_EL1,
 823         MISCREG_APIBKeyHi_EL1,
 824         MISCREG_APIBKeyLo_EL1,
 825
 826         // GICv3, CPU interface
 827         MISCREG_ICC_PMR_EL1,
 828         MISCREG_ICC_IAR0_EL1,
 829         MISCREG_ICC_EOIR0_EL1,
 830         MISCREG_ICC_HPPIR0_EL1,
 831         MISCREG_ICC_BPR0_EL1,
 832         MISCREG_ICC_AP0R0_EL1,
 833         MISCREG_ICC_AP0R1_EL1,
 834         MISCREG_ICC_AP0R2_EL1,
 835         MISCREG_ICC_AP0R3_EL1,
 836         MISCREG_ICC_AP1R0_EL1,
 837         MISCREG_ICC_AP1R0_EL1_NS,
 838         MISCREG_ICC_AP1R0_EL1_S,
 839         MISCREG_ICC_AP1R1_EL1,
 840         MISCREG_ICC_AP1R1_EL1_NS,
 841         MISCREG_ICC_AP1R1_EL1_S,
 842         MISCREG_ICC_AP1R2_EL1,
 843         MISCREG_ICC_AP1R2_EL1_NS,
 844         MISCREG_ICC_AP1R2_EL1_S,
 845         MISCREG_ICC_AP1R3_EL1,
 846         MISCREG_ICC_AP1R3_EL1_NS,
 847         MISCREG_ICC_AP1R3_EL1_S,
 848         MISCREG_ICC_DIR_EL1,
 849         MISCREG_ICC_RPR_EL1,
 850         MISCREG_ICC_SGI1R_EL1,
 851         MISCREG_ICC_ASGI1R_EL1,
 852         MISCREG_ICC_SGI0R_EL1,
 853         MISCREG_ICC_IAR1_EL1,
 854         MISCREG_ICC_EOIR1_EL1,
 855         MISCREG_ICC_HPPIR1_EL1,
 856         MISCREG_ICC_BPR1_EL1,
 857         MISCREG_ICC_BPR1_EL1_NS,
 858         MISCREG_ICC_BPR1_EL1_S,
 859         MISCREG_ICC_CTLR_EL1,
 860         MISCREG_ICC_CTLR_EL1_NS,
 861         MISCREG_ICC_CTLR_EL1_S,
 862         MISCREG_ICC_SRE_EL1,
 863         MISCREG_ICC_SRE_EL1_NS,
 864         MISCREG_ICC_SRE_EL1_S,
 865         MISCREG_ICC_IGRPEN0_EL1,
 866         MISCREG_ICC_IGRPEN1_EL1,
 867         MISCREG_ICC_IGRPEN1_EL1_NS,
 868         MISCREG_ICC_IGRPEN1_EL1_S,
 869         MISCREG_ICC_SRE_EL2,
 870         MISCREG_ICC_CTLR_EL3,
 871         MISCREG_ICC_SRE_EL3,
 872         MISCREG_ICC_IGRPEN1_EL3,
 873
 874         // GICv3, CPU interface, virtualization
 875         MISCREG_ICH_AP0R0_EL2,
 876         MISCREG_ICH_AP0R1_EL2,
 877         MISCREG_ICH_AP0R2_EL2,
 878         MISCREG_ICH_AP0R3_EL2,
 879         MISCREG_ICH_AP1R0_EL2,
 880         MISCREG_ICH_AP1R1_EL2,
 881         MISCREG_ICH_AP1R2_EL2,
 882         MISCREG_ICH_AP1R3_EL2,
 883         MISCREG_ICH_HCR_EL2,
 884         MISCREG_ICH_VTR_EL2,
 885         MISCREG_ICH_MISR_EL2,
 886         MISCREG_ICH_EISR_EL2,
 887         MISCREG_ICH_ELRSR_EL2,
 888         MISCREG_ICH_VMCR_EL2,
 889         MISCREG_ICH_LR0_EL2,
 890         MISCREG_ICH_LR1_EL2,
 891         MISCREG_ICH_LR2_EL2,
 892         MISCREG_ICH_LR3_EL2,
 893         MISCREG_ICH_LR4_EL2,
 894         MISCREG_ICH_LR5_EL2,
 895         MISCREG_ICH_LR6_EL2,
 896         MISCREG_ICH_LR7_EL2,
 897         MISCREG_ICH_LR8_EL2,
 898         MISCREG_ICH_LR9_EL2,
 899         MISCREG_ICH_LR10_EL2,
 900         MISCREG_ICH_LR11_EL2,
 901         MISCREG_ICH_LR12_EL2,
 902         MISCREG_ICH_LR13_EL2,
 903         MISCREG_ICH_LR14_EL2,
 904         MISCREG_ICH_LR15_EL2,
 905
 906         MISCREG_ICV_PMR_EL1,
 907         MISCREG_ICV_IAR0_EL1,
 908         MISCREG_ICV_EOIR0_EL1,
 909         MISCREG_ICV_HPPIR0_EL1,
 910         MISCREG_ICV_BPR0_EL1,
 911         MISCREG_ICV_AP0R0_EL1,
 912         MISCREG_ICV_AP0R1_EL1,
 913         MISCREG_ICV_AP0R2_EL1,
 914         MISCREG_ICV_AP0R3_EL1,
 915         MISCREG_ICV_AP1R0_EL1,
 916         MISCREG_ICV_AP1R0_EL1_NS,
 917         MISCREG_ICV_AP1R0_EL1_S,
 918         MISCREG_ICV_AP1R1_EL1,
 919         MISCREG_ICV_AP1R1_EL1_NS,
 920         MISCREG_ICV_AP1R1_EL1_S,
 921         MISCREG_ICV_AP1R2_EL1,
 922         MISCREG_ICV_AP1R2_EL1_NS,
 923         MISCREG_ICV_AP1R2_EL1_S,
 924         MISCREG_ICV_AP1R3_EL1,
 925         MISCREG_ICV_AP1R3_EL1_NS,
 926         MISCREG_ICV_AP1R3_EL1_S,
 927         MISCREG_ICV_DIR_EL1,
 928         MISCREG_ICV_RPR_EL1,
 929         MISCREG_ICV_SGI1R_EL1,
 930         MISCREG_ICV_ASGI1R_EL1,
 931         MISCREG_ICV_SGI0R_EL1,
 932         MISCREG_ICV_IAR1_EL1,
 933         MISCREG_ICV_EOIR1_EL1,
 934         MISCREG_ICV_HPPIR1_EL1,
 935         MISCREG_ICV_BPR1_EL1,
 936         MISCREG_ICV_BPR1_EL1_NS,
 937         MISCREG_ICV_BPR1_EL1_S,
 938         MISCREG_ICV_CTLR_EL1,
 939         MISCREG_ICV_CTLR_EL1_NS,
 940         MISCREG_ICV_CTLR_EL1_S,
 941         MISCREG_ICV_SRE_EL1,
 942         MISCREG_ICV_SRE_EL1_NS,
 943         MISCREG_ICV_SRE_EL1_S,
 944         MISCREG_ICV_IGRPEN0_EL1,
 945         MISCREG_ICV_IGRPEN1_EL1,
 946         MISCREG_ICV_IGRPEN1_EL1_NS,
 947         MISCREG_ICV_IGRPEN1_EL1_S,
 948
 949         MISCREG_ICC_AP0R0,
 950         MISCREG_ICC_AP0R1,
 951         MISCREG_ICC_AP0R2,
 952         MISCREG_ICC_AP0R3,
 953         MISCREG_ICC_AP1R0,
 954         MISCREG_ICC_AP1R0_NS,
 955         MISCREG_ICC_AP1R0_S,
 956         MISCREG_ICC_AP1R1,
 957         MISCREG_ICC_AP1R1_NS,
 958         MISCREG_ICC_AP1R1_S,
 959         MISCREG_ICC_AP1R2,
 960         MISCREG_ICC_AP1R2_NS,
 961         MISCREG_ICC_AP1R2_S,
 962         MISCREG_ICC_AP1R3,
 963         MISCREG_ICC_AP1R3_NS,
 964         MISCREG_ICC_AP1R3_S,
 965         MISCREG_ICC_ASGI1R,
 966         MISCREG_ICC_BPR0,
 967         MISCREG_ICC_BPR1,
 968         MISCREG_ICC_BPR1_NS,
 969         MISCREG_ICC_BPR1_S,
 970         MISCREG_ICC_CTLR,
 971         MISCREG_ICC_CTLR_NS,
 972         MISCREG_ICC_CTLR_S,
 973         MISCREG_ICC_DIR,
 974         MISCREG_ICC_EOIR0,
 975         MISCREG_ICC_EOIR1,
 976         MISCREG_ICC_HPPIR0,
 977         MISCREG_ICC_HPPIR1,
 978         MISCREG_ICC_HSRE,
 979         MISCREG_ICC_IAR0,
 980         MISCREG_ICC_IAR1,
 981         MISCREG_ICC_IGRPEN0,
 982         MISCREG_ICC_IGRPEN1,
 983         MISCREG_ICC_IGRPEN1_NS,
 984         MISCREG_ICC_IGRPEN1_S,
 985         MISCREG_ICC_MCTLR,
 986         MISCREG_ICC_MGRPEN1,
 987         MISCREG_ICC_MSRE,
 988         MISCREG_ICC_PMR,
 989         MISCREG_ICC_RPR,
 990         MISCREG_ICC_SGI0R,
 991         MISCREG_ICC_SGI1R,
 992         MISCREG_ICC_SRE,
 993         MISCREG_ICC_SRE_NS,
 994         MISCREG_ICC_SRE_S,
 995
 996         MISCREG_ICH_AP0R0,
 997         MISCREG_ICH_AP0R1,
 998         MISCREG_ICH_AP0R2,
 999         MISCREG_ICH_AP0R3,
1000         MISCREG_ICH_AP1R0,
1001         MISCREG_ICH_AP1R1,
1002         MISCREG_ICH_AP1R2,
1003         MISCREG_ICH_AP1R3,
1004         MISCREG_ICH_HCR,
1005         MISCREG_ICH_VTR,
1006         MISCREG_ICH_MISR,
1007         MISCREG_ICH_EISR,
1008         MISCREG_ICH_ELRSR,
1009         MISCREG_ICH_VMCR,
1010         MISCREG_ICH_LR0,
1011         MISCREG_ICH_LR1,
1012         MISCREG_ICH_LR2,
1013         MISCREG_ICH_LR3,
1014         MISCREG_ICH_LR4,
1015         MISCREG_ICH_LR5,
1016         MISCREG_ICH_LR6,
1017         MISCREG_ICH_LR7,
1018         MISCREG_ICH_LR8,
1019         MISCREG_ICH_LR9,
1020         MISCREG_ICH_LR10,
1021         MISCREG_ICH_LR11,
1022         MISCREG_ICH_LR12,
1023         MISCREG_ICH_LR13,
1024         MISCREG_ICH_LR14,
1025         MISCREG_ICH_LR15,
1026         MISCREG_ICH_LRC0,
1027         MISCREG_ICH_LRC1,
1028         MISCREG_ICH_LRC2,
1029         MISCREG_ICH_LRC3,
1030         MISCREG_ICH_LRC4,
1031         MISCREG_ICH_LRC5,
1032         MISCREG_ICH_LRC6,
1033         MISCREG_ICH_LRC7,
1034         MISCREG_ICH_LRC8,
1035         MISCREG_ICH_LRC9,
1036         MISCREG_ICH_LRC10,
1037         MISCREG_ICH_LRC11,
1038         MISCREG_ICH_LRC12,
1039         MISCREG_ICH_LRC13,
1040         MISCREG_ICH_LRC14,
1041         MISCREG_ICH_LRC15,
1042
1043         // SVE
1044         MISCREG_ID_AA64ZFR0_EL1,
1045         MISCREG_ZCR_EL3,
1046         MISCREG_ZCR_EL2,
1047         MISCREG_ZCR_EL12,
1048         MISCREG_ZCR_EL1,
1049
1050         // NUM_PHYS_MISCREGS specifies the number of actual physical
1051         // registers, not considering the following pseudo-registers
1052         // (dummy registers), like UNKNOWN, CP15_UNIMPL, MISCREG_IMPDEF_UNIMPL.
1053         // Checkpointing should use this physical index when
1054         // saving/restoring register values.
1055         NUM_PHYS_MISCREGS,
1056
1057         // Dummy registers
1058         MISCREG_NOP,
1059         MISCREG_RAZ,
1060         MISCREG_CP14_UNIMPL,
1061         MISCREG_CP15_UNIMPL,
1062         MISCREG_UNKNOWN,
1063
1064         // Implementation defined register: this represent
1065         // a pool of unimplemented registers whose access can throw
1066         // either UNDEFINED or hypervisor trap exception.
1067         MISCREG_IMPDEF_UNIMPL,
1068
1069         // RAS extension (unimplemented)
1070         MISCREG_ERRIDR_EL1,
1071         MISCREG_ERRSELR_EL1,
1072         MISCREG_ERXFR_EL1,
1073         MISCREG_ERXCTLR_EL1,
1074         MISCREG_ERXSTATUS_EL1,
1075         MISCREG_ERXADDR_EL1,
1076         MISCREG_ERXMISC0_EL1,
1077         MISCREG_ERXMISC1_EL1,
1078         MISCREG_DISR_EL1,
1079         MISCREG_VSESR_EL2,
1080         MISCREG_VDISR_EL2,
1081
1082         // PSTATE
1083         MISCREG_PAN,
1084
1085         // Total number of Misc Registers: Physical + Dummy
1086         NUM_MISCREGS
1087     };
1088
1089     enum MiscRegInfo {
1090         MISCREG_IMPLEMENTED,
1091         MISCREG_UNVERIFIABLE,   // Does the value change on every read (e.g. a
1092                                 // arch generic counter)
1093         MISCREG_WARN_NOT_FAIL,  // If MISCREG_IMPLEMENTED is deasserted, it
1094                                 // tells whether the instruction should raise a
1095                                 // warning or fail
1096         MISCREG_MUTEX,  // True if the register corresponds to a pair of
1097                         // mutually exclusive registers
1098         MISCREG_BANKED,  // True if the register is banked between the two
1099                          // security states, and this is the parent node of the
1100                          // two banked registers
1101         MISCREG_BANKED64, // True if the register is banked between the two
1102                           // security states, and this is the parent node of
1103                           // the two banked registers. Used in AA64 only.
1104         MISCREG_BANKED_CHILD, // The entry is one of the child registers that
1105                               // forms a banked set of regs (along with the
1106                               // other child regs)
1107
1108         // Access permissions
1109         // User mode
1110         MISCREG_USR_NS_RD,
1111         MISCREG_USR_NS_WR,
1112         MISCREG_USR_S_RD,
1113         MISCREG_USR_S_WR,
1114         // Privileged modes other than hypervisor or monitor
1115         MISCREG_PRI_NS_RD,
1116         MISCREG_PRI_NS_WR,
1117         MISCREG_PRI_S_RD,
1118         MISCREG_PRI_S_WR,
1119         // Hypervisor mode
1120         MISCREG_HYP_RD,
1121         MISCREG_HYP_WR,
1122         // Hypervisor mode, HCR_EL2.E2H == 1
1123         MISCREG_HYP_E2H_RD,
1124         MISCREG_HYP_E2H_WR,
1125         // Monitor mode, SCR.NS == 0
1126         MISCREG_MON_NS0_RD,
1127         MISCREG_MON_NS0_WR,
1128         // Monitor mode, SCR.NS == 1
1129         MISCREG_MON_NS1_RD,
1130         MISCREG_MON_NS1_WR,
1131         // Monitor mode, HCR_EL2.E2H == 1
1132         MISCREG_MON_E2H_RD,
1133         MISCREG_MON_E2H_WR,
1134
1135         NUM_MISCREG_INFOS
1136     };
1137
1138     extern std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS];
1139
1140     // Decodes 32-bit CP14 registers accessible through MCR/MRC instructions
1141     MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1,
1142                                unsigned crm, unsigned opc2);
1143     MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1,
1144                                      unsigned crn, unsigned crm,
1145                                      unsigned op2);
1146     // Whether a particular AArch64 system register is -always- read only.
1147     bool aarch64SysRegReadOnly(MiscRegIndex miscReg);
1148
1149     // Decodes 32-bit CP15 registers accessible through MCR/MRC instructions
1150     MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
1151                                unsigned crm, unsigned opc2);
1152
1153     // Decodes 64-bit CP15 registers accessible through MCRR/MRRC instructions
1154     MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1);
1155
1156
1157     const char * const miscRegName[] = {
1158         "cpsr",
1159         "spsr",
1160         "spsr_fiq",
1161         "spsr_irq",
1162         "spsr_svc",
1163         "spsr_mon",
1164         "spsr_abt",
1165         "spsr_hyp",
1166         "spsr_und",
1167         "elr_hyp",
1168         "fpsid",
1169         "fpscr",
1170         "mvfr1",
1171         "mvfr0",
1172         "fpexc",
1173
1174         // Helper registers
1175         "cpsr_mode",
1176         "cpsr_q",
1177         "fpscr_exc",
1178         "fpscr_qc",
1179         "lockaddr",
1180         "lockflag",
1181         "prrr_mair0",
1182         "prrr_mair0_ns",
1183         "prrr_mair0_s",
1184         "nmrr_mair1",
1185         "nmrr_mair1_ns",
1186         "nmrr_mair1_s",
1187         "pmxevtyper_pmccfiltr",
1188         "sctlr_rst",
1189         "sev_mailbox",
1190
1191         // AArch32 CP14 registers
1192         "dbgdidr",
1193         "dbgdscrint",
1194         "dbgdccint",
1195         "dbgdtrtxint",
1196         "dbgdtrrxint",
1197         "dbgwfar",
1198         "dbgvcr",
1199         "dbgdtrrxext",
1200         "dbgdscrext",
1201         "dbgdtrtxext",
1202         "dbgoseccr",
1203         "dbgbvr0",
1204         "dbgbvr1",
1205         "dbgbvr2",
1206         "dbgbvr3",
1207         "dbgbvr4",
1208         "dbgbvr5",
1209         "dbgbvr6",
1210         "dbgbvr7",
1211         "dbgbvr8",
1212         "dbgbvr9",
1213         "dbgbvr10",
1214         "dbgbvr11",
1215         "dbgbvr12",
1216         "dbgbvr13",
1217         "dbgbvr14",
1218         "dbgbvr15",
1219         "dbgbcr0",
1220         "dbgbcr1",
1221         "dbgbcr2",
1222         "dbgbcr3",
1223         "dbgbcr4",
1224         "dbgbcr5",
1225         "dbgbcr6",
1226         "dbgbcr7",
1227         "dbgbcr8",
1228         "dbgbcr9",
1229         "dbgbcr10",
1230         "dbgbcr11",
1231         "dbgbcr12",
1232         "dbgbcr13",
1233         "dbgbcr14",
1234         "dbgbcr15",
1235         "dbgwvr0",
1236         "dbgwvr1",
1237         "dbgwvr2",
1238         "dbgwvr3",
1239         "dbgwvr4",
1240         "dbgwvr5",
1241         "dbgwvr6",
1242         "dbgwvr7",
1243         "dbgwvr8",
1244         "dbgwvr9",
1245         "dbgwvr10",
1246         "dbgwvr11",
1247         "dbgwvr12",
1248         "dbgwvr13",
1249         "dbgwvr14",
1250         "dbgwvr15",
1251         "dbgwcr0",
1252         "dbgwcr1",
1253         "dbgwcr2",
1254         "dbgwcr3",
1255         "dbgwcr4",
1256         "dbgwcr5",
1257         "dbgwcr6",
1258         "dbgwcr7",
1259         "dbgwcr8",
1260         "dbgwcr9",
1261         "dbgwcr10",
1262         "dbgwcr11",
1263         "dbgwcr12",
1264         "dbgwcr13",
1265         "dbgwcr14",
1266         "dbgwcr15",
1267         "dbgdrar",
1268         "dbgbxvr0",
1269         "dbgbxvr1",
1270         "dbgbxvr2",
1271         "dbgbxvr3",
1272         "dbgbxvr4",
1273         "dbgbxvr5",
1274         "dbgbxvr6",
1275         "dbgbxvr7",
1276         "dbgbxvr8",
1277         "dbgbxvr9",
1278         "dbgbxvr10",
1279         "dbgbxvr11",
1280         "dbgbxvr12",
1281         "dbgbxvr13",
1282         "dbgbxvr14",
1283         "dbgbxvr15",
1284         "dbgoslar",
1285         "dbgoslsr",
1286         "dbgosdlr",
1287         "dbgprcr",
1288         "dbgdsar",
1289         "dbgclaimset",
1290         "dbgclaimclr",
1291         "dbgauthstatus",
1292         "dbgdevid2",
1293         "dbgdevid1",
1294         "dbgdevid0",
1295         "teecr",
1296         "jidr",
1297         "teehbr",
1298         "joscr",
1299         "jmcr",
1300
1301         // AArch32 CP15 registers
1302         "midr",
1303         "ctr",
1304         "tcmtr",
1305         "tlbtr",
1306         "mpidr",
1307         "revidr",
1308         "id_pfr0",
1309         "id_pfr1",
1310         "id_dfr0",
1311         "id_afr0",
1312         "id_mmfr0",
1313         "id_mmfr1",
1314         "id_mmfr2",
1315         "id_mmfr3",
1316         "id_isar0",
1317         "id_isar1",
1318         "id_isar2",
1319         "id_isar3",
1320         "id_isar4",
1321         "id_isar5",
1322         "ccsidr",
1323         "clidr",
1324         "aidr",
1325         "csselr",
1326         "csselr_ns",
1327         "csselr_s",
1328         "vpidr",
1329         "vmpidr",
1330         "sctlr",
1331         "sctlr_ns",
1332         "sctlr_s",
1333         "actlr",
1334         "actlr_ns",
1335         "actlr_s",
1336         "cpacr",
1337         "sdrc",
1338         "scr",
1339         "sder",
1340         "nsacr",
1341         "hsctlr",
1342         "hactlr",
1343         "hcr",
1344         "hcr2",
1345         "hdcr",
1346         "hcptr",
1347         "hstr",
1348         "hacr",
1349         "ttbr0",
1350         "ttbr0_ns",
1351         "ttbr0_s",
1352         "ttbr1",
1353         "ttbr1_ns",
1354         "ttbr1_s",
1355         "ttbcr",
1356         "ttbcr_ns",
1357         "ttbcr_s",
1358         "htcr",
1359         "vtcr",
1360         "dacr",
1361         "dacr_ns",
1362         "dacr_s",
1363         "dfsr",
1364         "dfsr_ns",
1365         "dfsr_s",
1366         "ifsr",
1367         "ifsr_ns",
1368         "ifsr_s",
1369         "adfsr",
1370         "adfsr_ns",
1371         "adfsr_s",
1372         "aifsr",
1373         "aifsr_ns",
1374         "aifsr_s",
1375         "hadfsr",
1376         "haifsr",
1377         "hsr",
1378         "dfar",
1379         "dfar_ns",
1380         "dfar_s",
1381         "ifar",
1382         "ifar_ns",
1383         "ifar_s",
1384         "hdfar",
1385         "hifar",
1386         "hpfar",
1387         "icialluis",
1388         "bpiallis",
1389         "par",
1390         "par_ns",
1391         "par_s",
1392         "iciallu",
1393         "icimvau",
1394         "cp15isb",
1395         "bpiall",
1396         "bpimva",
1397         "dcimvac",
1398         "dcisw",
1399         "ats1cpr",
1400         "ats1cpw",
1401         "ats1cur",
1402         "ats1cuw",
1403         "ats12nsopr",
1404         "ats12nsopw",
1405         "ats12nsour",
1406         "ats12nsouw",
1407         "dccmvac",
1408         "dccsw",
1409         "cp15dsb",
1410         "cp15dmb",
1411         "dccmvau",
1412         "dccimvac",
1413         "dccisw",
1414         "ats1hr",
1415         "ats1hw",
1416         "tlbiallis",
1417         "tlbimvais",
1418         "tlbiasidis",
1419         "tlbimvaais",
1420         "tlbimvalis",
1421         "tlbimvaalis",
1422         "itlbiall",
1423         "itlbimva",
1424         "itlbiasid",
1425         "dtlbiall",
1426         "dtlbimva",
1427         "dtlbiasid",
1428         "tlbiall",
1429         "tlbimva",
1430         "tlbiasid",
1431         "tlbimvaa",
1432         "tlbimval",
1433         "tlbimvaal",
1434         "tlbiipas2is",
1435         "tlbiipas2lis",
1436         "tlbiallhis",
1437         "tlbimvahis",
1438         "tlbiallnsnhis",
1439         "tlbimvalhis",
1440         "tlbiipas2",
1441         "tlbiipas2l",
1442         "tlbiallh",
1443         "tlbimvah",
1444         "tlbiallnsnh",
1445         "tlbimvalh",
1446         "pmcr",
1447         "pmcntenset",
1448         "pmcntenclr",
1449         "pmovsr",
1450         "pmswinc",
1451         "pmselr",
1452         "pmceid0",
1453         "pmceid1",
1454         "pmccntr",
1455         "pmxevtyper",
1456         "pmccfiltr",
1457         "pmxevcntr",
1458         "pmuserenr",
1459         "pmintenset",
1460         "pmintenclr",
1461         "pmovsset",
1462         "l2ctlr",
1463         "l2ectlr",
1464         "prrr",
1465         "prrr_ns",
1466         "prrr_s",
1467         "mair0",
1468         "mair0_ns",
1469         "mair0_s",
1470         "nmrr",
1471         "nmrr_ns",
1472         "nmrr_s",
1473         "mair1",
1474         "mair1_ns",
1475         "mair1_s",
1476         "amair0",
1477         "amair0_ns",
1478         "amair0_s",
1479         "amair1",
1480         "amair1_ns",
1481         "amair1_s",
1482         "hmair0",
1483         "hmair1",
1484         "hamair0",
1485         "hamair1",
1486         "vbar",
1487         "vbar_ns",
1488         "vbar_s",
1489         "mvbar",
1490         "rmr",
1491         "isr",
1492         "hvbar",
1493         "fcseidr",
1494         "contextidr",
1495         "contextidr_ns",
1496         "contextidr_s",
1497         "tpidrurw",
1498         "tpidrurw_ns",
1499         "tpidrurw_s",
1500         "tpidruro",
1501         "tpidruro_ns",
1502         "tpidruro_s",
1503         "tpidrprw",
1504         "tpidrprw_ns",
1505         "tpidrprw_s",
1506         "htpidr",
1507         "cntfrq",
1508         "cntpct",
1509         "cntvct",
1510         "cntp_ctl",
1511         "cntp_ctl_ns",
1512         "cntp_ctl_s",
1513         "cntp_cval",
1514         "cntp_cval_ns",
1515         "cntp_cval_s",
1516         "cntp_tval",
1517         "cntp_tval_ns",
1518         "cntp_tval_s",
1519         "cntv_ctl",
1520         "cntv_cval",
1521         "cntv_tval",
1522         "cntkctl",
1523         "cnthctl",
1524         "cnthp_ctl",
1525         "cnthp_cval",
1526         "cnthp_tval",
1527         "cntvoff",
1528         "il1data0",
1529         "il1data1",
1530         "il1data2",
1531         "il1data3",
1532         "dl1data0",
1533         "dl1data1",
1534         "dl1data2",
1535         "dl1data3",
1536         "dl1data4",
1537         "ramindex",
1538         "l2actlr",
1539         "cbar",
1540         "httbr",
1541         "vttbr",
1542         "cpumerrsr",
1543         "l2merrsr",
1544
1545         // AArch64 registers (Op0=2)
1546         "mdccint_el1",
1547         "osdtrrx_el1",
1548         "mdscr_el1",
1549         "osdtrtx_el1",
1550         "oseccr_el1",
1551         "dbgbvr0_el1",
1552         "dbgbvr1_el1",
1553         "dbgbvr2_el1",
1554         "dbgbvr3_el1",
1555         "dbgbvr4_el1",
1556         "dbgbvr5_el1",
1557         "dbgbvr6_el1",
1558         "dbgbvr7_el1",
1559         "dbgbvr8_el1",
1560         "dbgbvr9_el1",
1561         "dbgbvr10_el1",
1562         "dbgbvr11_el1",
1563         "dbgbvr12_el1",
1564         "dbgbvr13_el1",
1565         "dbgbvr14_el1",
1566         "dbgbvr15_el1",
1567         "dbgbcr0_el1",
1568         "dbgbcr1_el1",
1569         "dbgbcr2_el1",
1570         "dbgbcr3_el1",
1571         "dbgbcr4_el1",
1572         "dbgbcr5_el1",
1573         "dbgbcr6_el1",
1574         "dbgbcr7_el1",
1575         "dbgbcr8_el1",
1576         "dbgbcr9_el1",
1577         "dbgbcr10_el1",
1578         "dbgbcr11_el1",
1579         "dbgbcr12_el1",
1580         "dbgbcr13_el1",
1581         "dbgbcr14_el1",
1582         "dbgbcr15_el1",
1583         "dbgwvr0_el1",
1584         "dbgwvr1_el1",
1585         "dbgwvr2_el1",
1586         "dbgwvr3_el1",
1587         "dbgwvr4_el1",
1588         "dbgwvr5_el1",
1589         "dbgwvr6_el1",
1590         "dbgwvr7_el1",
1591         "dbgwvr8_el1",
1592         "dbgwvr9_el1",
1593         "dbgwvr10_el1",
1594         "dbgwvr11_el1",
1595         "dbgwvr12_el1",
1596         "dbgwvr13_el1",
1597         "dbgwvr14_el1",
1598         "dbgwvr15_el1",
1599         "dbgwcr0_el1",
1600         "dbgwcr1_el1",
1601         "dbgwcr2_el1",
1602         "dbgwcr3_el1",
1603         "dbgwcr4_el1",
1604         "dbgwcr5_el1",
1605         "dbgwcr6_el1",
1606         "dbgwcr7_el1",
1607         "dbgwcr8_el1",
1608         "dbgwcr9_el1",
1609         "dbgwcr10_el1",
1610         "dbgwcr11_el1",
1611         "dbgwcr12_el1",
1612         "dbgwcr13_el1",
1613         "dbgwcr14_el1",
1614         "dbgwcr15_el1",
1615         "mdccsr_el0",
1616         "mddtr_el0",
1617         "mddtrtx_el0",
1618         "mddtrrx_el0",
1619         "dbgvcr32_el2",
1620         "mdrar_el1",
1621         "oslar_el1",
1622         "oslsr_el1",
1623         "osdlr_el1",
1624         "dbgprcr_el1",
1625         "dbgclaimset_el1",
1626         "dbgclaimclr_el1",
1627         "dbgauthstatus_el1",
1628         "teecr32_el1",
1629         "teehbr32_el1",
1630
1631         // AArch64 registers (Op0=1,3)
1632         "midr_el1",
1633         "mpidr_el1",
1634         "revidr_el1",
1635         "id_pfr0_el1",
1636         "id_pfr1_el1",
1637         "id_dfr0_el1",
1638         "id_afr0_el1",
1639         "id_mmfr0_el1",
1640         "id_mmfr1_el1",
1641         "id_mmfr2_el1",
1642         "id_mmfr3_el1",
1643         "id_isar0_el1",
1644         "id_isar1_el1",
1645         "id_isar2_el1",
1646         "id_isar3_el1",
1647         "id_isar4_el1",
1648         "id_isar5_el1",
1649         "mvfr0_el1",
1650         "mvfr1_el1",
1651         "mvfr2_el1",
1652         "id_aa64pfr0_el1",
1653         "id_aa64pfr1_el1",
1654         "id_aa64dfr0_el1",
1655         "id_aa64dfr1_el1",
1656         "id_aa64afr0_el1",
1657         "id_aa64afr1_el1",
1658         "id_aa64isar0_el1",
1659         "id_aa64isar1_el1",
1660         "id_aa64mmfr0_el1",
1661         "id_aa64mmfr1_el1",
1662         "ccsidr_el1",
1663         "clidr_el1",
1664         "aidr_el1",
1665         "csselr_el1",
1666         "ctr_el0",
1667         "dczid_el0",
1668         "vpidr_el2",
1669         "vmpidr_el2",
1670         "sctlr_el1",
1671         "sctlr_el12",
1672         "actlr_el1",
1673         "cpacr_el1",
1674         "cpacr_el12",
1675         "sctlr_el2",
1676         "actlr_el2",
1677         "hcr_el2",
1678         "mdcr_el2",
1679         "cptr_el2",
1680         "hstr_el2",
1681         "hacr_el2",
1682         "sctlr_el3",
1683         "actlr_el3",
1684         "scr_el3",
1685         "sder32_el3",
1686         "cptr_el3",
1687         "mdcr_el3",
1688         "ttbr0_el1",
1689         "ttbr0_el12",
1690         "ttbr1_el1",
1691         "ttbr1_el12",
1692         "tcr_el1",
1693         "tcr_el12",
1694         "ttbr0_el2",
1695         "tcr_el2",
1696         "vttbr_el2",
1697         "vtcr_el2",
1698         "ttbr0_el3",
1699         "tcr_el3",
1700         "dacr32_el2",
1701         "spsr_el1",
1702         "spsr_el12",
1703         "elr_el1",
1704         "elr_el12",
1705         "sp_el0",
1706         "spsel",
1707         "currentel",
1708         "nzcv",
1709         "daif",
1710         "fpcr",
1711         "fpsr",
1712         "dspsr_el0",
1713         "dlr_el0",
1714         "spsr_el2",
1715         "elr_el2",
1716         "sp_el1",
1717         "spsr_irq_aa64",
1718         "spsr_abt_aa64",
1719         "spsr_und_aa64",
1720         "spsr_fiq_aa64",
1721         "spsr_el3",
1722         "elr_el3",
1723         "sp_el2",
1724         "afsr0_el1",
1725         "afsr0_el12",
1726         "afsr1_el1",
1727         "afsr1_el12",
1728         "esr_el1",
1729         "esr_el12",
1730         "ifsr32_el2",
1731         "afsr0_el2",
1732         "afsr1_el2",
1733         "esr_el2",
1734         "fpexc32_el2",
1735         "afsr0_el3",
1736         "afsr1_el3",
1737         "esr_el3",
1738         "far_el1",
1739         "far_el12",
1740         "far_el2",
1741         "hpfar_el2",
1742         "far_el3",
1743         "ic_ialluis",
1744         "par_el1",
1745         "ic_iallu",
1746         "dc_ivac_xt",
1747         "dc_isw_xt",
1748         "at_s1e1r_xt",
1749         "at_s1e1w_xt",
1750         "at_s1e0r_xt",
1751         "at_s1e0w_xt",
1752         "dc_csw_xt",
1753         "dc_cisw_xt",
1754         "dc_zva_xt",
1755         "ic_ivau_xt",
1756         "dc_cvac_xt",
1757         "dc_cvau_xt",
1758         "dc_civac_xt",
1759         "at_s1e2r_xt",
1760         "at_s1e2w_xt",
1761         "at_s12e1r_xt",
1762         "at_s12e1w_xt",
1763         "at_s12e0r_xt",
1764         "at_s12e0w_xt",
1765         "at_s1e3r_xt",
1766         "at_s1e3w_xt",
1767         "tlbi_vmalle1is",
1768         "tlbi_vae1is_xt",
1769         "tlbi_aside1is_xt",
1770         "tlbi_vaae1is_xt",
1771         "tlbi_vale1is_xt",
1772         "tlbi_vaale1is_xt",
1773         "tlbi_vmalle1",
1774         "tlbi_vae1_xt",
1775         "tlbi_aside1_xt",
1776         "tlbi_vaae1_xt",
1777         "tlbi_vale1_xt",
1778         "tlbi_vaale1_xt",
1779         "tlbi_ipas2e1is_xt",
1780         "tlbi_ipas2le1is_xt",
1781         "tlbi_alle2is",
1782         "tlbi_vae2is_xt",
1783         "tlbi_alle1is",
1784         "tlbi_vale2is_xt",
1785         "tlbi_vmalls12e1is",
1786         "tlbi_ipas2e1_xt",
1787         "tlbi_ipas2le1_xt",
1788         "tlbi_alle2",
1789         "tlbi_vae2_xt",
1790         "tlbi_alle1",
1791         "tlbi_vale2_xt",
1792         "tlbi_vmalls12e1",
1793         "tlbi_alle3is",
1794         "tlbi_vae3is_xt",
1795         "tlbi_vale3is_xt",
1796         "tlbi_alle3",
1797         "tlbi_vae3_xt",
1798         "tlbi_vale3_xt",
1799         "pmintenset_el1",
1800         "pmintenclr_el1",
1801         "pmcr_el0",
1802         "pmcntenset_el0",
1803         "pmcntenclr_el0",
1804         "pmovsclr_el0",
1805         "pmswinc_el0",
1806         "pmselr_el0",
1807         "pmceid0_el0",
1808         "pmceid1_el0",
1809         "pmccntr_el0",
1810         "pmxevtyper_el0",
1811         "pmccfiltr_el0",
1812         "pmxevcntr_el0",
1813         "pmuserenr_el0",
1814         "pmovsset_el0",
1815         "mair_el1",
1816         "mair_el12",
1817         "amair_el1",
1818         "amair_el12",
1819         "mair_el2",
1820         "amair_el2",
1821         "mair_el3",
1822         "amair_el3",
1823         "l2ctlr_el1",
1824         "l2ectlr_el1",
1825         "vbar_el1",
1826         "vbar_el12",
1827         "rvbar_el1",
1828         "isr_el1",
1829         "vbar_el2",
1830         "rvbar_el2",
1831         "vbar_el3",
1832         "rvbar_el3",
1833         "rmr_el3",
1834         "contextidr_el1",
1835         "contextidr_el12",
1836         "tpidr_el1",
1837         "tpidr_el0",
1838         "tpidrro_el0",
1839         "tpidr_el2",
1840         "tpidr_el3",
1841         "cntfrq_el0",
1842         "cntpct_el0",
1843         "cntvct_el0",
1844         "cntp_ctl_el0",
1845         "cntp_cval_el0",
1846         "cntp_tval_el0",
1847         "cntv_ctl_el0",
1848         "cntv_cval_el0",
1849         "cntv_tval_el0",
1850         "cntp_ctl_el02",
1851         "cntp_cval_el02",
1852         "cntp_tval_el02",
1853         "cntv_ctl_el02",
1854         "cntv_cval_el02",
1855         "cntv_tval_el02",
1856         "cntkctl_el1",
1857         "cntkctl_el12",
1858         "cntps_ctl_el1",
1859         "cntps_cval_el1",
1860         "cntps_tval_el1",
1861         "cnthctl_el2",
1862         "cnthp_ctl_el2",
1863         "cnthp_cval_el2",
1864         "cnthp_tval_el2",
1865         "cnthps_ctl_el2",
1866         "cnthps_cval_el2",
1867         "cnthps_tval_el2",
1868         "cnthv_ctl_el2",
1869         "cnthv_cval_el2",
1870         "cnthv_tval_el2",
1871         "cnthvs_ctl_el2",
1872         "cnthvs_cval_el2",
1873         "cnthvs_tval_el2",
1874         "cntvoff_el2",
1875         "pmevcntr0_el0",
1876         "pmevcntr1_el0",
1877         "pmevcntr2_el0",
1878         "pmevcntr3_el0",
1879         "pmevcntr4_el0",
1880         "pmevcntr5_el0",
1881         "pmevtyper0_el0",
1882         "pmevtyper1_el0",
1883         "pmevtyper2_el0",
1884         "pmevtyper3_el0",
1885         "pmevtyper4_el0",
1886         "pmevtyper5_el0",
1887         "il1data0_el1",
1888         "il1data1_el1",
1889         "il1data2_el1",
1890         "il1data3_el1",
1891         "dl1data0_el1",
1892         "dl1data1_el1",
1893         "dl1data2_el1",
1894         "dl1data3_el1",
1895         "dl1data4_el1",
1896         "l2actlr_el1",
1897         "cpuactlr_el1",
1898         "cpuectlr_el1",
1899         "cpumerrsr_el1",
1900         "l2merrsr_el1",
1901         "cbar_el1",
1902         "contextidr_el2",
1903
1904         "ttbr1_el2",
1905         "id_aa64mmfr2_el1",
1906
1907         "apdakeyhi_el1",
1908         "apdakeylo_el1",
1909         "apdbkeyhi_el1",
1910         "apdbkeylo_el1",
1911         "apgakeyhi_el1",
1912         "apgakeylo_el1",
1913         "apiakeyhi_el1",
1914         "apiakeylo_el1",
1915         "apibkeyhi_el1",
1916         "apibkeylo_el1",
1917         // GICv3, CPU interface
1918         "icc_pmr_el1",
1919         "icc_iar0_el1",
1920         "icc_eoir0_el1",
1921         "icc_hppir0_el1",
1922         "icc_bpr0_el1",
1923         "icc_ap0r0_el1",
1924         "icc_ap0r1_el1",
1925         "icc_ap0r2_el1",
1926         "icc_ap0r3_el1",
1927         "icc_ap1r0_el1",
1928         "icc_ap1r0_el1_ns",
1929         "icc_ap1r0_el1_s",
1930         "icc_ap1r1_el1",
1931         "icc_ap1r1_el1_ns",
1932         "icc_ap1r1_el1_s",
1933         "icc_ap1r2_el1",
1934         "icc_ap1r2_el1_ns",
1935         "icc_ap1r2_el1_s",
1936         "icc_ap1r3_el1",
1937         "icc_ap1r3_el1_ns",
1938         "icc_ap1r3_el1_s",
1939         "icc_dir_el1",
1940         "icc_rpr_el1",
1941         "icc_sgi1r_el1",
1942         "icc_asgi1r_el1",
1943         "icc_sgi0r_el1",
1944         "icc_iar1_el1",
1945         "icc_eoir1_el1",
1946         "icc_hppir1_el1",
1947         "icc_bpr1_el1",
1948         "icc_bpr1_el1_ns",
1949         "icc_bpr1_el1_s",
1950         "icc_ctlr_el1",
1951         "icc_ctlr_el1_ns",
1952         "icc_ctlr_el1_s",
1953         "icc_sre_el1",
1954         "icc_sre_el1_ns",
1955         "icc_sre_el1_s",
1956         "icc_igrpen0_el1",
1957         "icc_igrpen1_el1",
1958         "icc_igrpen1_el1_ns",
1959         "icc_igrpen1_el1_s",
1960         "icc_sre_el2",
1961         "icc_ctlr_el3",
1962         "icc_sre_el3",
1963         "icc_igrpen1_el3",
1964
1965         // GICv3, CPU interface, virtualization
1966         "ich_ap0r0_el2",
1967         "ich_ap0r1_el2",
1968         "ich_ap0r2_el2",
1969         "ich_ap0r3_el2",
1970         "ich_ap1r0_el2",
1971         "ich_ap1r1_el2",
1972         "ich_ap1r2_el2",
1973         "ich_ap1r3_el2",
1974         "ich_hcr_el2",
1975         "ich_vtr_el2",
1976         "ich_misr_el2",
1977         "ich_eisr_el2",
1978         "ich_elrsr_el2",
1979         "ich_vmcr_el2",
1980         "ich_lr0_el2",
1981         "ich_lr1_el2",
1982         "ich_lr2_el2",
1983         "ich_lr3_el2",
1984         "ich_lr4_el2",
1985         "ich_lr5_el2",
1986         "ich_lr6_el2",
1987         "ich_lr7_el2",
1988         "ich_lr8_el2",
1989         "ich_lr9_el2",
1990         "ich_lr10_el2",
1991         "ich_lr11_el2",
1992         "ich_lr12_el2",
1993         "ich_lr13_el2",
1994         "ich_lr14_el2",
1995         "ich_lr15_el2",
1996
1997         "icv_pmr_el1",
1998         "icv_iar0_el1",
1999         "icv_eoir0_el1",
2000         "icv_hppir0_el1",
2001         "icv_bpr0_el1",
2002         "icv_ap0r0_el1",
2003         "icv_ap0r1_el1",
2004         "icv_ap0r2_el1",
2005         "icv_ap0r3_el1",
2006         "icv_ap1r0_el1",
2007         "icv_ap1r0_el1_ns",
2008         "icv_ap1r0_el1_s",
2009         "icv_ap1r1_el1",
2010         "icv_ap1r1_el1_ns",
2011         "icv_ap1r1_el1_s",
2012         "icv_ap1r2_el1",
2013         "icv_ap1r2_el1_ns",
2014         "icv_ap1r2_el1_s",
2015         "icv_ap1r3_el1",
2016         "icv_ap1r3_el1_ns",
2017         "icv_ap1r3_el1_s",
2018         "icv_dir_el1",
2019         "icv_rpr_el1",
2020         "icv_sgi1r_el1",
2021         "icv_asgi1r_el1",
2022         "icv_sgi0r_el1",
2023         "icv_iar1_el1",
2024         "icv_eoir1_el1",
2025         "icv_hppir1_el1",
2026         "icv_bpr1_el1",
2027         "icv_bpr1_el1_ns",
2028         "icv_bpr1_el1_s",
2029         "icv_ctlr_el1",
2030         "icv_ctlr_el1_ns",
2031         "icv_ctlr_el1_s",
2032         "icv_sre_el1",
2033         "icv_sre_el1_ns",
2034         "icv_sre_el1_s",
2035         "icv_igrpen0_el1",
2036         "icv_igrpen1_el1",
2037         "icv_igrpen1_el1_ns",
2038         "icv_igrpen1_el1_s",
2039
2040         "icc_ap0r0",
2041         "icc_ap0r1",
2042         "icc_ap0r2",
2043         "icc_ap0r3",
2044         "icc_ap1r0",
2045         "icc_ap1r0_ns",
2046         "icc_ap1r0_s",
2047         "icc_ap1r1",
2048         "icc_ap1r1_ns",
2049         "icc_ap1r1_s",
2050         "icc_ap1r2",
2051         "icc_ap1r2_ns",
2052         "icc_ap1r2_s",
2053         "icc_ap1r3",
2054         "icc_ap1r3_ns",
2055         "icc_ap1r3_s",
2056         "icc_asgi1r",
2057         "icc_bpr0",
2058         "icc_bpr1",
2059         "icc_bpr1_ns",
2060         "icc_bpr1_s",
2061         "icc_ctlr",
2062         "icc_ctlr_ns",
2063         "icc_ctlr_s",
2064         "icc_dir",
2065         "icc_eoir0",
2066         "icc_eoir1",
2067         "icc_hppir0",
2068         "icc_hppir1",
2069         "icc_hsre",
2070         "icc_iar0",
2071         "icc_iar1",
2072         "icc_igrpen0",
2073         "icc_igrpen1",
2074         "icc_igrpen1_ns",
2075         "icc_igrpen1_s",
2076         "icc_mctlr",
2077         "icc_mgrpen1",
2078         "icc_msre",
2079         "icc_pmr",
2080         "icc_rpr",
2081         "icc_sgi0r",
2082         "icc_sgi1r",
2083         "icc_sre",
2084         "icc_sre_ns",
2085         "icc_sre_s",
2086
2087         "ich_ap0r0",
2088         "ich_ap0r1",
2089         "ich_ap0r2",
2090         "ich_ap0r3",
2091         "ich_ap1r0",
2092         "ich_ap1r1",
2093         "ich_ap1r2",
2094         "ich_ap1r3",
2095         "ich_hcr",
2096         "ich_vtr",
2097         "ich_misr",
2098         "ich_eisr",
2099         "ich_elrsr",
2100         "ich_vmcr",
2101         "ich_lr0",
2102         "ich_lr1",
2103         "ich_lr2",
2104         "ich_lr3",
2105         "ich_lr4",
2106         "ich_lr5",
2107         "ich_lr6",
2108         "ich_lr7",
2109         "ich_lr8",
2110         "ich_lr9",
2111         "ich_lr10",
2112         "ich_lr11",
2113         "ich_lr12",
2114         "ich_lr13",
2115         "ich_lr14",
2116         "ich_lr15",
2117         "ich_lrc0",
2118         "ich_lrc1",
2119         "ich_lrc2",
2120         "ich_lrc3",
2121         "ich_lrc4",
2122         "ich_lrc5",
2123         "ich_lrc6",
2124         "ich_lrc7",
2125         "ich_lrc8",
2126         "ich_lrc9",
2127         "ich_lrc10",
2128         "ich_lrc11",
2129         "ich_lrc12",
2130         "ich_lrc13",
2131         "ich_lrc14",
2132         "ich_lrc15",
2133
2134         "id_aa64zfr0_el1",
2135         "zcr_el3",
2136         "zcr_el2",
2137         "zcr_el12",
2138         "zcr_el1",
2139
2140         "num_phys_regs",
2141
2142         // Dummy registers
2143         "nop",
2144         "raz",
2145         "cp14_unimpl",
2146         "cp15_unimpl",
2147         "unknown",
2148         "impl_defined",
2149         "erridr_el1",
2150         "errselr_el1",
2151         "erxfr_el1",
2152         "erxctlr_el1",
2153         "erxstatus_el1",
2154         "erxaddr_el1",
2155         "erxmisc0_el1",
2156         "erxmisc1_el1",
2157         "disr_el1",
2158         "vsesr_el2",
2159         "vdisr_el2",
2160
2161         // PSTATE
2162         "pan",
2163     };
2164
2165     static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
2166                   "The miscRegName array and NUM_MISCREGS are inconsistent.");
2167
2168     // This mask selects bits of the CPSR that actually go in the CondCodes
2169     // integer register to allow renaming.
2170     static const uint32_t CondCodesMask   = 0xF00F0000;
2171     static const uint32_t CpsrMaskQ       = 0x08000000;
2172
2173     // APSR (Application Program Status Register Mask). It is the user level
2174     // alias for the CPSR. The APSR is a subset of the CPSR. Although
2175     // bits[15:0] are UNKNOWN on reads, it is permitted that, on a read of
2176     // APSR:
2177     // Bit[9] returns the value of CPSR.E.
2178     // Bits[8:6] return the value of CPSR.{A,I, F}, the mask bits.
2179     static const uint32_t ApsrMask = CpsrMaskQ | CondCodesMask | 0x000001D0;
2180
2181     // CPSR (Current Program Status Register Mask).
2182     static const uint32_t CpsrMask = ApsrMask | 0x00F003DF;
2183
2184     // This mask selects bits of the FPSCR that actually go in the FpCondCodes
2185     // integer register to allow renaming.
2186     static const uint32_t FpCondCodesMask = 0xF0000000;
2187     // This mask selects the cumulative saturation flag of the FPSCR.
2188     static const uint32_t FpscrQcMask = 0x08000000;
2189     // This mask selects the AHP bit of the FPSCR.
2190     static const uint32_t FpscrAhpMask = 0x04000000;
2191     // This mask selects the cumulative FP exception flags of the FPSCR.
2192     static const uint32_t FpscrExcMask = 0x0000009F;
2193
2194     /**
2195      * Check for permission to read coprocessor registers.
2196      *
2197      * Checks whether an instruction at the current program mode has
2198      * permissions to read the coprocessor registers. This function
2199      * returns whether the check is undefined and if not whether the
2200      * read access is permitted.
2201      *
2202      * @param the misc reg indicating the coprocessor
2203      * @param the SCR
2204      * @param the CPSR
2205      * @param the thread context on the core
2206      * @return a tuple of booleans: can_read, undefined
2207      */
2208     std::tuple<bool, bool> canReadCoprocReg(MiscRegIndex reg, SCR scr,
2209                                             CPSR cpsr, ThreadContext *tc);
2210
2211     /**
2212      * Check for permission to write coprocessor registers.
2213      *
2214      * Checks whether an instruction at the current program mode has
2215      * permissions to write the coprocessor registers. This function
2216      * returns whether the check is undefined and if not whether the
2217      * write access is permitted.
2218      *
2219      * @param the misc reg indicating the coprocessor
2220      * @param the SCR
2221      * @param the CPSR
2222      * @param the thread context on the core
2223      * @return a tuple of booleans: can_write, undefined
2224      */
2225     std::tuple<bool, bool> canWriteCoprocReg(MiscRegIndex reg, SCR scr,
2226                                              CPSR cpsr, ThreadContext *tc);
2227
2228     // Checks for UNDEFINED behaviours when accessing AArch32
2229     // Generic Timer system registers
2230     bool AArch32isUndefinedGenericTimer(MiscRegIndex reg, ThreadContext *tc);
2231
2232     // Checks read access permissions to AArch64 system registers
2233     bool canReadAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
2234                               ThreadContext *tc);
2235
2236     // Checks write access permissions to AArch64 system registers
2237     bool canWriteAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
2238                                ThreadContext *tc);
2239
2240     // Uses just the scr.ns bit to pre flatten the misc regs. This is useful
2241     // for MCR/MRC instructions
2242     int
2243     snsBankedIndex(MiscRegIndex reg, ThreadContext *tc);
2244
2245     // Flattens a misc reg index using the specified security state. This is
2246     // used for opperations (eg address translations) where the security
2247     // state of the register access may differ from the current state of the
2248     // processor
2249     int
2250     snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns);
2251
2252     int
2253     snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc);
2254
2255     // Takes a misc reg index and returns the root reg if its one of a set of
2256     // banked registers
2257     void
2258     preUnflattenMiscReg();
2259
2260     int
2261     unflattenMiscReg(int reg);
2262
2263 }
2264
2265 #endif // __ARCH_ARM_MISCREGS_HH__