src/arch/arm/miscregs.hh

   1 /*
   2  * Copyright (c) 2010 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2009 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Gabe Black
  41  */
  42 #ifndef __ARCH_ARM_MISCREGS_HH__
  43 #define __ARCH_ARM_MISCREGS_HH__
  44
  45 #include "base/bitunion.hh"
  46
  47 namespace ArmISA
  48 {
  49     enum ConditionCode {
  50         COND_EQ  =   0,
  51         COND_NE, //  1
  52         COND_CS, //  2
  53         COND_CC, //  3
  54         COND_MI, //  4
  55         COND_PL, //  5
  56         COND_VS, //  6
  57         COND_VC, //  7
  58         COND_HI, //  8
  59         COND_LS, //  9
  60         COND_GE, // 10
  61         COND_LT, // 11
  62         COND_GT, // 12
  63         COND_LE, // 13
  64         COND_AL, // 14
  65         COND_UC  // 15
  66     };
  67
  68     enum MiscRegIndex {
  69         MISCREG_CPSR = 0,
  70         MISCREG_SPSR,
  71         MISCREG_SPSR_FIQ,
  72         MISCREG_SPSR_IRQ,
  73         MISCREG_SPSR_SVC,
  74         MISCREG_SPSR_MON,
  75         MISCREG_SPSR_UND,
  76         MISCREG_SPSR_ABT,
  77         MISCREG_FPSR,
  78         MISCREG_FPSID,
  79         MISCREG_FPSCR,
  80         MISCREG_FPSCR_QC,  // Cumulative saturation flag
  81         MISCREG_FPSCR_EXC,  // Cumulative FP exception flags
  82         MISCREG_FPEXC,
  83         MISCREG_MVFR0,
  84         MISCREG_MVFR1,
  85         MISCREG_SCTLR_RST,
  86         MISCREG_SEV_MAILBOX,
  87
  88         // CP15 registers
  89         MISCREG_CP15_START,
  90         MISCREG_SCTLR = MISCREG_CP15_START,
  91         MISCREG_DCCISW,
  92         MISCREG_DCCIMVAC,
  93         MISCREG_DCCMVAC,
  94         MISCREG_CONTEXTIDR,
  95         MISCREG_TPIDRURW,
  96         MISCREG_TPIDRURO,
  97         MISCREG_TPIDRPRW,
  98         MISCREG_CP15ISB,
  99         MISCREG_CP15DSB,
 100         MISCREG_CP15DMB,
 101         MISCREG_CPACR,
 102         MISCREG_CLIDR,
 103         MISCREG_CCSIDR,
 104         MISCREG_CSSELR,
 105         MISCREG_ICIALLUIS,
 106         MISCREG_ICIALLU,
 107         MISCREG_ICIMVAU,
 108         MISCREG_BPIMVA,
 109         MISCREG_BPIALLIS,
 110         MISCREG_BPIALL,
 111         MISCREG_MIDR,
 112         MISCREG_TTBR0,
 113         MISCREG_TTBR1,
 114         MISCREG_TLBTR,
 115         MISCREG_DACR,
 116         MISCREG_TLBIALLIS,
 117         MISCREG_TLBIMVAIS,
 118         MISCREG_TLBIASIDIS,
 119         MISCREG_TLBIMVAAIS,
 120         MISCREG_ITLBIALL,
 121         MISCREG_ITLBIMVA,
 122         MISCREG_ITLBIASID,
 123         MISCREG_DTLBIALL,
 124         MISCREG_DTLBIMVA,
 125         MISCREG_DTLBIASID,
 126         MISCREG_TLBIALL,
 127         MISCREG_TLBIMVA,
 128         MISCREG_TLBIASID,
 129         MISCREG_TLBIMVAA,
 130         MISCREG_DFSR,
 131         MISCREG_IFSR,
 132         MISCREG_DFAR,
 133         MISCREG_IFAR,
 134         MISCREG_MPIDR,
 135         MISCREG_PRRR,
 136         MISCREG_NMRR,
 137         MISCREG_TTBCR,
 138         MISCREG_ID_PFR0,
 139         MISCREG_CTR,
 140         MISCREG_SCR,
 141         MISCREG_SDER,
 142         MISCREG_PAR,
 143         MISCREG_V2PCWPR,
 144         MISCREG_V2PCWPW,
 145         MISCREG_V2PCWUR,
 146         MISCREG_V2PCWUW,
 147         MISCREG_V2POWPR,
 148         MISCREG_V2POWPW,
 149         MISCREG_V2POWUR,
 150         MISCREG_V2POWUW,
 151         MISCREG_ID_MMFR0,
 152         MISCREG_ID_MMFR3,
 153         MISCREG_ACTLR,
 154         MISCREG_PMCR,
 155         MISCREG_PMCCNTR,
 156         MISCREG_PMCNTENSET,
 157         MISCREG_PMCNTENCLR,
 158         MISCREG_PMOVSR,
 159         MISCREG_PMSWINC,
 160         MISCREG_PMSELR,
 161         MISCREG_PMCEID0,
 162         MISCREG_PMCEID1,
 163         MISCREG_PMC_OTHER,
 164         MISCREG_PMXEVCNTR,
 165         MISCREG_PMUSERENR,
 166         MISCREG_PMINTENSET,
 167         MISCREG_PMINTENCLR,
 168         MISCREG_ID_ISAR0,
 169         MISCREG_ID_ISAR1,
 170         MISCREG_ID_ISAR2,
 171         MISCREG_ID_ISAR3,
 172         MISCREG_ID_ISAR4,
 173         MISCREG_ID_ISAR5,
 174         MISCREG_CPSR_MODE,
 175         MISCREG_LOCKFLAG,
 176         MISCREG_LOCKADDR,
 177         MISCREG_ID_PFR1,
 178         MISCREG_CP15_UNIMP_START,
 179         MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
 180         MISCREG_ID_DFR0,
 181         MISCREG_ID_AFR0,
 182         MISCREG_ID_MMFR1,
 183         MISCREG_ID_MMFR2,
 184         MISCREG_AIDR,
 185         MISCREG_ADFSR,
 186         MISCREG_AIFSR,
 187         MISCREG_DCIMVAC,
 188         MISCREG_DCISW,
 189         MISCREG_MCCSW,
 190         MISCREG_DCCMVAU,
 191         MISCREG_NSACR,
 192         MISCREG_VBAR,
 193         MISCREG_MVBAR,
 194         MISCREG_ISR,
 195         MISCREG_FCEIDR,
 196         MISCREG_L2LATENCY,
 197
 198
 199         MISCREG_CP15_END,
 200
 201         // Dummy indices
 202         MISCREG_NOP = MISCREG_CP15_END,
 203         MISCREG_RAZ,
 204
 205         NUM_MISCREGS
 206     };
 207
 208     MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
 209                                unsigned crm, unsigned opc2);
 210
 211     const char * const miscRegName[NUM_MISCREGS] = {
 212         "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
 213         "spsr_mon", "spsr_und", "spsr_abt",
 214         "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc",
 215         "mvfr0", "mvfr1",
 216         "sctlr_rst", "sev_mailbox",
 217         "sctlr", "dccisw", "dccimvac", "dccmvac",
 218         "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
 219         "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
 220         "clidr", "ccsidr", "csselr",
 221         "icialluis", "iciallu", "icimvau",
 222         "bpimva", "bpiallis", "bpiall",
 223         "midr", "ttbr0", "ttbr1", "tlbtr", "dacr",
 224         "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais",
 225         "itlbiall", "itlbimva", "itlbiasid",
 226         "dtlbiall", "dtlbimva", "dtlbiasid",
 227         "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
 228         "dfsr", "ifsr", "dfar", "ifar", "mpidr",
 229         "prrr", "nmrr",  "ttbcr", "id_pfr0", "ctr",
 230         "scr", "sder", "par",
 231         "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
 232         "v2powpr", "v2powpw", "v2powur", "v2powuw",
 233         "id_mmfr0", "id_mmfr3", "actlr", "pmcr", "pmccntr",
 234         "pmcntenset", "pmcntenclr", "pmovsr",
 235         "pmswinc", "pmselr", "pmceid0",
 236         "pmceid1", "pmc_other", "pmxevcntr",
 237         "pmuserenr", "pmintenset", "pmintenclr",
 238         "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
 239         "cpsr_mode", "lockflag", "lockaddr", "id_pfr1",
 240          // Unimplemented below
 241         "tcmtr",
 242         "id_dfr0", "id_afr0",
 243         "id_mmfr1", "id_mmfr2",
 244         "aidr", "adfsr", "aifsr",
 245         "dcimvac", "dcisw", "mccsw",
 246         "dccmvau",
 247         "nsacr",
 248         "vbar", "mvbar", "isr", "fceidr", "l2latency",
 249         "nop", "raz"
 250     };
 251
 252     BitUnion32(CPSR)
 253         Bitfield<31> n;
 254         Bitfield<30> z;
 255         Bitfield<29> c;
 256         Bitfield<28> v;
 257         Bitfield<27> q;
 258         Bitfield<26,25> it1;
 259         Bitfield<24> j;
 260         Bitfield<19, 16> ge;
 261         Bitfield<15,10> it2;
 262         Bitfield<9> e;
 263         Bitfield<8> a;
 264         Bitfield<7> i;
 265         Bitfield<6> f;
 266         Bitfield<5> t;
 267         Bitfield<4, 0> mode;
 268     EndBitUnion(CPSR)
 269
 270     // This mask selects bits of the CPSR that actually go in the CondCodes
 271     // integer register to allow renaming.
 272     static const uint32_t CondCodesMask   = 0xF80F0000;
 273     static const uint32_t CondCodesMaskF  = 0xF0000000;
 274     static const uint32_t CondCodesMaskQ  = 0x08000000;
 275     static const uint32_t CondCodesMaskGE = 0x000F0000;
 276
 277     BitUnion32(SCTLR)
 278         Bitfield<31> ie;  // Instruction endianness
 279         Bitfield<30> te;  // Thumb Exception Enable
 280         Bitfield<29> afe; // Access flag enable
 281         Bitfield<28> tre; // TEX Remap bit
 282         Bitfield<27> nmfi;// Non-maskable fast interrupts enable
 283         Bitfield<25> ee;  // Exception Endianness bit
 284         Bitfield<24> ve;  // Interrupt vectors enable
 285         Bitfield<23> xp; //  Extended page table enable bit
 286         Bitfield<22> u;   // Alignment (now unused)
 287         Bitfield<21> fi;  // Fast interrupts configuration enable
 288         Bitfield<19> dz;  // Divide by Zero fault enable bit
 289         Bitfield<18> rao2;// Read as one
 290         Bitfield<17> br;  // Background region bit
 291         Bitfield<16> rao3;// Read as one
 292         Bitfield<14> rr;  // Round robin cache replacement
 293         Bitfield<13> v;   // Base address for exception vectors
 294         Bitfield<12> i;   // instruction cache enable
 295         Bitfield<11> z;   // branch prediction enable bit
 296         Bitfield<10> sw;  // Enable swp/swpb
 297         Bitfield<9,8> rs;   // deprecated protection bits
 298         Bitfield<6,3> rao4;// Read as one
 299         Bitfield<7>  b;   // Endianness support (unused)
 300         Bitfield<2>  c;   // Cache enable bit
 301         Bitfield<1>  a;   // Alignment fault checking
 302         Bitfield<0>  m;   // MMU enable bit
 303     EndBitUnion(SCTLR)
 304
 305     BitUnion32(CPACR)
 306         Bitfield<1, 0> cp0;
 307         Bitfield<3, 2> cp1;
 308         Bitfield<5, 4> cp2;
 309         Bitfield<7, 6> cp3;
 310         Bitfield<9, 8> cp4;
 311         Bitfield<11, 10> cp5;
 312         Bitfield<13, 12> cp6;
 313         Bitfield<15, 14> cp7;
 314         Bitfield<17, 16> cp8;
 315         Bitfield<19, 18> cp9;
 316         Bitfield<21, 20> cp10;
 317         Bitfield<23, 22> cp11;
 318         Bitfield<25, 24> cp12;
 319         Bitfield<27, 26> cp13;
 320         Bitfield<29, 28> rsvd;
 321         Bitfield<30> d32dis;
 322         Bitfield<31> asedis;
 323     EndBitUnion(CPACR)
 324
 325     BitUnion32(FSR)
 326         Bitfield<3, 0> fsLow;
 327         Bitfield<7, 4> domain;
 328         Bitfield<10> fsHigh;
 329         Bitfield<11> wnr;
 330         Bitfield<12> ext;
 331     EndBitUnion(FSR)
 332
 333     BitUnion32(FPSCR)
 334         Bitfield<0> ioc;
 335         Bitfield<1> dzc;
 336         Bitfield<2> ofc;
 337         Bitfield<3> ufc;
 338         Bitfield<4> ixc;
 339         Bitfield<7> idc;
 340         Bitfield<8> ioe;
 341         Bitfield<9> dze;
 342         Bitfield<10> ofe;
 343         Bitfield<11> ufe;
 344         Bitfield<12> ixe;
 345         Bitfield<15> ide;
 346         Bitfield<18, 16> len;
 347         Bitfield<21, 20> stride;
 348         Bitfield<23, 22> rMode;
 349         Bitfield<24> fz;
 350         Bitfield<25> dn;
 351         Bitfield<26> ahp;
 352         Bitfield<27> qc;
 353         Bitfield<28> v;
 354         Bitfield<29> c;
 355         Bitfield<30> z;
 356         Bitfield<31> n;
 357     EndBitUnion(FPSCR)
 358
 359     // This mask selects bits of the FPSCR that actually go in the FpCondCodes
 360     // integer register to allow renaming.
 361     static const uint32_t FpCondCodesMask = 0xF0000000;
 362     // This mask selects the cumulative FP exception flags of the FPSCR.
 363     static const uint32_t FpscrExcMask = 0x0000009F;
 364     // This mask selects the cumulative saturation flag of the FPSCR.
 365     static const uint32_t FpscrQcMask = 0x08000000;
 366
 367     BitUnion32(FPEXC)
 368         Bitfield<31> ex;
 369         Bitfield<30> en;
 370         Bitfield<29, 0> subArchDefined;
 371     EndBitUnion(FPEXC)
 372
 373     BitUnion32(MVFR0)
 374         Bitfield<3, 0> advSimdRegisters;
 375         Bitfield<7, 4> singlePrecision;
 376         Bitfield<11, 8> doublePrecision;
 377         Bitfield<15, 12> vfpExceptionTrapping;
 378         Bitfield<19, 16> divide;
 379         Bitfield<23, 20> squareRoot;
 380         Bitfield<27, 24> shortVectors;
 381         Bitfield<31, 28> roundingModes;
 382     EndBitUnion(MVFR0)
 383
 384     BitUnion32(MVFR1)
 385         Bitfield<3, 0> flushToZero;
 386         Bitfield<7, 4> defaultNaN;
 387         Bitfield<11, 8> advSimdLoadStore;
 388         Bitfield<15, 12> advSimdInteger;
 389         Bitfield<19, 16> advSimdSinglePrecision;
 390         Bitfield<23, 20> advSimdHalfPrecision;
 391         Bitfield<27, 24> vfpHalfPrecision;
 392         Bitfield<31, 28> raz;
 393     EndBitUnion(MVFR1)
 394
 395     BitUnion32(PRRR)
 396        Bitfield<1,0> tr0;
 397        Bitfield<3,2> tr1;
 398        Bitfield<5,4> tr2;
 399        Bitfield<7,6> tr3;
 400        Bitfield<9,8> tr4;
 401        Bitfield<11,10> tr5;
 402        Bitfield<13,12> tr6;
 403        Bitfield<15,14> tr7;
 404        Bitfield<16> ds0;
 405        Bitfield<17> ds1;
 406        Bitfield<18> ns0;
 407        Bitfield<19> ns1;
 408        Bitfield<24> nos0;
 409        Bitfield<25> nos1;
 410        Bitfield<26> nos2;
 411        Bitfield<27> nos3;
 412        Bitfield<28> nos4;
 413        Bitfield<29> nos5;
 414        Bitfield<30> nos6;
 415        Bitfield<31> nos7;
 416    EndBitUnion(PRRR)
 417
 418    BitUnion32(NMRR)
 419        Bitfield<1,0> ir0;
 420        Bitfield<3,2> ir1;
 421        Bitfield<5,4> ir2;
 422        Bitfield<7,6> ir3;
 423        Bitfield<9,8> ir4;
 424        Bitfield<11,10> ir5;
 425        Bitfield<13,12> ir6;
 426        Bitfield<15,14> ir7;
 427        Bitfield<17,16> or0;
 428        Bitfield<19,18> or1;
 429        Bitfield<21,20> or2;
 430        Bitfield<23,22> or3;
 431        Bitfield<25,24> or4;
 432        Bitfield<27,26> or5;
 433        Bitfield<29,28> or6;
 434        Bitfield<31,30> or7;
 435    EndBitUnion(NMRR)
 436
 437 };
 438
 439 #endif // __ARCH_ARM_MISCREGS_HH__