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43 #ifndef __ARCH_ARM_MISCREGS_HH__
44 #define __ARCH_ARM_MISCREGS_HH__
48 #include "base/bitunion.hh"
49 #include "base/compiler.hh"
57 MISCREG_CPSR = 0, // 0
59 MISCREG_SPSR_FIQ, // 2
60 MISCREG_SPSR_IRQ, // 3
61 MISCREG_SPSR_SVC, // 4
62 MISCREG_SPSR_MON, // 5
63 MISCREG_SPSR_ABT, // 6
64 MISCREG_SPSR_HYP, // 7
65 MISCREG_SPSR_UND, // 8
74 MISCREG_CPSR_MODE, // 15
76 MISCREG_FPSCR_EXC, // 17
77 MISCREG_FPSCR_QC, // 18
78 MISCREG_LOCKADDR, // 19
79 MISCREG_LOCKFLAG, // 20
80 MISCREG_PRRR_MAIR0, // 21
81 MISCREG_PRRR_MAIR0_NS, // 22
82 MISCREG_PRRR_MAIR0_S, // 23
83 MISCREG_NMRR_MAIR1, // 24
84 MISCREG_NMRR_MAIR1_NS, // 25
85 MISCREG_NMRR_MAIR1_S, // 26
86 MISCREG_PMXEVTYPER_PMCCFILTR, // 27
87 MISCREG_SCTLR_RST, // 28
88 MISCREG_SEV_MAILBOX, // 29
90 // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control)
91 MISCREG_DBGDIDR, // 30
92 MISCREG_DBGDSCRint, // 31
93 MISCREG_DBGDCCINT, // 32
94 MISCREG_DBGDTRTXint, // 33
95 MISCREG_DBGDTRRXint, // 34
96 MISCREG_DBGWFAR, // 35
98 MISCREG_DBGDTRRXext, // 37
99 MISCREG_DBGDSCRext, // 38
100 MISCREG_DBGDTRTXext, // 39
101 MISCREG_DBGOSECCR, // 40
102 MISCREG_DBGBVR0, // 41
103 MISCREG_DBGBVR1, // 42
104 MISCREG_DBGBVR2, // 43
105 MISCREG_DBGBVR3, // 44
106 MISCREG_DBGBVR4, // 45
107 MISCREG_DBGBVR5, // 46
108 MISCREG_DBGBCR0, // 47
109 MISCREG_DBGBCR1, // 48
110 MISCREG_DBGBCR2, // 49
111 MISCREG_DBGBCR3, // 50
112 MISCREG_DBGBCR4, // 51
113 MISCREG_DBGBCR5, // 52
114 MISCREG_DBGWVR0, // 53
115 MISCREG_DBGWVR1, // 54
116 MISCREG_DBGWVR2, // 55
117 MISCREG_DBGWVR3, // 56
118 MISCREG_DBGWCR0, // 57
119 MISCREG_DBGWCR1, // 58
120 MISCREG_DBGWCR2, // 59
121 MISCREG_DBGWCR3, // 60
122 MISCREG_DBGDRAR, // 61
123 MISCREG_DBGBXVR4, // 62
124 MISCREG_DBGBXVR5, // 63
125 MISCREG_DBGOSLAR, // 64
126 MISCREG_DBGOSLSR, // 65
127 MISCREG_DBGOSDLR, // 66
128 MISCREG_DBGPRCR, // 67
129 MISCREG_DBGDSAR, // 68
130 MISCREG_DBGCLAIMSET, // 69
131 MISCREG_DBGCLAIMCLR, // 70
132 MISCREG_DBGAUTHSTATUS, // 71
133 MISCREG_DBGDEVID2, // 72
134 MISCREG_DBGDEVID1, // 73
135 MISCREG_DBGDEVID0, // 74
138 MISCREG_TEEHBR, // 77
142 // AArch32 CP15 registers (system control)
148 MISCREG_REVIDR, // 85
149 MISCREG_ID_PFR0, // 86
150 MISCREG_ID_PFR1, // 87
151 MISCREG_ID_DFR0, // 88
152 MISCREG_ID_AFR0, // 89
153 MISCREG_ID_MMFR0, // 90
154 MISCREG_ID_MMFR1, // 91
155 MISCREG_ID_MMFR2, // 92
156 MISCREG_ID_MMFR3, // 93
157 MISCREG_ID_ISAR0, // 94
158 MISCREG_ID_ISAR1, // 95
159 MISCREG_ID_ISAR2, // 96
160 MISCREG_ID_ISAR3, // 97
161 MISCREG_ID_ISAR4, // 98
162 MISCREG_ID_ISAR5, // 99
163 MISCREG_CCSIDR, // 100
164 MISCREG_CLIDR, // 101
166 MISCREG_CSSELR, // 103
167 MISCREG_CSSELR_NS, // 104
168 MISCREG_CSSELR_S, // 105
169 MISCREG_VPIDR, // 106
170 MISCREG_VMPIDR, // 107
171 MISCREG_SCTLR, // 108
172 MISCREG_SCTLR_NS, // 109
173 MISCREG_SCTLR_S, // 110
174 MISCREG_ACTLR, // 111
175 MISCREG_ACTLR_NS, // 112
176 MISCREG_ACTLR_S, // 113
177 MISCREG_CPACR, // 114
180 MISCREG_NSACR, // 117
181 MISCREG_HSCTLR, // 118
182 MISCREG_HACTLR, // 119
185 MISCREG_HCPTR, // 122
188 MISCREG_TTBR0, // 125
189 MISCREG_TTBR0_NS, // 126
190 MISCREG_TTBR0_S, // 127
191 MISCREG_TTBR1, // 128
192 MISCREG_TTBR1_NS, // 129
193 MISCREG_TTBR1_S, // 130
194 MISCREG_TTBCR, // 131
195 MISCREG_TTBCR_NS, // 132
196 MISCREG_TTBCR_S, // 133
200 MISCREG_DACR_NS, // 137
201 MISCREG_DACR_S, // 138
203 MISCREG_DFSR_NS, // 140
204 MISCREG_DFSR_S, // 141
206 MISCREG_IFSR_NS, // 143
207 MISCREG_IFSR_S, // 144
208 MISCREG_ADFSR, // 145
209 MISCREG_ADFSR_NS, // 146
210 MISCREG_ADFSR_S, // 147
211 MISCREG_AIFSR, // 148
212 MISCREG_AIFSR_NS, // 149
213 MISCREG_AIFSR_S, // 150
214 MISCREG_HADFSR, // 151
215 MISCREG_HAIFSR, // 152
218 MISCREG_DFAR_NS, // 155
219 MISCREG_DFAR_S, // 156
221 MISCREG_IFAR_NS, // 158
222 MISCREG_IFAR_S, // 159
223 MISCREG_HDFAR, // 160
224 MISCREG_HIFAR, // 161
225 MISCREG_HPFAR, // 162
226 MISCREG_ICIALLUIS, // 163
227 MISCREG_BPIALLIS, // 164
229 MISCREG_PAR_NS, // 166
230 MISCREG_PAR_S, // 167
231 MISCREG_ICIALLU, // 168
232 MISCREG_ICIMVAU, // 169
233 MISCREG_CP15ISB, // 170
234 MISCREG_BPIALL, // 171
235 MISCREG_BPIMVA, // 172
236 MISCREG_DCIMVAC, // 173
237 MISCREG_DCISW, // 174
238 MISCREG_ATS1CPR, // 175
239 MISCREG_ATS1CPW, // 176
240 MISCREG_ATS1CUR, // 177
241 MISCREG_ATS1CUW, // 178
242 MISCREG_ATS12NSOPR, // 179
243 MISCREG_ATS12NSOPW, // 180
244 MISCREG_ATS12NSOUR, // 181
245 MISCREG_ATS12NSOUW, // 182
246 MISCREG_DCCMVAC, // 183
247 MISCREG_DCCSW, // 184
248 MISCREG_CP15DSB, // 185
249 MISCREG_CP15DMB, // 186
250 MISCREG_DCCMVAU, // 187
251 MISCREG_DCCIMVAC, // 188
252 MISCREG_DCCISW, // 189
253 MISCREG_ATS1HR, // 190
254 MISCREG_ATS1HW, // 191
255 MISCREG_TLBIALLIS, // 192
256 MISCREG_TLBIMVAIS, // 193
257 MISCREG_TLBIASIDIS, // 194
258 MISCREG_TLBIMVAAIS, // 195
259 MISCREG_TLBIMVALIS, // 196
260 MISCREG_TLBIMVAALIS, // 197
261 MISCREG_ITLBIALL, // 198
262 MISCREG_ITLBIMVA, // 199
263 MISCREG_ITLBIASID, // 200
264 MISCREG_DTLBIALL, // 201
265 MISCREG_DTLBIMVA, // 202
266 MISCREG_DTLBIASID, // 203
267 MISCREG_TLBIALL, // 204
268 MISCREG_TLBIMVA, // 205
269 MISCREG_TLBIASID, // 206
270 MISCREG_TLBIMVAA, // 207
271 MISCREG_TLBIMVAL, // 208
272 MISCREG_TLBIMVAAL, // 209
273 MISCREG_TLBIIPAS2IS, // 210
274 MISCREG_TLBIIPAS2LIS, // 211
275 MISCREG_TLBIALLHIS, // 212
276 MISCREG_TLBIMVAHIS, // 213
277 MISCREG_TLBIALLNSNHIS, // 214
278 MISCREG_TLBIMVALHIS, // 215
279 MISCREG_TLBIIPAS2, // 216
280 MISCREG_TLBIIPAS2L, // 217
281 MISCREG_TLBIALLH, // 218
282 MISCREG_TLBIMVAH, // 219
283 MISCREG_TLBIALLNSNH, // 220
284 MISCREG_TLBIMVALH, // 221
286 MISCREG_PMCNTENSET, // 223
287 MISCREG_PMCNTENCLR, // 224
288 MISCREG_PMOVSR, // 225
289 MISCREG_PMSWINC, // 226
290 MISCREG_PMSELR, // 227
291 MISCREG_PMCEID0, // 228
292 MISCREG_PMCEID1, // 229
293 MISCREG_PMCCNTR, // 230
294 MISCREG_PMXEVTYPER, // 231
295 MISCREG_PMCCFILTR, // 232
296 MISCREG_PMXEVCNTR, // 233
297 MISCREG_PMUSERENR, // 234
298 MISCREG_PMINTENSET, // 235
299 MISCREG_PMINTENCLR, // 236
300 MISCREG_PMOVSSET, // 237
301 MISCREG_L2CTLR, // 238
302 MISCREG_L2ECTLR, // 239
304 MISCREG_PRRR_NS, // 241
305 MISCREG_PRRR_S, // 242
306 MISCREG_MAIR0, // 243
307 MISCREG_MAIR0_NS, // 244
308 MISCREG_MAIR0_S, // 245
310 MISCREG_NMRR_NS, // 247
311 MISCREG_NMRR_S, // 248
312 MISCREG_MAIR1, // 249
313 MISCREG_MAIR1_NS, // 250
314 MISCREG_MAIR1_S, // 251
315 MISCREG_AMAIR0, // 252
316 MISCREG_AMAIR0_NS, // 253
317 MISCREG_AMAIR0_S, // 254
318 MISCREG_AMAIR1, // 255
319 MISCREG_AMAIR1_NS, // 256
320 MISCREG_AMAIR1_S, // 257
321 MISCREG_HMAIR0, // 258
322 MISCREG_HMAIR1, // 259
323 MISCREG_HAMAIR0, // 260
324 MISCREG_HAMAIR1, // 261
326 MISCREG_VBAR_NS, // 263
327 MISCREG_VBAR_S, // 264
328 MISCREG_MVBAR, // 265
331 MISCREG_HVBAR, // 268
332 MISCREG_FCSEIDR, // 269
333 MISCREG_CONTEXTIDR, // 270
334 MISCREG_CONTEXTIDR_NS, // 271
335 MISCREG_CONTEXTIDR_S, // 272
336 MISCREG_TPIDRURW, // 273
337 MISCREG_TPIDRURW_NS, // 274
338 MISCREG_TPIDRURW_S, // 275
339 MISCREG_TPIDRURO, // 276
340 MISCREG_TPIDRURO_NS, // 277
341 MISCREG_TPIDRURO_S, // 278
342 MISCREG_TPIDRPRW, // 279
343 MISCREG_TPIDRPRW_NS, // 280
344 MISCREG_TPIDRPRW_S, // 281
345 MISCREG_HTPIDR, // 282
346 MISCREG_CNTFRQ, // 283
347 MISCREG_CNTKCTL, // 284
348 MISCREG_CNTP_TVAL, // 285
349 MISCREG_CNTP_TVAL_NS, // 286
350 MISCREG_CNTP_TVAL_S, // 287
351 MISCREG_CNTP_CTL, // 288
352 MISCREG_CNTP_CTL_NS, // 289
353 MISCREG_CNTP_CTL_S, // 290
354 MISCREG_CNTV_TVAL, // 291
355 MISCREG_CNTV_CTL, // 292
356 MISCREG_CNTHCTL, // 293
357 MISCREG_CNTHP_TVAL, // 294
358 MISCREG_CNTHP_CTL, // 295
359 MISCREG_IL1DATA0, // 296
360 MISCREG_IL1DATA1, // 297
361 MISCREG_IL1DATA2, // 298
362 MISCREG_IL1DATA3, // 299
363 MISCREG_DL1DATA0, // 300
364 MISCREG_DL1DATA1, // 301
365 MISCREG_DL1DATA2, // 302
366 MISCREG_DL1DATA3, // 303
367 MISCREG_DL1DATA4, // 304
368 MISCREG_RAMINDEX, // 305
369 MISCREG_L2ACTLR, // 306
371 MISCREG_HTTBR, // 308
372 MISCREG_VTTBR, // 309
373 MISCREG_CNTPCT, // 310
374 MISCREG_CNTVCT, // 311
375 MISCREG_CNTP_CVAL, // 312
376 MISCREG_CNTP_CVAL_NS, // 313
377 MISCREG_CNTP_CVAL_S, // 314
378 MISCREG_CNTV_CVAL, // 315
379 MISCREG_CNTVOFF, // 316
380 MISCREG_CNTHP_CVAL, // 317
381 MISCREG_CPUMERRSR, // 318
382 MISCREG_L2MERRSR, // 319
384 // AArch64 registers (Op0=2)
385 MISCREG_MDCCINT_EL1, // 320
386 MISCREG_OSDTRRX_EL1, // 321
387 MISCREG_MDSCR_EL1, // 322
388 MISCREG_OSDTRTX_EL1, // 323
389 MISCREG_OSECCR_EL1, // 324
390 MISCREG_DBGBVR0_EL1, // 325
391 MISCREG_DBGBVR1_EL1, // 326
392 MISCREG_DBGBVR2_EL1, // 327
393 MISCREG_DBGBVR3_EL1, // 328
394 MISCREG_DBGBVR4_EL1, // 329
395 MISCREG_DBGBVR5_EL1, // 330
396 MISCREG_DBGBCR0_EL1, // 331
397 MISCREG_DBGBCR1_EL1, // 332
398 MISCREG_DBGBCR2_EL1, // 333
399 MISCREG_DBGBCR3_EL1, // 334
400 MISCREG_DBGBCR4_EL1, // 335
401 MISCREG_DBGBCR5_EL1, // 336
402 MISCREG_DBGWVR0_EL1, // 337
403 MISCREG_DBGWVR1_EL1, // 338
404 MISCREG_DBGWVR2_EL1, // 339
405 MISCREG_DBGWVR3_EL1, // 340
406 MISCREG_DBGWCR0_EL1, // 341
407 MISCREG_DBGWCR1_EL1, // 342
408 MISCREG_DBGWCR2_EL1, // 343
409 MISCREG_DBGWCR3_EL1, // 344
410 MISCREG_MDCCSR_EL0, // 345
411 MISCREG_MDDTR_EL0, // 346
412 MISCREG_MDDTRTX_EL0, // 347
413 MISCREG_MDDTRRX_EL0, // 348
414 MISCREG_DBGVCR32_EL2, // 349
415 MISCREG_MDRAR_EL1, // 350
416 MISCREG_OSLAR_EL1, // 351
417 MISCREG_OSLSR_EL1, // 352
418 MISCREG_OSDLR_EL1, // 353
419 MISCREG_DBGPRCR_EL1, // 354
420 MISCREG_DBGCLAIMSET_EL1, // 355
421 MISCREG_DBGCLAIMCLR_EL1, // 356
422 MISCREG_DBGAUTHSTATUS_EL1, // 357
423 MISCREG_TEECR32_EL1, // 358
424 MISCREG_TEEHBR32_EL1, // 359
426 // AArch64 registers (Op0=1,3)
427 MISCREG_MIDR_EL1, // 360
428 MISCREG_MPIDR_EL1, // 361
429 MISCREG_REVIDR_EL1, // 362
430 MISCREG_ID_PFR0_EL1, // 363
431 MISCREG_ID_PFR1_EL1, // 364
432 MISCREG_ID_DFR0_EL1, // 365
433 MISCREG_ID_AFR0_EL1, // 366
434 MISCREG_ID_MMFR0_EL1, // 367
435 MISCREG_ID_MMFR1_EL1, // 368
436 MISCREG_ID_MMFR2_EL1, // 369
437 MISCREG_ID_MMFR3_EL1, // 370
438 MISCREG_ID_ISAR0_EL1, // 371
439 MISCREG_ID_ISAR1_EL1, // 372
440 MISCREG_ID_ISAR2_EL1, // 373
441 MISCREG_ID_ISAR3_EL1, // 374
442 MISCREG_ID_ISAR4_EL1, // 375
443 MISCREG_ID_ISAR5_EL1, // 376
444 MISCREG_MVFR0_EL1, // 377
445 MISCREG_MVFR1_EL1, // 378
446 MISCREG_MVFR2_EL1, // 379
447 MISCREG_ID_AA64PFR0_EL1, // 380
448 MISCREG_ID_AA64PFR1_EL1, // 381
449 MISCREG_ID_AA64DFR0_EL1, // 382
450 MISCREG_ID_AA64DFR1_EL1, // 383
451 MISCREG_ID_AA64AFR0_EL1, // 384
452 MISCREG_ID_AA64AFR1_EL1, // 385
453 MISCREG_ID_AA64ISAR0_EL1, // 386
454 MISCREG_ID_AA64ISAR1_EL1, // 387
455 MISCREG_ID_AA64MMFR0_EL1, // 388
456 MISCREG_ID_AA64MMFR1_EL1, // 389
457 MISCREG_CCSIDR_EL1, // 390
458 MISCREG_CLIDR_EL1, // 391
459 MISCREG_AIDR_EL1, // 392
460 MISCREG_CSSELR_EL1, // 393
461 MISCREG_CTR_EL0, // 394
462 MISCREG_DCZID_EL0, // 395
463 MISCREG_VPIDR_EL2, // 396
464 MISCREG_VMPIDR_EL2, // 397
465 MISCREG_SCTLR_EL1, // 398
466 MISCREG_ACTLR_EL1, // 399
467 MISCREG_CPACR_EL1, // 400
468 MISCREG_SCTLR_EL2, // 401
469 MISCREG_ACTLR_EL2, // 402
470 MISCREG_HCR_EL2, // 403
471 MISCREG_MDCR_EL2, // 404
472 MISCREG_CPTR_EL2, // 405
473 MISCREG_HSTR_EL2, // 406
474 MISCREG_HACR_EL2, // 407
475 MISCREG_SCTLR_EL3, // 408
476 MISCREG_ACTLR_EL3, // 409
477 MISCREG_SCR_EL3, // 410
478 MISCREG_SDER32_EL3, // 411
479 MISCREG_CPTR_EL3, // 412
480 MISCREG_MDCR_EL3, // 413
481 MISCREG_TTBR0_EL1, // 414
482 MISCREG_TTBR1_EL1, // 415
483 MISCREG_TCR_EL1, // 416
484 MISCREG_TTBR0_EL2, // 417
485 MISCREG_TCR_EL2, // 418
486 MISCREG_VTTBR_EL2, // 419
487 MISCREG_VTCR_EL2, // 420
488 MISCREG_TTBR0_EL3, // 421
489 MISCREG_TCR_EL3, // 422
490 MISCREG_DACR32_EL2, // 423
491 MISCREG_SPSR_EL1, // 424
492 MISCREG_ELR_EL1, // 425
493 MISCREG_SP_EL0, // 426
494 MISCREG_SPSEL, // 427
495 MISCREG_CURRENTEL, // 428
500 MISCREG_DSPSR_EL0, // 433
501 MISCREG_DLR_EL0, // 434
502 MISCREG_SPSR_EL2, // 435
503 MISCREG_ELR_EL2, // 436
504 MISCREG_SP_EL1, // 437
505 MISCREG_SPSR_IRQ_AA64, // 438
506 MISCREG_SPSR_ABT_AA64, // 439
507 MISCREG_SPSR_UND_AA64, // 440
508 MISCREG_SPSR_FIQ_AA64, // 441
509 MISCREG_SPSR_EL3, // 442
510 MISCREG_ELR_EL3, // 443
511 MISCREG_SP_EL2, // 444
512 MISCREG_AFSR0_EL1, // 445
513 MISCREG_AFSR1_EL1, // 446
514 MISCREG_ESR_EL1, // 447
515 MISCREG_IFSR32_EL2, // 448
516 MISCREG_AFSR0_EL2, // 449
517 MISCREG_AFSR1_EL2, // 450
518 MISCREG_ESR_EL2, // 451
519 MISCREG_FPEXC32_EL2, // 452
520 MISCREG_AFSR0_EL3, // 453
521 MISCREG_AFSR1_EL3, // 454
522 MISCREG_ESR_EL3, // 455
523 MISCREG_FAR_EL1, // 456
524 MISCREG_FAR_EL2, // 457
525 MISCREG_HPFAR_EL2, // 458
526 MISCREG_FAR_EL3, // 459
527 MISCREG_IC_IALLUIS, // 460
528 MISCREG_PAR_EL1, // 461
529 MISCREG_IC_IALLU, // 462
530 MISCREG_DC_IVAC_Xt, // 463
531 MISCREG_DC_ISW_Xt, // 464
532 MISCREG_AT_S1E1R_Xt, // 465
533 MISCREG_AT_S1E1W_Xt, // 466
534 MISCREG_AT_S1E0R_Xt, // 467
535 MISCREG_AT_S1E0W_Xt, // 468
536 MISCREG_DC_CSW_Xt, // 469
537 MISCREG_DC_CISW_Xt, // 470
538 MISCREG_DC_ZVA_Xt, // 471
539 MISCREG_IC_IVAU_Xt, // 472
540 MISCREG_DC_CVAC_Xt, // 473
541 MISCREG_DC_CVAU_Xt, // 474
542 MISCREG_DC_CIVAC_Xt, // 475
543 MISCREG_AT_S1E2R_Xt, // 476
544 MISCREG_AT_S1E2W_Xt, // 477
545 MISCREG_AT_S12E1R_Xt, // 478
546 MISCREG_AT_S12E1W_Xt, // 479
547 MISCREG_AT_S12E0R_Xt, // 480
548 MISCREG_AT_S12E0W_Xt, // 481
549 MISCREG_AT_S1E3R_Xt, // 482
550 MISCREG_AT_S1E3W_Xt, // 483
551 MISCREG_TLBI_VMALLE1IS, // 484
552 MISCREG_TLBI_VAE1IS_Xt, // 485
553 MISCREG_TLBI_ASIDE1IS_Xt, // 486
554 MISCREG_TLBI_VAAE1IS_Xt, // 487
555 MISCREG_TLBI_VALE1IS_Xt, // 488
556 MISCREG_TLBI_VAALE1IS_Xt, // 489
557 MISCREG_TLBI_VMALLE1, // 490
558 MISCREG_TLBI_VAE1_Xt, // 491
559 MISCREG_TLBI_ASIDE1_Xt, // 492
560 MISCREG_TLBI_VAAE1_Xt, // 493
561 MISCREG_TLBI_VALE1_Xt, // 494
562 MISCREG_TLBI_VAALE1_Xt, // 495
563 MISCREG_TLBI_IPAS2E1IS_Xt, // 496
564 MISCREG_TLBI_IPAS2LE1IS_Xt, // 497
565 MISCREG_TLBI_ALLE2IS, // 498
566 MISCREG_TLBI_VAE2IS_Xt, // 499
567 MISCREG_TLBI_ALLE1IS, // 500
568 MISCREG_TLBI_VALE2IS_Xt, // 501
569 MISCREG_TLBI_VMALLS12E1IS, // 502
570 MISCREG_TLBI_IPAS2E1_Xt, // 503
571 MISCREG_TLBI_IPAS2LE1_Xt, // 504
572 MISCREG_TLBI_ALLE2, // 505
573 MISCREG_TLBI_VAE2_Xt, // 506
574 MISCREG_TLBI_ALLE1, // 507
575 MISCREG_TLBI_VALE2_Xt, // 508
576 MISCREG_TLBI_VMALLS12E1, // 509
577 MISCREG_TLBI_ALLE3IS, // 510
578 MISCREG_TLBI_VAE3IS_Xt, // 511
579 MISCREG_TLBI_VALE3IS_Xt, // 512
580 MISCREG_TLBI_ALLE3, // 513
581 MISCREG_TLBI_VAE3_Xt, // 514
582 MISCREG_TLBI_VALE3_Xt, // 515
583 MISCREG_PMINTENSET_EL1, // 516
584 MISCREG_PMINTENCLR_EL1, // 517
585 MISCREG_PMCR_EL0, // 518
586 MISCREG_PMCNTENSET_EL0, // 519
587 MISCREG_PMCNTENCLR_EL0, // 520
588 MISCREG_PMOVSCLR_EL0, // 521
589 MISCREG_PMSWINC_EL0, // 522
590 MISCREG_PMSELR_EL0, // 523
591 MISCREG_PMCEID0_EL0, // 524
592 MISCREG_PMCEID1_EL0, // 525
593 MISCREG_PMCCNTR_EL0, // 526
594 MISCREG_PMXEVTYPER_EL0, // 527
595 MISCREG_PMCCFILTR_EL0, // 528
596 MISCREG_PMXEVCNTR_EL0, // 529
597 MISCREG_PMUSERENR_EL0, // 530
598 MISCREG_PMOVSSET_EL0, // 531
599 MISCREG_MAIR_EL1, // 532
600 MISCREG_AMAIR_EL1, // 533
601 MISCREG_MAIR_EL2, // 534
602 MISCREG_AMAIR_EL2, // 535
603 MISCREG_MAIR_EL3, // 536
604 MISCREG_AMAIR_EL3, // 537
605 MISCREG_L2CTLR_EL1, // 538
606 MISCREG_L2ECTLR_EL1, // 539
607 MISCREG_VBAR_EL1, // 540
608 MISCREG_RVBAR_EL1, // 541
609 MISCREG_ISR_EL1, // 542
610 MISCREG_VBAR_EL2, // 543
611 MISCREG_RVBAR_EL2, // 544
612 MISCREG_VBAR_EL3, // 545
613 MISCREG_RVBAR_EL3, // 546
614 MISCREG_RMR_EL3, // 547
615 MISCREG_CONTEXTIDR_EL1, // 548
616 MISCREG_TPIDR_EL1, // 549
617 MISCREG_TPIDR_EL0, // 550
618 MISCREG_TPIDRRO_EL0, // 551
619 MISCREG_TPIDR_EL2, // 552
620 MISCREG_TPIDR_EL3, // 553
621 MISCREG_CNTKCTL_EL1, // 554
622 MISCREG_CNTFRQ_EL0, // 555
623 MISCREG_CNTPCT_EL0, // 556
624 MISCREG_CNTVCT_EL0, // 557
625 MISCREG_CNTP_TVAL_EL0, // 558
626 MISCREG_CNTP_CTL_EL0, // 559
627 MISCREG_CNTP_CVAL_EL0, // 560
628 MISCREG_CNTV_TVAL_EL0, // 561
629 MISCREG_CNTV_CTL_EL0, // 562
630 MISCREG_CNTV_CVAL_EL0, // 563
631 MISCREG_PMEVCNTR0_EL0, // 564
632 MISCREG_PMEVCNTR1_EL0, // 565
633 MISCREG_PMEVCNTR2_EL0, // 566
634 MISCREG_PMEVCNTR3_EL0, // 567
635 MISCREG_PMEVCNTR4_EL0, // 568
636 MISCREG_PMEVCNTR5_EL0, // 569
637 MISCREG_PMEVTYPER0_EL0, // 570
638 MISCREG_PMEVTYPER1_EL0, // 571
639 MISCREG_PMEVTYPER2_EL0, // 572
640 MISCREG_PMEVTYPER3_EL0, // 573
641 MISCREG_PMEVTYPER4_EL0, // 574
642 MISCREG_PMEVTYPER5_EL0, // 575
643 MISCREG_CNTVOFF_EL2, // 576
644 MISCREG_CNTHCTL_EL2, // 577
645 MISCREG_CNTHP_TVAL_EL2, // 578
646 MISCREG_CNTHP_CTL_EL2, // 579
647 MISCREG_CNTHP_CVAL_EL2, // 580
648 MISCREG_CNTPS_TVAL_EL1, // 581
649 MISCREG_CNTPS_CTL_EL1, // 582
650 MISCREG_CNTPS_CVAL_EL1, // 583
651 MISCREG_IL1DATA0_EL1, // 584
652 MISCREG_IL1DATA1_EL1, // 585
653 MISCREG_IL1DATA2_EL1, // 586
654 MISCREG_IL1DATA3_EL1, // 587
655 MISCREG_DL1DATA0_EL1, // 588
656 MISCREG_DL1DATA1_EL1, // 589
657 MISCREG_DL1DATA2_EL1, // 590
658 MISCREG_DL1DATA3_EL1, // 591
659 MISCREG_DL1DATA4_EL1, // 592
660 MISCREG_L2ACTLR_EL1, // 593
661 MISCREG_CPUACTLR_EL1, // 594
662 MISCREG_CPUECTLR_EL1, // 595
663 MISCREG_CPUMERRSR_EL1, // 596
664 MISCREG_L2MERRSR_EL1, // 597
665 MISCREG_CBAR_EL1, // 598
666 MISCREG_CONTEXTIDR_EL2, // 599
671 MISCREG_CP14_UNIMPL, // 602
672 MISCREG_CP15_UNIMPL, // 603
673 MISCREG_A64_UNIMPL, // 604
674 MISCREG_UNKNOWN, // 605
681 MISCREG_UNVERIFIABLE, // Does the value change on every read (e.g. a
682 // arch generic counter)
683 MISCREG_WARN_NOT_FAIL, // If MISCREG_IMPLEMENTED is deasserted, it
684 // tells whether the instruction should raise a
686 MISCREG_MUTEX, // True if the register corresponds to a pair of
687 // mutually exclusive registers
688 MISCREG_BANKED, // True if the register is banked between the two
689 // security states, and this is the parent node of the
690 // two banked registers
691 MISCREG_BANKED_CHILD, // The entry is one of the child registers that
692 // forms a banked set of regs (along with the
695 // Access permissions
701 // Privileged modes other than hypervisor or monitor
709 // Monitor mode, SCR.NS == 0
712 // Monitor mode, SCR.NS == 1
719 extern std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS];
721 // Decodes 32-bit CP14 registers accessible through MCR/MRC instructions
722 MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1,
723 unsigned crm, unsigned opc2);
724 MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1,
725 unsigned crn, unsigned crm,
727 // Whether a particular AArch64 system register is -always- read only.
728 bool aarch64SysRegReadOnly(MiscRegIndex miscReg);
730 // Decodes 32-bit CP15 registers accessible through MCR/MRC instructions
731 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
732 unsigned crm, unsigned opc2);
734 // Decodes 64-bit CP15 registers accessible through MCRR/MRRC instructions
735 MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1);
738 const char * const miscRegName[] = {
768 "pmxevtyper_pmccfiltr",
772 // AArch32 CP14 registers
824 // AArch32 CP15 registers
1066 // AArch64 registers (Op0=2)
1104 "dbgauthstatus_el1",
1108 // AArch64 registers (Op0=1,3)
1245 "tlbi_ipas2e1is_xt",
1246 "tlbi_ipas2le1is_xt",
1251 "tlbi_vmalls12e1is",
1359 static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
1360 "The miscRegName array and NUM_MISCREGS are inconsistent.");
1363 Bitfield<31, 30> nz;
1367 Bitfield<26, 25> it1;
1369 Bitfield<23, 22> res0_23_22;
1370 Bitfield<21> ss; // AArch64
1371 Bitfield<20> il; // AArch64
1372 Bitfield<19, 16> ge;
1373 Bitfield<15, 10> it2;
1374 Bitfield<9> d; // AArch64
1380 Bitfield<9, 6> daif; // AArch64
1382 Bitfield<4> width; // AArch64
1383 Bitfield<3, 2> el; // AArch64
1384 Bitfield<4, 0> mode;
1385 Bitfield<0> sp; // AArch64
1388 // This mask selects bits of the CPSR that actually go in the CondCodes
1389 // integer register to allow renaming.
1390 static const uint32_t CondCodesMask = 0xF00F0000;
1391 static const uint32_t CpsrMaskQ = 0x08000000;
1401 Bitfield<4, 0> hpmn;
1412 Bitfield<10> tfp; // AArch64
1446 Bitfield<33> id; // AArch64
1447 Bitfield<32> cd; // AArch64
1448 Bitfield<31> rw; // AArch64
1449 Bitfield<30> trvm; // AArch64
1450 Bitfield<29> hcd; // AArch64
1451 Bitfield<28> tdz; // AArch64
1460 Bitfield<21> tacr; // AArch64
1470 Bitfield<11, 10> bsu;
1473 Bitfield<8> vse; // AArch64
1485 Bitfield<20> nstrcdis;
1487 Bitfield<15> nsasedis;
1488 Bitfield<14> nsd32dis;
1508 Bitfield<11> st; // AArch64
1509 Bitfield<10> rw; // AArch64
1513 Bitfield<7> smd; // AArch64
1524 Bitfield<30> te; // Thumb Exception Enable (AArch32 only)
1525 Bitfield<29> afe; // Access flag enable (AArch32 only)
1526 Bitfield<28> tre; // TEX remap enable (AArch32 only)
1527 Bitfield<27> nmfi; // Non-maskable FIQ support (ARMv7 only)
1528 Bitfield<26> uci; // Enable EL0 access to DC CVAU, DC CIVAC,
1529 // DC CVAC and IC IVAU instructions
1530 // (AArch64 SCTLR_EL1 only)
1531 Bitfield<25> ee; // Exception Endianness
1532 Bitfield<24> ve; // Interrupt Vectors Enable (ARMv7 only)
1533 Bitfield<24> e0e; // Endianness of explicit data accesses at EL0
1534 // (AArch64 SCTLR_EL1 only)
1535 Bitfield<23> xp; // Extended page table enable (dropped in ARMv7)
1536 Bitfield<22> u; // Alignment (dropped in ARMv7)
1537 Bitfield<21> fi; // Fast interrupts configuration enable
1539 Bitfield<20> uwxn; // Unprivileged write permission implies EL1 XN
1541 Bitfield<19> dz; // Divide by Zero fault enable
1542 // (dropped in ARMv7)
1543 Bitfield<19> wxn; // Write permission implies XN
1544 Bitfield<18> ntwe; // Not trap WFE
1545 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1546 Bitfield<18> rao2; // Read as one
1547 Bitfield<16> ntwi; // Not trap WFI
1548 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1549 Bitfield<16> rao3; // Read as one
1550 Bitfield<15> uct; // Enable EL0 access to CTR_EL0
1551 // (AArch64 SCTLR_EL1 only)
1552 Bitfield<14> rr; // Round Robin select (ARMv7 only)
1553 Bitfield<14> dze; // Enable EL0 access to DC ZVA
1554 // (AArch64 SCTLR_EL1 only)
1555 Bitfield<13> v; // Vectors bit (AArch32 only)
1556 Bitfield<12> i; // Instruction cache enable
1557 Bitfield<11> z; // Branch prediction enable (ARMv7 only)
1558 Bitfield<10> sw; // SWP/SWPB enable (ARMv7 only)
1559 Bitfield<9, 8> rs; // Deprecated protection bits (dropped in ARMv7)
1560 Bitfield<9> uma; // User mask access (AArch64 SCTLR_EL1 only)
1561 Bitfield<8> sed; // SETEND disable
1562 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1563 Bitfield<7> b; // Endianness support (dropped in ARMv7)
1564 Bitfield<7> itd; // IT disable
1565 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1566 Bitfield<6, 3> rao4; // Read as one
1567 Bitfield<6> thee; // ThumbEE enable
1568 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1569 Bitfield<5> cp15ben; // CP15 barrier enable
1570 // (AArch32 and AArch64 SCTLR_EL1 only)
1571 Bitfield<4> sa0; // Stack Alignment Check Enable for EL0
1572 // (AArch64 SCTLR_EL1 only)
1573 Bitfield<3> sa; // Stack Alignment Check Enable (AArch64 only)
1574 Bitfield<2> c; // Cache enable
1575 Bitfield<1> a; // Alignment check enable
1576 Bitfield<0> m; // MMU enable
1585 Bitfield<11, 10> cp5;
1586 Bitfield<13, 12> cp6;
1587 Bitfield<15, 14> cp7;
1588 Bitfield<17, 16> cp8;
1589 Bitfield<19, 18> cp9;
1590 Bitfield<21, 20> cp10;
1591 Bitfield<21, 20> fpen; // AArch64
1592 Bitfield<23, 22> cp11;
1593 Bitfield<25, 24> cp12;
1594 Bitfield<27, 26> cp13;
1595 Bitfield<29, 28> rsvd;
1596 Bitfield<28> tta; // AArch64
1597 Bitfield<30> d32dis;
1598 Bitfield<31> asedis;
1602 Bitfield<3, 0> fsLow;
1603 Bitfield<5, 0> status; // LPAE
1604 Bitfield<7, 4> domain;
1606 Bitfield<10> fsHigh;
1609 Bitfield<13> cm; // LPAE
1625 Bitfield<18, 16> len;
1626 Bitfield<21, 20> stride;
1627 Bitfield<23, 22> rMode;
1638 // This mask selects bits of the FPSCR that actually go in the FpCondCodes
1639 // integer register to allow renaming.
1640 static const uint32_t FpCondCodesMask = 0xF0000000;
1641 // This mask selects the cumulative FP exception flags of the FPSCR.
1642 static const uint32_t FpscrExcMask = 0x0000009F;
1643 // This mask selects the cumulative saturation flag of the FPSCR.
1644 static const uint32_t FpscrQcMask = 0x08000000;
1649 Bitfield<29, 0> subArchDefined;
1653 Bitfield<3, 0> advSimdRegisters;
1654 Bitfield<7, 4> singlePrecision;
1655 Bitfield<11, 8> doublePrecision;
1656 Bitfield<15, 12> vfpExceptionTrapping;
1657 Bitfield<19, 16> divide;
1658 Bitfield<23, 20> squareRoot;
1659 Bitfield<27, 24> shortVectors;
1660 Bitfield<31, 28> roundingModes;
1664 Bitfield<3, 0> flushToZero;
1665 Bitfield<7, 4> defaultNaN;
1666 Bitfield<11, 8> advSimdLoadStore;
1667 Bitfield<15, 12> advSimdInteger;
1668 Bitfield<19, 16> advSimdSinglePrecision;
1669 Bitfield<23, 20> advSimdHalfPrecision;
1670 Bitfield<27, 24> vfpHalfPrecision;
1671 Bitfield<31, 28> raz;
1675 // Short-descriptor translation table format
1679 // Long-descriptor translation table format
1680 Bitfield<5, 0> t0sz;
1682 Bitfield<9, 8> irgn0;
1683 Bitfield<11, 10> orgn0;
1684 Bitfield<13, 12> sh0;
1686 Bitfield<21, 16> t1sz;
1689 Bitfield<25, 24> irgn1;
1690 Bitfield<27, 26> orgn1;
1691 Bitfield<29, 28> sh1;
1693 Bitfield<34, 32> ips;
1699 // TCR_EL2/3 (AArch64)
1700 Bitfield<18, 16> ps;
1704 // Fields of TCR_EL{1,2,3} (mostly overlapping)
1705 // TCR_EL1 is natively 64 bits, the others are 32 bits
1707 Bitfield<5, 0> t0sz;
1708 Bitfield<7> epd0; // EL1
1709 Bitfield<9, 8> irgn0;
1710 Bitfield<11, 10> orgn0;
1711 Bitfield<13, 12> sh0;
1712 Bitfield<15, 14> tg0;
1713 Bitfield<18, 16> ps;
1714 Bitfield<20> tbi; // EL2/EL3
1715 Bitfield<21, 16> t1sz; // EL1
1716 Bitfield<22> a1; // EL1
1717 Bitfield<23> epd1; // EL1
1718 Bitfield<25, 24> irgn1; // EL1
1719 Bitfield<27, 26> orgn1; // EL1
1720 Bitfield<29, 28> sh1; // EL1
1721 Bitfield<31, 30> tg1; // EL1
1722 Bitfield<34, 32> ips; // EL1
1723 Bitfield<36> as; // EL1
1724 Bitfield<37> tbi0; // EL1
1725 Bitfield<38> tbi1; // EL1
1729 Bitfield<2, 0> t0sz;
1730 Bitfield<9, 8> irgn0;
1731 Bitfield<11, 10> orgn0;
1732 Bitfield<13, 12> sh0;
1736 Bitfield<3, 0> t0sz;
1739 Bitfield<9, 8> irgn0;
1740 Bitfield<11, 10> orgn0;
1741 Bitfield<13, 12> sh0;
1750 Bitfield<11,10> tr5;
1751 Bitfield<13,12> tr6;
1752 Bitfield<15,14> tr7;
1773 Bitfield<11,10> ir5;
1774 Bitfield<13,12> ir6;
1775 Bitfield<15,14> ir7;
1776 Bitfield<17,16> or0;
1777 Bitfield<19,18> or1;
1778 Bitfield<21,20> or2;
1779 Bitfield<23,22> or3;
1780 Bitfield<25,24> or4;
1781 Bitfield<27,26> or5;
1782 Bitfield<29,28> or6;
1783 Bitfield<31,30> or7;
1786 BitUnion32(CONTEXTIDR)
1788 Bitfield<31,8> procid;
1789 EndBitUnion(CONTEXTIDR)
1792 Bitfield<2,0> sataRAMLatency;
1793 Bitfield<4,3> reserved_4_3;
1794 Bitfield<5> dataRAMSetup;
1795 Bitfield<8,6> tagRAMLatency;
1796 Bitfield<9> tagRAMSetup;
1797 Bitfield<11,10> dataRAMSlice;
1798 Bitfield<12> tagRAMSlice;
1799 Bitfield<20,13> reserved_20_13;
1800 Bitfield<21> eccandParityEnable;
1801 Bitfield<22> reserved_22;
1802 Bitfield<23> interptCtrlPresent;
1803 Bitfield<25,24> numCPUs;
1804 Bitfield<30,26> reserved_30_26;
1805 Bitfield<31> l2rstDISABLE_monitor;
1809 Bitfield<3,0> iCacheLineSize;
1810 Bitfield<13,4> raz_13_4;
1811 Bitfield<15,14> l1IndexPolicy;
1812 Bitfield<19,16> dCacheLineSize;
1813 Bitfield<23,20> erg;
1814 Bitfield<27,24> cwg;
1815 Bitfield<28> raz_28;
1816 Bitfield<31,29> format;
1825 Bitfield<63, 56> attr;
1826 Bitfield<39, 12> pa;
1834 Bitfield<31, 26> ec;
1836 Bitfield<15, 0> imm16;
1842 Bitfield<13, 12> res1_13_12_el2;
1844 Bitfield<9, 0> res1_9_0_el2;
1848 // Checks read access permissions to coproc. registers
1849 bool canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1852 // Checks write access permissions to coproc. registers
1853 bool canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1856 // Checks read access permissions to AArch64 system registers
1857 bool canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1860 // Checks write access permissions to AArch64 system registers
1861 bool canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1864 // Uses just the scr.ns bit to pre flatten the misc regs. This is useful
1865 // for MCR/MRC instructions
1867 flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc);
1869 // Flattens a misc reg index using the specified security state. This is
1870 // used for opperations (eg address translations) where the security
1871 // state of the register access may differ from the current state of the
1874 flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns);
1876 // Takes a misc reg index and returns the root reg if its one of a set of
1879 preUnflattenMiscReg();
1882 unflattenMiscReg(int reg);
1886 #endif // __ARCH_ARM_MISCREGS_HH__