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arm: Mark some miscregs (timer counter) registers at unverifiable.
[gem5.git] / src / arch / arm / miscregs.hh
1 /*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 * Giacomo Gabrielli
42 */
43 #ifndef __ARCH_ARM_MISCREGS_HH__
44 #define __ARCH_ARM_MISCREGS_HH__
45
46 #include <bitset>
47
48 #include "base/bitunion.hh"
49 #include "base/compiler.hh"
50
51 class ThreadContext;
52
53
54 namespace ArmISA
55 {
56 enum MiscRegIndex {
57 MISCREG_CPSR = 0, // 0
58 MISCREG_SPSR, // 1
59 MISCREG_SPSR_FIQ, // 2
60 MISCREG_SPSR_IRQ, // 3
61 MISCREG_SPSR_SVC, // 4
62 MISCREG_SPSR_MON, // 5
63 MISCREG_SPSR_ABT, // 6
64 MISCREG_SPSR_HYP, // 7
65 MISCREG_SPSR_UND, // 8
66 MISCREG_ELR_HYP, // 9
67 MISCREG_FPSID, // 10
68 MISCREG_FPSCR, // 11
69 MISCREG_MVFR1, // 12
70 MISCREG_MVFR0, // 13
71 MISCREG_FPEXC, // 14
72
73 // Helper registers
74 MISCREG_CPSR_MODE, // 15
75 MISCREG_CPSR_Q, // 16
76 MISCREG_FPSCR_EXC, // 17
77 MISCREG_FPSCR_QC, // 18
78 MISCREG_LOCKADDR, // 19
79 MISCREG_LOCKFLAG, // 20
80 MISCREG_PRRR_MAIR0, // 21
81 MISCREG_PRRR_MAIR0_NS, // 22
82 MISCREG_PRRR_MAIR0_S, // 23
83 MISCREG_NMRR_MAIR1, // 24
84 MISCREG_NMRR_MAIR1_NS, // 25
85 MISCREG_NMRR_MAIR1_S, // 26
86 MISCREG_PMXEVTYPER_PMCCFILTR, // 27
87 MISCREG_SCTLR_RST, // 28
88 MISCREG_SEV_MAILBOX, // 29
89
90 // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control)
91 MISCREG_DBGDIDR, // 30
92 MISCREG_DBGDSCRint, // 31
93 MISCREG_DBGDCCINT, // 32
94 MISCREG_DBGDTRTXint, // 33
95 MISCREG_DBGDTRRXint, // 34
96 MISCREG_DBGWFAR, // 35
97 MISCREG_DBGVCR, // 36
98 MISCREG_DBGDTRRXext, // 37
99 MISCREG_DBGDSCRext, // 38
100 MISCREG_DBGDTRTXext, // 39
101 MISCREG_DBGOSECCR, // 40
102 MISCREG_DBGBVR0, // 41
103 MISCREG_DBGBVR1, // 42
104 MISCREG_DBGBVR2, // 43
105 MISCREG_DBGBVR3, // 44
106 MISCREG_DBGBVR4, // 45
107 MISCREG_DBGBVR5, // 46
108 MISCREG_DBGBCR0, // 47
109 MISCREG_DBGBCR1, // 48
110 MISCREG_DBGBCR2, // 49
111 MISCREG_DBGBCR3, // 50
112 MISCREG_DBGBCR4, // 51
113 MISCREG_DBGBCR5, // 52
114 MISCREG_DBGWVR0, // 53
115 MISCREG_DBGWVR1, // 54
116 MISCREG_DBGWVR2, // 55
117 MISCREG_DBGWVR3, // 56
118 MISCREG_DBGWCR0, // 57
119 MISCREG_DBGWCR1, // 58
120 MISCREG_DBGWCR2, // 59
121 MISCREG_DBGWCR3, // 60
122 MISCREG_DBGDRAR, // 61
123 MISCREG_DBGBXVR4, // 62
124 MISCREG_DBGBXVR5, // 63
125 MISCREG_DBGOSLAR, // 64
126 MISCREG_DBGOSLSR, // 65
127 MISCREG_DBGOSDLR, // 66
128 MISCREG_DBGPRCR, // 67
129 MISCREG_DBGDSAR, // 68
130 MISCREG_DBGCLAIMSET, // 69
131 MISCREG_DBGCLAIMCLR, // 70
132 MISCREG_DBGAUTHSTATUS, // 71
133 MISCREG_DBGDEVID2, // 72
134 MISCREG_DBGDEVID1, // 73
135 MISCREG_DBGDEVID0, // 74
136 MISCREG_TEECR, // 75
137 MISCREG_JIDR, // 76
138 MISCREG_TEEHBR, // 77
139 MISCREG_JOSCR, // 78
140 MISCREG_JMCR, // 79
141
142 // AArch32 CP15 registers (system control)
143 MISCREG_MIDR, // 80
144 MISCREG_CTR, // 81
145 MISCREG_TCMTR, // 82
146 MISCREG_TLBTR, // 83
147 MISCREG_MPIDR, // 84
148 MISCREG_REVIDR, // 85
149 MISCREG_ID_PFR0, // 86
150 MISCREG_ID_PFR1, // 87
151 MISCREG_ID_DFR0, // 88
152 MISCREG_ID_AFR0, // 89
153 MISCREG_ID_MMFR0, // 90
154 MISCREG_ID_MMFR1, // 91
155 MISCREG_ID_MMFR2, // 92
156 MISCREG_ID_MMFR3, // 93
157 MISCREG_ID_ISAR0, // 94
158 MISCREG_ID_ISAR1, // 95
159 MISCREG_ID_ISAR2, // 96
160 MISCREG_ID_ISAR3, // 97
161 MISCREG_ID_ISAR4, // 98
162 MISCREG_ID_ISAR5, // 99
163 MISCREG_CCSIDR, // 100
164 MISCREG_CLIDR, // 101
165 MISCREG_AIDR, // 102
166 MISCREG_CSSELR, // 103
167 MISCREG_CSSELR_NS, // 104
168 MISCREG_CSSELR_S, // 105
169 MISCREG_VPIDR, // 106
170 MISCREG_VMPIDR, // 107
171 MISCREG_SCTLR, // 108
172 MISCREG_SCTLR_NS, // 109
173 MISCREG_SCTLR_S, // 110
174 MISCREG_ACTLR, // 111
175 MISCREG_ACTLR_NS, // 112
176 MISCREG_ACTLR_S, // 113
177 MISCREG_CPACR, // 114
178 MISCREG_SCR, // 115
179 MISCREG_SDER, // 116
180 MISCREG_NSACR, // 117
181 MISCREG_HSCTLR, // 118
182 MISCREG_HACTLR, // 119
183 MISCREG_HCR, // 120
184 MISCREG_HDCR, // 121
185 MISCREG_HCPTR, // 122
186 MISCREG_HSTR, // 123
187 MISCREG_HACR, // 124
188 MISCREG_TTBR0, // 125
189 MISCREG_TTBR0_NS, // 126
190 MISCREG_TTBR0_S, // 127
191 MISCREG_TTBR1, // 128
192 MISCREG_TTBR1_NS, // 129
193 MISCREG_TTBR1_S, // 130
194 MISCREG_TTBCR, // 131
195 MISCREG_TTBCR_NS, // 132
196 MISCREG_TTBCR_S, // 133
197 MISCREG_HTCR, // 134
198 MISCREG_VTCR, // 135
199 MISCREG_DACR, // 136
200 MISCREG_DACR_NS, // 137
201 MISCREG_DACR_S, // 138
202 MISCREG_DFSR, // 139
203 MISCREG_DFSR_NS, // 140
204 MISCREG_DFSR_S, // 141
205 MISCREG_IFSR, // 142
206 MISCREG_IFSR_NS, // 143
207 MISCREG_IFSR_S, // 144
208 MISCREG_ADFSR, // 145
209 MISCREG_ADFSR_NS, // 146
210 MISCREG_ADFSR_S, // 147
211 MISCREG_AIFSR, // 148
212 MISCREG_AIFSR_NS, // 149
213 MISCREG_AIFSR_S, // 150
214 MISCREG_HADFSR, // 151
215 MISCREG_HAIFSR, // 152
216 MISCREG_HSR, // 153
217 MISCREG_DFAR, // 154
218 MISCREG_DFAR_NS, // 155
219 MISCREG_DFAR_S, // 156
220 MISCREG_IFAR, // 157
221 MISCREG_IFAR_NS, // 158
222 MISCREG_IFAR_S, // 159
223 MISCREG_HDFAR, // 160
224 MISCREG_HIFAR, // 161
225 MISCREG_HPFAR, // 162
226 MISCREG_ICIALLUIS, // 163
227 MISCREG_BPIALLIS, // 164
228 MISCREG_PAR, // 165
229 MISCREG_PAR_NS, // 166
230 MISCREG_PAR_S, // 167
231 MISCREG_ICIALLU, // 168
232 MISCREG_ICIMVAU, // 169
233 MISCREG_CP15ISB, // 170
234 MISCREG_BPIALL, // 171
235 MISCREG_BPIMVA, // 172
236 MISCREG_DCIMVAC, // 173
237 MISCREG_DCISW, // 174
238 MISCREG_ATS1CPR, // 175
239 MISCREG_ATS1CPW, // 176
240 MISCREG_ATS1CUR, // 177
241 MISCREG_ATS1CUW, // 178
242 MISCREG_ATS12NSOPR, // 179
243 MISCREG_ATS12NSOPW, // 180
244 MISCREG_ATS12NSOUR, // 181
245 MISCREG_ATS12NSOUW, // 182
246 MISCREG_DCCMVAC, // 183
247 MISCREG_DCCSW, // 184
248 MISCREG_CP15DSB, // 185
249 MISCREG_CP15DMB, // 186
250 MISCREG_DCCMVAU, // 187
251 MISCREG_DCCIMVAC, // 188
252 MISCREG_DCCISW, // 189
253 MISCREG_ATS1HR, // 190
254 MISCREG_ATS1HW, // 191
255 MISCREG_TLBIALLIS, // 192
256 MISCREG_TLBIMVAIS, // 193
257 MISCREG_TLBIASIDIS, // 194
258 MISCREG_TLBIMVAAIS, // 195
259 MISCREG_TLBIMVALIS, // 196
260 MISCREG_TLBIMVAALIS, // 197
261 MISCREG_ITLBIALL, // 198
262 MISCREG_ITLBIMVA, // 199
263 MISCREG_ITLBIASID, // 200
264 MISCREG_DTLBIALL, // 201
265 MISCREG_DTLBIMVA, // 202
266 MISCREG_DTLBIASID, // 203
267 MISCREG_TLBIALL, // 204
268 MISCREG_TLBIMVA, // 205
269 MISCREG_TLBIASID, // 206
270 MISCREG_TLBIMVAA, // 207
271 MISCREG_TLBIMVAL, // 208
272 MISCREG_TLBIMVAAL, // 209
273 MISCREG_TLBIIPAS2IS, // 210
274 MISCREG_TLBIIPAS2LIS, // 211
275 MISCREG_TLBIALLHIS, // 212
276 MISCREG_TLBIMVAHIS, // 213
277 MISCREG_TLBIALLNSNHIS, // 214
278 MISCREG_TLBIMVALHIS, // 215
279 MISCREG_TLBIIPAS2, // 216
280 MISCREG_TLBIIPAS2L, // 217
281 MISCREG_TLBIALLH, // 218
282 MISCREG_TLBIMVAH, // 219
283 MISCREG_TLBIALLNSNH, // 220
284 MISCREG_TLBIMVALH, // 221
285 MISCREG_PMCR, // 222
286 MISCREG_PMCNTENSET, // 223
287 MISCREG_PMCNTENCLR, // 224
288 MISCREG_PMOVSR, // 225
289 MISCREG_PMSWINC, // 226
290 MISCREG_PMSELR, // 227
291 MISCREG_PMCEID0, // 228
292 MISCREG_PMCEID1, // 229
293 MISCREG_PMCCNTR, // 230
294 MISCREG_PMXEVTYPER, // 231
295 MISCREG_PMCCFILTR, // 232
296 MISCREG_PMXEVCNTR, // 233
297 MISCREG_PMUSERENR, // 234
298 MISCREG_PMINTENSET, // 235
299 MISCREG_PMINTENCLR, // 236
300 MISCREG_PMOVSSET, // 237
301 MISCREG_L2CTLR, // 238
302 MISCREG_L2ECTLR, // 239
303 MISCREG_PRRR, // 240
304 MISCREG_PRRR_NS, // 241
305 MISCREG_PRRR_S, // 242
306 MISCREG_MAIR0, // 243
307 MISCREG_MAIR0_NS, // 244
308 MISCREG_MAIR0_S, // 245
309 MISCREG_NMRR, // 246
310 MISCREG_NMRR_NS, // 247
311 MISCREG_NMRR_S, // 248
312 MISCREG_MAIR1, // 249
313 MISCREG_MAIR1_NS, // 250
314 MISCREG_MAIR1_S, // 251
315 MISCREG_AMAIR0, // 252
316 MISCREG_AMAIR0_NS, // 253
317 MISCREG_AMAIR0_S, // 254
318 MISCREG_AMAIR1, // 255
319 MISCREG_AMAIR1_NS, // 256
320 MISCREG_AMAIR1_S, // 257
321 MISCREG_HMAIR0, // 258
322 MISCREG_HMAIR1, // 259
323 MISCREG_HAMAIR0, // 260
324 MISCREG_HAMAIR1, // 261
325 MISCREG_VBAR, // 262
326 MISCREG_VBAR_NS, // 263
327 MISCREG_VBAR_S, // 264
328 MISCREG_MVBAR, // 265
329 MISCREG_RMR, // 266
330 MISCREG_ISR, // 267
331 MISCREG_HVBAR, // 268
332 MISCREG_FCSEIDR, // 269
333 MISCREG_CONTEXTIDR, // 270
334 MISCREG_CONTEXTIDR_NS, // 271
335 MISCREG_CONTEXTIDR_S, // 272
336 MISCREG_TPIDRURW, // 273
337 MISCREG_TPIDRURW_NS, // 274
338 MISCREG_TPIDRURW_S, // 275
339 MISCREG_TPIDRURO, // 276
340 MISCREG_TPIDRURO_NS, // 277
341 MISCREG_TPIDRURO_S, // 278
342 MISCREG_TPIDRPRW, // 279
343 MISCREG_TPIDRPRW_NS, // 280
344 MISCREG_TPIDRPRW_S, // 281
345 MISCREG_HTPIDR, // 282
346 MISCREG_CNTFRQ, // 283
347 MISCREG_CNTKCTL, // 284
348 MISCREG_CNTP_TVAL, // 285
349 MISCREG_CNTP_TVAL_NS, // 286
350 MISCREG_CNTP_TVAL_S, // 287
351 MISCREG_CNTP_CTL, // 288
352 MISCREG_CNTP_CTL_NS, // 289
353 MISCREG_CNTP_CTL_S, // 290
354 MISCREG_CNTV_TVAL, // 291
355 MISCREG_CNTV_CTL, // 292
356 MISCREG_CNTHCTL, // 293
357 MISCREG_CNTHP_TVAL, // 294
358 MISCREG_CNTHP_CTL, // 295
359 MISCREG_IL1DATA0, // 296
360 MISCREG_IL1DATA1, // 297
361 MISCREG_IL1DATA2, // 298
362 MISCREG_IL1DATA3, // 299
363 MISCREG_DL1DATA0, // 300
364 MISCREG_DL1DATA1, // 301
365 MISCREG_DL1DATA2, // 302
366 MISCREG_DL1DATA3, // 303
367 MISCREG_DL1DATA4, // 304
368 MISCREG_RAMINDEX, // 305
369 MISCREG_L2ACTLR, // 306
370 MISCREG_CBAR, // 307
371 MISCREG_HTTBR, // 308
372 MISCREG_VTTBR, // 309
373 MISCREG_CNTPCT, // 310
374 MISCREG_CNTVCT, // 311
375 MISCREG_CNTP_CVAL, // 312
376 MISCREG_CNTP_CVAL_NS, // 313
377 MISCREG_CNTP_CVAL_S, // 314
378 MISCREG_CNTV_CVAL, // 315
379 MISCREG_CNTVOFF, // 316
380 MISCREG_CNTHP_CVAL, // 317
381 MISCREG_CPUMERRSR, // 318
382 MISCREG_L2MERRSR, // 319
383
384 // AArch64 registers (Op0=2)
385 MISCREG_MDCCINT_EL1, // 320
386 MISCREG_OSDTRRX_EL1, // 321
387 MISCREG_MDSCR_EL1, // 322
388 MISCREG_OSDTRTX_EL1, // 323
389 MISCREG_OSECCR_EL1, // 324
390 MISCREG_DBGBVR0_EL1, // 325
391 MISCREG_DBGBVR1_EL1, // 326
392 MISCREG_DBGBVR2_EL1, // 327
393 MISCREG_DBGBVR3_EL1, // 328
394 MISCREG_DBGBVR4_EL1, // 329
395 MISCREG_DBGBVR5_EL1, // 330
396 MISCREG_DBGBCR0_EL1, // 331
397 MISCREG_DBGBCR1_EL1, // 332
398 MISCREG_DBGBCR2_EL1, // 333
399 MISCREG_DBGBCR3_EL1, // 334
400 MISCREG_DBGBCR4_EL1, // 335
401 MISCREG_DBGBCR5_EL1, // 336
402 MISCREG_DBGWVR0_EL1, // 337
403 MISCREG_DBGWVR1_EL1, // 338
404 MISCREG_DBGWVR2_EL1, // 339
405 MISCREG_DBGWVR3_EL1, // 340
406 MISCREG_DBGWCR0_EL1, // 341
407 MISCREG_DBGWCR1_EL1, // 342
408 MISCREG_DBGWCR2_EL1, // 343
409 MISCREG_DBGWCR3_EL1, // 344
410 MISCREG_MDCCSR_EL0, // 345
411 MISCREG_MDDTR_EL0, // 346
412 MISCREG_MDDTRTX_EL0, // 347
413 MISCREG_MDDTRRX_EL0, // 348
414 MISCREG_DBGVCR32_EL2, // 349
415 MISCREG_MDRAR_EL1, // 350
416 MISCREG_OSLAR_EL1, // 351
417 MISCREG_OSLSR_EL1, // 352
418 MISCREG_OSDLR_EL1, // 353
419 MISCREG_DBGPRCR_EL1, // 354
420 MISCREG_DBGCLAIMSET_EL1, // 355
421 MISCREG_DBGCLAIMCLR_EL1, // 356
422 MISCREG_DBGAUTHSTATUS_EL1, // 357
423 MISCREG_TEECR32_EL1, // 358
424 MISCREG_TEEHBR32_EL1, // 359
425
426 // AArch64 registers (Op0=1,3)
427 MISCREG_MIDR_EL1, // 360
428 MISCREG_MPIDR_EL1, // 361
429 MISCREG_REVIDR_EL1, // 362
430 MISCREG_ID_PFR0_EL1, // 363
431 MISCREG_ID_PFR1_EL1, // 364
432 MISCREG_ID_DFR0_EL1, // 365
433 MISCREG_ID_AFR0_EL1, // 366
434 MISCREG_ID_MMFR0_EL1, // 367
435 MISCREG_ID_MMFR1_EL1, // 368
436 MISCREG_ID_MMFR2_EL1, // 369
437 MISCREG_ID_MMFR3_EL1, // 370
438 MISCREG_ID_ISAR0_EL1, // 371
439 MISCREG_ID_ISAR1_EL1, // 372
440 MISCREG_ID_ISAR2_EL1, // 373
441 MISCREG_ID_ISAR3_EL1, // 374
442 MISCREG_ID_ISAR4_EL1, // 375
443 MISCREG_ID_ISAR5_EL1, // 376
444 MISCREG_MVFR0_EL1, // 377
445 MISCREG_MVFR1_EL1, // 378
446 MISCREG_MVFR2_EL1, // 379
447 MISCREG_ID_AA64PFR0_EL1, // 380
448 MISCREG_ID_AA64PFR1_EL1, // 381
449 MISCREG_ID_AA64DFR0_EL1, // 382
450 MISCREG_ID_AA64DFR1_EL1, // 383
451 MISCREG_ID_AA64AFR0_EL1, // 384
452 MISCREG_ID_AA64AFR1_EL1, // 385
453 MISCREG_ID_AA64ISAR0_EL1, // 386
454 MISCREG_ID_AA64ISAR1_EL1, // 387
455 MISCREG_ID_AA64MMFR0_EL1, // 388
456 MISCREG_ID_AA64MMFR1_EL1, // 389
457 MISCREG_CCSIDR_EL1, // 390
458 MISCREG_CLIDR_EL1, // 391
459 MISCREG_AIDR_EL1, // 392
460 MISCREG_CSSELR_EL1, // 393
461 MISCREG_CTR_EL0, // 394
462 MISCREG_DCZID_EL0, // 395
463 MISCREG_VPIDR_EL2, // 396
464 MISCREG_VMPIDR_EL2, // 397
465 MISCREG_SCTLR_EL1, // 398
466 MISCREG_ACTLR_EL1, // 399
467 MISCREG_CPACR_EL1, // 400
468 MISCREG_SCTLR_EL2, // 401
469 MISCREG_ACTLR_EL2, // 402
470 MISCREG_HCR_EL2, // 403
471 MISCREG_MDCR_EL2, // 404
472 MISCREG_CPTR_EL2, // 405
473 MISCREG_HSTR_EL2, // 406
474 MISCREG_HACR_EL2, // 407
475 MISCREG_SCTLR_EL3, // 408
476 MISCREG_ACTLR_EL3, // 409
477 MISCREG_SCR_EL3, // 410
478 MISCREG_SDER32_EL3, // 411
479 MISCREG_CPTR_EL3, // 412
480 MISCREG_MDCR_EL3, // 413
481 MISCREG_TTBR0_EL1, // 414
482 MISCREG_TTBR1_EL1, // 415
483 MISCREG_TCR_EL1, // 416
484 MISCREG_TTBR0_EL2, // 417
485 MISCREG_TCR_EL2, // 418
486 MISCREG_VTTBR_EL2, // 419
487 MISCREG_VTCR_EL2, // 420
488 MISCREG_TTBR0_EL3, // 421
489 MISCREG_TCR_EL3, // 422
490 MISCREG_DACR32_EL2, // 423
491 MISCREG_SPSR_EL1, // 424
492 MISCREG_ELR_EL1, // 425
493 MISCREG_SP_EL0, // 426
494 MISCREG_SPSEL, // 427
495 MISCREG_CURRENTEL, // 428
496 MISCREG_NZCV, // 429
497 MISCREG_DAIF, // 430
498 MISCREG_FPCR, // 431
499 MISCREG_FPSR, // 432
500 MISCREG_DSPSR_EL0, // 433
501 MISCREG_DLR_EL0, // 434
502 MISCREG_SPSR_EL2, // 435
503 MISCREG_ELR_EL2, // 436
504 MISCREG_SP_EL1, // 437
505 MISCREG_SPSR_IRQ_AA64, // 438
506 MISCREG_SPSR_ABT_AA64, // 439
507 MISCREG_SPSR_UND_AA64, // 440
508 MISCREG_SPSR_FIQ_AA64, // 441
509 MISCREG_SPSR_EL3, // 442
510 MISCREG_ELR_EL3, // 443
511 MISCREG_SP_EL2, // 444
512 MISCREG_AFSR0_EL1, // 445
513 MISCREG_AFSR1_EL1, // 446
514 MISCREG_ESR_EL1, // 447
515 MISCREG_IFSR32_EL2, // 448
516 MISCREG_AFSR0_EL2, // 449
517 MISCREG_AFSR1_EL2, // 450
518 MISCREG_ESR_EL2, // 451
519 MISCREG_FPEXC32_EL2, // 452
520 MISCREG_AFSR0_EL3, // 453
521 MISCREG_AFSR1_EL3, // 454
522 MISCREG_ESR_EL3, // 455
523 MISCREG_FAR_EL1, // 456
524 MISCREG_FAR_EL2, // 457
525 MISCREG_HPFAR_EL2, // 458
526 MISCREG_FAR_EL3, // 459
527 MISCREG_IC_IALLUIS, // 460
528 MISCREG_PAR_EL1, // 461
529 MISCREG_IC_IALLU, // 462
530 MISCREG_DC_IVAC_Xt, // 463
531 MISCREG_DC_ISW_Xt, // 464
532 MISCREG_AT_S1E1R_Xt, // 465
533 MISCREG_AT_S1E1W_Xt, // 466
534 MISCREG_AT_S1E0R_Xt, // 467
535 MISCREG_AT_S1E0W_Xt, // 468
536 MISCREG_DC_CSW_Xt, // 469
537 MISCREG_DC_CISW_Xt, // 470
538 MISCREG_DC_ZVA_Xt, // 471
539 MISCREG_IC_IVAU_Xt, // 472
540 MISCREG_DC_CVAC_Xt, // 473
541 MISCREG_DC_CVAU_Xt, // 474
542 MISCREG_DC_CIVAC_Xt, // 475
543 MISCREG_AT_S1E2R_Xt, // 476
544 MISCREG_AT_S1E2W_Xt, // 477
545 MISCREG_AT_S12E1R_Xt, // 478
546 MISCREG_AT_S12E1W_Xt, // 479
547 MISCREG_AT_S12E0R_Xt, // 480
548 MISCREG_AT_S12E0W_Xt, // 481
549 MISCREG_AT_S1E3R_Xt, // 482
550 MISCREG_AT_S1E3W_Xt, // 483
551 MISCREG_TLBI_VMALLE1IS, // 484
552 MISCREG_TLBI_VAE1IS_Xt, // 485
553 MISCREG_TLBI_ASIDE1IS_Xt, // 486
554 MISCREG_TLBI_VAAE1IS_Xt, // 487
555 MISCREG_TLBI_VALE1IS_Xt, // 488
556 MISCREG_TLBI_VAALE1IS_Xt, // 489
557 MISCREG_TLBI_VMALLE1, // 490
558 MISCREG_TLBI_VAE1_Xt, // 491
559 MISCREG_TLBI_ASIDE1_Xt, // 492
560 MISCREG_TLBI_VAAE1_Xt, // 493
561 MISCREG_TLBI_VALE1_Xt, // 494
562 MISCREG_TLBI_VAALE1_Xt, // 495
563 MISCREG_TLBI_IPAS2E1IS_Xt, // 496
564 MISCREG_TLBI_IPAS2LE1IS_Xt, // 497
565 MISCREG_TLBI_ALLE2IS, // 498
566 MISCREG_TLBI_VAE2IS_Xt, // 499
567 MISCREG_TLBI_ALLE1IS, // 500
568 MISCREG_TLBI_VALE2IS_Xt, // 501
569 MISCREG_TLBI_VMALLS12E1IS, // 502
570 MISCREG_TLBI_IPAS2E1_Xt, // 503
571 MISCREG_TLBI_IPAS2LE1_Xt, // 504
572 MISCREG_TLBI_ALLE2, // 505
573 MISCREG_TLBI_VAE2_Xt, // 506
574 MISCREG_TLBI_ALLE1, // 507
575 MISCREG_TLBI_VALE2_Xt, // 508
576 MISCREG_TLBI_VMALLS12E1, // 509
577 MISCREG_TLBI_ALLE3IS, // 510
578 MISCREG_TLBI_VAE3IS_Xt, // 511
579 MISCREG_TLBI_VALE3IS_Xt, // 512
580 MISCREG_TLBI_ALLE3, // 513
581 MISCREG_TLBI_VAE3_Xt, // 514
582 MISCREG_TLBI_VALE3_Xt, // 515
583 MISCREG_PMINTENSET_EL1, // 516
584 MISCREG_PMINTENCLR_EL1, // 517
585 MISCREG_PMCR_EL0, // 518
586 MISCREG_PMCNTENSET_EL0, // 519
587 MISCREG_PMCNTENCLR_EL0, // 520
588 MISCREG_PMOVSCLR_EL0, // 521
589 MISCREG_PMSWINC_EL0, // 522
590 MISCREG_PMSELR_EL0, // 523
591 MISCREG_PMCEID0_EL0, // 524
592 MISCREG_PMCEID1_EL0, // 525
593 MISCREG_PMCCNTR_EL0, // 526
594 MISCREG_PMXEVTYPER_EL0, // 527
595 MISCREG_PMCCFILTR_EL0, // 528
596 MISCREG_PMXEVCNTR_EL0, // 529
597 MISCREG_PMUSERENR_EL0, // 530
598 MISCREG_PMOVSSET_EL0, // 531
599 MISCREG_MAIR_EL1, // 532
600 MISCREG_AMAIR_EL1, // 533
601 MISCREG_MAIR_EL2, // 534
602 MISCREG_AMAIR_EL2, // 535
603 MISCREG_MAIR_EL3, // 536
604 MISCREG_AMAIR_EL3, // 537
605 MISCREG_L2CTLR_EL1, // 538
606 MISCREG_L2ECTLR_EL1, // 539
607 MISCREG_VBAR_EL1, // 540
608 MISCREG_RVBAR_EL1, // 541
609 MISCREG_ISR_EL1, // 542
610 MISCREG_VBAR_EL2, // 543
611 MISCREG_RVBAR_EL2, // 544
612 MISCREG_VBAR_EL3, // 545
613 MISCREG_RVBAR_EL3, // 546
614 MISCREG_RMR_EL3, // 547
615 MISCREG_CONTEXTIDR_EL1, // 548
616 MISCREG_TPIDR_EL1, // 549
617 MISCREG_TPIDR_EL0, // 550
618 MISCREG_TPIDRRO_EL0, // 551
619 MISCREG_TPIDR_EL2, // 552
620 MISCREG_TPIDR_EL3, // 553
621 MISCREG_CNTKCTL_EL1, // 554
622 MISCREG_CNTFRQ_EL0, // 555
623 MISCREG_CNTPCT_EL0, // 556
624 MISCREG_CNTVCT_EL0, // 557
625 MISCREG_CNTP_TVAL_EL0, // 558
626 MISCREG_CNTP_CTL_EL0, // 559
627 MISCREG_CNTP_CVAL_EL0, // 560
628 MISCREG_CNTV_TVAL_EL0, // 561
629 MISCREG_CNTV_CTL_EL0, // 562
630 MISCREG_CNTV_CVAL_EL0, // 563
631 MISCREG_PMEVCNTR0_EL0, // 564
632 MISCREG_PMEVCNTR1_EL0, // 565
633 MISCREG_PMEVCNTR2_EL0, // 566
634 MISCREG_PMEVCNTR3_EL0, // 567
635 MISCREG_PMEVCNTR4_EL0, // 568
636 MISCREG_PMEVCNTR5_EL0, // 569
637 MISCREG_PMEVTYPER0_EL0, // 570
638 MISCREG_PMEVTYPER1_EL0, // 571
639 MISCREG_PMEVTYPER2_EL0, // 572
640 MISCREG_PMEVTYPER3_EL0, // 573
641 MISCREG_PMEVTYPER4_EL0, // 574
642 MISCREG_PMEVTYPER5_EL0, // 575
643 MISCREG_CNTVOFF_EL2, // 576
644 MISCREG_CNTHCTL_EL2, // 577
645 MISCREG_CNTHP_TVAL_EL2, // 578
646 MISCREG_CNTHP_CTL_EL2, // 579
647 MISCREG_CNTHP_CVAL_EL2, // 580
648 MISCREG_CNTPS_TVAL_EL1, // 581
649 MISCREG_CNTPS_CTL_EL1, // 582
650 MISCREG_CNTPS_CVAL_EL1, // 583
651 MISCREG_IL1DATA0_EL1, // 584
652 MISCREG_IL1DATA1_EL1, // 585
653 MISCREG_IL1DATA2_EL1, // 586
654 MISCREG_IL1DATA3_EL1, // 587
655 MISCREG_DL1DATA0_EL1, // 588
656 MISCREG_DL1DATA1_EL1, // 589
657 MISCREG_DL1DATA2_EL1, // 590
658 MISCREG_DL1DATA3_EL1, // 591
659 MISCREG_DL1DATA4_EL1, // 592
660 MISCREG_L2ACTLR_EL1, // 593
661 MISCREG_CPUACTLR_EL1, // 594
662 MISCREG_CPUECTLR_EL1, // 595
663 MISCREG_CPUMERRSR_EL1, // 596
664 MISCREG_L2MERRSR_EL1, // 597
665 MISCREG_CBAR_EL1, // 598
666
667 // Dummy registers
668 MISCREG_NOP, // 599
669 MISCREG_RAZ, // 600
670 MISCREG_CP14_UNIMPL, // 601
671 MISCREG_CP15_UNIMPL, // 602
672 MISCREG_A64_UNIMPL, // 603
673 MISCREG_UNKNOWN, // 604
674
675 NUM_MISCREGS // 605
676 };
677
678 enum MiscRegInfo {
679 MISCREG_IMPLEMENTED,
680 MISCREG_UNVERIFIABLE, // Does the value change on every read (e.g. a
681 // arch generic counter)
682 MISCREG_WARN_NOT_FAIL, // If MISCREG_IMPLEMENTED is deasserted, it
683 // tells whether the instruction should raise a
684 // warning or fail
685 MISCREG_MUTEX, // True if the register corresponds to a pair of
686 // mutually exclusive registers
687 MISCREG_BANKED, // True if the register is banked between the two
688 // security states, and this is the parent node of the
689 // two banked registers
690 MISCREG_BANKED_CHILD, // The entry is one of the child registers that
691 // forms a banked set of regs (along with the
692 // other child regs)
693
694 // Access permissions
695 // User mode
696 MISCREG_USR_NS_RD,
697 MISCREG_USR_NS_WR,
698 MISCREG_USR_S_RD,
699 MISCREG_USR_S_WR,
700 // Privileged modes other than hypervisor or monitor
701 MISCREG_PRI_NS_RD,
702 MISCREG_PRI_NS_WR,
703 MISCREG_PRI_S_RD,
704 MISCREG_PRI_S_WR,
705 // Hypervisor mode
706 MISCREG_HYP_RD,
707 MISCREG_HYP_WR,
708 // Monitor mode, SCR.NS == 0
709 MISCREG_MON_NS0_RD,
710 MISCREG_MON_NS0_WR,
711 // Monitor mode, SCR.NS == 1
712 MISCREG_MON_NS1_RD,
713 MISCREG_MON_NS1_WR,
714
715 NUM_MISCREG_INFOS
716 };
717
718 extern std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS];
719
720 // Decodes 32-bit CP14 registers accessible through MCR/MRC instructions
721 MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1,
722 unsigned crm, unsigned opc2);
723 MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1,
724 unsigned crn, unsigned crm,
725 unsigned op2);
726 // Whether a particular AArch64 system register is -always- read only.
727 bool aarch64SysRegReadOnly(MiscRegIndex miscReg);
728
729 // Decodes 32-bit CP15 registers accessible through MCR/MRC instructions
730 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
731 unsigned crm, unsigned opc2);
732
733 // Decodes 64-bit CP15 registers accessible through MCRR/MRRC instructions
734 MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1);
735
736
737 const char * const miscRegName[] = {
738 "cpsr",
739 "spsr",
740 "spsr_fiq",
741 "spsr_irq",
742 "spsr_svc",
743 "spsr_mon",
744 "spsr_abt",
745 "spsr_hyp",
746 "spsr_und",
747 "elr_hyp",
748 "fpsid",
749 "fpscr",
750 "mvfr1",
751 "mvfr0",
752 "fpexc",
753
754 // Helper registers
755 "cpsr_mode",
756 "cpsr_q",
757 "fpscr_exc",
758 "fpscr_qc",
759 "lockaddr",
760 "lockflag",
761 "prrr_mair0",
762 "prrr_mair0_ns",
763 "prrr_mair0_s",
764 "nmrr_mair1",
765 "nmrr_mair1_ns",
766 "nmrr_mair1_s",
767 "pmxevtyper_pmccfiltr",
768 "sctlr_rst",
769 "sev_mailbox",
770
771 // AArch32 CP14 registers
772 "dbgdidr",
773 "dbgdscrint",
774 "dbgdccint",
775 "dbgdtrtxint",
776 "dbgdtrrxint",
777 "dbgwfar",
778 "dbgvcr",
779 "dbgdtrrxext",
780 "dbgdscrext",
781 "dbgdtrtxext",
782 "dbgoseccr",
783 "dbgbvr0",
784 "dbgbvr1",
785 "dbgbvr2",
786 "dbgbvr3",
787 "dbgbvr4",
788 "dbgbvr5",
789 "dbgbcr0",
790 "dbgbcr1",
791 "dbgbcr2",
792 "dbgbcr3",
793 "dbgbcr4",
794 "dbgbcr5",
795 "dbgwvr0",
796 "dbgwvr1",
797 "dbgwvr2",
798 "dbgwvr3",
799 "dbgwcr0",
800 "dbgwcr1",
801 "dbgwcr2",
802 "dbgwcr3",
803 "dbgdrar",
804 "dbgbxvr4",
805 "dbgbxvr5",
806 "dbgoslar",
807 "dbgoslsr",
808 "dbgosdlr",
809 "dbgprcr",
810 "dbgdsar",
811 "dbgclaimset",
812 "dbgclaimclr",
813 "dbgauthstatus",
814 "dbgdevid2",
815 "dbgdevid1",
816 "dbgdevid0",
817 "teecr",
818 "jidr",
819 "teehbr",
820 "joscr",
821 "jmcr",
822
823 // AArch32 CP15 registers
824 "midr",
825 "ctr",
826 "tcmtr",
827 "tlbtr",
828 "mpidr",
829 "revidr",
830 "id_pfr0",
831 "id_pfr1",
832 "id_dfr0",
833 "id_afr0",
834 "id_mmfr0",
835 "id_mmfr1",
836 "id_mmfr2",
837 "id_mmfr3",
838 "id_isar0",
839 "id_isar1",
840 "id_isar2",
841 "id_isar3",
842 "id_isar4",
843 "id_isar5",
844 "ccsidr",
845 "clidr",
846 "aidr",
847 "csselr",
848 "csselr_ns",
849 "csselr_s",
850 "vpidr",
851 "vmpidr",
852 "sctlr",
853 "sctlr_ns",
854 "sctlr_s",
855 "actlr",
856 "actlr_ns",
857 "actlr_s",
858 "cpacr",
859 "scr",
860 "sder",
861 "nsacr",
862 "hsctlr",
863 "hactlr",
864 "hcr",
865 "hdcr",
866 "hcptr",
867 "hstr",
868 "hacr",
869 "ttbr0",
870 "ttbr0_ns",
871 "ttbr0_s",
872 "ttbr1",
873 "ttbr1_ns",
874 "ttbr1_s",
875 "ttbcr",
876 "ttbcr_ns",
877 "ttbcr_s",
878 "htcr",
879 "vtcr",
880 "dacr",
881 "dacr_ns",
882 "dacr_s",
883 "dfsr",
884 "dfsr_ns",
885 "dfsr_s",
886 "ifsr",
887 "ifsr_ns",
888 "ifsr_s",
889 "adfsr",
890 "adfsr_ns",
891 "adfsr_s",
892 "aifsr",
893 "aifsr_ns",
894 "aifsr_s",
895 "hadfsr",
896 "haifsr",
897 "hsr",
898 "dfar",
899 "dfar_ns",
900 "dfar_s",
901 "ifar",
902 "ifar_ns",
903 "ifar_s",
904 "hdfar",
905 "hifar",
906 "hpfar",
907 "icialluis",
908 "bpiallis",
909 "par",
910 "par_ns",
911 "par_s",
912 "iciallu",
913 "icimvau",
914 "cp15isb",
915 "bpiall",
916 "bpimva",
917 "dcimvac",
918 "dcisw",
919 "ats1cpr",
920 "ats1cpw",
921 "ats1cur",
922 "ats1cuw",
923 "ats12nsopr",
924 "ats12nsopw",
925 "ats12nsour",
926 "ats12nsouw",
927 "dccmvac",
928 "dccsw",
929 "cp15dsb",
930 "cp15dmb",
931 "dccmvau",
932 "dccimvac",
933 "dccisw",
934 "ats1hr",
935 "ats1hw",
936 "tlbiallis",
937 "tlbimvais",
938 "tlbiasidis",
939 "tlbimvaais",
940 "tlbimvalis",
941 "tlbimvaalis",
942 "itlbiall",
943 "itlbimva",
944 "itlbiasid",
945 "dtlbiall",
946 "dtlbimva",
947 "dtlbiasid",
948 "tlbiall",
949 "tlbimva",
950 "tlbiasid",
951 "tlbimvaa",
952 "tlbimval",
953 "tlbimvaal",
954 "tlbiipas2is",
955 "tlbiipas2lis",
956 "tlbiallhis",
957 "tlbimvahis",
958 "tlbiallnsnhis",
959 "tlbimvalhis",
960 "tlbiipas2",
961 "tlbiipas2l",
962 "tlbiallh",
963 "tlbimvah",
964 "tlbiallnsnh",
965 "tlbimvalh",
966 "pmcr",
967 "pmcntenset",
968 "pmcntenclr",
969 "pmovsr",
970 "pmswinc",
971 "pmselr",
972 "pmceid0",
973 "pmceid1",
974 "pmccntr",
975 "pmxevtyper",
976 "pmccfiltr",
977 "pmxevcntr",
978 "pmuserenr",
979 "pmintenset",
980 "pmintenclr",
981 "pmovsset",
982 "l2ctlr",
983 "l2ectlr",
984 "prrr",
985 "prrr_ns",
986 "prrr_s",
987 "mair0",
988 "mair0_ns",
989 "mair0_s",
990 "nmrr",
991 "nmrr_ns",
992 "nmrr_s",
993 "mair1",
994 "mair1_ns",
995 "mair1_s",
996 "amair0",
997 "amair0_ns",
998 "amair0_s",
999 "amair1",
1000 "amair1_ns",
1001 "amair1_s",
1002 "hmair0",
1003 "hmair1",
1004 "hamair0",
1005 "hamair1",
1006 "vbar",
1007 "vbar_ns",
1008 "vbar_s",
1009 "mvbar",
1010 "rmr",
1011 "isr",
1012 "hvbar",
1013 "fcseidr",
1014 "contextidr",
1015 "contextidr_ns",
1016 "contextidr_s",
1017 "tpidrurw",
1018 "tpidrurw_ns",
1019 "tpidrurw_s",
1020 "tpidruro",
1021 "tpidruro_ns",
1022 "tpidruro_s",
1023 "tpidrprw",
1024 "tpidrprw_ns",
1025 "tpidrprw_s",
1026 "htpidr",
1027 "cntfrq",
1028 "cntkctl",
1029 "cntp_tval",
1030 "cntp_tval_ns",
1031 "cntp_tval_s",
1032 "cntp_ctl",
1033 "cntp_ctl_ns",
1034 "cntp_ctl_s",
1035 "cntv_tval",
1036 "cntv_ctl",
1037 "cnthctl",
1038 "cnthp_tval",
1039 "cnthp_ctl",
1040 "il1data0",
1041 "il1data1",
1042 "il1data2",
1043 "il1data3",
1044 "dl1data0",
1045 "dl1data1",
1046 "dl1data2",
1047 "dl1data3",
1048 "dl1data4",
1049 "ramindex",
1050 "l2actlr",
1051 "cbar",
1052 "httbr",
1053 "vttbr",
1054 "cntpct",
1055 "cntvct",
1056 "cntp_cval",
1057 "cntp_cval_ns",
1058 "cntp_cval_s",
1059 "cntv_cval",
1060 "cntvoff",
1061 "cnthp_cval",
1062 "cpumerrsr",
1063 "l2merrsr",
1064
1065 // AArch64 registers (Op0=2)
1066 "mdccint_el1",
1067 "osdtrrx_el1",
1068 "mdscr_el1",
1069 "osdtrtx_el1",
1070 "oseccr_el1",
1071 "dbgbvr0_el1",
1072 "dbgbvr1_el1",
1073 "dbgbvr2_el1",
1074 "dbgbvr3_el1",
1075 "dbgbvr4_el1",
1076 "dbgbvr5_el1",
1077 "dbgbcr0_el1",
1078 "dbgbcr1_el1",
1079 "dbgbcr2_el1",
1080 "dbgbcr3_el1",
1081 "dbgbcr4_el1",
1082 "dbgbcr5_el1",
1083 "dbgwvr0_el1",
1084 "dbgwvr1_el1",
1085 "dbgwvr2_el1",
1086 "dbgwvr3_el1",
1087 "dbgwcr0_el1",
1088 "dbgwcr1_el1",
1089 "dbgwcr2_el1",
1090 "dbgwcr3_el1",
1091 "mdccsr_el0",
1092 "mddtr_el0",
1093 "mddtrtx_el0",
1094 "mddtrrx_el0",
1095 "dbgvcr32_el2",
1096 "mdrar_el1",
1097 "oslar_el1",
1098 "oslsr_el1",
1099 "osdlr_el1",
1100 "dbgprcr_el1",
1101 "dbgclaimset_el1",
1102 "dbgclaimclr_el1",
1103 "dbgauthstatus_el1",
1104 "teecr32_el1",
1105 "teehbr32_el1",
1106
1107 // AArch64 registers (Op0=1,3)
1108 "midr_el1",
1109 "mpidr_el1",
1110 "revidr_el1",
1111 "id_pfr0_el1",
1112 "id_pfr1_el1",
1113 "id_dfr0_el1",
1114 "id_afr0_el1",
1115 "id_mmfr0_el1",
1116 "id_mmfr1_el1",
1117 "id_mmfr2_el1",
1118 "id_mmfr3_el1",
1119 "id_isar0_el1",
1120 "id_isar1_el1",
1121 "id_isar2_el1",
1122 "id_isar3_el1",
1123 "id_isar4_el1",
1124 "id_isar5_el1",
1125 "mvfr0_el1",
1126 "mvfr1_el1",
1127 "mvfr2_el1",
1128 "id_aa64pfr0_el1",
1129 "id_aa64pfr1_el1",
1130 "id_aa64dfr0_el1",
1131 "id_aa64dfr1_el1",
1132 "id_aa64afr0_el1",
1133 "id_aa64afr1_el1",
1134 "id_aa64isar0_el1",
1135 "id_aa64isar1_el1",
1136 "id_aa64mmfr0_el1",
1137 "id_aa64mmfr1_el1",
1138 "ccsidr_el1",
1139 "clidr_el1",
1140 "aidr_el1",
1141 "csselr_el1",
1142 "ctr_el0",
1143 "dczid_el0",
1144 "vpidr_el2",
1145 "vmpidr_el2",
1146 "sctlr_el1",
1147 "actlr_el1",
1148 "cpacr_el1",
1149 "sctlr_el2",
1150 "actlr_el2",
1151 "hcr_el2",
1152 "mdcr_el2",
1153 "cptr_el2",
1154 "hstr_el2",
1155 "hacr_el2",
1156 "sctlr_el3",
1157 "actlr_el3",
1158 "scr_el3",
1159 "sder32_el3",
1160 "cptr_el3",
1161 "mdcr_el3",
1162 "ttbr0_el1",
1163 "ttbr1_el1",
1164 "tcr_el1",
1165 "ttbr0_el2",
1166 "tcr_el2",
1167 "vttbr_el2",
1168 "vtcr_el2",
1169 "ttbr0_el3",
1170 "tcr_el3",
1171 "dacr32_el2",
1172 "spsr_el1",
1173 "elr_el1",
1174 "sp_el0",
1175 "spsel",
1176 "currentel",
1177 "nzcv",
1178 "daif",
1179 "fpcr",
1180 "fpsr",
1181 "dspsr_el0",
1182 "dlr_el0",
1183 "spsr_el2",
1184 "elr_el2",
1185 "sp_el1",
1186 "spsr_irq_aa64",
1187 "spsr_abt_aa64",
1188 "spsr_und_aa64",
1189 "spsr_fiq_aa64",
1190 "spsr_el3",
1191 "elr_el3",
1192 "sp_el2",
1193 "afsr0_el1",
1194 "afsr1_el1",
1195 "esr_el1",
1196 "ifsr32_el2",
1197 "afsr0_el2",
1198 "afsr1_el2",
1199 "esr_el2",
1200 "fpexc32_el2",
1201 "afsr0_el3",
1202 "afsr1_el3",
1203 "esr_el3",
1204 "far_el1",
1205 "far_el2",
1206 "hpfar_el2",
1207 "far_el3",
1208 "ic_ialluis",
1209 "par_el1",
1210 "ic_iallu",
1211 "dc_ivac_xt",
1212 "dc_isw_xt",
1213 "at_s1e1r_xt",
1214 "at_s1e1w_xt",
1215 "at_s1e0r_xt",
1216 "at_s1e0w_xt",
1217 "dc_csw_xt",
1218 "dc_cisw_xt",
1219 "dc_zva_xt",
1220 "ic_ivau_xt",
1221 "dc_cvac_xt",
1222 "dc_cvau_xt",
1223 "dc_civac_xt",
1224 "at_s1e2r_xt",
1225 "at_s1e2w_xt",
1226 "at_s12e1r_xt",
1227 "at_s12e1w_xt",
1228 "at_s12e0r_xt",
1229 "at_s12e0w_xt",
1230 "at_s1e3r_xt",
1231 "at_s1e3w_xt",
1232 "tlbi_vmalle1is",
1233 "tlbi_vae1is_xt",
1234 "tlbi_aside1is_xt",
1235 "tlbi_vaae1is_xt",
1236 "tlbi_vale1is_xt",
1237 "tlbi_vaale1is_xt",
1238 "tlbi_vmalle1",
1239 "tlbi_vae1_xt",
1240 "tlbi_aside1_xt",
1241 "tlbi_vaae1_xt",
1242 "tlbi_vale1_xt",
1243 "tlbi_vaale1_xt",
1244 "tlbi_ipas2e1is_xt",
1245 "tlbi_ipas2le1is_xt",
1246 "tlbi_alle2is",
1247 "tlbi_vae2is_xt",
1248 "tlbi_alle1is",
1249 "tlbi_vale2is_xt",
1250 "tlbi_vmalls12e1is",
1251 "tlbi_ipas2e1_xt",
1252 "tlbi_ipas2le1_xt",
1253 "tlbi_alle2",
1254 "tlbi_vae2_xt",
1255 "tlbi_alle1",
1256 "tlbi_vale2_xt",
1257 "tlbi_vmalls12e1",
1258 "tlbi_alle3is",
1259 "tlbi_vae3is_xt",
1260 "tlbi_vale3is_xt",
1261 "tlbi_alle3",
1262 "tlbi_vae3_xt",
1263 "tlbi_vale3_xt",
1264 "pmintenset_el1",
1265 "pmintenclr_el1",
1266 "pmcr_el0",
1267 "pmcntenset_el0",
1268 "pmcntenclr_el0",
1269 "pmovsclr_el0",
1270 "pmswinc_el0",
1271 "pmselr_el0",
1272 "pmceid0_el0",
1273 "pmceid1_el0",
1274 "pmccntr_el0",
1275 "pmxevtyper_el0",
1276 "pmccfiltr_el0",
1277 "pmxevcntr_el0",
1278 "pmuserenr_el0",
1279 "pmovsset_el0",
1280 "mair_el1",
1281 "amair_el1",
1282 "mair_el2",
1283 "amair_el2",
1284 "mair_el3",
1285 "amair_el3",
1286 "l2ctlr_el1",
1287 "l2ectlr_el1",
1288 "vbar_el1",
1289 "rvbar_el1",
1290 "isr_el1",
1291 "vbar_el2",
1292 "rvbar_el2",
1293 "vbar_el3",
1294 "rvbar_el3",
1295 "rmr_el3",
1296 "contextidr_el1",
1297 "tpidr_el1",
1298 "tpidr_el0",
1299 "tpidrro_el0",
1300 "tpidr_el2",
1301 "tpidr_el3",
1302 "cntkctl_el1",
1303 "cntfrq_el0",
1304 "cntpct_el0",
1305 "cntvct_el0",
1306 "cntp_tval_el0",
1307 "cntp_ctl_el0",
1308 "cntp_cval_el0",
1309 "cntv_tval_el0",
1310 "cntv_ctl_el0",
1311 "cntv_cval_el0",
1312 "pmevcntr0_el0",
1313 "pmevcntr1_el0",
1314 "pmevcntr2_el0",
1315 "pmevcntr3_el0",
1316 "pmevcntr4_el0",
1317 "pmevcntr5_el0",
1318 "pmevtyper0_el0",
1319 "pmevtyper1_el0",
1320 "pmevtyper2_el0",
1321 "pmevtyper3_el0",
1322 "pmevtyper4_el0",
1323 "pmevtyper5_el0",
1324 "cntvoff_el2",
1325 "cnthctl_el2",
1326 "cnthp_tval_el2",
1327 "cnthp_ctl_el2",
1328 "cnthp_cval_el2",
1329 "cntps_tval_el1",
1330 "cntps_ctl_el1",
1331 "cntps_cval_el1",
1332 "il1data0_el1",
1333 "il1data1_el1",
1334 "il1data2_el1",
1335 "il1data3_el1",
1336 "dl1data0_el1",
1337 "dl1data1_el1",
1338 "dl1data2_el1",
1339 "dl1data3_el1",
1340 "dl1data4_el1",
1341 "l2actlr_el1",
1342 "cpuactlr_el1",
1343 "cpuectlr_el1",
1344 "cpumerrsr_el1",
1345 "l2merrsr_el1",
1346 "cbar_el1",
1347
1348 // Dummy registers
1349 "nop",
1350 "raz",
1351 "cp14_unimpl",
1352 "cp15_unimpl",
1353 "a64_unimpl",
1354 "unknown"
1355 };
1356
1357 static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
1358 "The miscRegName array and NUM_MISCREGS are inconsistent.");
1359
1360 BitUnion32(CPSR)
1361 Bitfield<31, 30> nz;
1362 Bitfield<29> c;
1363 Bitfield<28> v;
1364 Bitfield<27> q;
1365 Bitfield<26, 25> it1;
1366 Bitfield<24> j;
1367 Bitfield<23, 22> res0_23_22;
1368 Bitfield<21> ss; // AArch64
1369 Bitfield<20> il; // AArch64
1370 Bitfield<19, 16> ge;
1371 Bitfield<15, 10> it2;
1372 Bitfield<9> d; // AArch64
1373 Bitfield<9> e;
1374 Bitfield<8> a;
1375 Bitfield<7> i;
1376 Bitfield<6> f;
1377 Bitfield<9, 6> daif; // AArch64
1378 Bitfield<5> t;
1379 Bitfield<4> width; // AArch64
1380 Bitfield<3, 2> el; // AArch64
1381 Bitfield<4, 0> mode;
1382 Bitfield<0> sp; // AArch64
1383 EndBitUnion(CPSR)
1384
1385 // This mask selects bits of the CPSR that actually go in the CondCodes
1386 // integer register to allow renaming.
1387 static const uint32_t CondCodesMask = 0xF00F0000;
1388 static const uint32_t CpsrMaskQ = 0x08000000;
1389
1390 BitUnion32(HDCR)
1391 Bitfield<11> tdra;
1392 Bitfield<10> tdosa;
1393 Bitfield<9> tda;
1394 Bitfield<8> tde;
1395 Bitfield<7> hpme;
1396 Bitfield<6> tpm;
1397 Bitfield<5> tpmcr;
1398 Bitfield<4, 0> hpmn;
1399 EndBitUnion(HDCR)
1400
1401 BitUnion32(HCPTR)
1402 Bitfield<31> tcpac;
1403 Bitfield<20> tta;
1404 Bitfield<15> tase;
1405 Bitfield<13> tcp13;
1406 Bitfield<12> tcp12;
1407 Bitfield<11> tcp11;
1408 Bitfield<10> tcp10;
1409 Bitfield<10> tfp; // AArch64
1410 Bitfield<9> tcp9;
1411 Bitfield<8> tcp8;
1412 Bitfield<7> tcp7;
1413 Bitfield<6> tcp6;
1414 Bitfield<5> tcp5;
1415 Bitfield<4> tcp4;
1416 Bitfield<3> tcp3;
1417 Bitfield<2> tcp2;
1418 Bitfield<1> tcp1;
1419 Bitfield<0> tcp0;
1420 EndBitUnion(HCPTR)
1421
1422 BitUnion32(HSTR)
1423 Bitfield<17> tjdbx;
1424 Bitfield<16> ttee;
1425 Bitfield<15> t15;
1426 Bitfield<13> t13;
1427 Bitfield<12> t12;
1428 Bitfield<11> t11;
1429 Bitfield<10> t10;
1430 Bitfield<9> t9;
1431 Bitfield<8> t8;
1432 Bitfield<7> t7;
1433 Bitfield<6> t6;
1434 Bitfield<5> t5;
1435 Bitfield<4> t4;
1436 Bitfield<3> t3;
1437 Bitfield<2> t2;
1438 Bitfield<1> t1;
1439 Bitfield<0> t0;
1440 EndBitUnion(HSTR)
1441
1442 BitUnion64(HCR)
1443 Bitfield<33> id; // AArch64
1444 Bitfield<32> cd; // AArch64
1445 Bitfield<31> rw; // AArch64
1446 Bitfield<30> trvm; // AArch64
1447 Bitfield<29> hcd; // AArch64
1448 Bitfield<28> tdz; // AArch64
1449
1450 Bitfield<27> tge;
1451 Bitfield<26> tvm;
1452 Bitfield<25> ttlb;
1453 Bitfield<24> tpu;
1454 Bitfield<23> tpc;
1455 Bitfield<22> tsw;
1456 Bitfield<21> tac;
1457 Bitfield<21> tacr; // AArch64
1458 Bitfield<20> tidcp;
1459 Bitfield<19> tsc;
1460 Bitfield<18> tid3;
1461 Bitfield<17> tid2;
1462 Bitfield<16> tid1;
1463 Bitfield<15> tid0;
1464 Bitfield<14> twe;
1465 Bitfield<13> twi;
1466 Bitfield<12> dc;
1467 Bitfield<11, 10> bsu;
1468 Bitfield<9> fb;
1469 Bitfield<8> va;
1470 Bitfield<8> vse; // AArch64
1471 Bitfield<7> vi;
1472 Bitfield<6> vf;
1473 Bitfield<5> amo;
1474 Bitfield<4> imo;
1475 Bitfield<3> fmo;
1476 Bitfield<2> ptw;
1477 Bitfield<1> swio;
1478 Bitfield<0> vm;
1479 EndBitUnion(HCR)
1480
1481 BitUnion32(NSACR)
1482 Bitfield<20> nstrcdis;
1483 Bitfield<19> rfr;
1484 Bitfield<15> nsasedis;
1485 Bitfield<14> nsd32dis;
1486 Bitfield<13> cp13;
1487 Bitfield<12> cp12;
1488 Bitfield<11> cp11;
1489 Bitfield<10> cp10;
1490 Bitfield<9> cp9;
1491 Bitfield<8> cp8;
1492 Bitfield<7> cp7;
1493 Bitfield<6> cp6;
1494 Bitfield<5> cp5;
1495 Bitfield<4> cp4;
1496 Bitfield<3> cp3;
1497 Bitfield<2> cp2;
1498 Bitfield<1> cp1;
1499 Bitfield<0> cp0;
1500 EndBitUnion(NSACR)
1501
1502 BitUnion32(SCR)
1503 Bitfield<13> twe;
1504 Bitfield<12> twi;
1505 Bitfield<11> st; // AArch64
1506 Bitfield<10> rw; // AArch64
1507 Bitfield<9> sif;
1508 Bitfield<8> hce;
1509 Bitfield<7> scd;
1510 Bitfield<7> smd; // AArch64
1511 Bitfield<6> nEt;
1512 Bitfield<5> aw;
1513 Bitfield<4> fw;
1514 Bitfield<3> ea;
1515 Bitfield<2> fiq;
1516 Bitfield<1> irq;
1517 Bitfield<0> ns;
1518 EndBitUnion(SCR)
1519
1520 BitUnion32(SCTLR)
1521 Bitfield<30> te; // Thumb Exception Enable (AArch32 only)
1522 Bitfield<29> afe; // Access flag enable (AArch32 only)
1523 Bitfield<28> tre; // TEX remap enable (AArch32 only)
1524 Bitfield<27> nmfi; // Non-maskable FIQ support (ARMv7 only)
1525 Bitfield<26> uci; // Enable EL0 access to DC CVAU, DC CIVAC,
1526 // DC CVAC and IC IVAU instructions
1527 // (AArch64 SCTLR_EL1 only)
1528 Bitfield<25> ee; // Exception Endianness
1529 Bitfield<24> ve; // Interrupt Vectors Enable (ARMv7 only)
1530 Bitfield<24> e0e; // Endianness of explicit data accesses at EL0
1531 // (AArch64 SCTLR_EL1 only)
1532 Bitfield<23> xp; // Extended page table enable (dropped in ARMv7)
1533 Bitfield<22> u; // Alignment (dropped in ARMv7)
1534 Bitfield<21> fi; // Fast interrupts configuration enable
1535 // (ARMv7 only)
1536 Bitfield<20> uwxn; // Unprivileged write permission implies EL1 XN
1537 // (AArch32 only)
1538 Bitfield<19> dz; // Divide by Zero fault enable
1539 // (dropped in ARMv7)
1540 Bitfield<19> wxn; // Write permission implies XN
1541 Bitfield<18> ntwe; // Not trap WFE
1542 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1543 Bitfield<18> rao2; // Read as one
1544 Bitfield<16> ntwi; // Not trap WFI
1545 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1546 Bitfield<16> rao3; // Read as one
1547 Bitfield<15> uct; // Enable EL0 access to CTR_EL0
1548 // (AArch64 SCTLR_EL1 only)
1549 Bitfield<14> rr; // Round Robin select (ARMv7 only)
1550 Bitfield<14> dze; // Enable EL0 access to DC ZVA
1551 // (AArch64 SCTLR_EL1 only)
1552 Bitfield<13> v; // Vectors bit (AArch32 only)
1553 Bitfield<12> i; // Instruction cache enable
1554 Bitfield<11> z; // Branch prediction enable (ARMv7 only)
1555 Bitfield<10> sw; // SWP/SWPB enable (ARMv7 only)
1556 Bitfield<9, 8> rs; // Deprecated protection bits (dropped in ARMv7)
1557 Bitfield<9> uma; // User mask access (AArch64 SCTLR_EL1 only)
1558 Bitfield<8> sed; // SETEND disable
1559 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1560 Bitfield<7> b; // Endianness support (dropped in ARMv7)
1561 Bitfield<7> itd; // IT disable
1562 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1563 Bitfield<6, 3> rao4; // Read as one
1564 Bitfield<6> thee; // ThumbEE enable
1565 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1566 Bitfield<5> cp15ben; // CP15 barrier enable
1567 // (AArch32 and AArch64 SCTLR_EL1 only)
1568 Bitfield<4> sa0; // Stack Alignment Check Enable for EL0
1569 // (AArch64 SCTLR_EL1 only)
1570 Bitfield<3> sa; // Stack Alignment Check Enable (AArch64 only)
1571 Bitfield<2> c; // Cache enable
1572 Bitfield<1> a; // Alignment check enable
1573 Bitfield<0> m; // MMU enable
1574 EndBitUnion(SCTLR)
1575
1576 BitUnion32(CPACR)
1577 Bitfield<1, 0> cp0;
1578 Bitfield<3, 2> cp1;
1579 Bitfield<5, 4> cp2;
1580 Bitfield<7, 6> cp3;
1581 Bitfield<9, 8> cp4;
1582 Bitfield<11, 10> cp5;
1583 Bitfield<13, 12> cp6;
1584 Bitfield<15, 14> cp7;
1585 Bitfield<17, 16> cp8;
1586 Bitfield<19, 18> cp9;
1587 Bitfield<21, 20> cp10;
1588 Bitfield<21, 20> fpen; // AArch64
1589 Bitfield<23, 22> cp11;
1590 Bitfield<25, 24> cp12;
1591 Bitfield<27, 26> cp13;
1592 Bitfield<29, 28> rsvd;
1593 Bitfield<28> tta; // AArch64
1594 Bitfield<30> d32dis;
1595 Bitfield<31> asedis;
1596 EndBitUnion(CPACR)
1597
1598 BitUnion32(FSR)
1599 Bitfield<3, 0> fsLow;
1600 Bitfield<5, 0> status; // LPAE
1601 Bitfield<7, 4> domain;
1602 Bitfield<9> lpae;
1603 Bitfield<10> fsHigh;
1604 Bitfield<11> wnr;
1605 Bitfield<12> ext;
1606 Bitfield<13> cm; // LPAE
1607 EndBitUnion(FSR)
1608
1609 BitUnion32(FPSCR)
1610 Bitfield<0> ioc;
1611 Bitfield<1> dzc;
1612 Bitfield<2> ofc;
1613 Bitfield<3> ufc;
1614 Bitfield<4> ixc;
1615 Bitfield<7> idc;
1616 Bitfield<8> ioe;
1617 Bitfield<9> dze;
1618 Bitfield<10> ofe;
1619 Bitfield<11> ufe;
1620 Bitfield<12> ixe;
1621 Bitfield<15> ide;
1622 Bitfield<18, 16> len;
1623 Bitfield<21, 20> stride;
1624 Bitfield<23, 22> rMode;
1625 Bitfield<24> fz;
1626 Bitfield<25> dn;
1627 Bitfield<26> ahp;
1628 Bitfield<27> qc;
1629 Bitfield<28> v;
1630 Bitfield<29> c;
1631 Bitfield<30> z;
1632 Bitfield<31> n;
1633 EndBitUnion(FPSCR)
1634
1635 // This mask selects bits of the FPSCR that actually go in the FpCondCodes
1636 // integer register to allow renaming.
1637 static const uint32_t FpCondCodesMask = 0xF0000000;
1638 // This mask selects the cumulative FP exception flags of the FPSCR.
1639 static const uint32_t FpscrExcMask = 0x0000009F;
1640 // This mask selects the cumulative saturation flag of the FPSCR.
1641 static const uint32_t FpscrQcMask = 0x08000000;
1642
1643 BitUnion32(FPEXC)
1644 Bitfield<31> ex;
1645 Bitfield<30> en;
1646 Bitfield<29, 0> subArchDefined;
1647 EndBitUnion(FPEXC)
1648
1649 BitUnion32(MVFR0)
1650 Bitfield<3, 0> advSimdRegisters;
1651 Bitfield<7, 4> singlePrecision;
1652 Bitfield<11, 8> doublePrecision;
1653 Bitfield<15, 12> vfpExceptionTrapping;
1654 Bitfield<19, 16> divide;
1655 Bitfield<23, 20> squareRoot;
1656 Bitfield<27, 24> shortVectors;
1657 Bitfield<31, 28> roundingModes;
1658 EndBitUnion(MVFR0)
1659
1660 BitUnion32(MVFR1)
1661 Bitfield<3, 0> flushToZero;
1662 Bitfield<7, 4> defaultNaN;
1663 Bitfield<11, 8> advSimdLoadStore;
1664 Bitfield<15, 12> advSimdInteger;
1665 Bitfield<19, 16> advSimdSinglePrecision;
1666 Bitfield<23, 20> advSimdHalfPrecision;
1667 Bitfield<27, 24> vfpHalfPrecision;
1668 Bitfield<31, 28> raz;
1669 EndBitUnion(MVFR1)
1670
1671 BitUnion64(TTBCR)
1672 // Short-descriptor translation table format
1673 Bitfield<2, 0> n;
1674 Bitfield<4> pd0;
1675 Bitfield<5> pd1;
1676 // Long-descriptor translation table format
1677 Bitfield<5, 0> t0sz;
1678 Bitfield<7> epd0;
1679 Bitfield<9, 8> irgn0;
1680 Bitfield<11, 10> orgn0;
1681 Bitfield<13, 12> sh0;
1682 Bitfield<14> tg0;
1683 Bitfield<21, 16> t1sz;
1684 Bitfield<22> a1;
1685 Bitfield<23> epd1;
1686 Bitfield<25, 24> irgn1;
1687 Bitfield<27, 26> orgn1;
1688 Bitfield<29, 28> sh1;
1689 Bitfield<30> tg1;
1690 Bitfield<34, 32> ips;
1691 Bitfield<36> as;
1692 Bitfield<37> tbi0;
1693 Bitfield<38> tbi1;
1694 // Common
1695 Bitfield<31> eae;
1696 // TCR_EL2/3 (AArch64)
1697 Bitfield<18, 16> ps;
1698 Bitfield<20> tbi;
1699 EndBitUnion(TTBCR)
1700
1701 // Fields of TCR_EL{1,2,3} (mostly overlapping)
1702 // TCR_EL1 is natively 64 bits, the others are 32 bits
1703 BitUnion64(TCR)
1704 Bitfield<5, 0> t0sz;
1705 Bitfield<7> epd0; // EL1
1706 Bitfield<9, 8> irgn0;
1707 Bitfield<11, 10> orgn0;
1708 Bitfield<13, 12> sh0;
1709 Bitfield<15, 14> tg0;
1710 Bitfield<18, 16> ps;
1711 Bitfield<20> tbi; // EL2/EL3
1712 Bitfield<21, 16> t1sz; // EL1
1713 Bitfield<22> a1; // EL1
1714 Bitfield<23> epd1; // EL1
1715 Bitfield<25, 24> irgn1; // EL1
1716 Bitfield<27, 26> orgn1; // EL1
1717 Bitfield<29, 28> sh1; // EL1
1718 Bitfield<31, 30> tg1; // EL1
1719 Bitfield<34, 32> ips; // EL1
1720 Bitfield<36> as; // EL1
1721 Bitfield<37> tbi0; // EL1
1722 Bitfield<38> tbi1; // EL1
1723 EndBitUnion(TCR)
1724
1725 BitUnion32(HTCR)
1726 Bitfield<2, 0> t0sz;
1727 Bitfield<9, 8> irgn0;
1728 Bitfield<11, 10> orgn0;
1729 Bitfield<13, 12> sh0;
1730 EndBitUnion(HTCR)
1731
1732 BitUnion32(VTCR_t)
1733 Bitfield<3, 0> t0sz;
1734 Bitfield<4> s;
1735 Bitfield<7, 6> sl0;
1736 Bitfield<9, 8> irgn0;
1737 Bitfield<11, 10> orgn0;
1738 Bitfield<13, 12> sh0;
1739 EndBitUnion(VTCR_t)
1740
1741 BitUnion32(PRRR)
1742 Bitfield<1,0> tr0;
1743 Bitfield<3,2> tr1;
1744 Bitfield<5,4> tr2;
1745 Bitfield<7,6> tr3;
1746 Bitfield<9,8> tr4;
1747 Bitfield<11,10> tr5;
1748 Bitfield<13,12> tr6;
1749 Bitfield<15,14> tr7;
1750 Bitfield<16> ds0;
1751 Bitfield<17> ds1;
1752 Bitfield<18> ns0;
1753 Bitfield<19> ns1;
1754 Bitfield<24> nos0;
1755 Bitfield<25> nos1;
1756 Bitfield<26> nos2;
1757 Bitfield<27> nos3;
1758 Bitfield<28> nos4;
1759 Bitfield<29> nos5;
1760 Bitfield<30> nos6;
1761 Bitfield<31> nos7;
1762 EndBitUnion(PRRR)
1763
1764 BitUnion32(NMRR)
1765 Bitfield<1,0> ir0;
1766 Bitfield<3,2> ir1;
1767 Bitfield<5,4> ir2;
1768 Bitfield<7,6> ir3;
1769 Bitfield<9,8> ir4;
1770 Bitfield<11,10> ir5;
1771 Bitfield<13,12> ir6;
1772 Bitfield<15,14> ir7;
1773 Bitfield<17,16> or0;
1774 Bitfield<19,18> or1;
1775 Bitfield<21,20> or2;
1776 Bitfield<23,22> or3;
1777 Bitfield<25,24> or4;
1778 Bitfield<27,26> or5;
1779 Bitfield<29,28> or6;
1780 Bitfield<31,30> or7;
1781 EndBitUnion(NMRR)
1782
1783 BitUnion32(CONTEXTIDR)
1784 Bitfield<7,0> asid;
1785 Bitfield<31,8> procid;
1786 EndBitUnion(CONTEXTIDR)
1787
1788 BitUnion32(L2CTLR)
1789 Bitfield<2,0> sataRAMLatency;
1790 Bitfield<4,3> reserved_4_3;
1791 Bitfield<5> dataRAMSetup;
1792 Bitfield<8,6> tagRAMLatency;
1793 Bitfield<9> tagRAMSetup;
1794 Bitfield<11,10> dataRAMSlice;
1795 Bitfield<12> tagRAMSlice;
1796 Bitfield<20,13> reserved_20_13;
1797 Bitfield<21> eccandParityEnable;
1798 Bitfield<22> reserved_22;
1799 Bitfield<23> interptCtrlPresent;
1800 Bitfield<25,24> numCPUs;
1801 Bitfield<30,26> reserved_30_26;
1802 Bitfield<31> l2rstDISABLE_monitor;
1803 EndBitUnion(L2CTLR)
1804
1805 BitUnion32(CTR)
1806 Bitfield<3,0> iCacheLineSize;
1807 Bitfield<13,4> raz_13_4;
1808 Bitfield<15,14> l1IndexPolicy;
1809 Bitfield<19,16> dCacheLineSize;
1810 Bitfield<23,20> erg;
1811 Bitfield<27,24> cwg;
1812 Bitfield<28> raz_28;
1813 Bitfield<31,29> format;
1814 EndBitUnion(CTR)
1815
1816 BitUnion32(PMSELR)
1817 Bitfield<4, 0> sel;
1818 EndBitUnion(PMSELR)
1819
1820 BitUnion64(PAR)
1821 // 64-bit format
1822 Bitfield<63, 56> attr;
1823 Bitfield<39, 12> pa;
1824 Bitfield<11> lpae;
1825 Bitfield<9> ns;
1826 Bitfield<8, 7> sh;
1827 Bitfield<0> f;
1828 EndBitUnion(PAR)
1829
1830 BitUnion32(ESR)
1831 Bitfield<31, 26> ec;
1832 Bitfield<25> il;
1833 Bitfield<15, 0> imm16;
1834 EndBitUnion(ESR)
1835
1836 BitUnion32(CPTR)
1837 Bitfield<31> tcpac;
1838 Bitfield<20> tta;
1839 Bitfield<13, 12> res1_13_12_el2;
1840 Bitfield<10> tfp;
1841 Bitfield<9, 0> res1_9_0_el2;
1842 EndBitUnion(CPTR)
1843
1844
1845 // Checks read access permissions to coproc. registers
1846 bool canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1847 ThreadContext *tc);
1848
1849 // Checks write access permissions to coproc. registers
1850 bool canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1851 ThreadContext *tc);
1852
1853 // Checks read access permissions to AArch64 system registers
1854 bool canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1855 ThreadContext *tc);
1856
1857 // Checks write access permissions to AArch64 system registers
1858 bool canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1859 ThreadContext *tc);
1860
1861 // Uses just the scr.ns bit to pre flatten the misc regs. This is useful
1862 // for MCR/MRC instructions
1863 int
1864 flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc);
1865
1866 // Flattens a misc reg index using the specified security state. This is
1867 // used for opperations (eg address translations) where the security
1868 // state of the register access may differ from the current state of the
1869 // processor
1870 int
1871 flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns);
1872
1873 // Takes a misc reg index and returns the root reg if its one of a set of
1874 // banked registers
1875 void
1876 preUnflattenMiscReg();
1877
1878 int
1879 unflattenMiscReg(int reg);
1880
1881 }
1882
1883 #endif // __ARCH_ARM_MISCREGS_HH__