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42 #ifndef __ARCH_ARM_MISCREGS_HH__
43 #define __ARCH_ARM_MISCREGS_HH__
45 #include "base/bitunion.hh"
89 MISCREG_SCTLR = MISCREG_CP15_START,
166 MISCREG_CP15_UNIMP_START,
167 MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
197 MISCREG_NOP = MISCREG_CP15_END,
203 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
204 unsigned crm, unsigned opc2);
206 const char * const miscRegName[NUM_MISCREGS] = {
207 "cpsr", "itstate", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
208 "spsr_mon", "spsr_und", "spsr_abt",
209 "fpsr", "fpsid", "fpscr", "fpexc", "mvfr0", "mvfr1",
210 "sctlr_rst", "sev_mailbox",
211 "sctlr", "dccisw", "dccimvac", "dccmvac",
212 "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
213 "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
214 "clidr", "ccsidr", "csselr",
215 "icialluis", "iciallu", "icimvau",
216 "bpimva", "bpiallis", "bpiall",
217 "midr", "ttbr0", "ttbr1", "tlbtr", "dacr",
218 "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais",
219 "itlbiall", "itlbimva", "itlbiasid",
220 "dtlbiall", "dtlbimva", "dtlbiasid",
221 "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
222 "dfsr", "ifsr", "dfar", "ifar", "mpidr",
223 "prrr", "nmrr", "ttbcr", "id_pfr0", "ctr",
224 "scr", "sder", "par",
225 "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
226 "v2powpr", "v2powpw", "v2powur", "v2powuw",
227 "id_mmfr0","actlr", "pmcr", "pmcntr",
228 "pmcntenset", "pmcntenclr", "pmovsr",
229 "pmswinc", "pmselr", "pmceid0",
230 "pmceid1", "pmc_other", "pmxevcntr",
231 "pmuserenr", "pmintenset", "pmintenclr",
232 // Unimplemented below
234 "id_pfr1", "id_dfr0", "id_afr0",
235 "id_mmfr1", "id_mmfr2", "id_mmfr3",
236 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
239 "dcimvac", "dcisw", "mccsw",
242 "vbar", "mvbar", "isr", "fceidr",
267 // Bitfields for moving to/from CPSR
269 Bitfield<1, 0> bottom2;
272 // This mask selects bits of the CPSR that actually go in the CondCodes
273 // integer register to allow renaming.
274 static const uint32_t CondCodesMask = 0xF80F0000;
277 Bitfield<31> ie; // Instruction endianness
278 Bitfield<30> te; // Thumb Exception Enable
279 Bitfield<29> afe; // Access flag enable
280 Bitfield<28> tre; // TEX Remap bit
281 Bitfield<27> nmfi;// Non-maskable fast interrupts enable
282 Bitfield<25> ee; // Exception Endianness bit
283 Bitfield<24> ve; // Interrupt vectors enable
284 Bitfield<23> xp; // Extended page table enable bit
285 Bitfield<22> u; // Alignment (now unused)
286 Bitfield<21> fi; // Fast interrupts configuration enable
287 Bitfield<19> dz; // Divide by Zero fault enable bit
288 Bitfield<18> rao2;// Read as one
289 Bitfield<17> br; // Background region bit
290 Bitfield<16> rao3;// Read as one
291 Bitfield<14> rr; // Round robin cache replacement
292 Bitfield<13> v; // Base address for exception vectors
293 Bitfield<12> i; // instruction cache enable
294 Bitfield<11> z; // branch prediction enable bit
295 Bitfield<10> sw; // Enable swp/swpb
296 Bitfield<9,8> rs; // deprecated protection bits
297 Bitfield<6,3> rao4;// Read as one
298 Bitfield<7> b; // Endianness support (unused)
299 Bitfield<2> c; // Cache enable bit
300 Bitfield<1> a; // Alignment fault checking
301 Bitfield<0> m; // MMU enable bit
310 Bitfield<11, 10> cp5;
311 Bitfield<13, 12> cp6;
312 Bitfield<15, 14> cp7;
313 Bitfield<17, 16> cp8;
314 Bitfield<19, 18> cp9;
315 Bitfield<21, 20> cp10;
316 Bitfield<23, 22> cp11;
317 Bitfield<25, 24> cp12;
318 Bitfield<27, 26> cp13;
324 Bitfield<3, 0> fsLow;
325 Bitfield<7, 4> domain;
344 Bitfield<18, 16> len;
345 Bitfield<21, 20> stride;
346 Bitfield<23, 22> rMode;
357 // This mask selects bits of the FPSCR that actually go in the FpCondCodes
358 // integer register to allow renaming.
359 static const uint32_t FpCondCodesMask = 0xF800009F;
364 Bitfield<29, 0> subArchDefined;
368 Bitfield<3, 0> advSimdRegisters;
369 Bitfield<7, 4> singlePrecision;
370 Bitfield<11, 8> doublePrecision;
371 Bitfield<15, 12> vfpExceptionTrapping;
372 Bitfield<19, 16> divide;
373 Bitfield<23, 20> squareRoot;
374 Bitfield<27, 24> shortVectors;
375 Bitfield<31, 28> roundingModes;
379 Bitfield<3, 0> flushToZero;
380 Bitfield<7, 4> defaultNaN;
381 Bitfield<11, 8> advSimdLoadStore;
382 Bitfield<15, 12> advSimdInteger;
383 Bitfield<19, 16> advSimdSinglePrecision;
384 Bitfield<23, 20> advSimdHalfPrecision;
385 Bitfield<27, 24> vfpHalfPrecision;
386 Bitfield<31, 28> raz;
433 #endif // __ARCH_ARM_MISCREGS_HH__